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zjI=kxy0MTeSDH~6-sI$5d9Asw&^Z2pm5BwraSf2sq}|?jA1(P>(O}GYZX(x%xuLW- z`XZ}og_p`{rT*656$~Vl0D^GP)8P%YV&UD}j3*%}>{6djq^^N?_e8=e$jMgYOUfu7 zQc|NKCaqh(ynFd2kVEP(sfLDxYK6U!4p`eJyri2_N2@A`BvDPPO0PzS1+f9fMO}T} zrS;Nsd1JI$S4-buE?Sao=FSH#gI4R^5W*3AJBi!c%rIU9YUFy4tyNqCTlXFy&ekg@L02&?9Lt&aG55$9|9)uA9a z(Q03Z^hxxz2I|uvTId4jpRVtN74hQaoU@MZn9TsG^r(zPL^Ml@$F^-OaO(NhUx^pdM|6e z6z~qtEqO`T-zCVx+HpdDwXXV>q*p6ws{Tq&6|M(8y;G&qYW)=(@AzSg09#j6<(FXA zjtCW{=+!#yTuHCyJF5Kj`frf*b&{c4&s{GG)O%!ehXlv6OxY(weG%M0+gOb zu8>v5Dcp$DO0U+3_euJrR%FDB)6(10=+%6;pNtwu>lzWNt6N26_!WfK^3{6tY&l^r zPs5kZnt=Y3q*wY^>(YxQ{mUvtQYif?2Kc@OFJGal_3L8VZinNz2ol%y@*hGD$*<_u zI=71q3&*#}xGhI|`Tv5vLYxXs-KW3v1woXKuhJ^q4>Ve{RrG3I;OGeHe+F7=YDKTs z*FTcVBlRNnpr8Bydfq|07^j{`>@nh$#B>dlSN?Lxo2z zah@SB+nYp$*43;>dVOeNKMjSWo6Umi!W=90VB9Tj=9viam>W&!>Q~?`DJRJG!+AaZ*|CluRqP +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(int); + +pifi genAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, in1, res; + pifi fPtr; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genAdd (fPtr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d + %d = %d\n", in0, in1, res); + if (res == (in0 + in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Add-With-Specialization.power b/CodeExamples/Add-With-Specialization.power new file mode 100755 index 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z>6D+!)syP^vgETQc^eJ~NWM3T|55NYHr7v8N%`s|`AwWZww}$LKh~eqiM~c})RNvK z@8t4h=a*jaXAqteH`NGqkUztl%eKn?bC}G*^)1d9Ve|8!)9?>sfaodw`OAX@dt8pw6EaJs za(TbR!E+ite=OyDuNCsg5vMB%T40;O+(~|Eo0Q)=SIDoEj_*^PFY=n7UjU!* zNuD3SO#0y;j!N8AJ3cM-zr9B2*MS#Z`$2Uc8vS^N^w?&z&LsSw=lb)RdTW6wzp(B} zi8GywQ~yzCIme_t)@vYGk{`%agHQEI?uYB7eBpW_-y;jSlk;UIOr%N5 zAHG4zpQp1wT=#-c_3TY*uTK&m_$Qb9X|6})H9sFt!#|RS{~N-yF^8#jzS7ml<$j66-rzH^Dw9a!Q;})2*Nsvq&-Xk{#wlNuK z*#rlXIPx*|2Xh{JUBt`SQj0>Qs}KV?QU2XXG52IsemD-CN6O*H|w1kRd zu#;%L$C2DZTT^>Hla$Wl9V?_qlSAH|OAZthD=|t~u7nh_MRpyHOyya9%DB zrEvn=5{3qm6W~HD+}@72QQ!p{J6dq;>I=c~sVIMkp^_RKqv)kFM(6S>3=mY1{I8Ud zn$%qQ2T(d$prr!eE`X|YEl_?XuZ7jRMWl+?g;|KG{ObG*lwZ0ai6^G{QP&?KhABRg zU!9YI@{9KObdd~QYX7bDEClZzd<(0}?~~_dp!`xNB+2!U$S91N8oT6JHMc)dm zIM%&YTP( z=Ijq-RQz8MFqhvW%kPo-8)u;L|l4M=I^D+4OcPl2HdLuDF01=caj7VIE?Kp7Ulnoa{Qb-*46^>Q|0%3ROF{m KPR&I* +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(int); + +pifi genAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x780F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, in1, res; + pifi fPtr; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genAdd (fPtr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d + %d = %d\n", in0, in1, res); + if (res == (in0 + in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Add-With-Specialization.riscv b/CodeExamples/Add-With-Specialization.riscv new file mode 100755 index 0000000000000000000000000000000000000000..bf3a43a6afa1065502cd2044874f927bb40fd210 GIT binary patch literal 29136 zcmeHweSB2Kx&NF!n`}Zb1OkFp%bHD2Vw!9qs1+3mVM9oZkOFGGSAWZrEMb35vSD}e z?bZVBh8J6fHde8vEyW0khzJ-cMGUZz5D@|fjFdunkvEYK@gbcbnIJ3R7se??nC&?LdL=n-p7or3rk`q z7RSOlO=-jecuJk{G3o?H|>@kGFPfhR|0knPAW zB&Rt8B1BU@$q>!-nf-Mcvp$?g1u(r=%cHVl{%iiPw|+S*@$UP7>t26mZq3@C{HoXB z-@N|oN8THFTc6)_nHf0k>*;#rwO^Y@4LZMS?!%u^389YK%YZ9#J>bW|_Y0vZCnJRZ zG3Z)-JO87gn?mS2K*xme{{*x#gq{tWO;Y4z*f#;Hb9_j?1iCV$ymZhFA+!Z_ZU{ds zuzN~u1$MXN1v@L5;&HPQyUXQtG5d244<+PHvbmVe<8-hhTVbIyk6Eqg>O8C4V{>_| zMK(tv!+_$gTeU>wt{N+=x@!Do*RzZzvNk ze!RfKRPZEGoWKE>LU95ZTtABQ0f~8l;)wFCiRjV%~+Btbj$c-o?jniM6`O-AX zDMS1(uateBkkLAQ!yija-`sK~&(Q91es9(E8R1)JAAfpCX|~Dt&5V^9ah9RNOVc*4 zd46)-Ue?ECE^jeO`nLWHyovs{QiDm7+YoClooO=5Efo8*nQ{h~rjN_Ay);ee9=;=P zJBu+%8^s< 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(signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(int); + +pifi genAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x73F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, in1, res; + pifi fPtr; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genAdd (fPtr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d + %d = %d\n", in0, in1, res); + if (res == (in0 + in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Add-With-Transprecision.aarch64 b/CodeExamples/Add-With-Transprecision.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..ba791eed19985442f5601c0deb43e65c871b34f5 GIT binary patch literal 43928 zcmeHw3w%`7wf8=AW-^m^NFr}x!lNRZ1kfS~mPr7Sf(i+~uC0?vGD)T;Ght?eQTXbh z*jn+nU%^K!Xm6>tUrk%DL9Mk{?k%loZLg03wYAlLrM}Zj=l<7z%b1K#NZc9QeJ@W+*dmtATx=Gb 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z?xcR`tFIRX7B%qoLqA*6r|NITHbL++Wq2v{O6Ga}l+U&c0(zxNzZ9KrWQs2C8&ZoZQTtT$!ANtJ&b&@$0q Put(6-yAAr4l4Sn_3uW)) literal 0 HcmV?d00001 diff --git a/CodeExamples/Add-With-Transprecision.aarch64.c b/CodeExamples/Add-With-Transprecision.aarch64.c new file mode 100644 index 0000000..dad6e14 --- /dev/null +++ b/CodeExamples/Add-With-Transprecision.aarch64.c @@ -0,0 +1,1101 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x72 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x272 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRI_F_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_FADD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef float (*pifff)(float, float); +typedef double (*pifdd)(double, double); + +// Simple addition between variables with +// specialization transprecision on data width +// Width depend on the platform. At least 32 & 64 bits. +// Could also be 16 on RISCV or 128 on INTEL + +h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +int main(int argc, char * argv[]) +{ + float in0, in1, resf; + double resd; +#if 0 + long double resD; +#endif + pifff fPtr1; + pifdd fPtr2; + + if (argc < 2) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atof(argv[1]); // Get the users values in1 & in2 + in1 = atof(argv[2]); + fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions +#if 0 + fPtr1 = genAdd (ptr, 16); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); +#endif + + fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); + + fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions + resd = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); + +#if 0 + fPtr2 = genAdd (ptr, 128); // Generate instructions + resD = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); +#endif + + return 0; + +} diff --git a/CodeExamples/Add-With-Transprecision.power b/CodeExamples/Add-With-Transprecision.power new file mode 100755 index 0000000000000000000000000000000000000000..75732780162f3482e581ed1471c2617f4e16dfba GIT binary patch literal 78288 zcmeHv3wRvGm2UOSNHelzdHlebr`y;jlB1UmF=MdNNPbDSF~Se<-XuFSl19>iG$Uq4 zFeVa~9kQ5&+_k?o8?8XoShJ~yYe7Q;ji44Yl z|5J}qt2JZE4=vig-BNc|ojP@@&Rxk$S>4Hprray%T6qE+Y-Y|M#}%K1p32suB}Je(}ZOogh26z0f0 z8E}5YdDtEhR24F=jkr=<^^Zlq{;|gSRT!iO;n*)jRgRiR<@~aoUzSs0k8GF!s(&x#C$yqpRT2{Kb5@zQY%%27KIC~u9_FTA$AwQ=FKWrg2S1qzD)EbpsTTHF10WVe_a;( z>MZnGS?G6zuH&>Ggj=R|F3Uo{Gz)!77J6wGIt!;FN!A{Y$76BU-jPhurJ*H+L_88r zHnHY#vOUxsPDJhrv$pnlEE#S{vbIobYpj7Kl8q?Hn(mHAl3^A~#+q0lfPvHyNF+n? zWS}h+i84ylkXp!AuBokF8dy*^|2nWWx5c88ji$I`$e%flOdJ~i>Jh4O{dAfRxNkqqxKCU(B{t`<`%kI=xIAc+8kJ0CLdN?dWA}Z+QVbUG*cwSPeP7 zUv;t?%DdQwSnx_fKAuY2oNi`a}}^zpWvi0$38iV=(Ac7}^Cs%0{+xwzM&m^v zHa@C@ndNWu)#+dCOkR0kXR`3V&WE)7(sj)^=ekIzq4hzJ2e9f=`;8xeWEj=7 zv;?!WhVjP5FwdG`_Yiys(i zOkc!t#au$&@1kArqOA{`<`r}qs!tEf4j6BK^fcO%%CGE9T^8y5wU*ae!73L$bu&ZX z>x*<&xf4dS2H{p}7p0NEwY{*o3n7ma9>NjO4 zsBRi(qVC%}Q?nmH{S!KaEU@UQ+Zb<4qihSptyE7D+g25n^&fE0>ms^g6fZj9F78UL zp3{|DzqIQy*c#$F?JnM^vtr;_TvC8?WzYw9wq^xF;yrEDFYbS(!S~ol!Zr~;-DtbA zM;0BlY&zU2b!cZ>22!)X+?o3Hx49lElOCN?kC~{u1-McAy|t{fRnqSPcJ1u%dsVvz z(5^h$F7R_+=*0VFJ9HrZnwtDenwwUI{<5yNt9^P+SNrLCU3LCdT@%=WVp^s@L;sgKy`D0*`5^hcNPj)+K2qhww(Ylj77TNu%38fdzf9 zNFLQ*)pu(khx%zW?KQU}Ps&q$jBqE#sm}ef&amXUodx=$H2&5v!#J4T^~lG@YHHJR znNNMYW0ZYM$?cRy^Oj=cA7Wu0PP3ECVGBJy3$P5RzN1dblw{`Ue{k!>mXF<&AQO{k4k&;W}Sx@V&FPek?YC+$FHe@c+cvNK^thP^M zjCi+J)a1#rSc`BT#;$5_?ar&ww=|AO7TF$zJE;t}l`=k)8yK9| zJGkC{=wAD?fz}t)eG+Hi5mrm< zM<3~nww*M~aI?KWvI9kIOYb{>7%WS+4C`(c^{)^8`+&?djG*r|8K-(hUl%`su@Sj3 zw-`6E#U(zJqr9T-tNM_}I(0R$+KY9w+eh;1An#cz<0HuXs!1MUf3|Canj1PW!rA-z z4+ix(o3UqJD{qnW_y}Yk1@6b$-w*V%HwOBdF)+Ypo@83(Nsksdd8t;3Ih9xPIOf@h zz?kB@5kJK$ABbR%Jc#(^nuvFE`WxFFn$er9&Fm}G0)1sDFV=;5T}MzJdw3sX-yWdQ zBSWtYXRvSYARbNd@VJY;u$yQe*2mKYEN>^J4TCN6%J?)^yAytznpe4e-mm`OU>woh zq;cv+yB@;&M`NZJW0>@i{qLWEHk$d`B%epC+<8pu*o*SNMj0KtA7fjq-a?#kI0Cw= z^AO@n?m@&AZu=1b4fv-$S-g?v@-9t;%vT&HyEFm#T-hyXuRBCY^N8{YyCY1@RH1_MqUtP5b_r%!WR4?g8 zoNzqgzPjtz!2T^@{~r23wSGDJOxTBh$lCl{QJ2Cnn=G1VBr6wl%AwJm60(%7Az7tT zmg<9SvS^-?tg9jGD#)VoMeTB!+Vy6?XqT9)e2qKFm>+xHS{~Avq4W$nzBI(uSc@R; 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// Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define PPC_FADDS_RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); +#define PPC_FADDS__RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDFP_RRR_F_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xa & 0x7ff) >> 0)); } while(0); +#define P1_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); +#define P1_FADD__RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FADDS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FADDS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDFP_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FADD__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef float (*pifff)(float, float); +typedef double (*pifdd)(double, double); + +// Simple addition between variables with +// specialization transprecision on data width +// Width depend on the platform. At least 32 & 64 bits. +// Could also be 16 on RISCV or 128 on INTEL + +h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +int main(int argc, char * argv[]) +{ + float in0, in1, resf; + double resd; +#if 0 + long double resD; +#endif + pifff fPtr1; + pifdd fPtr2; + + if (argc < 2) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atof(argv[1]); // Get the users values in1 & in2 + in1 = atof(argv[2]); + fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions +#if 0 + fPtr1 = genAdd (ptr, 16); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); +#endif + + fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); + + fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions + resd = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); + +#if 0 + fPtr2 = genAdd (ptr, 128); // Generate instructions + resD = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); +#endif + + return 0; + +} diff --git a/CodeExamples/Add-With-Transprecision.riscv b/CodeExamples/Add-With-Transprecision.riscv new file mode 100755 index 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H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32F_FADD_S_RRR_F_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FADD_D_RRR_F_64_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef float (*pifff)(float, float); +typedef double (*pifdd)(double, double); + +// Simple addition between variables with +// specialization transprecision on data width +// Width depend on the platform. At least 32 & 64 bits. +// Could also be 16 on RISCV or 128 on INTEL + +h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +int main(int argc, char * argv[]) +{ + float in0, in1, resf; + double resd; +#if 0 + long double resD; +#endif + pifff fPtr1; + pifdd fPtr2; + + if (argc < 2) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atof(argv[1]); // Get the users values in1 & in2 + in1 = atof(argv[2]); + fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions +#if 0 + fPtr1 = genAdd (ptr, 16); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); +#endif + + fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions + resf = fPtr1(in0, in1); // Call generated code + printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); + + fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions + resd = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); + +#if 0 + fPtr2 = genAdd (ptr, 128); // Generate instructions + resD = fPtr2(in0, in1); // Call generated code + printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); +#endif + + return 0; + +} diff --git a/CodeExamples/Array-Ld-flt.aarch64 b/CodeExamples/Array-Ld-flt.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..5fe4e94f5bb0ff172c5cb8f0347f11781a5523ff GIT binary patch literal 48048 zcmeHw3w%`7wf8=A=9PCyB1Awq;ZYGy0>L6EUQQAaxuRl%ulBZ+Nis>MCX+BTK@=*3 z+SXfXB^P|ODg?E+2JKh+`fRGb2DPs%ZMj8STdNMJw|=en-qc4mS8(os?Z@QIWF`+n z@_oPW=Sj}ld#}CL+H0@9_IsZ*+g7i;#HMLXT{iXvqfnpAl)F>P(Jx&^M?s?dK+=66>69Clf+<(!kMc(M2FY)O%|wX8 zCOORD&q0@P>019rxRLzDZ9E9qnw1p>*}hrz^!%PGfzKya?8^_Cw12KS;lss+;Z^IKHc+MMc0qG z1B~@g`Do2R{_&MvhHdt5XB+xabsuJI=MS0H?=2&;Ujb4g!k zvB+;`;eJDB`;Y17!11}P>))Y2SnY2Z>wBBIyWfr+-|@DNu#T{fu)gpsZ`%>JBWy?5 ze&JW%J{XJLdkA+o^vn9!44904|G8Lf8tGr@w-5SdQLXDB+!DAe8T$)h8%h{ET=K!H z0WWC!b!|UGxe#44KJcEOb7I?(%IxiTmYk^E1wP-O1KO$+s|M;htu0PVX`bBjFWeU1 z$zlUXkY=5&YI%gQPrd><4Hl`Xv)PuvlVuK^-0}>!lh+|{>^Amq(LB~0o6UMrXNsb; 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zZhSz}_gj(S&rb?(Poh`j-99pETt)T5RZmlSr28ef*7Vgn^b3B0pw{mcnJiWnWb{4< z(JTF{_3Aez{US0h%cbYi3lPkr(&V#RQNbN z1XJ>>`N-yoz^D^W{FzMuC&WDv=YOgtbgK{lmw@!+am}~s@%Bd u;P&BG_M_TmDxM@21HxGM +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_F_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x5e2 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_F_32_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x5e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_F_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_F_64_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x3f5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_F_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int); +typedef double (*pifsi)(double *, int); + +/* C compilette prototype */ +h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0002, immValueZero); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4f ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK; + float res32; + double res64; + pifii fPtr32; + pifsi fPtr64; + + + float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; + double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0); // Call generated code + if (f32[in0] != res32) + resultOK ++; + PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); + printf ("res (32) f32[%d] = %f\n", in0, res32); + + /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ + /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ + /* res64 = fPtr64(f64, in0); // Call generated code */ + /* if (f64[in0] != res64) */ + /* resultOK ++; */ + /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ + /* printf ("res (64) f64[%d] = %f\n", in0, res64); */ + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-Ld-flt.power b/CodeExamples/Array-Ld-flt.power new file mode 100755 index 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index 0000000..4c1794b --- /dev/null +++ b/CodeExamples/Array-Ld-flt.power.c @@ -0,0 +1,895 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_LFS_RRI_F_32_1(r0,r1,i0) do /* r */ { power_G32(((0x30 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LFS_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int); +typedef double (*pifsi)(double *, int); + +/* C compilette prototype */ +h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x381F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = power_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4f ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK; + float res32; + double res64; + pifii fPtr32; + pifsi fPtr64; + + + float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; + double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0); // Call generated code + if (f32[in0] != res32) + resultOK ++; + PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); + printf ("res (32) f32[%d] = %f\n", in0, res32); + + /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ + /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ + /* res64 = fPtr64(f64, in0); // Call generated code */ + /* if (f64[in0] != res64) */ + /* resultOK ++; */ + /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ + /* printf ("res (64) f64[%d] = %f\n", in0, res64); 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z>3$%dF$0hHYl8#0TG@@~;7!QJc+(04@aX4(fNV~ji02ssGPLCFDxN0qL%A43=d??> zgU`VmT>v?>O4N15vc(f|Me literal 0 HcmV?d00001 diff --git a/CodeExamples/Array-Ld-flt.riscv.c b/CodeExamples/Array-Ld-flt.riscv.c new file mode 100644 index 0000000..db41554 --- /dev/null +++ b/CodeExamples/Array-Ld-flt.riscv.c @@ -0,0 +1,815 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32F_FLW_RRI_F_32_1(r2,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r2 & 0x1f) << 7)|((0x7 & 0x7f) >> 0)); } while(0); +#define RV64D_FLW_RRI_F_64_1(r2,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x3 & 0x7) << 12)|((r2 & 0x1f) << 7)|((0x7 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32F_FLW_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV64D_FLW_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int); +typedef double (*pifsi)(double *, int); + +/* C compilette prototype */ +h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF1F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4f ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK; + float res32; + double res64; + pifii fPtr32; + pifsi fPtr64; + + + float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; + double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0); // Call generated code + if (f32[in0] != res32) + resultOK ++; + PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); + printf ("res (32) f32[%d] = %f\n", in0, res32); + + /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ + /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ + /* res64 = fPtr64(f64, in0); // Call generated code */ + /* if (f64[in0] != res64) */ + /* resultOK ++; */ + /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ + /* printf ("res (64) f64[%d] = %f\n", in0, res64); */ + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-Ld.aarch64 b/CodeExamples/Array-Ld.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..a2a38992e0f9dbf96b355f1b03984d06fd75b0c9 GIT binary patch literal 43952 zcmc(I3w%`7o&ULW=aqLz!W-cxKt(hO4~rnUOcD@SP%*)3*S3>MGD)T;GjV33AZ!_w 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+#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifii)(int *, int); +typedef short (*pifsi)(short *, int); +typedef char (*pifci)(char *, int); + +/* C compilette prototype */ +h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 0, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0002, immValueZero); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4d ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; + short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions + res = fPtr32(a32, in0); // Call generated code + if (a32[in0] != res) + resultOK ++; + PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); + printf ("res (32) a32[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions + res = fPtr16(a16, in0); // Call generated code + PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); + if (a16[in0] != res) + resultOK ++; + printf ("res (16) a16[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions + res = fPtr8(a8, in0); // Call generated code + if (a8[in0] != res) + resultOK ++; + PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); + printf ("res (8) a8[%d] = %d\n", in0, res); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-Ld.power b/CodeExamples/Array-Ld.power new file mode 100755 index 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zV~3=Kt};l0WP4sulfR$8p+m37j@6u`jt!^Df66H&zoiD2RFj-P6O3dYiGCqha9c+k zmTO3srMH=hmyF-L1wvB!F`gM0m0!^hAfUoZhUmgMg1aUuF)7N5!ARy&{?1DTH%<}L zk&Hh{B|*fchh+X^baTT|gtHN+>OabV)9+D|AOeT6$BIPxKUR*PbH~?}<_D?r-+7J5 MPp_hykEAI3|N55}kN^Mx literal 0 HcmV?d00001 diff --git a/CodeExamples/Array-Ld.power.c b/CodeExamples/Array-Ld.power.c new file mode 100644 index 0000000..11e0390 --- /dev/null +++ b/CodeExamples/Array-Ld.power.c @@ -0,0 +1,882 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifii)(int *, int); +typedef short (*pifsi)(short *, int); +typedef char (*pifci)(char *, int); + +/* C compilette prototype */ +h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 3, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x781F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = power_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4d ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; + short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions + res = fPtr32(a32, in0); // Call generated code + if (a32[in0] != res) + resultOK ++; + PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); + printf ("res (32) a32[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions + res = fPtr16(a16, in0); // Call generated code + PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); + if (a16[in0] != res) + resultOK ++; + printf ("res (16) a16[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions + res = fPtr8(a8, in0); // Call generated code + if (a8[in0] != res) + resultOK ++; + PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); + printf ("res (8) a8[%d] = %d\n", in0, res); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-Ld.riscv b/CodeExamples/Array-Ld.riscv new file mode 100755 index 0000000000000000000000000000000000000000..6785e5c7406b813e93dffc28b3461b6e4e53cd62 GIT binary patch literal 33248 zcmeHw3s@9Kwtx3@!=MmE(U|8tGSCn%j*3|~=AnRt$i}EqlWhKX^Nk1t@+~iCFq`Bi z8+8WJyfjNTYC@th1dZ`Q)TlAWpiV@ML1NGlmnc4>#uy>mfGCgu?^JisjHoDH@AuvN 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pMV|MroaB4T6Jts!^<$woxwRZ-v_qQ>r;c2i>dKQrIy8({z!j}M3 z{d5GO{%F8sy~;-b?h(&(^!ymnKMHs>_8#aNI)a}Doa3dRWWW=>=%)gveQ-Lu>o8w? zIRaiD7=1|7l+A@c_ut(z&d7$>nU;g=@s+N=$+ld3?$p#&T!>Swc*2}L0&mI9v?OCi zVYS02Ov%>1!I_eqZG+Q1^*Ii{R8EF9*P4P|?ki$gQqi0x$!1G>-hx%3?RhTM24CEg zGBq>vd60NPSYoB;UV<7+Wc@~^n3#tG&L&3#$)1&*cvg_Do9-tK6RStkvQHS+h^#)1}!qJbBM5pfA@dIZvgh z#-k1?1#>Y?4D9}c#&1!{c?6a#e?$4zT z(mu!PopssQSUrXJD|aL;_yqzU-nV#x<40NOgR61l$E*A+A8z%KqSVS3MHb6=bL@mz zOI&K-nCoR#+w_wLvpVbm+_sdaqXcx!GV3=Chi&5BJ)0jnwYY|G@NtQ0Jim0r7~vP%~< zuw7q%3^!SOeLnl2$Znk_{%SLbR=+rJ*J*N!jQh z8=Kd!=X5ua=qiBAhWh<*<=f#Jt#XCnI3qIX-YDUbUpyZL2BftEmlJmU5ocQM5Z(sh zkzYnWkg@_I-%1H|XRrbHPzjH%n~?Y`lI`(m%bHd!_(fZ+&q zi6uO`4;%&HU8J>xaOrpyf$rfF9<9H20FPD^TDz1_;V%eu&zI7)E;|Oi0Z4nd3lQH# zR(Oa*OzSne8{tHn>Z4T<@keWk3sthL*Q3@uG%J0`-Pq=b5C?b5EjH{Kmd__>2NIDo5_-PI27|D|%=Vy(~%FQOe@ zGX_k;74T?%N!gmb!*R1g``$URNM#g;wZj{k1v#idJv2Ou+1OC?=hFfl6IfqF@d(s! lK?t<70{yv<`Ok9Pbgfg7t5r=qAl`U);?~I+t +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifii)(int *, int); +typedef short (*pifsi)(short *, int); +typedef char (*pifci)(char *, int); + +/* C compilette prototype */ +h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 2 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genR_3(tmp0002, tmp0001, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%4d ", ARRAY[i]); \ + } \ + printf ("\n"); + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; + short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; + char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + resultOK = 0; + printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions + res = fPtr32(a32, in0); // Call generated code + if (a32[in0] != res) + resultOK ++; + PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); + printf ("res (32) a32[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions + res = fPtr16(a16, in0); // Call generated code + PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); + if (a16[in0] != res) + resultOK ++; + printf ("res (16) a16[%d] = %d\n", in0, res); + + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions + res = fPtr8(a8, in0); // Call generated code + if (a8[in0] != res) + resultOK ++; + PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); + printf ("res (8) a8[%d] = %d\n", in0, res); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-Mult-Specialization.aarch64 b/CodeExamples/Array-Mult-Specialization.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..5f29e67b077e9bbe10576173bf02cfc097a84fde GIT binary patch literal 48416 zcmc(I3t&{$ng6+SXOhYLDNltP9zM_{5EMbNOcD`UP%z+Y-G3*O$t0N)X5!2QgU~XF zZQ0@~v*2SFm7w)sgWZ-@yPE2*LF~3&Y^4QT{_AUkb<0+}rQjeK?$47vY3NSV^diM zAXeNC9z(A1Dfe^9TDf+Kr^6+>xfTJKYjJRoawiHfQ?8PbT$_v&jzflo`|{UCP`Qlf zMm$N@qcZ;J*Q+_Aa-WuR*hw&ci4+M;be~JQ&n2C5qf#*Cs{B#j=w2!LuCzE1qOgM; zX7FdfOSp6`{~**zetQQG!gX+ua;M4kl&k1&0v*XY+^bL`*2(nJ>1CXhU%4`QR@v%p zsBCR4Z}s}xJIY96Zd1W;O#{C$ z4V-wS;^RmIUk-Q?8^^YWtKkzi#XX)5Z-}*d0s()3wY7(W^l-Ph0?gg&cdufu27dtY z0k1FA#N4h{09msq)aGjT1ig2A*y^@`Kjd+T*lH0M3^jrmYq~4o4SAR=tg|zuhGAn5typR9JXlb;+k4#RmH3;f!(~??~~Y0h-ew`mkgtPX!u(X zSJmH#BM-rZEbLnpi7UE6blJY zr#47k^(MG#FDS0X1UI)$Z6-LiQR?b2!ByE&oO7D~=BahBbe+;!q=B*Rr`GL#x<_~Z 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zI@dz-w8{SEX$hx|I;2n4KT7qmy8%zdALkx9pXEy&oCDvV4_`#$C)cmXBz{|)z~}qo zf&T=Da~27Y=OzB!YJnd`n6B60lAKQ`mHRIxe%SBecuGIC*NF1Fd4hoR^BKT6D&bGd zdOed<;b1%QN4Y1KYB=Pae81R9Ykp@0n@_EhW;6(iF0elP6;NL=WS_Y0+ z&8x%H8qKT1{5`OrO~Y%4#N}PSmg~oQUu&!LE{|)Kv&qK*^Hl&A2n9p!O-)#+Z1mtn zBR_)a46Vj0q~GVE<-bP1v$@sZ;A(X?V&NXk>FphIO*7g#E*j$9W?(IA z3SgDq+1S2%^;(daLWwJDgvyVtmD6Fj@)d0!H(m{R@8+k@D&(pugl(w;UC_5kob$wr zHUM<;6M&Uoyf{Fx)!$qt@Vp_M%8S29nBH)IaC;XRH&V1^93e%%lZiiKk24zCW-uxR-Yd!V za&B(TD?FjadnZM)75f=J>T5#_}zyjc;q0>?yC2g9a@X5|gFvew{)tRUj$-DJ)a@<=ZT%^(y%S`$H_ zj*pw;Sw(Q|>X54eZYUt!7UhFodGL0)g6}!0u3218FW@ThPPC%M6>MP@jca`%7H%jY zV&s9^gn$!qc-`hA0_kgO4Y3NY_ll6G1AhM6q$1$wHKM}PBAZEiw-*ly3emI*3gri5 zyj#Z0yk<)y-%3AR?y#8$y*i(IY?$;v0WH~%qF3)RK9}@SnSW(pDqUpbGCT=O7}?^yXdI4lU#r7zj>Lkq-9$*<;9TP1zH zLX@sbSAl;I56M4M0i>(wljmGgot%bHkKtA@Ny?o)VG-Jz6q%f#7|@bXIHBVnL4Qq_ zaMd#zHwS=Z7~y_>i=g;GDMm6##vPxAzTp8uU{MWU8v5yyK3RW_+XcbP%J7otl^iqE zq;KpH1ax%Gd?`8wyE+a1vBw0)R)r|tWc?Grq$D_I_;E= +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include + +typedef int (*pifi)(int *); +pifi genMulArray(pifi ptr, int b, int len) +{ + /* Code Generation of 12 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0701, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + l = aarch64_genMV_3(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, l); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = aarch64_genMUL_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0003 = aarch64_genADD_3(tmp0003, a, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = aarch64_genMUL_3(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0005 = aarch64_genADD_3(tmp0005, a, tmp0004); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = aarch64_genR_3(tmp0006, tmp0005, immValueZero); + tmp0007 = aarch64_genMUL_3(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + aarch64_genW_3(tmp0003, tmp0007, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +void printArray(int * array, int len) +{ + printf ("Array values (%d) : ", len); + for (int i = 0; i < len; i++) + printf ("%d ", array[i]); + printf ("\n"); +} + +void mulArray(int * array, int len, int value) +{ + for (int i = 0; i < len; i++) + array[i] = array[i] * value; +} + +int main(int argc, char * argv[]) +{ + int arrayLen, mulValue, i, resultOK; + pifi fPtr; + int *array1, *array2; + clock_t startC, stopC, startHg, stopHg; + + if (argc < 3) + { + printf("Give 2 values (array len & mult. coefficient )\n"); + exit(-1); + } + arrayLen = atoi (argv[1]); // Get the + mulValue = atoi (argv[2]); + array1 = calloc (arrayLen, sizeof (int)); + array2 = calloc (arrayLen, sizeof (int)); + for (i = 0; i < arrayLen; i++) + { + array1[i] = random () % 100; + array2[i] = array1[i]; + } + printArray (array1, arrayLen); + printf("// Multiply an array with a constant value\n"); + printf("// Array len = %d constant value %d\n", arrayLen, mulValue); + // Allocate memory for 1024 instructions, generate kernel + fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); + startHg = clock(); + fPtr(array1); // Call generated code + stopHg = clock(); + printArray (array1, arrayLen); + resultOK = 0; + startC = clock(); + mulArray (array2, arrayLen, mulValue); + stopC = clock(); + printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); + for (int i = 0; i < arrayLen; i++) + { + if (array2[i] != array1[i]) + { + printf("Erreur multiplication!\n"); + resultOK = -1; + break; + } + } + return resultOK; +} diff --git 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b/CodeExamples/Array-Mult-Specialization.power.c new file mode 100644 index 0000000..10fa011 --- /dev/null +++ b/CodeExamples/Array-Mult-Specialization.power.c @@ -0,0 +1,1052 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genBGE_1(h2_sValue_t P0); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include + +typedef int (*pifi)(int *); +pifi genMulArray(pifi ptr, int b, int len) +{ + /* Code Generation of 12 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF80F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + l = power_genMV_2(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, l); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = power_genMUL_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0003 = power_genADD_3(tmp0003, a, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = power_genMUL_3(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0005 = power_genADD_3(tmp0005, a, tmp0004); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = power_genR_3(tmp0006, tmp0005, immValueZero); + tmp0007 = power_genMUL_3(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + power_genW_3(tmp0003, tmp0007, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +void printArray(int * array, int len) +{ + printf ("Array values (%d) : ", len); + for (int i = 0; i < len; i++) + printf ("%d ", array[i]); + printf ("\n"); +} + +void mulArray(int * array, int len, int value) +{ + for (int i = 0; i < len; i++) + array[i] = array[i] * value; +} + +int main(int argc, char * argv[]) +{ + int arrayLen, mulValue, i, resultOK; + pifi fPtr; + int *array1, *array2; + clock_t startC, stopC, startHg, stopHg; + + if (argc < 3) + { + printf("Give 2 values (array len & mult. coefficient )\n"); + exit(-1); + } + arrayLen = atoi (argv[1]); // Get the + mulValue = atoi (argv[2]); + array1 = calloc (arrayLen, sizeof (int)); + array2 = calloc (arrayLen, sizeof (int)); + for (i = 0; i < arrayLen; i++) + { + array1[i] = random () % 100; + array2[i] = array1[i]; + } + printArray (array1, arrayLen); + printf("// Multiply an array with a constant value\n"); + printf("// Array len = %d constant value %d\n", arrayLen, mulValue); + // Allocate memory for 1024 instructions, generate kernel + fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); + startHg = clock(); + fPtr(array1); // Call generated code + stopHg = clock(); + printArray (array1, arrayLen); + resultOK = 0; + startC = clock(); + mulArray (array2, arrayLen, mulValue); + stopC = clock(); + printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); + for (int i = 0; i < arrayLen; i++) + { + if (array2[i] != array1[i]) + { + printf("Erreur multiplication!\n"); + resultOK = -1; + break; + } + } + return resultOK; +} diff --git a/CodeExamples/Array-Mult-Specialization.riscv b/CodeExamples/Array-Mult-Specialization.riscv new file mode 100755 index 0000000000000000000000000000000000000000..4aa1d4f2ecd1180a921acc40650398f5b9311358 GIT binary patch literal 37596 zcmeHw3tUuX-v607hl@anqG`8vWZ*dQ;&`hzZBxWSWY^SHt8L%icOn>(ceyz;UbhsT z;i8$EnvzRKgh*s+YU;XXXp^X!k(rrmikH;P1nnqdT>jtRbIutCM4+P2=ly*Cd-R#- z`90_NdoJJS`&`d3XHN9!ks6JLQ!g#|14ok1Tf;pBKj9^g^Md~nr{nxM1E=RgIBzCX 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z@QX`DBdH=gKvQo$_nZ}6S0p;ZQNw^q4N^2((~23Ueb;?ZqZyT!GPJj|LkRIOm1kRy z(<6>{WTZ!XfLz?rA*^1Q%Giae49AzU-gfBGcjefVJ^40UJCH6t1-*gi$CMuJ5d#pQ z{eiqIr1hrk=y)D8qg+1d*~tKDddnWuqxpCQ9F_sH9`=-W2pb@)7fjgo2Yk}=Yf6Up zn)GBuhp?J2#gqFJ96j%*FzrE2(Cd$|XTA`*L^vvI6dXM>r!_}0!jxV&IJ!ssreruO z1KI1aM$wUiS||jm4&kLPFv^NX5gWfLOCrn6>_8dXbt5V|Nv9x^Qm%&jzNRO?3)3FAluyUzo zrN_sr9<9;thn`7Qg0GhEu!kP4jh}^{e3Bq5tLf1*X3C%Pr8Q?V^eBDxQp2YZq3Y4z zl=LE1CFLH8=itbuKMA-k4~IN)SH5N=M9(JFOU;)aKd524cMN*tR3-RS zCc5Yeg{PhYgp5)<2kxu)?ro;`ztcFbK)vaqhvlu?hSCq1f$wCrphtUaitbNJxF*a* zA8M8_-5=IW?@!poj-wmOMM2e3-%zh&bcA#aV7(C$4M*)31lI|UaRokIJ+nEkPHj}k UYSMJt +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include + +typedef int (*pifi)(int *); +pifi genMulArray(pifi ptr, int b, int len) +{ + /* Code Generation of 11 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x77F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + l = riscv_genMV_2(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGE_3(i, l, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = riscv_genMUL_4(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0003 = riscv_genADD_3(tmp0003, a, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = riscv_genMUL_4(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0005 = riscv_genADD_3(tmp0005, a, tmp0004); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = riscv_genR_3(tmp0006, tmp0005, immValueZero); + tmp0007 = riscv_genMUL_4(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + riscv_genW_3(tmp0003, tmp0007, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001]; + i = riscv_genBGE_3(i, l, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +void printArray(int * array, int len) +{ + printf ("Array values (%d) : ", len); + for (int i = 0; i < len; i++) + printf ("%d ", array[i]); + printf ("\n"); +} + +void mulArray(int * array, int len, int value) +{ + for (int i = 0; i < len; i++) + array[i] = array[i] * value; +} + +int main(int argc, char * argv[]) +{ + int arrayLen, mulValue, i, resultOK; + pifi fPtr; + int *array1, *array2; + clock_t startC, stopC, startHg, stopHg; + + if (argc < 3) + { + printf("Give 2 values (array len & mult. coefficient )\n"); + exit(-1); + } + arrayLen = atoi (argv[1]); // Get the + mulValue = atoi (argv[2]); + array1 = calloc (arrayLen, sizeof (int)); + array2 = calloc (arrayLen, sizeof (int)); + for (i = 0; i < arrayLen; i++) + { + array1[i] = random () % 100; + array2[i] = array1[i]; + } + printArray (array1, arrayLen); + printf("// Multiply an array with a constant value\n"); + printf("// Array len = %d constant value %d\n", arrayLen, mulValue); + // Allocate memory for 1024 instructions, generate kernel + fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); + startHg = clock(); + fPtr(array1); // Call generated code + stopHg = clock(); + printArray (array1, arrayLen); + resultOK = 0; + startC = clock(); + mulArray (array2, arrayLen, mulValue); + stopC = clock(); + printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); + for (int i = 0; i < arrayLen; i++) + { + if (array2[i] != array1[i]) + { + printf("Erreur multiplication!\n"); + resultOK = -1; + break; + } + } + return resultOK; +} diff --git a/CodeExamples/Array-St-flt.aarch64 b/CodeExamples/Array-St-flt.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..d2163ddebe7e345e7e3693996edcc83b6672f8a7 GIT binary patch literal 48112 zcmeHw3w)H-nfH0;ok=G5kVHVB@FqY-GzkPnP%LiySGGIsoX3WG6|En`{u z&SP^~2EcZ_3eS{2<(`nNmFtvjbV;|&CIHK9Cif_JrT{bLDhbJT$T;DcG9=vQfCws= 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zDB@0ctB2N!tzcL*He2K(GB=#oI!|aFEepF`tsQ<}OdG%q`dw{qUo)2J-Hq5cN#K*X zmtm0xSG922txM>gU7=tCb-Xnh4lpl<- zd5YbtRzG;*Q^6Au%uoqf1@>Ax&@4h&Ph(dr=x9p?a1rD?9V)7^F@RbiL$tN2{LqW? zVslJ+B_~UN^hv$6VnlsAhG+a)W;3PBogphqY8)V9#fg_p1QdO}&E!$_5@7I9{DW>V z;W-~6IyR{2x7bXC@VhAqP~#NBp+}9M6(2g6gsUF>ivEzz1cZKv#T_7DEbpNlSiG9fUwLk&OLHHDf;Ogi?JHG=)z<4>i1rBFAP21!ijy8^|u}|Sc8tq zuhwU?Wrht&sq(MnRPHs1r{8L+uv*7mltiB_zhui=;UQ5Ky;|?xBug1qp(0PptQ@CbgkbMndYx-)xVczuuu_Os!*{uS9UD7N4tM%<=l0LRmCkd4P z6g}=uV=Qw+i};vxKX@ z$+$THB*O@|;|@XbN2M6aAQ_j|OOs)QTKi2wU{eiW8v6N?K3RYDdj-Ldl;I`Ot27s- zNx$$uK|nvvvObDV!7fTeA9+Av>{f` +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_F_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_F_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STUR_RRI_F_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_F_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STUR_RRI_F_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_F_128_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1e4 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_F_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_F_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_F_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STUR_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STUR_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 128) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_F_128_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int, float); +typedef double (*pifsi)(double *, int, double); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + aarch64_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != (float) i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%2.2f ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK, loopLimit; + float in132, res32; + double in164, res64; + pifii fPtr32; + pifsi fPtr64; + + float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + + in0 = atoi (argv[1]); // Get index value + in164 = in132 = atof (argv[2]); // fp number to store + resultOK = 0; + loopLimit = sizeof(f32) / sizeof (float); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0, in132); // Call generated code + printf("%2.2f, %2.2f\n", f32[in0], in132); + CHECK (f32, in0, resultOK, loopLimit, in132); + PRINTARRAY("32 bits : ", f32, loopLimit); + printf ("ResultOK %d\n", resultOK); + + loopLimit = sizeof(f64) / sizeof (double); + fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions + res64 = fPtr64(f64, in0, in164); // Call generated code + printf("%2.2f, %2.2f\n", f64[in0], in164); + CHECK (f64, in0, resultOK, loopLimit, in164); + PRINTARRAY("64 bits : ", f64, loopLimit); + printf ("ResultOK %d\n", resultOK); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-St-flt.power b/CodeExamples/Array-St-flt.power new file mode 100755 index 0000000000000000000000000000000000000000..652c5e42a177b7c559ea7c32694a4c39e52b9183 GIT binary patch literal 78544 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// int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_STFS_RRI_F_32_1(r1,r0,i0) do /* w */ { power_G32(((0x34 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STFD_RRI_F_64_1(r1,r0,i0) do /* w */ { power_G32(((0x36 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STFS_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STFD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int, float); +typedef double (*pifsi)(double *, int, double); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x381F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = power_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + power_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != (float) i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%2.2f ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK, loopLimit; + float in132, res32; + double in164, res64; + pifii fPtr32; + pifsi fPtr64; + + float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + + in0 = atoi (argv[1]); // Get index value + in164 = in132 = atof (argv[2]); // fp number to store + resultOK = 0; + loopLimit = sizeof(f32) / sizeof (float); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0, in132); // Call generated code + printf("%2.2f, %2.2f\n", f32[in0], in132); + CHECK (f32, in0, resultOK, loopLimit, in132); + PRINTARRAY("32 bits : ", f32, loopLimit); + printf ("ResultOK %d\n", resultOK); + + loopLimit = sizeof(f64) / sizeof (double); + fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions + res64 = fPtr64(f64, in0, in164); // Call generated code + printf("%2.2f, %2.2f\n", f64[in0], in164); + CHECK (f64, in0, resultOK, loopLimit, in164); + PRINTARRAY("64 bits : ", f64, loopLimit); + printf ("ResultOK %d\n", resultOK); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-St-flt.riscv b/CodeExamples/Array-St-flt.riscv new file mode 100755 index 0000000000000000000000000000000000000000..29fa139cbb89c72cecd6d6422cdbca563d5e9e38 GIT binary patch literal 33332 zcmeHw3tUvy+V|eGHw+3PhGuss1~$YCqhfWs8sZ>QCLXmqeedZvA`HlPxXBD-+t_@Aqr# znzf#_o@cG+dG>#;z1G^By{9CO9M1DRryV-(7mlbVKc2e}@!CIgoFC%*I0M&{i{gx2 z80XJu$|D}0i-!OO5&0AZ1UqOu>ZK3{ngW#}o67TF9*=~2j8$W;oOqOjQaooK!?8em za3M+^q6PKk@hqf+Z5aaTMddn*P#%JE3N4^1P`Re#Jn+whZWIj2r=XRM{=uFe^%TcN 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h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32F_FSW_RRI_F_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x27 & 0x7f) >> 0)); } while(0); +#define RV64D_FSW_RRI_F_64_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x3 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x27 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32F_FSW_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV64D_FSW_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef float (*pifii)(float *, int, float); +typedef double (*pifsi)(double *, int, double); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF1F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + riscv_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != (float) i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf("%2.2f ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resultOK, loopLimit; + float in132, res32; + double in164, res64; + pifii fPtr32; + pifsi fPtr64; + + float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + + in0 = atoi (argv[1]); // Get index value + in164 = in132 = atof (argv[2]); // fp number to store + resultOK = 0; + loopLimit = sizeof(f32) / sizeof (float); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions + res32 = fPtr32(f32, in0, in132); // Call generated code + printf("%2.2f, %2.2f\n", f32[in0], in132); + CHECK (f32, in0, resultOK, loopLimit, in132); + PRINTARRAY("32 bits : ", f32, loopLimit); + printf ("ResultOK %d\n", resultOK); + + loopLimit = sizeof(f64) / sizeof (double); + fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions + res64 = fPtr64(f64, in0, in164); // Call generated code + printf("%2.2f, %2.2f\n", f64[in0], in164); + CHECK (f64, in0, resultOK, loopLimit, in164); + PRINTARRAY("64 bits : ", f64, loopLimit); + printf ("ResultOK %d\n", resultOK); + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Array-St.aarch64 b/CodeExamples/Array-St.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..46f3931aa6143e3c437560d01afc4c63e1c579c4 GIT binary patch literal 48056 zcmeHw3w%`7x$oMu=aqLzBJaXZfP!ceK#QPwm?R)lQ81xOkKRru$t0N)X2Q$_gU~Xl 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Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifli)(long int *, int, long int); +typedef int (*pifii)(int *, int, int); +typedef int (*pifsi)(short *, int, short); +typedef int (*pifci)(char *, int, char); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0107, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + aarch64_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf(" %2d ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK, loopLimit; + pifli fPtr64; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + + if (argc < 2) + { + printf("Give 1 value\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); + resultOK = 0; + + long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a64) / sizeof (long int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions + res = fPtr64(a64, in0, 42); // Call generated code + CHECK (a64, in0, resultOK, loopLimit, 42); + PRINTARRAY("64 bits : ", a64, loopLimit); + + int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a32) / sizeof (int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions + res = fPtr32(a32, in0, 42); // Call generated code + CHECK (a32, in0, resultOK, loopLimit, 42); + PRINTARRAY("32 bits : ", a32, loopLimit); + + short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a16) / sizeof (short); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions + res = fPtr16(a16, in0, 42); // Call generated code + PRINTARRAY("16 bits : ", a16, loopLimit); + CHECK (a16, in0, resultOK, loopLimit, 42); + + char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a8) / sizeof (char); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions + res = fPtr8(a8, in0, 42); // Call generated code + CHECK (a8, in0, resultOK, loopLimit, 42); + PRINTARRAY("8 bits : ", a8, loopLimit); + + if (resultOK != 0) + return -1; + return 0; +} diff --git a/CodeExamples/Array-St.power b/CodeExamples/Array-St.power new file mode 100755 index 0000000000000000000000000000000000000000..6965a9b9ef372956b4fbb5adc0aee89a3dbfcda2 GIT binary patch literal 78304 zcmeHw3w&JFdFQz^BWYyG^7w%<3Be<!R0Sk zG%lorA|ML!dyTkSPa}LSsUn8WWo)|dI2(2P|_nW;dF%-2AUoc=IJsG zBt6m!HfgMZQW_zD*;oHNs@(sMCFu=pVTW)X*HG0Eg56`ipsp9x^$hIO9W&6#N7;C9 z)bat!_6+o+jF(^jDq1G%ewJ)xz1PF408rL5@HvGR29lQ7Cs2?5oam*LCBzopUM{_y z)%`b6iz^njMt3e-x~R2r+0x2Hd*u?g%f65=Y1VJrj$a||JVmC|57j#j_f*`(m*BQv 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fscOI23_OV)-B+#;vekd}qpCh%eYIa1S@C}Wt?;%2 literal 0 HcmV?d00001 diff --git a/CodeExamples/Array-St.power.c b/CodeExamples/Array-St.power.c new file mode 100644 index 0000000..a90192b --- /dev/null +++ b/CodeExamples/Array-St.power.c @@ -0,0 +1,909 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifli)(long int *, int, long int); +typedef int (*pifii)(int *, int, int); +typedef int (*pifsi)(short *, int, short); +typedef int (*pifci)(char *, int, char); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 5, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x383F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); + tmp0001 = power_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + power_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf(" %2d ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK, loopLimit; + pifli fPtr64; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + + if (argc < 2) + { + printf("Give 1 value\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); + resultOK = 0; + + long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a64) / sizeof (long int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions + res = fPtr64(a64, in0, 42); // Call generated code + CHECK (a64, in0, resultOK, loopLimit, 42); + PRINTARRAY("64 bits : ", a64, loopLimit); + + int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a32) / sizeof (int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions + res = fPtr32(a32, in0, 42); // Call generated code + CHECK (a32, in0, resultOK, loopLimit, 42); + PRINTARRAY("32 bits : ", a32, loopLimit); + + short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a16) / sizeof (short); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions + res = fPtr16(a16, in0, 42); // Call generated code + PRINTARRAY("16 bits : ", a16, loopLimit); + CHECK (a16, in0, resultOK, loopLimit, 42); + + char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a8) / sizeof (char); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions + res = fPtr8(a8, in0, 42); // Call generated code + CHECK (a8, in0, resultOK, loopLimit, 42); + PRINTARRAY("8 bits : ", a8, loopLimit); + + if (resultOK != 0) + return -1; + return 0; +} diff --git a/CodeExamples/Array-St.riscv b/CodeExamples/Array-St.riscv new file mode 100755 index 0000000000000000000000000000000000000000..a53c8cb343de46718a54e0f720fbbacecf9a567c GIT binary patch literal 33256 zcmeHwdt6l2+W+3OH_Rx6D4Jc5BLf@a;CSnF%1#P6h@4D4YIXX(^%)UH7>md+D$ujQj5xnkj#j@pqUx!BzOsl(8xndYHDVJwgFKtzwfj5-otnoU*FH?{iCgG z)_T@@p0(EVtnXTTt+f|>KNml44A1kNcImiZIifQCcapq;j^nDv z@yyjBjhvSL7o>x{=%V~lJU0pHzV&NE966FlvE1PFv}uFWQwF7{Wz2qRP*$2F`N`qK z2BoEE4j-0ccG%5BRbI-A_!GuIj9;Z4C=a^G#y7$BfTMB);phs0BOU`>PdK_L53(KE zh2*qLj{wn>PBKJuV%$(&%>1=;C<9J(X=#*K@PFt1W807OBkugei;j&a7wuU8`@i)Y z`Onw?@u!dOyXlsH_RQ%#;qIIDr`P^r9{)h|>P7c|Lpk_fR9_CbqN@+w6u2QiG^ND& z(7yv+C3f*Y1iI0Oz7=$^5C88$8-3^npt+|M`C#r;CzUzXCtU(v=9Awr(DgpF1@uH8 zelFGK%uGtPInti7ahbE74ldJ{m1WQ3Y)_>*DI$4BQWlrww5M@1lhV`e$(+@SrcSmx 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unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 1 pointer, an index and return int */ +typedef int (*pifli)(long int *, int, long int); +typedef int (*pifii)(int *, int, int); +typedef int (*pifsi)(short *, int, short); +typedef int (*pifci)(char *, int, char); + +/* C compilette prototype */ +h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 12, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1F1F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + riscv_genW_3(tmp0001, value, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ + for (int i = 0; i < LIMIT; i++) \ + { \ + if (INDICE == i) \ + { \ + if (ARRAY[INDICE] != VALUE) \ + { \ + RESULT ++; \ + } \ + } \ + else \ + { \ + if (ARRAY[i] != i) \ + { \ + RESULT ++; \ + } \ + } \ + } + +#define PRINTARRAY(MSG, ARRAY, LIMIT)\ + printf (MSG); \ + for (int i = 0; i < LIMIT; i++) \ + { \ + printf(" %2d ", ARRAY[i]); \ + } \ + printf ("\n"); + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK, loopLimit; + pifli fPtr64; + pifii fPtr32; + pifsi fPtr16; + pifci fPtr8; + + + if (argc < 2) + { + printf("Give 1 value\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 + printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); + resultOK = 0; + + long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a64) / sizeof (long int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions + res = fPtr64(a64, in0, 42); // Call generated code + CHECK (a64, in0, resultOK, loopLimit, 42); + PRINTARRAY("64 bits : ", a64, loopLimit); + + int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a32) / sizeof (int); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions + res = fPtr32(a32, in0, 42); // Call generated code + CHECK (a32, in0, resultOK, loopLimit, 42); + PRINTARRAY("32 bits : ", a32, loopLimit); + + short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a16) / sizeof (short); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions + res = fPtr16(a16, in0, 42); // Call generated code + PRINTARRAY("16 bits : ", a16, loopLimit); + CHECK (a16, in0, resultOK, loopLimit, 42); + + char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + loopLimit = sizeof(a8) / sizeof (char); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions + res = fPtr8(a8, in0, 42); // Call generated code + CHECK (a8, in0, resultOK, loopLimit, 42); + PRINTARRAY("8 bits : ", a8, loopLimit); + + if (resultOK != 0) + return -1; + return 0; +} diff --git a/CodeExamples/Array-Sum-2D.aarch64 b/CodeExamples/Array-Sum-2D.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..2696a911a59ff2cf42f7e908bdd9b1c704fe4397 GIT binary patch literal 52312 zcmeHwe_&MAmH&P7W|B!JzevJwgb9cunuK5SL$FK|5Lpl~LB(~qlSwipS;8dDOf(29 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z66chH$un33c2erSMo7XH=0KZKaWa z$U}Q>Mv(eSjuA#hTUEvFWXe3o3Vdr<`&|`q{a)eLC?71ujV;##evqT6cws*6Y87Ck zv7pA~t6>FIYduITT)$Vu-0t@J@XelxfD>`p!*Wpq>1(L-vjVQ=0>8Tne!dq`;H~FI zUf`~gZ5wTvg+n5RXb(jSq5M=Qbl6{3>W#O)=6hdK=ewM8aGIE ze$plx0hNBa$-$#&+)kIBKf5029wV-+5u)RYDt(j5fe^jF#hvix0O8Q3#^;I-orl8b z4(e627>b3{ ztM|%ioJ80C!U;d4^|uHySo;q1uhxa%lj-T0H(iQ<#iw#tAdcP%Q(?7!jDv&xvI_@C zZzK7aU{(zeWu?-qb>;~&y&6xc{G;VxBhwd4f@(c_g-oE{gQMUO+|lXR0Y*9@{^(Nc z)>|b&=~=`IUX`ER+i@GytNG~xnf{Cs8UC!O@W!b0YCPReMvdzpIMLaWJIJ^Um(rgC;rnY5>DBuC(SH^gqlmcS ziq3y8;*9yLb^0@OJ{{NnQ3;~+{|Rt1a4R;|I>Tua3|BP13M;n_IJD-h(yMjZ^t4PL zPzj~0(kb_?sPt;xqGqc|5HEj4_9Q$+OYyJfJ54fuxk8k#%2$E^2oLc;Ndcs*(nrr# zr8;>ULOp|9!DLeIY?b+Mjf%`NBEe4^6HzD}!~TB+;!w9u_mq=hz4PTt}<7N72{mpw^B>06gyr}dlPx|ha@=Fxq>=zEb5@x)j zac9R#f0QaFE?EpBfM>M+iC$C|9Jl +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int(*pifpii)(int *, int, int); + +// Sum a 2D array with a constant +// Code specialisation on stride and constant value +pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ +{ + /* Code Generation of 22 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0F07, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + sum = aarch64_genMV_3(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = aarch64_genMV_3(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = aarch64_genCMP_2(line, nLine); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = aarch64_genMV_3(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = aarch64_genCMP_2(column, nColumn); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0003 = aarch64_genMUL_3(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}); + tmp0004 = aarch64_genADD_3(tmp0004, tmp0003, column); + if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); + tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = aarch64_genADD_3(tmp0006, a, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = aarch64_genADD_3(tmp0008, sum, tmp0007); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = aarch64_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = aarch64_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = aarch64_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, sum, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) +{ + int sum = 0; + for (int line = 0; line < nLine; line = line + 1) + for (int column = 0; column < nColumn; column = column + 1) + sum = sum + a[line][column] + constant; + return sum; +} + +int main(int argc, char * argv[]) +{ + pifpii ptr; + int in0, resultH, resultS; + int constant, nLine, nColumn; + + if (argc < 3) + { + printf ("./%s \n", argv[0]); + exit(-1); + } + nLine = atoi(argv[1]); + nColumn = atoi(argv[2]); + constant = atoi(argv[3]); + + printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); + int a32[nLine][nColumn]; // Create & fill the array + for (int line = 0; line < nLine; line++) + { + printf ("%d: ", line); + for (int column = 0; column < nColumn; column++) + { + a32[line][column] = line+column; + printf ("%d ", a32[line][column]); + } + printf ("\n"); + } + ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions + resultH = ptr((int *)a32, nLine, nColumn); // Call generated code + + resultS = sumArray(nLine, nColumn, a32, constant); + printf ("%d %d\n", resultH, resultS); + if (resultS == resultH) + return 0; + else + return -1; + +} diff --git a/CodeExamples/Array-Sum-2D.power b/CodeExamples/Array-Sum-2D.power new file mode 100755 index 0000000000000000000000000000000000000000..c8addeb9d750a8f9c08b247293f482866053ef8e GIT binary patch literal 78352 zcmeHw4}4VBmH&M+lVn0d7$9O)G=qRm*d&BM#X&$OAxHwKS%FG_tG~&R49V1F5+@TK zY$5|oTkPU)(t?ftu;7-uxIcAcm;IHxc8y)uMVEGwA8n~iC3LkrqpY9Usttei{l4e^ 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+#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBGE_1(h2_sValue_t P0); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int(*pifpii)(int *, int, int); + +// Sum a 2D array with a constant +// Code specialisation on stride and constant value +pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ +{ + /* Code Generation of 22 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1F83F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + sum = power_genMV_2(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = power_genMV_2(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = power_genCMP_2(line, nLine); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = power_genMV_2(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = power_genCMP_2(column, nColumn); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0003 = power_genMUL_3(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}); + tmp0004 = power_genADD_3(tmp0004, tmp0003, column); + if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); + tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = power_genADD_3(tmp0006, a, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = power_genADD_3(tmp0008, sum, tmp0007); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = power_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = power_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = power_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, sum); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) +{ + int sum = 0; + for (int line = 0; line < nLine; line = line + 1) + for (int column = 0; column < nColumn; column = column + 1) + sum = sum + a[line][column] + constant; + return sum; +} + +int main(int argc, char * argv[]) +{ + pifpii ptr; + int in0, resultH, resultS; + int constant, nLine, nColumn; + + if (argc < 3) + { + printf ("./%s \n", argv[0]); + exit(-1); + } + nLine = atoi(argv[1]); + nColumn = atoi(argv[2]); + constant = atoi(argv[3]); + + printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); + int a32[nLine][nColumn]; // Create & fill the array + for (int line = 0; line < nLine; line++) + { + printf ("%d: ", line); + for (int column = 0; column < nColumn; column++) + { + a32[line][column] = line+column; + printf ("%d ", a32[line][column]); + } + printf ("\n"); + } + ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions + resultH = ptr((int *)a32, nLine, nColumn); // Call generated code + + resultS = sumArray(nLine, nColumn, a32, constant); + printf ("%d %d\n", resultH, resultS); + if (resultS == resultH) + return 0; + else + return -1; + +} diff --git a/CodeExamples/Array-Sum-2D.riscv b/CodeExamples/Array-Sum-2D.riscv new file mode 100755 index 0000000000000000000000000000000000000000..80c5e7ead5d7ee0b2785ff843fead7681112aec0 GIT binary patch literal 41540 zcmeHweOy#k{{Nl11A`AChGlKFP7GWpzBnqjeXHFRaTMJ(b=9qHzgr{1h_pO4Gnl!i z=nPM0N@9q{8WAFq8mW=FW~h_+l#)wkW=d&dWnp$@d;)&&&$;)`3_bvB^m_gN=<1n! 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+#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int(*pifpii)(int *, int, int); + +// Sum a 2D array with a constant +// Code specialisation on stride and constant value +pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ +{ + /* Code Generation of 20 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1FFF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + sum = riscv_genMV_2(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = riscv_genMV_2(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = riscv_genBGE_3(line, nLine, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = riscv_genMV_2(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = riscv_genBGE_3(column, nColumn, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0003 = riscv_genMUL_4(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}, immValueZero); + tmp0004 = riscv_genADD_3(tmp0004, tmp0003, column); + if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); + tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = riscv_genADD_3(tmp0006, a, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = riscv_genADD_3(tmp0008, sum, tmp0007); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = riscv_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + column = riscv_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + line = riscv_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, sum); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005]; + line = riscv_genBGE_3(line, nLine, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000001]; + column = riscv_genBGE_3(column, nColumn, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) +{ + int sum = 0; + for (int line = 0; line < nLine; line = line + 1) + for (int column = 0; column < nColumn; column = column + 1) + sum = sum + a[line][column] + constant; + return sum; +} + +int main(int argc, char * argv[]) +{ + pifpii ptr; + int in0, resultH, resultS; + int constant, nLine, nColumn; + + if (argc < 3) + { + printf ("./%s \n", argv[0]); + exit(-1); + } + nLine = atoi(argv[1]); + nColumn = atoi(argv[2]); + constant = atoi(argv[3]); + + printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); + int a32[nLine][nColumn]; // Create & fill the array + for (int line = 0; line < nLine; line++) + { + printf ("%d: ", line); + for (int column = 0; column < nColumn; column++) + { + a32[line][column] = line+column; + printf ("%d ", a32[line][column]); + } + printf ("\n"); + } + ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions + resultH = ptr((int *)a32, nLine, nColumn); // Call generated code + + resultS = sumArray(nLine, nColumn, a32, constant); + printf ("%d %d\n", resultH, resultS); + if (resultS == resultH) + return 0; + else + return -1; + +} diff --git a/CodeExamples/CelciusFarenheit.aarch64 b/CodeExamples/CelciusFarenheit.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..3cc903f9dd5b16ccb2d95517dd25b29752bc1661 GIT binary patch literal 48128 zcmeHw3w&F}mG@j-$&%ks@&s}nClFF>Cjml2LL=J=X*PibJCx9NE6cWQt2mM)$sv&J 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b/CodeExamples/CelciusFarenheit.aarch64.c @@ -0,0 +1,1306 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genC2F(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); + tmp0001 = aarch64_genDIV_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + r = aarch64_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + if (!r.dontFree) h2_freeReg(tmp0001.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +h2_insn_t * genF2C(h2_insn_t * ptr) +{ + /* Code Generation of 4 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = aarch64_genMUL_3(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); + r = aarch64_genDIV_3(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); + if (!r.dontFree) h2_freeReg(tmp0000.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifi fC2F, fF2C; + + resultOK = 0; + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + printf("// Compilette for conversion from celcius to farenheit\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fC2F = (pifi) genC2F (ptr); // + res = fC2F(in0); // Call generated code + printf("%d (celcius) -> (farenheit)%d\n", in0, res); + if (res != (in0 * 9 / 5 + 32)) + resultOK += 1; + printf("// Compilette for conversion from farenheit to celcius\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fF2C = (pifi) genF2C (ptr); // + res = fF2C(in0); // Call generated code + printf("%d (farenheit) -> (celcius)%d\n", in0, res); + if (res != ((in0 - 32) * 5 / 9)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/CelciusFarenheit.power b/CodeExamples/CelciusFarenheit.power new file mode 100755 index 0000000000000000000000000000000000000000..da8d19922cdd6e1a180e5a93d5767b5a7f8aadbe GIT binary patch literal 78272 zcmeHw3wRvGm2UOSNE%rWj~^HT4sK(cNRIWeVa*t9G?Hao@(aZeaB|6xM$$+ckYU2+Q$Ex+KZJNf^VPh9C%6Xj3MK}*#=qM00 zHY7dF%`$PF$1Y>($U8U=7Xej04*Ml*1)YM7*#W7Zn-~hn>5=Dfnm{uJm4pP-WSIn< z9%&9cg957{29N>;xStEYN1ZxRK7yqHv~+wH^+?XK9-JwNH_7%=+2yp9 zUqRIm#m#}*rB@a=*Dt-YC>knSLhX_)#FuE+Y}|?~g0$qUZ~FWn&HIMPBQ!o;MG_(*IJi?erXDPbqf64 z6!_bK*KsBuWVd8;R;0jRoB}^R1->u^p84AXF&6emBB2Nix5lD$scZ5f6A1)k4Xn{0 z3;P=V(ZKC~))J0{V*a`qYwbjym#8csW&gk#54PIZ6fjCcN2?m6-4}2G!v< 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z0$!>wxij{%te-%}4oC`JRgeUU`n;W@em8&PhhDcG$~l1@>rYYtq*G9SPfaYzCb51x z5Q#V8wWdQZ0UKtlvU%^iyq0)+m;QW~ayDFhDA +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genC2F(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x780F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); + tmp0001 = power_genDIV_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + r = power_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + if (!r.dontFree) h2_freeReg(tmp0001.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +h2_insn_t * genF2C(h2_insn_t * ptr) +{ + /* Code Generation of 4 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x780F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = power_genMUL_3(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); + r = power_genDIV_3(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); + if (!r.dontFree) h2_freeReg(tmp0000.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifi fC2F, fF2C; + + resultOK = 0; + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + printf("// Compilette for conversion from celcius to farenheit\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fC2F = (pifi) genC2F (ptr); // + res = fC2F(in0); // Call generated code + printf("%d (celcius) -> (farenheit)%d\n", in0, res); + if (res != (in0 * 9 / 5 + 32)) + resultOK += 1; + printf("// Compilette for conversion from farenheit to celcius\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fF2C = (pifi) genF2C (ptr); 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H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genC2F(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x73F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}, immValueZero); + tmp0001 = riscv_genDIV_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}, immValueZero); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + r = riscv_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + if (!r.dontFree) h2_freeReg(tmp0001.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + +h2_insn_t * genF2C(h2_insn_t * ptr) +{ + /* Code Generation of 4 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x73F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = riscv_genMUL_4(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}, immValueZero); + r = riscv_genDIV_4(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}, immValueZero); + if (!r.dontFree) h2_freeReg(tmp0000.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, res, resultOK; + pifi fC2F, fF2C; + + resultOK = 0; + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + printf("// Compilette for conversion from celcius to farenheit\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fC2F = (pifi) genC2F (ptr); // + res = fC2F(in0); // Call generated code + printf("%d (celcius) -> (farenheit)%d\n", in0, res); + if (res != (in0 * 9 / 5 + 32)) + resultOK += 1; + printf("// Compilette for conversion from farenheit to celcius\n"); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fF2C = (pifi) genF2C (ptr); // + res = fF2C(in0); // Call generated code + printf("%d (farenheit) -> (celcius)%d\n", in0, res); + if (res != ((in0 - 32) * 5 / 9)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Constants-Operations.aarch64 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zp#XeI91KE-ss9m^h9b@CvWtN&MV^pcEw3)#!;GZFnyjQX`Fk_g}N#7PO6a;B=7srkD<66~RsIAx{IsP(XyODhA!~V#~FHKgdy4 zy{4RYwJNaDSkdYUwz7(*O@0&>VJIMSuJs1!>q!F=ZscJP%R>cZtg|h|D!5!LLf(yt z^Sy|QKnK_A3U8|%+i1fqo)RU*cqmG!I0$3I7CU4u9iW9v1+PF5Ll>|L?C-Q=2nDm= zhOQQrqir0(MUwBXsH}#D04zeLXggKKAr}?JhMbB@O4>bYEKypiqI*8vMSd)?xn#(L zK`U9xKM=X%Nt;Y0RC%>-MBmJz!{XP(1-Him#}|+yS5TGTXmcTj?(|+U!14styKA=HW$x2Dgmvs!Fb-1%Sn}2 z^XD4C;c~^xtM|$_NCt1`)Do9u`CW`GtbND%SL?!W$@27=HyzSlj@P63-GDrLCrqW) z`Z0Yciw=ul>CxMP{7W!vL4>MO<<&a#d|6)kO{)In_Fp5*S4)CwJ$i#Ipx%R{-66{>`KxvHC9-^eQUN7DMd0qF@@oD4qD=yW zo_p7iBy#K#WD<(1U#-)((z9_mnvx16*Z*DM$gxpbS+x6~3BOUhPY?c8db(>Q`hBBSN$k|7u>dQI@Y)h%!|5D)8?RA^sOC zfDBdnPcAI|A{7ED@?}GHwn4$uPqG ztNTTXx0PTdfn?n2Y06j2Em)fx_|lZ0C(9?xZ{?$+z)zIoC6!lv(D(OLT%w5J2@%jM zVfvAbyDUxl{bZOpWH*QeuF3KzdP!Aq-1@&4MS94%ag^co;#B&h#%1cBBoPCG +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(); + +pifi genConstAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstSub(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstMul(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genMUL_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstDiv(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genDIV_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, res; + int isOK = true; + pifi fPtr; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + + printf("// Compilette for simple addition between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstAdd (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d + %d = %d\n", 42, in0, res); + isOK &= (res == (42+in0)); + + printf("// Compilette for simple substraction between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstSub (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d - %d = %d\n", 42, in0, res); + isOK &= (res == (42 - in0)); + + printf("// Compilette for simple multiplication between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstMul (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d * %d = %d\n", 42, in0, res); + isOK &= (res == (42 * in0)); + + printf("// Compilette for simple division between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstDiv (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d / %d = %d\n", 42, in0, res); + isOK &= (res == (42 / in0)); + + return isOK?0:1; +} diff --git a/CodeExamples/Constants-Operations.power b/CodeExamples/Constants-Operations.power new file mode 100755 index 0000000000000000000000000000000000000000..24b1682f4dcd421f03e8efae3b955c4c93e19474 GIT binary patch literal 78360 zcmeHw4PaE&mH&M+lVn0d7$9K$eoS5_ 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+#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(); + +pifi genConstAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstSub(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstMul(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genMUL_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstDiv(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genDIV_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, res; + int isOK = true; + pifi fPtr; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + + printf("// Compilette for simple addition between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstAdd (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d + %d = %d\n", 42, in0, res); + isOK &= (res == (42+in0)); + + printf("// Compilette for simple substraction between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstSub (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d - %d = %d\n", 42, in0, res); + isOK &= (res == (42 - in0)); + + printf("// Compilette for simple multiplication between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstMul (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d * %d = %d\n", 42, in0, res); + isOK &= (res == (42 * in0)); + + printf("// Compilette for simple division between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstDiv (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d / %d = %d\n", 42, in0, res); + isOK &= (res == (42 / in0)); + + return isOK?0:1; +} diff --git a/CodeExamples/Constants-Operations.riscv b/CodeExamples/Constants-Operations.riscv new file mode 100755 index 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z%pQm(6`74~=7lABr`s$PuNoT&SjZ`*I#Y;>2Izl*Nrb{mlB&4pJH zqcxWmK$I7u@>XLk8hPZaB|Ms&FT?{K((VhdB7Xf8cUo}~9<9;ndn1~MDXTD=-zkB- zlNaH~B|P#W6TxFhw#TDwb6Q~$9~L;!yQ?7j$> zu3sXMADPOdHDC?!Xhq|$m+~q68v^;ADNSp`q)w0FG#SuO(cl!`#UYx0QLk*4zc zA<#2g&*ULc8;G9fw&i$0e7G;-fx-*~Hy+Jt=-az{$$g<-R32SVA`l+6kLF6t7vp;y z5`cQS@ty4)kE#)f55nVf z)C$F4P9R-wmdLH^#-q8_?ZCT_V<?fyWVuW)K0m2#@CK?u(vL_znSe7P<4yz$2f5`*PPyZUJ|i zp49+vf*T1jwTUkB9C+j1{4R9cJvi{({p{9uc>i9>7}U^nxszB%cxdQh^ZWQt!u=4i zJ9&?aH%KjE)CU+t?dm1m5$*8CKrtq`3sK7>kOGYj_qA{{6%|Z@j;L%=kK-Xy|g|{eQ3ZXbAuS literal 0 HcmV?d00001 diff --git a/CodeExamples/Constants-Operations.riscv.c b/CodeExamples/Constants-Operations.riscv.c new file mode 100644 index 0000000..8d7de02 --- /dev/null +++ b/CodeExamples/Constants-Operations.riscv.c @@ -0,0 +1,1025 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} + +/* End Header autogenerated part */ +#include // -*- c -*- +#include + +typedef int (*pifi)(); + +pifi genConstAdd(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x33F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstSub(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x33F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstMul(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x33F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genMUL_4(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +pifi genConstDiv(pifi ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x33F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genDIV_4(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (pifi) ptr; +} + +int main(int argc, char * argv[]) +{ + int in0, res; + int isOK = true; + pifi fPtr; + + if (argc < 2) + { + printf("Give 1 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in0 + fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions + + printf("// Compilette for simple addition between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstAdd (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d + %d = %d\n", 42, in0, res); + isOK &= (res == (42+in0)); + + printf("// Compilette for simple substraction between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstSub (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d - %d = %d\n", 42, in0, res); + isOK &= (res == (42 - in0)); + + printf("// Compilette for simple multiplication between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstMul (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d * %d = %d\n", 42, in0, res); + isOK &= (res == (42 * in0)); + + printf("// Compilette for simple division between constants\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = genConstDiv (fPtr, in0); // Generate instructions + res = fPtr(); // Call generated code + printf("%d / %d = %d\n", 42, in0, res); + isOK &= (res == (42 / in0)); + + return isOK?0:1; +} diff --git a/CodeExamples/If-in-Loop.aarch64 b/CodeExamples/If-in-Loop.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..7d24abd538baab0e56deefcc7b83b7db5c559bfe GIT binary patch literal 52344 zcmeHw34B}CmG^ymk}dC!ZL&flXMqr~odrTdLL=J=Ax$8`2}_6hD$BOKOdQEbatI`C z6atiCY2qdV+o#Ma@8QKo@KtCKpTRLQ>DG4oKTR={r&6Lhe2EyW!p!uJ>$XBu? z+wt=KzTb~$zjyCF_uO;OIrrS}aZ-k=93`pTXR_R9vYZOTk}(x3`A9Z8*GYQo zEKZ~-?WBM?__a4ATsqdgAFQMJYavQe=!^-c%lcHP%3X_c#OFYde2G{k>r1AW@sfWP z%IaBJb5l)Ob6rVulecwKiQDb3ZJd8eX~0)HN61a|33vH5*YTRDz0-M2TqvD~GaF|H z&K#Wjkt-8KgK$YUl9k$?=#ZW>ac1Ep7U`rigwORL80Fj(eBp=po{J#qLFfeua*0+V z__ayki<7{wPXfOn3H%#?J8;Gy69GuX59u!v{HsaejwEoRk%-Q`B=AbW$FT8i)6R0l zM7!{aXH!#MG;DqV9+ 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+#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_NE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr) +{ + /* Code Generation of 22 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0F01, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = aarch64_genDIV_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + reste = aarch64_genMUL_3(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + if (!reste.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, reste); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, res; + int i, tmp; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (LoopValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr); // Generate instructions + res = iPtr(selected); // Call generated code + printf ("Result %d : %d\n", selected, res); + for (i = 0; i < selected; i = i + 1) + { + if (i % 2) tmp = tmp + i; + } + + return tmp == res; +} diff --git a/CodeExamples/If-in-Loop.power b/CodeExamples/If-in-Loop.power new file mode 100755 index 0000000000000000000000000000000000000000..5f619834866535b5ae37302561bb6082b91ecbfe GIT binary patch literal 78384 zcmeHw4SZC`b?@9=eXNiW%ZIUS6LT@(N(2dk9kSS9BmqX^%ZdS;^toLv(n?xetQ2Ww zi$pSl&=xmN3k^%%LT~LhLRrl5>B+yLPISfVYE;jRuFtD%tE*jLJG{>IKXe`82`4XY>+j>8J-auko{N>sTLRZhb$C76aQfpFlavInqNi1@Y~wzEpNO ztK`>Ex5K=K$mWGN&TFVycwq&-R0=({v&QhyW&@W7ZuS|iT zkph1o@Fvd0gLX?M=kgTzt5e`7rN9@az>9EOBqo}|&CQL?qNz33!b^312sh1qG>&% zLFS?_S@!t99`}08GArMK*Zq)qzwk&_S0K&4qmMiXUJVtQWjgSBj4~tNfp_|`Vh5gm zP#*yYp5s6tB@Vn({&EMN<4Yfv4!mXY2Td6M>}X6Z4cmjSnjmdS&A}mJ&JZIfsG7d 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z5;7BRMLrOTIF@g^!p3&;#&IOtpHvAZlGNu_`QjYA@C<-ToVx#L|IOdiB$!ARFt4-g czgiDGi5)B}*9XbU-$cc5@Ksvpk#H;iKO>z1VgLXD literal 0 HcmV?d00001 diff --git a/CodeExamples/If-in-Loop.power.c b/CodeExamples/If-in-Loop.power.c new file mode 100644 index 0000000..8eabc2a --- /dev/null +++ b/CodeExamples/If-in-Loop.power.c @@ -0,0 +1,1172 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBNE_1(h2_sValue_t P0); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genBGE_1(h2_sValue_t P0); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BNE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr) +{ + /* Code Generation of 22 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1F80F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = power_genDIV_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + reste = power_genMUL_3(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + if (!reste.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, reste); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, res; + int i, tmp; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (LoopValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr); // Generate instructions + res = iPtr(selected); // Call generated code + printf ("Result %d : %d\n", selected, res); + for (i = 0; i < selected; i = i + 1) + { + if (i % 2) tmp = tmp + i; + } + + return tmp == res; +} diff --git a/CodeExamples/If-in-Loop.riscv b/CodeExamples/If-in-Loop.riscv new file mode 100755 index 0000000000000000000000000000000000000000..5080de950997ddccad7c7f5fe307bc927d298bbd GIT binary patch literal 41564 zcmeHw3s_Xu`uCpM8wM2-#nNuaiGl6J!SUAVbU7vBAaahWN3BlZzn%$UM7|JkW-Rlh zqBC4HQ&LkhQsN+z8F|#qV`^xVcuUF5%wvj|)XD^HD{9Dmzjy7uX9h)}!teRM=V|Mj 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z{Zm1!?dz<)je7<3+V0r1RO-JNwB9fOm7vL=lKppvKm7=_Kc3Hmrv6X;lfF6rIIeM>(_Yq zru^v&MgD&WJ;Lv~74%SSUTnj2lK+%-IcuNwNJXSmAl*t*El(dX7iD{N(%<3`eo;ZoaTr4xq>aZqbm%K?1 z%UBd=NwnD#U$S6TX?uwqYr|aLl00$z_?IB!M`4MU>S)B8Fcy=QUi8+piOq3Pw{iWz zW>1foU&Y5%6$$imJ`zT!V)+CzEhD9$%$Mp=-}`?&(f+)h5^Ywy^~Tgh`*=$x%iNy$ zg4N<9S+P&DWencaXBnj0lU|Tho=Q!2jN?X)V1=7 zht=iqL2>3MM#fo&CJg)A!1y@J=z+0AHKaOQN()t32rwL19uPUGfS*49K zZMAj3YUpRdd79OH2U#D ziV1ij!Z#^kI-JS=(s)PW7~CB;`94mKu?A#vCbmc#7@N?GR;DJbQ%vI$?c+F8@=NIu zmhTRm{Nx3z&5keWG$Jf`hQ&srDKibLBZqYoK5ZGy?o8HkiYuXovX|manKrA>t#Bs) zxX&}OqOoy+1)Q8)N(QpF%W*pZ7~g&~Mtf5IoNw1{s#_|}7u=3nyai{^E5pi@b_ew;ykbaqSv&mej| zA8nV@%8K}CE%yu}Rfq>7K#Ju@^NT?U7^WE?t?{Bkya`&ph?lOvA<+3T(lMol;lwVf_dPeJ*Gz6*x$P2m!Fabg3qq$8cGAbUUa>@A-^`gQ@^`kjb*Kv4804NugOV>06%8&SHuH5~3 zyf=@ydZ~PL%%<|u8kNpm>3cKkrSdI80@ag>qP44l0@P>3OL-7oia;}Z;-fWA&~<#o zLt!-nt$c}()=I%Q;oFSogdOqG8Xy#WwMrUpEUzHkD-oy;#K+OxEK5EoCz38IlP)^W zRrzR6b$1rWVVdl{)cWm1ipocG*U?$BK2=6FKRWZJ@~K>!6F!$E%YkGU +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr) +{ + /* Code Generation of 20 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7FF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGE_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0002 = riscv_genDIV_4(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, immValueZero); + reste = riscv_genMUL_4(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, immValueZero); + if (!reste.dontFree) h2_freeReg(tmp0002.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBNE_3(i, reste, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000005]; + i = riscv_genBGE_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_prologue_00000000]; + i = riscv_genBNE_3(i, reste, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, res; + int i, tmp; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (LoopValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr); // Generate instructions + res = iPtr(selected); // Call generated code + printf ("Result %d : %d\n", selected, res); + for (i = 0; i < selected; i = i + 1) + { + if (i % 2) tmp = tmp + i; + } + + return tmp == res; +} diff --git a/CodeExamples/If.aarch64 b/CodeExamples/If.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..2f4562fca1e54a3befcfe92f377923e76ac5ab8c GIT binary patch literal 44024 zcmeHwdtg-6wf8=A=9TwTK(KJaqavCF&?*R&Ndf`|6%$(VTAfUiNiuaZ6J{ogLN9~Z z)?2tO`M}3l9|Rw*LGLZCwKlc)GpOyg)!X8$^|n4Hs4ZV@zf#{R(z(C2A2VkrGa->A z-#vu)+Ni!7SP)L~(dGD`J3TpT2>jD2(uPfFM#mcv|Z zHk-xlfLL+5cn*akroxXTYZW>ro{o^{7Fh&fk;TO$Dx4<3Ood893T-k^1TL8p;np^h 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jsTdG^Z{$uMuvgN?k97G5=q5XoM-kmTXX-W1!1_FiK literal 0 HcmV?d00001 diff --git a/CodeExamples/If.aarch64.c b/CodeExamples/If.aarch64.c new file mode 100644 index 0000000..e3f6f2c --- /dev/null +++ b/CodeExamples/If.aarch64.c @@ -0,0 +1,1117 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_NE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) +{ + /* Code Generation of 12 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 10, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0701, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + threshold = aarch64_genMV_3(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + value = aarch64_genCMP_2(value, threshold); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, toTest, res; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (testValue, testedValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + toTest = atoi (argv[2]); // Value to be tested + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr, selected); // Generate instructions + res = iPtr(toTest); // Call generated code + printf ("Result %d = %d : %d\n", selected, toTest, res); + return res; +} diff --git a/CodeExamples/If.power b/CodeExamples/If.power new file mode 100755 index 0000000000000000000000000000000000000000..c5bbf4e813375810a588d6bcb1084fa5896efdb1 GIT binary patch literal 78264 zcmeHw4SZD9weLPNlVn0Z7$9Q&sGJDcgysvhI8iW@0FuauDWKBV>zz!JNiv$uOlKw< zY$5}f-eODNgYq7VDHOtlc=ZQ2}!RY(bDx1)FU}3dMTr=lkKImOTUy~ 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z`@kMqzmJ&XQvRXrr{p?>GIRTh{bIQ@s{EHTp&!Xl@wo#iN~`wKlbm&>tRJR2rc2dR z@EMeu+gH!UVcC$9Q?XF>RQ~@UVQxPz+mFlo4T@00+^b=`hEOOA9~GpB+5SY8WFk&|Qq~`!$qiQ#?gre-e^mUYziUY{5ipD$FB0v)ssca9j+T|y2dU~m Q^+8deUTHO7Nm=&)0PCebUjP6A literal 0 HcmV?d00001 diff --git a/CodeExamples/If.power.c b/CodeExamples/If.power.c new file mode 100644 index 0000000..41cb10b --- /dev/null +++ b/CodeExamples/If.power.c @@ -0,0 +1,936 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBNE_1(h2_sValue_t P0); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BNE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) +{ + /* Code Generation of 12 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 15, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF80F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + threshold = power_genMV_2(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + value = power_genCMP_2(value, threshold); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, toTest, res; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (testValue, testedValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + toTest = atoi (argv[2]); // Value to be tested + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr, selected); // Generate instructions + res = iPtr(toTest); // Call generated code + printf ("Result %d = %d : %d\n", selected, toTest, res); + return res; +} diff --git a/CodeExamples/If.riscv b/CodeExamples/If.riscv new file mode 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z+;ogXDOvaqvPQDKCaq}HC2w#k=+}UL#+C1iU?wJxF&6f*MU_e?s@Uy~>Kj2KOAmUpGK6+-J=0?iOh~`{MpgV?VaBr3P z*m??yXOL{oM_bvn>LET_XFY>NCDOFABHgGynj7>-z)vjWqx-|LAl?G49mGq=V+eF_ zm+GT+Sq1oLm7%pu`4s+&K=*te~nA2kErKWKGKioH^p%B>qMvrwM)kY z1gejUl<%%9-&_aD4vmj)foXiSe!P1S<`G&U%CzJ>q)AV>L-|fTz6YPbO{2@ zwuz6{ANp2w{v0!gJE)9~qX;C^g9seNNAqRvpfURi%CDcP}mv;00`EF0apB88r2Y9uzJ6rMnZ8YYgTA?4GxfNd{E|{dt@ZGQSY4-NV zO$hBf=%gZvQ0Uu=Z(tVepaS*K_$cE&-HZH01nS>#1ln +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +/* C compilette prototype */ +h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) +{ + /* Code Generation of 11 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 6, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_endtrue_00000001 */ + #define h2_endtrue_00000001 1 + 0, /* h2_iffalse_00000002 */ + #define h2_iffalse_00000002 2 + 0, /* h2_ifend_00000003 */ + #define h2_ifend_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x77F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + threshold = riscv_genMV_2(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + value = riscv_genBNE_3(value, threshold, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_endtrue_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_iffalse_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_ifend_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000000]; + value = riscv_genBNE_3(value, threshold, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_endtrue_00000001]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int selected, toTest, res; + pifi iPtr; + + if (argc < 2) + { + printf("Give 2 value (testValue, testedValue)\n"); + exit(-1); + } + selected = atoi (argv[1]); // Get threshold value + toTest = atoi (argv[2]); // Value to be tested + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifi) genIf (ptr, selected); // Generate instructions + res = iPtr(toTest); // Call generated code + printf ("Result %d = %d : %d\n", selected, toTest, res); + return res; +} diff --git a/CodeExamples/Loop-in-If.aarch64 b/CodeExamples/Loop-in-If.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..3df33b82cdd3b6517771f56b22b17b0e27196c6f GIT binary patch literal 52312 zcmeHwdtg-6wf8=AW-^m^NWw!vnD9^@CgGt7f@P9`$OQ#MRC?|0WReWYlrR%#CJMqW zgJ`c66!HbdTU3JDTLZn7R$H5^y#}$Zz1Wr(ZTq!8CZLt?(tf3aVlLu*zqKEeGn1J- zAj$WSCpl;Dz4lsbueJ8t`|QU#XErZheuGKVm^w`CMMkN1tAm5Ym9f=_c~ZjWvQ*|^ zlh{O-0*D!>gXd5vVk-PpvR0u@;^_#9ZmvlH=9(NlqQWr(%v7i(q|hSsMBtDq5x#t{ zNUD%=ZN!yiJ^7HxKlxAzkEn2`l;gAv6&)ps?o&zksiae3SPG^>r61`=XNBZfVR9fv zX$J+&&aYh|;nK14gJ2ECC;c-|B6RSG3dhRwRH*1~0UgQN*CR(Fmdo;z*=3ZJUxl)G zR$T9?Dz2|7toL{u*B826{_46pR~H3*MKguo#Gi1N+;Y`O#BGO4TgwO3D1m)5beBMXf#v(|15PEKcT;i1oeoGSg zf+X1CU4_vR@+jKO}+Mlfa2bB0jT|z{>z1#zwLAJ4+A~^}-|W z^`0PWaQpo}KWk_V2Ix{<=khaGmCuhHzsDO~!)o2Z23M^+;JL@m);0KjL3eeKt#j4a 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zDElcGz8@DuujccU{#jtqbMM9@zWk?=X)Ir@(>v(-bR0BJHy-ij|2s0Xa4Ip?I>Sj) z3`ab^N~^F9IJD-h=+(Oa=|0l`6tq;;ieBvxd@AX~Qh()Ns$AsSSL+saI|V_q@)g_Th!8I&zna&qm-Lki zQHH8q1^y5bl7EH*$WYP8&xxctISrwn#;IVElm|Oy`8(q>bBsuc)5b&`3dgYjFM)V{ zstDCJ9yc9;co^aS(;h+bfijF_5RZFV68h4;g21FYz9jUMC4Id87Cj>fURI75N3Z0V zk)(WfKoHO?Va7wzDcJlZ^hc>-;*ixK61c|OpZLWU!Er0UCrDbTapRbP(~VR4kLs7H hdg4qB2#%kKAhQ?y4Fg&t`pj1aJ-wS@JmQk<{{bE@$hZIi literal 0 HcmV?d00001 diff --git a/CodeExamples/Loop-in-If.aarch64.c b/CodeExamples/Loop-in-If.aarch64.c new file mode 100644 index 0000000..4eaf1ce --- /dev/null +++ b/CodeExamples/Loop-in-If.aarch64.c @@ -0,0 +1,1439 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_GT_I_I_64_1(i0) do /* bgt */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xc & 0x1f) >> 0)); } while(0); +#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genBGT_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_NE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genBGT_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGT instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGT + +// No specific optimisation for BGT/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GT_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGT instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genPlusOrMul(h2_insn_t * ptr) +{ + /* Code Generation of 32 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_endtrue_00000009 */ + #define h2_endtrue_00000009 9 + 0, /* h2_iffalse_00000010 */ + #define h2_iffalse_00000010 10 + 0, /* h2_ifend_00000011 */ + #define h2_ifend_00000011 11 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0F03, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + plus = aarch64_genCMP_2(plus, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genMUL_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_endtrue_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_iffalse_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_ifend_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000008] + 1; + aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000009]; + aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int plus, loopValue, res; + int i, tmp; + pifii iPtr; + + if (argc < 2) + { + printf("Give 2 values (Plus LoopValue)\n"); + exit(-1); + } + plus = atoi (argv[1]); // Get operator + = 1, other = * + loopValue = atoi (argv[2]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions + res = iPtr(plus, loopValue); // Call generated code + if (plus == 1) + for (tmp = 1, i = 1; i <= loopValue; i = i + 1) + { + tmp *= i; + } + else + for (tmp = 0, i = 1; i <= loopValue; i = i + 1) + { + tmp += i; + } + printf ("Result plus = %d, loopValue %d : %d (%d)\n", plus, loopValue, res, tmp); + return tmp != res; +} diff --git a/CodeExamples/Loop-in-If.power b/CodeExamples/Loop-in-If.power new file mode 100755 index 0000000000000000000000000000000000000000..1b3810cab7df8590800027ff37bb0de7ca07b409 GIT binary patch literal 78352 zcmeHw4}4VBmH&M+lVn0d7$9I&Dh~lSp-Bj6>7XDXfF%4g6|i)F_BS&mLo%Ao#K}ZM zn@C{UUF_Q5!WLU}v0z0PchSWz-KDM8=#O^MANyPSTeqcMs_0@jSy?x(+6G16e$Rd9 zPF`MS@&`%f^ZUF9@16V3J@?#m&OP_sKkwzumSwAMacP=Rhf7QnbXV>bKEjpL1xIy} zN#jDgT=+#cuG7V}A`|x>iNnQ&s+@$q%vwRONhaKYRL)NfO(^McFX4C-EfiD|63pN{ z29h3W3A;9%SOtaD#=MfO`bTEI{*fl>6%3LZT79QjIEG&aR!iEvFqG=>@)Vl|>UQHz3N)4lOXA}m6QSVRN@aHN_*b0QQ^ z1R6t;sGxgtsd-}gs;Y`5fw`q~J`b|G##ofe0+7ws@1OM^nK(53+X$%q{9C)eiKcal z2AKR;-pw&1P(af1b~`V^H3TJY3Y)lqN3+xxDfvBCnexVL=k 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ML9fbM58JKyZ<$W?E&u=k literal 0 HcmV?d00001 diff --git a/CodeExamples/Loop-in-If.power.c b/CodeExamples/Loop-in-If.power.c new file mode 100644 index 0000000..63df0f3 --- /dev/null +++ b/CodeExamples/Loop-in-If.power.c @@ -0,0 +1,1164 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_BGT_I_I_32_1(i0) do /* bgt */ { power_G32(((0x4181 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBNE_1(h2_sValue_t P0); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBGT_1(h2_sValue_t P0); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBNE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BNE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBGT_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGT instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGT + +// No specific optimisation for BGT/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGT_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGT instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genPlusOrMul(h2_insn_t * ptr) +{ + /* Code Generation of 32 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_endtrue_00000009 */ + #define h2_endtrue_00000009 9 + 0, /* h2_iffalse_00000010 */ + #define h2_iffalse_00000010 10 + 0, /* h2_ifend_00000011 */ + #define h2_ifend_00000011 11 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1F81F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + plus = power_genCMP_2(plus, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genMUL_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_endtrue_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_iffalse_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, LoopValue); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_ifend_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000008] + 1; + power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + power_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_endtrue_00000009]; + power_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + power_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int plus, loopValue, res; + int i, tmp; + pifii iPtr; + + if (argc < 2) + { + printf("Give 2 values (Plus LoopValue)\n"); + exit(-1); + } + plus = atoi (argv[1]); // Get operator + = 1, other = * + loopValue = atoi (argv[2]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions + res = iPtr(plus, loopValue); // Call generated code + if (plus == 1) + for (tmp = 1, i = 1; i <= loopValue; i = i + 1) + { + tmp *= i; + } + else + for (tmp = 0, i = 1; i <= loopValue; i = i + 1) + { + tmp += i; + } + printf ("Result plus = %d, loopValue %d : %d (%d)\n", plus, loopValue, res, tmp); + return tmp != res; +} diff --git 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+#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_BGT_RRI_I_32_1(r2,r1,i1) do /* BGT */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBGT_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBGT_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGT instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGT + +// No specific optimisation for BGT/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGT_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGT instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BNE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BNE + +// No specific optimisation for BNE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BNE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genPlusOrMul(h2_insn_t * ptr) +{ + /* Code Generation of 29 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_endtrue_00000009 */ + #define h2_endtrue_00000009 9 + 0, /* h2_iffalse_00000010 */ + #define h2_iffalse_00000010 10 + 0, /* h2_ifend_00000011 */ + #define h2_ifend_00000011 11 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + plus = riscv_genBNE_3(plus, tmp, intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genMUL_4(tmp, tmp, i, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_endtrue_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_iffalse_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, i); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_ifend_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_prologue_00000008]; + plus = riscv_genBNE_3(plus, tmp, intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000001]; + i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_endtrue_00000009]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000005]; + i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int plus, loopValue, res; + int i, tmp; + pifii iPtr; + + if (argc < 2) + { + printf("Give 2 values (Plus LoopValue)\n"); + exit(-1); + } + plus = atoi (argv[1]); // Get operator + = 1, other = * + loopValue = atoi (argv[2]); // Get threshold value + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions + res = iPtr(plus, loopValue); // Call generated code + if (plus == 1) + for (tmp = 1, i = 1; i <= loopValue; i = i + 1) + { + tmp *= i; + } + else + for (tmp = 0, i = 1; i <= loopValue; i = i + 1) + { + tmp += i; + } + printf ("Result plus = %d, loopValue %d : %d (%d)\n", plus, loopValue, res, tmp); + return tmp != res; +} diff --git a/CodeExamples/Loop.aarch64 b/CodeExamples/Loop.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..ffc1bf970ff29a20201ed1a4db9ec15f29e75c40 GIT binary patch literal 44024 zcmeHwdwi7Dng4m;cW${~22!G1q6@$h-OV#9oi4ykrAk6d?XpfJZdnp(v{e*U z%6Mg! zlm+5JxXRDS_QZ$uoQq!`ek3COh=%aF9)zG=dV()~=gt{OvL1w9nxU3>WrAOw1-?8B z{F*HAbF;ud2e^q}`Y{cFO!AQaGQs~g3*5{CCmxyjT#yA`2Y3ma!nSnOASdj?GyW}s zDC_Wt!=W(i=!{0_)Y$3^Ghag}jGAyD7;R=P{%D7<#UBaW;%Dt0;ZW4y7-j9gwzg0s zi$t41&YEuu2cmxFi-rQsMV4mkOi zI$RdGYMbhcEpYO8bxg6q)mW!G(*n1~!}%6C9|w}rLJQm~{}Kya#V#UoTi`T4)p5B6 zPUBA<>n(5^lj_)Hfzw!5ht~qPj(yKuaz&o33-AnFb< zcDUp(tA~n@uIM)PS-+fR8n37y>IO@6_fWCUcpWc0P@Zim=b~I|DHo#LU@4cPe5<8A z3FU_^iu3+r#eoSi>ps6t3Lq5<9 z8rpsayAWMEKJZ?e{qgpfYw~y8S@Chr?t{Re4cgkd?x6-wt0!ow&68XIo%_POd2HxA zXw$3LF70CM({DgdlXca5b$#i(dG4W;Tc6{8@)qQc?_@uZ6|uhfEY^oHQy!b;?!)*j ziJ=@TLVlZ8M)j1R#n@&o9^Xhfpz9`?RhxuAFdcZ)1s(=6$J2=(Fz~#3z+ekvhQ8ok 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zS&5NP*FW(~Yl2gFzbptlXmI10jh`Psi< OhQB)@a^jp$|Nj87K&ov3 literal 0 HcmV?d00001 diff --git a/CodeExamples/Loop.aarch64.c b/CodeExamples/Loop.aarch64.c new file mode 100644 index 0000000..38c7819 --- /dev/null +++ b/CodeExamples/Loop.aarch64.c @@ -0,0 +1,1125 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 13 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF1F03, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + res = aarch64_genMV_3(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + res = aarch64_genADD_3(res, res, increment); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, res, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtr; + + if (argc < 3) + { + printf("Give 2 increment values\n"); + exit(-1); + } + in0 = atoi (argv[1]); + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr = (pifii) genMul (ptr); // Generate instructions + res = fPtr(in0, in1); // Call generated code + printf("%d * %d = %d\n", in0, in1, res); + if (res == (in0 * in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Loop.power b/CodeExamples/Loop.power new file mode 100755 index 0000000000000000000000000000000000000000..c89a785b7e4a891262c6f35a8e6d18d2f8fe389e GIT binary patch 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+typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genBGE_1(h2_sValue_t P0); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 13 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 17, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3F81F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + res = power_genMV_2(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + res = power_genADD_3(res, res, increment); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, res); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtr; + + if (argc < 3) + { + printf("Give 2 increment values\n"); + exit(-1); + } + in0 = atoi (argv[1]); + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 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BRlul8xATv#1Ru+on1qiOf ssrsL?|M`HWsF)Y1yg-zHPfZ*gnl3A?FEW+Ch!lfkl?Zs8E-6X&Uu4~~IRF3v literal 0 HcmV?d00001 diff --git a/CodeExamples/Multiple-flt.power.c b/CodeExamples/Multiple-flt.power.c new file mode 100644 index 0000000..2b58444 --- /dev/null +++ b/CodeExamples/Multiple-flt.power.c @@ -0,0 +1,1157 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define PPC_FADDS_RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); +#define PPC_FADDS__RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDFP_RRR_F_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xa & 0x7ff) >> 0)); } while(0); +#define P1_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); +#define P1_FADD__RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); +#define PPC_FDIVS_RRR_F_32_1(r0,r1,r2) do /* div */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x24 & 0x7ff) >> 0)); } while(0); +#define P1_FDIV_RRR_F_64_1(r0,r1,r2) do /* div */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x24 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define PPC_FSUBS_RRR_F_32_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x28 & 0x7ff) >> 0)); } while(0); +#define PPC_FSUBS__RRR_F_32_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x29 & 0x7ff) >> 0)); } while(0); +#define P1_FSUB_RRR_F_64_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x28 & 0x7ff) >> 0)); } while(0); +#define P1_FSUB__RRR_F_64_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x29 & 0x7ff) >> 0)); } while(0); +#define PPC_FMULS_RRR_F_32_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x32 & 0x3f) >> 0)); } while(0); +#define PPC_FMULS__RRR_F_32_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x33 & 0x3f) >> 0)); } while(0); +#define P1_FMUL_RRR_F_64_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x32 & 0x3f) >> 0)); } while(0); +#define P1_FMUL__RRR_F_64_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x33 & 0x3f) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FMULS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FMULS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FMUL_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FMUL__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FSUBS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FSUBS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FSUB_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FSUB__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FADDS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FADDS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDFP_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FADD__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_FDIVS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_FDIV_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 floats and return float */ +typedef float (*pifff)(float, float); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genMUL_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3807, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genDIV_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + float fin0, fin1, fres; + pifff fPtrf; + int resultOK; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) + fin1 = atof (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifff) genAddf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple addition of 2 floating point values:\n"); + printf("%f + %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 + fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genSubf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple subraction of 2 floating point values:\n"); + printf("%f - %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 - fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genMulf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple multiplication of 2 floating point values:\n"); + printf("%f * %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 * fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genDivf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple division of 2 floating point values:\n"); + printf("%f / %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 / fin1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-flt.riscv b/CodeExamples/Multiple-flt.riscv new file mode 100755 index 0000000000000000000000000000000000000000..486b1b0c0bf1e0d02a177de8d4b3b6ec112d2cd4 GIT binary patch literal 57932 zcmeHw3wRVowtw~X!SJ7qHhzN*0A}^6e2rxoGgouby5yC@xh)lqS5D1z7?^O3BlgA91$o_Np zyJ@JdI@RY?)j4(QbXA?|$&}RLLj^%#o=d}iVgwZi3G5!k`wub}g!mq&V_jK1i)K+Q zn8TDuI08!n0R=7cDToL*z&4aiAqp@BdWLLzUT7&pLcK<-vFADAC>Ny!HoTPaKbN%`4*^YaQOP3~*Svt~U#Ah~Z| ze&K-RY`xX2?++ZRi^?MWv=NWuuJi-t(?v4A0ig>5)!Pk$uC54#6H0)3Q5hsVl1rGH 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Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32F_FADD_S_RRR_F_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FADD_D_RRR_F_64_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32F_FDIV_S_RRR_F_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0xc & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FDIV_D_RRR_F_64_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0xd & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32F_FMUL_S_RRR_F_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x8 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32F_FSUB_S_RRR_F_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x4 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FMUL_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FSUB_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FDIV_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32D_FDIV_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 floats and return float */ +typedef float (*pifff)(float, float); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genMUL_4(r, a, b, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genDIV_4(r, a, b, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + float fin0, fin1, fres; + pifff fPtrf; + int resultOK; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) + fin1 = atof (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifff) genAddf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple addition of 2 floating point values:\n"); + printf("%f + %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 + fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genSubf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple subraction of 2 floating point values:\n"); + printf("%f - %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 - fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genMulf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple multiplication of 2 floating point values:\n"); + printf("%f * %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 * fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genDivf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple division of 2 floating point values:\n"); + printf("%f / %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 / fin1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-int.aarch64 b/CodeExamples/Multiple-int.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..fadeda4cf1d0df9f07312f9e214fc7c8e94a9cab GIT binary patch literal 52288 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h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 ints and return int */ +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genMUL_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genDIV_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtrf; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) + in1 = atoi (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifii) genAddf (ptr); + res = fPtrf(in0, in1); + printf ("Simple addition of 2 int values:\n"); + printf("%d + %d = %d\n", in0, in1, res); + if (res != (in0 + in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genSubf (ptr); + res = fPtrf(in0, in1); + printf ("Simple subraction of 2 int values:\n"); + printf("%d - %d = %d\n", in0, in1, res); + if (res != (in0 - in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genMulf (ptr); + res = fPtrf(in0, in1); + printf ("Simple multiplication of 2 int values:\n"); + printf("%d * %d = %d\n", in0, in1, res); + if (res != (in0 * in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genDivf (ptr); + res = fPtrf(in0, in1); + printf ("Simple division of 2 int values:\n"); + printf("%d / %d = %d\n", in0, in1, res); + if (res != (in0 / in1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-int.power b/CodeExamples/Multiple-int.power new file mode 100755 index 0000000000000000000000000000000000000000..80db09406210c6b8d25f2ba9ce64b0566da20610 GIT binary patch literal 78336 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+/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 ints and return int */ +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x781F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x781F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genMUL_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x781F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x781F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genDIV_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtrf; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) + in1 = atoi (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifii) genAddf (ptr); + res = fPtrf(in0, in1); + printf ("Simple addition of 2 int values:\n"); + printf("%d + %d = %d\n", in0, in1, res); + if (res != (in0 + in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genSubf (ptr); + res = fPtrf(in0, in1); + printf ("Simple subraction of 2 int values:\n"); + printf("%d - %d = %d\n", in0, in1, res); + if (res != (in0 - in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genMulf (ptr); + res = fPtrf(in0, in1); + printf ("Simple multiplication of 2 int values:\n"); + printf("%d * %d = %d\n", in0, in1, res); + if (res != (in0 * in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genDivf (ptr); + res = fPtrf(in0, in1); + printf ("Simple division of 2 int values:\n"); + printf("%d / %d = %d\n", in0, in1, res); + if (res != (in0 / in1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-int.riscv b/CodeExamples/Multiple-int.riscv new file mode 100755 index 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b/CodeExamples/Multiple-int.riscv.c new file mode 100644 index 0000000..7bdfe2c --- /dev/null +++ b/CodeExamples/Multiple-int.riscv.c @@ -0,0 +1,1044 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 ints and return int */ +typedef int (*pifii)(int, int); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genMUL_4(r, a, b, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genDIV_4(r, a, b, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtrf; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) + in1 = atoi (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifii) genAddf (ptr); + res = fPtrf(in0, in1); + printf ("Simple addition of 2 int values:\n"); + printf("%d + %d = %d\n", in0, in1, res); + if (res != (in0 + in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genSubf (ptr); + res = fPtrf(in0, in1); + printf ("Simple subraction of 2 int values:\n"); + printf("%d - %d = %d\n", in0, in1, res); + if (res != (in0 - in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genMulf (ptr); + res = fPtrf(in0, in1); + printf ("Simple multiplication of 2 int values:\n"); + printf("%d * %d = %d\n", in0, in1, res); + if (res != (in0 * in1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifii) genDivf (ptr); + res = fPtrf(in0, in1); + printf ("Simple division of 2 int values:\n"); + printf("%d / %d = %d\n", in0, in1, res); + if (res != (in0 / in1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/RegressionSingleOp.py b/CodeExamples/RegressionSingleOp.py index d9d5ed0..fb02bd2 100755 --- a/CodeExamples/RegressionSingleOp.py +++ b/CodeExamples/RegressionSingleOp.py @@ -117,6 +117,7 @@ def genAndRunValue(singleArith, opList, wordLenList, vectorLen, archName, keep): parser.add_argument('-z', '--analyse', action='store_true', help='Analyse result') parser.add_argument('-d', '--dotests', action='store_true', help='Generate results') a = parser.parse_args() + print(a.wLen); # print (a) results = {} csvFileName = "regression-single-op-%s.csv"%a.arch[0] @@ -124,29 +125,20 @@ def genAndRunValue(singleArith, opList, wordLenList, vectorLen, archName, keep): if len(a.arch) != 1: exitError("Could only analyse 1 architecture") else: - # Read reference list - csvRef = csv.reader (open ("RegressionSingleOpReference.csv", "r"), delimiter=";") - # Restrict the list to 1 arch - refList = [(ref[0], ref[1], int(ref[2]), int(ref[3]), ref[4]) for ref in csvRef if ref[5] == a.arch[0]] - refList.sort() - # print (refList) - - # Read the generated results + csvArch = csv.reader (open (csvFileName, "r"), delimiter=";") - archList = [(ref[0], ref[1], int(ref[2]), int(ref[3]), ref[4]) for ref in csvArch] + archList = [(ref[0], ref[1], int(ref[2]), int(ref[3]), ref[4],ref[5],ref[6]) for ref in csvArch] archList.sort() # print (archList) - moreInArch = [x for x in refList + archList if x not in refList] - moreInRef = [x for x in refList + archList if x not in archList] - print ("moreInRef : "+str(moreInRef)) - print ("moreInArch : "+str(moreInArch)) - if archList == refList: - print ("same list") - sys.exit(0) - else: - print ("different list") - sys.exit(-1) + checkIf = False + for test in archList: + print(test) + if(test[6] == "Fail"): + checkIf = True + if(checkIf): + exit(-1) + elif a.dotests: if "value" in a.param: for archName in a.arch: diff --git a/CodeExamples/Tests/Test-Address-mul-int-008-128-aarch64+riscv+power.hl b/CodeExamples/Tests/Test-Address-mul-int-008-128-aarch64+riscv+power.hl new file mode 100644 index 0000000..2b9dab7 --- /dev/null +++ b/CodeExamples/Tests/Test-Address-mul-int-008-128-aarch64+riscv+power.hl @@ -0,0 +1,46 @@ +// -*- c -*- +#include +#include +/* C compilette prototype vector version*/ +typedef int8_t v8_128_int_t __attribute__ ((vector_size (128*sizeof (int8_t)))); +typedef void (*functionPointer)(v8_128_int_t*, v8_128_int_t*, v8_128_int_t*); +functionPointer genSingleOp(functionPointer ptr) /* C compilette prototype */ +{ + +#[ +int 32 1 compilette(int[] 8 128 a, int[] 8 128 b, int[] 8 128 r) +{ + r[0] = a[0] * b[0]; + return 1; +} +]# + return ptr; +} +int main(int argc, char * argv[]) +{ + functionPointer fPtr; + int i, returnValue; + if (argc < 256) + { + printf("Give 256 values\n"); + exit(-1); + } + v8_128_int_t in0, in1, res; + for (int i = 0; i < 128; i++) + { + in0[i] = atoi (argv[1+i]); + in1[i] = atoi (argv[1+128+i]); + } + fPtr = h2_malloc (1024); + fPtr = (functionPointer) genSingleOp(fPtr); + fPtr(&in0, &in1, &res); + printf ("Simple operation on 2 variables (wordLen: 8, vectorLen 128):\n"); + returnValue = 0; + for (i= 0; i < 128; i++) + { +printf("%d * %d = %d\n", in0[i], in1[i], res[i]); +if (res[i] != (in0[i] * in1[i])) + returnValue = -1; + } + return returnValue; +} \ No newline at end of file diff --git a/CodeExamples/Tests/Test-Value-sub-flt-064-001-+.hl b/CodeExamples/Tests/Test-Value-sub-flt-064-001-+.hl new file mode 100644 index 0000000..4eed885 --- /dev/null +++ b/CodeExamples/Tests/Test-Value-sub-flt-064-001-+.hl @@ -0,0 +1,46 @@ +// -*- c -*- +#include +#include +/* C compilette prototype scalar version*/ +typedef double (*functionPointer)(double, double); +functionPointer genSingleOp(h2_insn_t * ptr) /* C compilette prototype */ +{ + +#[ +flt 64 1 compilette(flt 64 1 a, flt 64 1 b) +{ + flt 64 1 r; + r = a - b; + return r; +} +]# + return (functionPointer) ptr; +} +int main(int argc, char * argv[]) +{ + functionPointer fPtr; + int i, returnValue; + if (argc < 2) + { + printf("Give 2 values\n"); + exit(-1); + } + double in0, in1, res; + for (int i = 0; i < 1; i++) + { + in0 = atof (argv[1]); + in1 = atof (argv[1]); + } + fPtr = h2_malloc (1024); + fPtr = (functionPointer) genSingleOp(fPtr); + res = fPtr(in0, in1); + printf ("Simple operation on 2 variables (wordLen: 64, vectorLen 1):\n"); + returnValue = 0; + for (i= 0; i < 1; i++) + { + printf("%f - %f = %f\n", in0, in1, res); + if (res != (in0 - in1)) + returnValue = -1; + } + return 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+add;int;8;128;value;aarch64;Fail +add;int;16;1;value;aarch64;Success; +add;int;16;2;value;aarch64;Fail +add;int;16;4;value;aarch64;Success; +add;int;16;8;value;aarch64;Fail +add;int;16;16;value;aarch64;Fail +add;int;16;32;value;aarch64;Fail +add;int;16;64;value;aarch64;Fail +add;int;16;128;value;aarch64;Fail +add;int;32;1;value;aarch64;Success; +add;int;32;2;value;aarch64;Fail +add;int;32;4;value;aarch64;Success; +add;int;32;8;value;aarch64;Fail +add;int;32;16;value;aarch64;Fail +add;int;32;32;value;aarch64;Fail +add;int;32;64;value;aarch64;Fail +add;int;32;128;value;aarch64;Fail +add;int;64;1;value;aarch64;Success; +add;int;64;2;value;aarch64;Fail +add;int;64;4;value;aarch64;Fail +add;int;64;8;value;aarch64;Fail +add;int;64;16;value;aarch64;Fail +add;int;64;32;value;aarch64;Fail +add;int;64;64;value;aarch64;Fail +add;int;64;128;value;aarch64;Fail +mul;int;8;1;value;aarch64;Success; +mul;int;8;2;value;aarch64;Fail +mul;int;8;4;value;aarch64;Fail +mul;int;8;8;value;aarch64;Fail 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+sub;int;64;64;value;aarch64;Fail +sub;int;64;128;value;aarch64;Fail +div;int;8;1;value;aarch64;Success; +div;int;8;2;value;aarch64;Fail +div;int;8;4;value;aarch64;Fail +div;int;8;8;value;aarch64;Fail +div;int;8;16;value;aarch64;Fail +div;int;8;32;value;aarch64;Fail +div;int;8;64;value;aarch64;Fail +div;int;8;128;value;aarch64;Fail +div;int;16;1;value;aarch64;Success; +div;int;16;2;value;aarch64;Fail +div;int;16;4;value;aarch64;Fail +div;int;16;8;value;aarch64;Fail +div;int;16;16;value;aarch64;Fail +div;int;16;32;value;aarch64;Fail +div;int;16;64;value;aarch64;Fail +div;int;16;128;value;aarch64;Fail +div;int;32;1;value;aarch64;Success; +div;int;32;2;value;aarch64;Fail +div;int;32;4;value;aarch64;Fail +div;int;32;8;value;aarch64;Fail +div;int;32;16;value;aarch64;Fail +div;int;32;32;value;aarch64;Fail +div;int;32;64;value;aarch64;Fail +div;int;32;128;value;aarch64;Fail +div;int;64;1;value;aarch64;Success; +div;int;64;2;value;aarch64;Fail +div;int;64;4;value;aarch64;Fail +div;int;64;8;value;aarch64;Fail +div;int;64;16;value;aarch64;Fail +div;int;64;32;value;aarch64;Fail +div;int;64;64;value;aarch64;Fail +div;int;64;128;value;aarch64;Fail +add;flt;32;1;value;aarch64;Success; +add;flt;32;2;value;aarch64;Fail +add;flt;32;4;value;aarch64;Fail +add;flt;32;8;value;aarch64;Fail +add;flt;32;16;value;aarch64;Fail +add;flt;32;32;value;aarch64;Fail +add;flt;32;64;value;aarch64;Fail +add;flt;32;128;value;aarch64;Fail +add;flt;64;1;value;aarch64;Success; +add;flt;64;2;value;aarch64;Fail +add;flt;64;4;value;aarch64;Fail +add;flt;64;8;value;aarch64;Fail +add;flt;64;16;value;aarch64;Fail +add;flt;64;32;value;aarch64;Fail +add;flt;64;64;value;aarch64;Fail +add;flt;64;128;value;aarch64;Fail +mul;flt;32;1;value;aarch64;Success; +mul;flt;32;2;value;aarch64;Fail +mul;flt;32;4;value;aarch64;Fail +mul;flt;32;8;value;aarch64;Fail +mul;flt;32;16;value;aarch64;Fail +mul;flt;32;32;value;aarch64;Fail +mul;flt;32;64;value;aarch64;Fail +mul;flt;32;128;value;aarch64;Fail +mul;flt;64;1;value;aarch64;Success; +mul;flt;64;2;value;aarch64;Fail +mul;flt;64;4;value;aarch64;Fail +mul;flt;64;8;value;aarch64;Fail +mul;flt;64;16;value;aarch64;Fail +mul;flt;64;32;value;aarch64;Fail +mul;flt;64;64;value;aarch64;Fail +mul;flt;64;128;value;aarch64;Fail +sub;flt;32;1;value;aarch64;Success; +sub;flt;32;2;value;aarch64;Fail +sub;flt;32;4;value;aarch64;Fail +sub;flt;32;8;value;aarch64;Fail +sub;flt;32;16;value;aarch64;Fail +sub;flt;32;32;value;aarch64;Fail +sub;flt;32;64;value;aarch64;Fail +sub;flt;32;128;value;aarch64;Fail +sub;flt;64;1;value;aarch64;Success; +sub;flt;64;2;value;aarch64;Fail +sub;flt;64;4;value;aarch64;Fail +sub;flt;64;8;value;aarch64;Fail +sub;flt;64;16;value;aarch64;Fail +sub;flt;64;32;value;aarch64;Fail +sub;flt;64;64;value;aarch64;Fail +sub;flt;64;128;value;aarch64;Fail +div;flt;32;1;value;aarch64;Success; +div;flt;32;2;value;aarch64;Fail +div;flt;32;4;value;aarch64;Fail +div;flt;32;8;value;aarch64;Fail +div;flt;32;16;value;aarch64;Fail +div;flt;32;32;value;aarch64;Fail +div;flt;32;64;value;aarch64;Fail +div;flt;32;128;value;aarch64;Fail +div;flt;64;1;value;aarch64;Success; +div;flt;64;2;value;aarch64;Fail +div;flt;64;4;value;aarch64;Fail +div;flt;64;8;value;aarch64;Fail +div;flt;64;16;value;aarch64;Fail +div;flt;64;32;value;aarch64;Fail +div;flt;64;64;value;aarch64;Fail +div;flt;64;128;value;aarch64;Fail +mod;int;8;1;value;aarch64;Fail +mod;int;8;2;value;aarch64;Fail +mod;int;8;4;value;aarch64;Fail +mod;int;8;8;value;aarch64;Fail +mod;int;8;16;value;aarch64;Fail +mod;int;8;32;value;aarch64;Fail +mod;int;8;64;value;aarch64;Fail +mod;int;8;128;value;aarch64;Fail +mod;int;16;1;value;aarch64;Fail +mod;int;16;2;value;aarch64;Fail +mod;int;16;4;value;aarch64;Fail +mod;int;16;8;value;aarch64;Fail +mod;int;16;16;value;aarch64;Fail +mod;int;16;32;value;aarch64;Fail +mod;int;16;64;value;aarch64;Fail +mod;int;16;128;value;aarch64;Fail +mod;int;32;1;value;aarch64;Fail +mod;int;32;2;value;aarch64;Fail +mod;int;32;4;value;aarch64;Fail +mod;int;32;8;value;aarch64;Fail +mod;int;32;16;value;aarch64;Fail +mod;int;32;32;value;aarch64;Fail +mod;int;32;64;value;aarch64;Fail +mod;int;32;128;value;aarch64;Fail +mod;int;64;1;value;aarch64;Fail +mod;int;64;2;value;aarch64;Fail +mod;int;64;4;value;aarch64;Fail +mod;int;64;8;value;aarch64;Fail +mod;int;64;16;value;aarch64;Fail +mod;int;64;32;value;aarch64;Fail +mod;int;64;64;value;aarch64;Fail +mod;int;64;128;value;aarch64;Fail +or;int;8;1;value;aarch64;Success; +or;int;8;2;value;aarch64;Fail +or;int;8;4;value;aarch64;Fail +or;int;8;8;value;aarch64;Fail +or;int;8;16;value;aarch64;Fail +or;int;8;32;value;aarch64;Fail +or;int;8;64;value;aarch64;Fail +or;int;8;128;value;aarch64;Fail +or;int;16;1;value;aarch64;Success; +or;int;16;2;value;aarch64;Fail +or;int;16;4;value;aarch64;Success; +or;int;16;8;value;aarch64;Fail +or;int;16;16;value;aarch64;Fail +or;int;16;32;value;aarch64;Fail +or;int;16;64;value;aarch64;Fail +or;int;16;128;value;aarch64;Fail +or;int;32;1;value;aarch64;Success; +or;int;32;2;value;aarch64;Fail +or;int;32;4;value;aarch64;Success; +or;int;32;8;value;aarch64;Fail +or;int;32;16;value;aarch64;Fail +or;int;32;32;value;aarch64;Fail +or;int;32;64;value;aarch64;Fail +or;int;32;128;value;aarch64;Fail +or;int;64;1;value;aarch64;Success; +or;int;64;2;value;aarch64;Fail +or;int;64;4;value;aarch64;Fail +or;int;64;8;value;aarch64;Fail +or;int;64;16;value;aarch64;Fail +or;int;64;32;value;aarch64;Fail +or;int;64;64;value;aarch64;Fail +or;int;64;128;value;aarch64;Fail +and;int;8;1;value;aarch64;Success; +and;int;8;2;value;aarch64;Fail +and;int;8;4;value;aarch64;Fail +and;int;8;8;value;aarch64;Fail +and;int;8;16;value;aarch64;Fail +and;int;8;32;value;aarch64;Fail +and;int;8;64;value;aarch64;Fail +and;int;8;128;value;aarch64;Fail +and;int;16;1;value;aarch64;Success; +and;int;16;2;value;aarch64;Fail +and;int;16;4;value;aarch64;Success; +and;int;16;8;value;aarch64;Fail +and;int;16;16;value;aarch64;Fail +and;int;16;32;value;aarch64;Fail +and;int;16;64;value;aarch64;Fail +and;int;16;128;value;aarch64;Fail +and;int;32;1;value;aarch64;Success; +and;int;32;2;value;aarch64;Fail +and;int;32;4;value;aarch64;Success; +and;int;32;8;value;aarch64;Fail +and;int;32;16;value;aarch64;Fail +and;int;32;32;value;aarch64;Fail +and;int;32;64;value;aarch64;Fail +and;int;32;128;value;aarch64;Fail +and;int;64;1;value;aarch64;Success; +and;int;64;2;value;aarch64;Fail +and;int;64;4;value;aarch64;Fail +and;int;64;8;value;aarch64;Fail +and;int;64;16;value;aarch64;Fail +and;int;64;32;value;aarch64;Fail +and;int;64;64;value;aarch64;Fail +and;int;64;128;value;aarch64;Fail +xor;int;8;1;value;aarch64;Success; +xor;int;8;2;value;aarch64;Fail +xor;int;8;4;value;aarch64;Fail +xor;int;8;8;value;aarch64;Fail +xor;int;8;16;value;aarch64;Fail +xor;int;8;32;value;aarch64;Fail +xor;int;8;64;value;aarch64;Fail +xor;int;8;128;value;aarch64;Fail +xor;int;16;1;value;aarch64;Success; +xor;int;16;2;value;aarch64;Fail +xor;int;16;4;value;aarch64;Success; +xor;int;16;8;value;aarch64;Fail +xor;int;16;16;value;aarch64;Fail +xor;int;16;32;value;aarch64;Fail +xor;int;16;64;value;aarch64;Fail +xor;int;16;128;value;aarch64;Fail +xor;int;32;1;value;aarch64;Success; +xor;int;32;2;value;aarch64;Fail +xor;int;32;4;value;aarch64;Success; +xor;int;32;8;value;aarch64;Fail +xor;int;32;16;value;aarch64;Fail +xor;int;32;32;value;aarch64;Fail +xor;int;32;64;value;aarch64;Fail +xor;int;32;128;value;aarch64;Fail +xor;int;64;1;value;aarch64;Success; +xor;int;64;2;value;aarch64;Fail +xor;int;64;4;value;aarch64;Fail +xor;int;64;8;value;aarch64;Fail +xor;int;64;16;value;aarch64;Fail +xor;int;64;32;value;aarch64;Fail +xor;int;64;64;value;aarch64;Fail +xor;int;64;128;value;aarch64;Fail +sl;int;8;1;value;aarch64;Success; +sl;int;8;2;value;aarch64;Fail +sl;int;8;4;value;aarch64;Fail +sl;int;8;8;value;aarch64;Fail +sl;int;8;16;value;aarch64;Fail +sl;int;8;32;value;aarch64;Fail +sl;int;8;64;value;aarch64;Fail +sl;int;8;128;value;aarch64;Fail +sl;int;16;1;value;aarch64;Success; +sl;int;16;2;value;aarch64;Fail +sl;int;16;4;value;aarch64;Fail +sl;int;16;8;value;aarch64;Fail +sl;int;16;16;value;aarch64;Fail +sl;int;16;32;value;aarch64;Fail +sl;int;16;64;value;aarch64;Fail +sl;int;16;128;value;aarch64;Fail +sl;int;32;1;value;aarch64;Success; +sl;int;32;2;value;aarch64;Fail +sl;int;32;4;value;aarch64;Fail +sl;int;32;8;value;aarch64;Fail +sl;int;32;16;value;aarch64;Fail +sl;int;32;32;value;aarch64;Fail +sl;int;32;64;value;aarch64;Fail +sl;int;32;128;value;aarch64;Fail +sl;int;64;1;value;aarch64;Success; +sl;int;64;2;value;aarch64;Fail +sl;int;64;4;value;aarch64;Fail +sl;int;64;8;value;aarch64;Fail +sl;int;64;16;value;aarch64;Fail +sl;int;64;32;value;aarch64;Fail +sl;int;64;64;value;aarch64;Fail +sl;int;64;128;value;aarch64;Fail +sr;int;8;1;value;aarch64;Success; +sr;int;8;2;value;aarch64;Fail +sr;int;8;4;value;aarch64;Fail +sr;int;8;8;value;aarch64;Fail +sr;int;8;16;value;aarch64;Fail +sr;int;8;32;value;aarch64;Fail +sr;int;8;64;value;aarch64;Fail +sr;int;8;128;value;aarch64;Fail +sr;int;16;1;value;aarch64;Success; +sr;int;16;2;value;aarch64;Fail +sr;int;16;4;value;aarch64;Fail +sr;int;16;8;value;aarch64;Fail +sr;int;16;16;value;aarch64;Fail +sr;int;16;32;value;aarch64;Fail +sr;int;16;64;value;aarch64;Fail +sr;int;16;128;value;aarch64;Fail +sr;int;32;1;value;aarch64;Success; +sr;int;32;2;value;aarch64;Fail +sr;int;32;4;value;aarch64;Fail +sr;int;32;8;value;aarch64;Fail +sr;int;32;16;value;aarch64;Fail +sr;int;32;32;value;aarch64;Fail +sr;int;32;64;value;aarch64;Fail +sr;int;32;128;value;aarch64;Fail +sr;int;64;1;value;aarch64;Success; +sr;int;64;2;value;aarch64;Fail +sr;int;64;4;value;aarch64;Fail +sr;int;64;8;value;aarch64;Fail +sr;int;64;16;value;aarch64;Fail +sr;int;64;32;value;aarch64;Fail +sr;int;64;64;value;aarch64;Fail +sr;int;64;128;value;aarch64;Fail +add;int;8;1;value;riscv;Success; +add;int;8;2;value;riscv;Fail +add;int;8;4;value;riscv;Fail +add;int;8;8;value;riscv;Fail +add;int;8;16;value;riscv;Fail +add;int;8;32;value;riscv;Fail +add;int;8;64;value;riscv;Fail +add;int;8;128;value;riscv;Fail +add;int;16;1;value;riscv;Success; +add;int;16;2;value;riscv;Fail +add;int;16;4;value;riscv;Fail +add;int;16;8;value;riscv;Fail +add;int;16;16;value;riscv;Fail +add;int;16;32;value;riscv;Fail +add;int;16;64;value;riscv;Fail +add;int;16;128;value;riscv;Fail +add;int;32;1;value;riscv;Success; +add;int;32;2;value;riscv;Fail +add;int;32;4;value;riscv;Fail +add;int;32;8;value;riscv;Fail +add;int;32;16;value;riscv;Fail +add;int;32;32;value;riscv;Fail +add;int;32;64;value;riscv;Fail +add;int;32;128;value;riscv;Fail +add;int;64;1;value;riscv;Fail +add;int;64;2;value;riscv;Fail +add;int;64;4;value;riscv;Fail +add;int;64;8;value;riscv;Fail +add;int;64;16;value;riscv;Fail +add;int;64;32;value;riscv;Fail +add;int;64;64;value;riscv;Fail +add;int;64;128;value;riscv;Fail +mul;int;8;1;value;riscv;Success; +mul;int;8;2;value;riscv;Fail +mul;int;8;4;value;riscv;Fail +mul;int;8;8;value;riscv;Fail +mul;int;8;16;value;riscv;Fail +mul;int;8;32;value;riscv;Fail +mul;int;8;64;value;riscv;Fail +mul;int;8;128;value;riscv;Fail +mul;int;16;1;value;riscv;Success; +mul;int;16;2;value;riscv;Fail +mul;int;16;4;value;riscv;Fail +mul;int;16;8;value;riscv;Fail +mul;int;16;16;value;riscv;Fail +mul;int;16;32;value;riscv;Fail +mul;int;16;64;value;riscv;Fail +mul;int;16;128;value;riscv;Fail +mul;int;32;1;value;riscv;Success; +mul;int;32;2;value;riscv;Fail +mul;int;32;4;value;riscv;Fail +mul;int;32;8;value;riscv;Fail +mul;int;32;16;value;riscv;Fail +mul;int;32;32;value;riscv;Fail +mul;int;32;64;value;riscv;Fail +mul;int;32;128;value;riscv;Fail +mul;int;64;1;value;riscv;Fail +mul;int;64;2;value;riscv;Fail +mul;int;64;4;value;riscv;Fail +mul;int;64;8;value;riscv;Fail +mul;int;64;16;value;riscv;Fail +mul;int;64;32;value;riscv;Fail +mul;int;64;64;value;riscv;Fail +mul;int;64;128;value;riscv;Fail +sub;int;8;1;value;riscv;Success; +sub;int;8;2;value;riscv;Fail +sub;int;8;4;value;riscv;Fail +sub;int;8;8;value;riscv;Fail +sub;int;8;16;value;riscv;Fail +sub;int;8;32;value;riscv;Fail +sub;int;8;64;value;riscv;Fail +sub;int;8;128;value;riscv;Fail +sub;int;16;1;value;riscv;Success; +sub;int;16;2;value;riscv;Fail +sub;int;16;4;value;riscv;Fail +sub;int;16;8;value;riscv;Fail +sub;int;16;16;value;riscv;Fail +sub;int;16;32;value;riscv;Fail +sub;int;16;64;value;riscv;Fail +sub;int;16;128;value;riscv;Fail +sub;int;32;1;value;riscv;Success; +sub;int;32;2;value;riscv;Fail +sub;int;32;4;value;riscv;Fail +sub;int;32;8;value;riscv;Fail +sub;int;32;16;value;riscv;Fail +sub;int;32;32;value;riscv;Fail +sub;int;32;64;value;riscv;Fail +sub;int;32;128;value;riscv;Fail +sub;int;64;1;value;riscv;Fail +sub;int;64;2;value;riscv;Fail +sub;int;64;4;value;riscv;Fail +sub;int;64;8;value;riscv;Fail +sub;int;64;16;value;riscv;Fail +sub;int;64;32;value;riscv;Fail +sub;int;64;64;value;riscv;Fail +sub;int;64;128;value;riscv;Fail +div;int;8;1;value;riscv;Success; +div;int;8;2;value;riscv;Fail +div;int;8;4;value;riscv;Fail +div;int;8;8;value;riscv;Fail +div;int;8;16;value;riscv;Fail +div;int;8;32;value;riscv;Fail +div;int;8;64;value;riscv;Fail +div;int;8;128;value;riscv;Fail +div;int;16;1;value;riscv;Success; +div;int;16;2;value;riscv;Fail +div;int;16;4;value;riscv;Fail +div;int;16;8;value;riscv;Fail +div;int;16;16;value;riscv;Fail +div;int;16;32;value;riscv;Fail +div;int;16;64;value;riscv;Fail +div;int;16;128;value;riscv;Fail +div;int;32;1;value;riscv;Success; +div;int;32;2;value;riscv;Fail +div;int;32;4;value;riscv;Fail +div;int;32;8;value;riscv;Fail +div;int;32;16;value;riscv;Fail +div;int;32;32;value;riscv;Fail +div;int;32;64;value;riscv;Fail +div;int;32;128;value;riscv;Fail +div;int;64;1;value;riscv;Fail +div;int;64;2;value;riscv;Fail +div;int;64;4;value;riscv;Fail +div;int;64;8;value;riscv;Fail +div;int;64;16;value;riscv;Fail +div;int;64;32;value;riscv;Fail +div;int;64;64;value;riscv;Fail +div;int;64;128;value;riscv;Fail +add;flt;32;1;value;riscv;Success; +add;flt;32;2;value;riscv;Fail +add;flt;32;4;value;riscv;Fail +add;flt;32;8;value;riscv;Fail +add;flt;32;16;value;riscv;Fail +add;flt;32;32;value;riscv;Fail +add;flt;32;64;value;riscv;Fail +add;flt;32;128;value;riscv;Fail +add;flt;64;1;value;riscv;Success; +add;flt;64;2;value;riscv;Fail +add;flt;64;4;value;riscv;Fail +add;flt;64;8;value;riscv;Fail +add;flt;64;16;value;riscv;Fail +add;flt;64;32;value;riscv;Fail +add;flt;64;64;value;riscv;Fail +add;flt;64;128;value;riscv;Fail +mul;flt;32;1;value;riscv;Success; +mul;flt;32;2;value;riscv;Fail +mul;flt;32;4;value;riscv;Fail +mul;flt;32;8;value;riscv;Fail +mul;flt;32;16;value;riscv;Fail +mul;flt;32;32;value;riscv;Fail +mul;flt;32;64;value;riscv;Fail +mul;flt;32;128;value;riscv;Fail +mul;flt;64;1;value;riscv;Fail +mul;flt;64;2;value;riscv;Fail +mul;flt;64;4;value;riscv;Fail +mul;flt;64;8;value;riscv;Fail +mul;flt;64;16;value;riscv;Fail +mul;flt;64;32;value;riscv;Fail +mul;flt;64;64;value;riscv;Fail +mul;flt;64;128;value;riscv;Fail +sub;flt;32;1;value;riscv;Success; +sub;flt;32;2;value;riscv;Fail +sub;flt;32;4;value;riscv;Fail +sub;flt;32;8;value;riscv;Fail +sub;flt;32;16;value;riscv;Fail +sub;flt;32;32;value;riscv;Fail +sub;flt;32;64;value;riscv;Fail +sub;flt;32;128;value;riscv;Fail +sub;flt;64;1;value;riscv;Fail +sub;flt;64;2;value;riscv;Fail +sub;flt;64;4;value;riscv;Fail +sub;flt;64;8;value;riscv;Fail +sub;flt;64;16;value;riscv;Fail +sub;flt;64;32;value;riscv;Fail +sub;flt;64;64;value;riscv;Fail +sub;flt;64;128;value;riscv;Fail +div;flt;32;1;value;riscv;Success; +div;flt;32;2;value;riscv;Fail +div;flt;32;4;value;riscv;Fail +div;flt;32;8;value;riscv;Fail +div;flt;32;16;value;riscv;Fail +div;flt;32;32;value;riscv;Fail +div;flt;32;64;value;riscv;Fail +div;flt;32;128;value;riscv;Fail +div;flt;64;1;value;riscv;Success; +div;flt;64;2;value;riscv;Fail +div;flt;64;4;value;riscv;Fail +div;flt;64;8;value;riscv;Fail +div;flt;64;16;value;riscv;Fail +div;flt;64;32;value;riscv;Fail +div;flt;64;64;value;riscv;Fail +div;flt;64;128;value;riscv;Fail +mod;int;8;1;value;riscv;Fail +mod;int;8;2;value;riscv;Fail +mod;int;8;4;value;riscv;Fail +mod;int;8;8;value;riscv;Fail +mod;int;8;16;value;riscv;Fail +mod;int;8;32;value;riscv;Fail +mod;int;8;64;value;riscv;Fail +mod;int;8;128;value;riscv;Fail +mod;int;16;1;value;riscv;Fail +mod;int;16;2;value;riscv;Fail +mod;int;16;4;value;riscv;Fail +mod;int;16;8;value;riscv;Fail +mod;int;16;16;value;riscv;Fail +mod;int;16;32;value;riscv;Fail +mod;int;16;64;value;riscv;Fail +mod;int;16;128;value;riscv;Fail +mod;int;32;1;value;riscv;Fail +mod;int;32;2;value;riscv;Fail +mod;int;32;4;value;riscv;Fail +mod;int;32;8;value;riscv;Fail +mod;int;32;16;value;riscv;Fail +mod;int;32;32;value;riscv;Fail +mod;int;32;64;value;riscv;Fail +mod;int;32;128;value;riscv;Fail +mod;int;64;1;value;riscv;Fail +mod;int;64;2;value;riscv;Fail +mod;int;64;4;value;riscv;Fail +mod;int;64;8;value;riscv;Fail +mod;int;64;16;value;riscv;Fail +mod;int;64;32;value;riscv;Fail +mod;int;64;64;value;riscv;Fail +mod;int;64;128;value;riscv;Fail +or;int;8;1;value;riscv;Success; +or;int;8;2;value;riscv;Fail +or;int;8;4;value;riscv;Fail +or;int;8;8;value;riscv;Fail +or;int;8;16;value;riscv;Fail +or;int;8;32;value;riscv;Fail +or;int;8;64;value;riscv;Fail +or;int;8;128;value;riscv;Fail +or;int;16;1;value;riscv;Success; +or;int;16;2;value;riscv;Fail +or;int;16;4;value;riscv;Fail +or;int;16;8;value;riscv;Fail +or;int;16;16;value;riscv;Fail +or;int;16;32;value;riscv;Fail +or;int;16;64;value;riscv;Fail +or;int;16;128;value;riscv;Fail +or;int;32;1;value;riscv;Success; +or;int;32;2;value;riscv;Fail +or;int;32;4;value;riscv;Fail +or;int;32;8;value;riscv;Fail +or;int;32;16;value;riscv;Fail +or;int;32;32;value;riscv;Fail +or;int;32;64;value;riscv;Fail +or;int;32;128;value;riscv;Fail +or;int;64;1;value;riscv;Fail +or;int;64;2;value;riscv;Fail +or;int;64;4;value;riscv;Fail +or;int;64;8;value;riscv;Fail +or;int;64;16;value;riscv;Fail +or;int;64;32;value;riscv;Fail +or;int;64;64;value;riscv;Fail +or;int;64;128;value;riscv;Fail +and;int;8;1;value;riscv;Success; +and;int;8;2;value;riscv;Fail +and;int;8;4;value;riscv;Fail +and;int;8;8;value;riscv;Fail +and;int;8;16;value;riscv;Fail +and;int;8;32;value;riscv;Fail +and;int;8;64;value;riscv;Fail +and;int;8;128;value;riscv;Fail +and;int;16;1;value;riscv;Success; +and;int;16;2;value;riscv;Fail +and;int;16;4;value;riscv;Fail +and;int;16;8;value;riscv;Fail +and;int;16;16;value;riscv;Fail +and;int;16;32;value;riscv;Fail +and;int;16;64;value;riscv;Fail +and;int;16;128;value;riscv;Fail +and;int;32;1;value;riscv;Success; +and;int;32;2;value;riscv;Fail +and;int;32;4;value;riscv;Fail +and;int;32;8;value;riscv;Fail +and;int;32;16;value;riscv;Fail +and;int;32;32;value;riscv;Fail +and;int;32;64;value;riscv;Fail +and;int;32;128;value;riscv;Fail +and;int;64;1;value;riscv;Fail +and;int;64;2;value;riscv;Fail +and;int;64;4;value;riscv;Fail +and;int;64;8;value;riscv;Fail +and;int;64;16;value;riscv;Fail +and;int;64;32;value;riscv;Fail +and;int;64;64;value;riscv;Fail +and;int;64;128;value;riscv;Fail +xor;int;8;1;value;riscv;Success; +xor;int;8;2;value;riscv;Fail +xor;int;8;4;value;riscv;Fail +xor;int;8;8;value;riscv;Fail +xor;int;8;16;value;riscv;Fail +xor;int;8;32;value;riscv;Fail +xor;int;8;64;value;riscv;Fail +xor;int;8;128;value;riscv;Fail +xor;int;16;1;value;riscv;Success; +xor;int;16;2;value;riscv;Fail +xor;int;16;4;value;riscv;Fail +xor;int;16;8;value;riscv;Fail +xor;int;16;16;value;riscv;Fail +xor;int;16;32;value;riscv;Fail +xor;int;16;64;value;riscv;Fail +xor;int;16;128;value;riscv;Fail +xor;int;32;1;value;riscv;Success; +xor;int;32;2;value;riscv;Fail +xor;int;32;4;value;riscv;Fail +xor;int;32;8;value;riscv;Fail +xor;int;32;16;value;riscv;Fail +xor;int;32;32;value;riscv;Fail +xor;int;32;64;value;riscv;Fail +xor;int;32;128;value;riscv;Fail +xor;int;64;1;value;riscv;Fail +xor;int;64;2;value;riscv;Fail +xor;int;64;4;value;riscv;Fail +xor;int;64;8;value;riscv;Fail +xor;int;64;16;value;riscv;Fail +xor;int;64;32;value;riscv;Fail +xor;int;64;64;value;riscv;Fail +xor;int;64;128;value;riscv;Fail +sl;int;8;1;value;riscv;Success; +sl;int;8;2;value;riscv;Fail +sl;int;8;4;value;riscv;Fail +sl;int;8;8;value;riscv;Fail +sl;int;8;16;value;riscv;Fail +sl;int;8;32;value;riscv;Fail +sl;int;8;64;value;riscv;Fail +sl;int;8;128;value;riscv;Fail +sl;int;16;1;value;riscv;Success; +sl;int;16;2;value;riscv;Fail +sl;int;16;4;value;riscv;Fail +sl;int;16;8;value;riscv;Fail +sl;int;16;16;value;riscv;Fail +sl;int;16;32;value;riscv;Fail +sl;int;16;64;value;riscv;Fail +sl;int;16;128;value;riscv;Fail +sl;int;32;1;value;riscv;Success; +sl;int;32;2;value;riscv;Fail +sl;int;32;4;value;riscv;Fail +sl;int;32;8;value;riscv;Fail +sl;int;32;16;value;riscv;Fail +sl;int;32;32;value;riscv;Fail +sl;int;32;64;value;riscv;Fail +sl;int;32;128;value;riscv;Fail +sl;int;64;1;value;riscv;Fail +sl;int;64;2;value;riscv;Fail +sl;int;64;4;value;riscv;Fail +sl;int;64;8;value;riscv;Fail +sl;int;64;16;value;riscv;Fail +sl;int;64;32;value;riscv;Fail +sl;int;64;64;value;riscv;Fail +sl;int;64;128;value;riscv;Fail +sr;int;8;1;value;riscv;Success; +sr;int;8;2;value;riscv;Fail +sr;int;8;4;value;riscv;Fail +sr;int;8;8;value;riscv;Fail +sr;int;8;16;value;riscv;Fail +sr;int;8;32;value;riscv;Fail +sr;int;8;64;value;riscv;Fail +sr;int;8;128;value;riscv;Fail +sr;int;16;1;value;riscv;Success; +sr;int;16;2;value;riscv;Fail +sr;int;16;4;value;riscv;Fail +sr;int;16;8;value;riscv;Fail +sr;int;16;16;value;riscv;Fail +sr;int;16;32;value;riscv;Fail +sr;int;16;64;value;riscv;Fail +sr;int;16;128;value;riscv;Fail +sr;int;32;1;value;riscv;Success; +sr;int;32;2;value;riscv;Fail +sr;int;32;4;value;riscv;Fail +sr;int;32;8;value;riscv;Fail +sr;int;32;16;value;riscv;Fail +sr;int;32;32;value;riscv;Fail +sr;int;32;64;value;riscv;Fail +sr;int;32;128;value;riscv;Fail +sr;int;64;1;value;riscv;Fail +sr;int;64;2;value;riscv;Fail +sr;int;64;4;value;riscv;Fail +sr;int;64;8;value;riscv;Fail +sr;int;64;16;value;riscv;Fail +sr;int;64;32;value;riscv;Fail +sr;int;64;64;value;riscv;Fail +sr;int;64;128;value;riscv;Fail +add;int;8;1;value;power;Success; +add;int;8;2;value;power;Fail +add;int;8;4;value;power;Fail +add;int;8;8;value;power;Fail +add;int;8;16;value;power;Fail +add;int;8;32;value;power;Fail +add;int;8;64;value;power;Fail +add;int;8;128;value;power;Fail +add;int;16;1;value;power;Success; +add;int;16;2;value;power;Fail +add;int;16;4;value;power;Fail +add;int;16;8;value;power;Fail +add;int;16;16;value;power;Fail +add;int;16;32;value;power;Fail +add;int;16;64;value;power;Fail +add;int;16;128;value;power;Fail +add;int;32;1;value;power;Success; +add;int;32;2;value;power;Fail +add;int;32;4;value;power;Fail +add;int;32;8;value;power;Fail +add;int;32;16;value;power;Fail +add;int;32;32;value;power;Fail +add;int;32;64;value;power;Fail +add;int;32;128;value;power;Fail +add;int;64;1;value;power;Fail +add;int;64;2;value;power;Fail +add;int;64;4;value;power;Fail +add;int;64;8;value;power;Fail +add;int;64;16;value;power;Fail +add;int;64;32;value;power;Fail +add;int;64;64;value;power;Fail +add;int;64;128;value;power;Fail +mul;int;8;1;value;power;Success; +mul;int;8;2;value;power;Fail +mul;int;8;4;value;power;Fail +mul;int;8;8;value;power;Fail +mul;int;8;16;value;power;Fail +mul;int;8;32;value;power;Fail +mul;int;8;64;value;power;Fail +mul;int;8;128;value;power;Fail +mul;int;16;1;value;power;Success; +mul;int;16;2;value;power;Fail +mul;int;16;4;value;power;Fail +mul;int;16;8;value;power;Fail +mul;int;16;16;value;power;Fail +mul;int;16;32;value;power;Fail +mul;int;16;64;value;power;Fail +mul;int;16;128;value;power;Fail +mul;int;32;1;value;power;Success; +mul;int;32;2;value;power;Fail +mul;int;32;4;value;power;Fail +mul;int;32;8;value;power;Fail +mul;int;32;16;value;power;Fail +mul;int;32;32;value;power;Fail +mul;int;32;64;value;power;Fail +mul;int;32;128;value;power;Fail +mul;int;64;1;value;power;Fail +mul;int;64;2;value;power;Fail +mul;int;64;4;value;power;Fail +mul;int;64;8;value;power;Fail +mul;int;64;16;value;power;Fail +mul;int;64;32;value;power;Fail +mul;int;64;64;value;power;Fail +mul;int;64;128;value;power;Fail +sub;int;8;1;value;power;Success; +sub;int;8;2;value;power;Fail +sub;int;8;4;value;power;Fail +sub;int;8;8;value;power;Fail +sub;int;8;16;value;power;Fail +sub;int;8;32;value;power;Fail +sub;int;8;64;value;power;Fail +sub;int;8;128;value;power;Fail +sub;int;16;1;value;power;Success; +sub;int;16;2;value;power;Fail +sub;int;16;4;value;power;Fail +sub;int;16;8;value;power;Fail +sub;int;16;16;value;power;Fail +sub;int;16;32;value;power;Fail +sub;int;16;64;value;power;Fail +sub;int;16;128;value;power;Fail +sub;int;32;1;value;power;Success; +sub;int;32;2;value;power;Fail +sub;int;32;4;value;power;Fail +sub;int;32;8;value;power;Fail +sub;int;32;16;value;power;Fail +sub;int;32;32;value;power;Fail +sub;int;32;64;value;power;Fail +sub;int;32;128;value;power;Fail +sub;int;64;1;value;power;Fail +sub;int;64;2;value;power;Fail +sub;int;64;4;value;power;Fail +sub;int;64;8;value;power;Fail +sub;int;64;16;value;power;Fail +sub;int;64;32;value;power;Fail +sub;int;64;64;value;power;Fail +sub;int;64;128;value;power;Fail +div;int;8;1;value;power;Success; +div;int;8;2;value;power;Fail +div;int;8;4;value;power;Fail +div;int;8;8;value;power;Fail +div;int;8;16;value;power;Fail +div;int;8;32;value;power;Fail +div;int;8;64;value;power;Fail +div;int;8;128;value;power;Fail +div;int;16;1;value;power;Success; +div;int;16;2;value;power;Fail +div;int;16;4;value;power;Fail +div;int;16;8;value;power;Fail +div;int;16;16;value;power;Fail +div;int;16;32;value;power;Fail +div;int;16;64;value;power;Fail +div;int;16;128;value;power;Fail +div;int;32;1;value;power;Success; +div;int;32;2;value;power;Fail +div;int;32;4;value;power;Fail +div;int;32;8;value;power;Fail +div;int;32;16;value;power;Fail +div;int;32;32;value;power;Fail +div;int;32;64;value;power;Fail +div;int;32;128;value;power;Fail +div;int;64;1;value;power;Fail +div;int;64;2;value;power;Fail +div;int;64;4;value;power;Fail +div;int;64;8;value;power;Fail +div;int;64;16;value;power;Fail +div;int;64;32;value;power;Fail +div;int;64;64;value;power;Fail +div;int;64;128;value;power;Fail +add;flt;32;1;value;power;Success; +add;flt;32;2;value;power;Fail +add;flt;32;4;value;power;Fail +add;flt;32;8;value;power;Fail +add;flt;32;16;value;power;Fail +add;flt;32;32;value;power;Fail +add;flt;32;64;value;power;Fail +add;flt;32;128;value;power;Fail +add;flt;64;1;value;power;Success; +add;flt;64;2;value;power;Fail +add;flt;64;4;value;power;Fail +add;flt;64;8;value;power;Fail +add;flt;64;16;value;power;Fail +add;flt;64;32;value;power;Fail +add;flt;64;64;value;power;Fail +add;flt;64;128;value;power;Fail +mul;flt;32;1;value;power;Success; +mul;flt;32;2;value;power;Fail +mul;flt;32;4;value;power;Fail +mul;flt;32;8;value;power;Fail +mul;flt;32;16;value;power;Fail +mul;flt;32;32;value;power;Fail +mul;flt;32;64;value;power;Fail +mul;flt;32;128;value;power;Fail +mul;flt;64;1;value;power;Success; +mul;flt;64;2;value;power;Fail +mul;flt;64;4;value;power;Fail +mul;flt;64;8;value;power;Fail +mul;flt;64;16;value;power;Fail +mul;flt;64;32;value;power;Fail +mul;flt;64;64;value;power;Fail +mul;flt;64;128;value;power;Fail +sub;flt;32;1;value;power;Success; +sub;flt;32;2;value;power;Fail +sub;flt;32;4;value;power;Fail +sub;flt;32;8;value;power;Fail +sub;flt;32;16;value;power;Fail +sub;flt;32;32;value;power;Fail +sub;flt;32;64;value;power;Fail +sub;flt;32;128;value;power;Fail +sub;flt;64;1;value;power;Success; +sub;flt;64;2;value;power;Fail +sub;flt;64;4;value;power;Fail +sub;flt;64;8;value;power;Fail +sub;flt;64;16;value;power;Fail +sub;flt;64;32;value;power;Fail +sub;flt;64;64;value;power;Fail +sub;flt;64;128;value;power;Fail +div;flt;32;1;value;power;Success; +div;flt;32;2;value;power;Fail +div;flt;32;4;value;power;Fail +div;flt;32;8;value;power;Fail +div;flt;32;16;value;power;Fail +div;flt;32;32;value;power;Fail +div;flt;32;64;value;power;Fail +div;flt;32;128;value;power;Fail +div;flt;64;1;value;power;Success; +div;flt;64;2;value;power;Fail +div;flt;64;4;value;power;Fail +div;flt;64;8;value;power;Fail +div;flt;64;16;value;power;Fail +div;flt;64;32;value;power;Fail +div;flt;64;64;value;power;Fail +div;flt;64;128;value;power;Fail +mod;int;8;1;value;power;Fail +mod;int;8;2;value;power;Fail +mod;int;8;4;value;power;Fail +mod;int;8;8;value;power;Fail +mod;int;8;16;value;power;Fail +mod;int;8;32;value;power;Fail +mod;int;8;64;value;power;Fail +mod;int;8;128;value;power;Fail +mod;int;16;1;value;power;Fail +mod;int;16;2;value;power;Fail +mod;int;16;4;value;power;Fail +mod;int;16;8;value;power;Fail +mod;int;16;16;value;power;Fail +mod;int;16;32;value;power;Fail +mod;int;16;64;value;power;Fail +mod;int;16;128;value;power;Fail +mod;int;32;1;value;power;Fail +mod;int;32;2;value;power;Fail +mod;int;32;4;value;power;Fail +mod;int;32;8;value;power;Fail +mod;int;32;16;value;power;Fail +mod;int;32;32;value;power;Fail +mod;int;32;64;value;power;Fail +mod;int;32;128;value;power;Fail +mod;int;64;1;value;power;Fail +mod;int;64;2;value;power;Fail +mod;int;64;4;value;power;Fail +mod;int;64;8;value;power;Fail +mod;int;64;16;value;power;Fail +mod;int;64;32;value;power;Fail +mod;int;64;64;value;power;Fail +mod;int;64;128;value;power;Fail +or;int;8;1;value;power;Success; +or;int;8;2;value;power;Fail +or;int;8;4;value;power;Fail +or;int;8;8;value;power;Fail +or;int;8;16;value;power;Fail +or;int;8;32;value;power;Fail +or;int;8;64;value;power;Fail +or;int;8;128;value;power;Fail +or;int;16;1;value;power;Success; +or;int;16;2;value;power;Fail +or;int;16;4;value;power;Fail +or;int;16;8;value;power;Fail +or;int;16;16;value;power;Fail +or;int;16;32;value;power;Fail +or;int;16;64;value;power;Fail +or;int;16;128;value;power;Fail +or;int;32;1;value;power;Success; +or;int;32;2;value;power;Fail +or;int;32;4;value;power;Fail +or;int;32;8;value;power;Fail +or;int;32;16;value;power;Fail +or;int;32;32;value;power;Fail +or;int;32;64;value;power;Fail +or;int;32;128;value;power;Fail +or;int;64;1;value;power;Fail +or;int;64;2;value;power;Fail +or;int;64;4;value;power;Fail +or;int;64;8;value;power;Fail +or;int;64;16;value;power;Fail +or;int;64;32;value;power;Fail +or;int;64;64;value;power;Fail +or;int;64;128;value;power;Fail +and;int;8;1;value;power;Success; +and;int;8;2;value;power;Fail +and;int;8;4;value;power;Fail +and;int;8;8;value;power;Fail +and;int;8;16;value;power;Fail +and;int;8;32;value;power;Fail +and;int;8;64;value;power;Fail +and;int;8;128;value;power;Fail +and;int;16;1;value;power;Success; +and;int;16;2;value;power;Fail +and;int;16;4;value;power;Fail +and;int;16;8;value;power;Fail +and;int;16;16;value;power;Fail +and;int;16;32;value;power;Fail +and;int;16;64;value;power;Fail +and;int;16;128;value;power;Fail +and;int;32;1;value;power;Success; +and;int;32;2;value;power;Fail +and;int;32;4;value;power;Fail +and;int;32;8;value;power;Fail +and;int;32;16;value;power;Fail +and;int;32;32;value;power;Fail +and;int;32;64;value;power;Fail +and;int;32;128;value;power;Fail +and;int;64;1;value;power;Fail +and;int;64;2;value;power;Fail +and;int;64;4;value;power;Fail +and;int;64;8;value;power;Fail +and;int;64;16;value;power;Fail +and;int;64;32;value;power;Fail +and;int;64;64;value;power;Fail +and;int;64;128;value;power;Fail +xor;int;8;1;value;power;Success; +xor;int;8;2;value;power;Fail +xor;int;8;4;value;power;Fail +xor;int;8;8;value;power;Fail +xor;int;8;16;value;power;Fail +xor;int;8;32;value;power;Fail +xor;int;8;64;value;power;Fail +xor;int;8;128;value;power;Fail +xor;int;16;1;value;power;Success; +xor;int;16;2;value;power;Fail +xor;int;16;4;value;power;Fail +xor;int;16;8;value;power;Fail +xor;int;16;16;value;power;Fail +xor;int;16;32;value;power;Fail +xor;int;16;64;value;power;Fail +xor;int;16;128;value;power;Fail +xor;int;32;1;value;power;Success; +xor;int;32;2;value;power;Fail +xor;int;32;4;value;power;Fail +xor;int;32;8;value;power;Fail +xor;int;32;16;value;power;Fail +xor;int;32;32;value;power;Fail +xor;int;32;64;value;power;Fail +xor;int;32;128;value;power;Fail +xor;int;64;1;value;power;Fail +xor;int;64;2;value;power;Fail +xor;int;64;4;value;power;Fail +xor;int;64;8;value;power;Fail +xor;int;64;16;value;power;Fail +xor;int;64;32;value;power;Fail +xor;int;64;64;value;power;Fail +xor;int;64;128;value;power;Fail +sl;int;8;1;value;power;Success; +sl;int;8;2;value;power;Fail +sl;int;8;4;value;power;Fail +sl;int;8;8;value;power;Fail +sl;int;8;16;value;power;Fail +sl;int;8;32;value;power;Fail +sl;int;8;64;value;power;Fail +sl;int;8;128;value;power;Fail +sl;int;16;1;value;power;Success; +sl;int;16;2;value;power;Fail +sl;int;16;4;value;power;Fail +sl;int;16;8;value;power;Fail +sl;int;16;16;value;power;Fail +sl;int;16;32;value;power;Fail +sl;int;16;64;value;power;Fail +sl;int;16;128;value;power;Fail +sl;int;32;1;value;power;Success; +sl;int;32;2;value;power;Fail +sl;int;32;4;value;power;Fail +sl;int;32;8;value;power;Fail +sl;int;32;16;value;power;Fail +sl;int;32;32;value;power;Fail +sl;int;32;64;value;power;Fail +sl;int;32;128;value;power;Fail +sl;int;64;1;value;power;Fail +sl;int;64;2;value;power;Fail +sl;int;64;4;value;power;Fail +sl;int;64;8;value;power;Fail +sl;int;64;16;value;power;Fail +sl;int;64;32;value;power;Fail +sl;int;64;64;value;power;Fail +sl;int;64;128;value;power;Fail +sr;int;8;1;value;power;Fail +sr;int;8;2;value;power;Fail +sr;int;8;4;value;power;Fail +sr;int;8;8;value;power;Fail +sr;int;8;16;value;power;Fail +sr;int;8;32;value;power;Fail +sr;int;8;64;value;power;Fail +sr;int;8;128;value;power;Fail +sr;int;16;1;value;power;Fail +sr;int;16;2;value;power;Fail +sr;int;16;4;value;power;Fail +sr;int;16;8;value;power;Fail +sr;int;16;16;value;power;Fail +sr;int;16;32;value;power;Fail +sr;int;16;64;value;power;Fail +sr;int;16;128;value;power;Fail +sr;int;32;1;value;power;Fail +sr;int;32;2;value;power;Fail +sr;int;32;4;value;power;Fail +sr;int;32;8;value;power;Fail +sr;int;32;16;value;power;Fail +sr;int;32;32;value;power;Fail +sr;int;32;64;value;power;Fail +sr;int;32;128;value;power;Fail +sr;int;64;1;value;power;Fail +sr;int;64;2;value;power;Fail +sr;int;64;4;value;power;Fail +sr;int;64;8;value;power;Fail +sr;int;64;16;value;power;Fail +sr;int;64;32;value;power;Fail +sr;int;64;64;value;power;Fail +sr;int;64;128;value;power;Fail +add;int;8;1;address;aarch64;Fail +add;int;8;2;address;aarch64;Fail +add;int;8;4;address;aarch64;Fail +add;int;8;8;address;aarch64;Success; +add;int;8;16;address;aarch64;Success; +add;int;8;32;address;aarch64;Fail +add;int;8;64;address;aarch64;Fail +add;int;8;128;address;aarch64;Fail +add;int;16;1;address;aarch64;Fail +add;int;16;2;address;aarch64;Fail +add;int;16;4;address;aarch64;Success; +add;int;16;8;address;aarch64;Success; +add;int;16;16;address;aarch64;Fail +add;int;16;32;address;aarch64;Fail +add;int;16;64;address;aarch64;Fail +add;int;16;128;address;aarch64;Fail +add;int;32;1;address;aarch64;Fail +add;int;32;2;address;aarch64;Success; +add;int;32;4;address;aarch64;Success; +add;int;32;8;address;aarch64;Fail +add;int;32;16;address;aarch64;Fail +add;int;32;32;address;aarch64;Fail +add;int;32;64;address;aarch64;Fail +add;int;32;128;address;aarch64;Fail +add;int;64;1;address;aarch64;Fail +add;int;64;2;address;aarch64;Fail +add;int;64;4;address;aarch64;Fail +add;int;64;8;address;aarch64;Fail +add;int;64;16;address;aarch64;Fail +add;int;64;32;address;aarch64;Fail +add;int;64;64;address;aarch64;Fail +add;int;64;128;address;aarch64;Fail +mul;int;8;1;address;aarch64;Fail +mul;int;8;2;address;aarch64;Fail +mul;int;8;4;address;aarch64;Fail +mul;int;8;8;address;aarch64;Fail +mul;int;8;16;address;aarch64;Fail +mul;int;8;32;address;aarch64;Fail +mul;int;8;64;address;aarch64;Fail +mul;int;8;128;address;aarch64;Fail +mul;int;16;1;address;aarch64;Fail +mul;int;16;2;address;aarch64;Fail +mul;int;16;4;address;aarch64;Success; +mul;int;16;8;address;aarch64;Success; +mul;int;16;16;address;aarch64;Fail +mul;int;16;32;address;aarch64;Fail +mul;int;16;64;address;aarch64;Fail +mul;int;16;128;address;aarch64;Fail +mul;int;32;1;address;aarch64;Fail +mul;int;32;2;address;aarch64;Success; +mul;int;32;4;address;aarch64;Success; +mul;int;32;8;address;aarch64;Fail +mul;int;32;16;address;aarch64;Fail +mul;int;32;32;address;aarch64;Fail +mul;int;32;64;address;aarch64;Fail +mul;int;32;128;address;aarch64;Fail +mul;int;64;1;address;aarch64;Fail +mul;int;64;2;address;aarch64;Fail +mul;int;64;4;address;aarch64;Fail +mul;int;64;8;address;aarch64;Fail +mul;int;64;16;address;aarch64;Fail +mul;int;64;32;address;aarch64;Fail +mul;int;64;64;address;aarch64;Fail +mul;int;64;128;address;aarch64;Fail +sub;int;8;1;address;aarch64;Fail +sub;int;8;2;address;aarch64;Fail +sub;int;8;4;address;aarch64;Fail +sub;int;8;8;address;aarch64;Success; +sub;int;8;16;address;aarch64;Success; +sub;int;8;32;address;aarch64;Fail +sub;int;8;64;address;aarch64;Fail +sub;int;8;128;address;aarch64;Fail +sub;int;16;1;address;aarch64;Fail +sub;int;16;2;address;aarch64;Fail +sub;int;16;4;address;aarch64;Success; +sub;int;16;8;address;aarch64;Success; +sub;int;16;16;address;aarch64;Fail +sub;int;16;32;address;aarch64;Fail +sub;int;16;64;address;aarch64;Fail +sub;int;16;128;address;aarch64;Fail +sub;int;32;1;address;aarch64;Fail +sub;int;32;2;address;aarch64;Success; +sub;int;32;4;address;aarch64;Success; +sub;int;32;8;address;aarch64;Fail +sub;int;32;16;address;aarch64;Fail +sub;int;32;32;address;aarch64;Fail +sub;int;32;64;address;aarch64;Fail +sub;int;32;128;address;aarch64;Fail +sub;int;64;1;address;aarch64;Fail +sub;int;64;2;address;aarch64;Fail +sub;int;64;4;address;aarch64;Fail +sub;int;64;8;address;aarch64;Fail +sub;int;64;16;address;aarch64;Fail +sub;int;64;32;address;aarch64;Fail +sub;int;64;64;address;aarch64;Fail +sub;int;64;128;address;aarch64;Fail +div;int;8;1;address;aarch64;Fail +div;int;8;2;address;aarch64;Fail +div;int;8;4;address;aarch64;Fail +div;int;8;8;address;aarch64;Fail +div;int;8;16;address;aarch64;Fail +div;int;8;32;address;aarch64;Fail +div;int;8;64;address;aarch64;Fail +div;int;8;128;address;aarch64;Fail +div;int;16;1;address;aarch64;Fail +div;int;16;2;address;aarch64;Fail +div;int;16;4;address;aarch64;Fail +div;int;16;8;address;aarch64;Fail +div;int;16;16;address;aarch64;Fail +div;int;16;32;address;aarch64;Fail +div;int;16;64;address;aarch64;Fail +div;int;16;128;address;aarch64;Fail +div;int;32;1;address;aarch64;Fail +div;int;32;2;address;aarch64;Fail +div;int;32;4;address;aarch64;Fail +div;int;32;8;address;aarch64;Fail +div;int;32;16;address;aarch64;Fail +div;int;32;32;address;aarch64;Fail +div;int;32;64;address;aarch64;Fail +div;int;32;128;address;aarch64;Fail +div;int;64;1;address;aarch64;Fail +div;int;64;2;address;aarch64;Fail +div;int;64;4;address;aarch64;Fail +div;int;64;8;address;aarch64;Fail +div;int;64;16;address;aarch64;Fail +div;int;64;32;address;aarch64;Fail +div;int;64;64;address;aarch64;Fail +div;int;64;128;address;aarch64;Fail +add;flt;32;1;address;aarch64;Fail +add;flt;32;2;address;aarch64;Fail +add;flt;32;4;address;aarch64;Fail +add;flt;32;8;address;aarch64;Fail +add;flt;32;16;address;aarch64;Fail +add;flt;32;32;address;aarch64;Fail +add;flt;32;64;address;aarch64;Fail +add;flt;32;128;address;aarch64;Fail +add;flt;64;1;address;aarch64;Fail +add;flt;64;2;address;aarch64;Fail +add;flt;64;4;address;aarch64;Fail +add;flt;64;8;address;aarch64;Fail +add;flt;64;16;address;aarch64;Fail +add;flt;64;32;address;aarch64;Fail +add;flt;64;64;address;aarch64;Fail +add;flt;64;128;address;aarch64;Fail +mul;flt;32;1;address;aarch64;Fail +mul;flt;32;2;address;aarch64;Fail +mul;flt;32;4;address;aarch64;Fail +mul;flt;32;8;address;aarch64;Fail +mul;flt;32;16;address;aarch64;Fail +mul;flt;32;32;address;aarch64;Fail +mul;flt;32;64;address;aarch64;Fail +mul;flt;32;128;address;aarch64;Fail +mul;flt;64;1;address;aarch64;Fail +mul;flt;64;2;address;aarch64;Fail +mul;flt;64;4;address;aarch64;Fail +mul;flt;64;8;address;aarch64;Fail +mul;flt;64;16;address;aarch64;Fail +mul;flt;64;32;address;aarch64;Fail +mul;flt;64;64;address;aarch64;Fail +mul;flt;64;128;address;aarch64;Fail +sub;flt;32;1;address;aarch64;Fail +sub;flt;32;2;address;aarch64;Fail +sub;flt;32;4;address;aarch64;Fail +sub;flt;32;8;address;aarch64;Fail +sub;flt;32;16;address;aarch64;Fail +sub;flt;32;32;address;aarch64;Fail +sub;flt;32;64;address;aarch64;Fail +sub;flt;32;128;address;aarch64;Fail +sub;flt;64;1;address;aarch64;Fail +sub;flt;64;2;address;aarch64;Fail +sub;flt;64;4;address;aarch64;Fail +sub;flt;64;8;address;aarch64;Fail +sub;flt;64;16;address;aarch64;Fail +sub;flt;64;32;address;aarch64;Fail +sub;flt;64;64;address;aarch64;Fail +sub;flt;64;128;address;aarch64;Fail +div;flt;32;1;address;aarch64;Fail +div;flt;32;2;address;aarch64;Fail +div;flt;32;4;address;aarch64;Fail +div;flt;32;8;address;aarch64;Fail +div;flt;32;16;address;aarch64;Fail +div;flt;32;32;address;aarch64;Fail +div;flt;32;64;address;aarch64;Fail +div;flt;32;128;address;aarch64;Fail +div;flt;64;1;address;aarch64;Fail +div;flt;64;2;address;aarch64;Fail +div;flt;64;4;address;aarch64;Fail +div;flt;64;8;address;aarch64;Fail +div;flt;64;16;address;aarch64;Fail +div;flt;64;32;address;aarch64;Fail +div;flt;64;64;address;aarch64;Fail +div;flt;64;128;address;aarch64;Fail +mod;int;8;1;address;aarch64;Fail +mod;int;8;2;address;aarch64;Fail +mod;int;8;4;address;aarch64;Fail +mod;int;8;8;address;aarch64;Fail +mod;int;8;16;address;aarch64;Fail +mod;int;8;32;address;aarch64;Fail +mod;int;8;64;address;aarch64;Fail +mod;int;8;128;address;aarch64;Fail +mod;int;16;1;address;aarch64;Fail +mod;int;16;2;address;aarch64;Fail +mod;int;16;4;address;aarch64;Fail +mod;int;16;8;address;aarch64;Fail +mod;int;16;16;address;aarch64;Fail +mod;int;16;32;address;aarch64;Fail +mod;int;16;64;address;aarch64;Fail +mod;int;16;128;address;aarch64;Fail +mod;int;32;1;address;aarch64;Fail +mod;int;32;2;address;aarch64;Fail +mod;int;32;4;address;aarch64;Fail +mod;int;32;8;address;aarch64;Fail +mod;int;32;16;address;aarch64;Fail +mod;int;32;32;address;aarch64;Fail +mod;int;32;64;address;aarch64;Fail +mod;int;32;128;address;aarch64;Fail +mod;int;64;1;address;aarch64;Fail +mod;int;64;2;address;aarch64;Fail +mod;int;64;4;address;aarch64;Fail +mod;int;64;8;address;aarch64;Fail +mod;int;64;16;address;aarch64;Fail +mod;int;64;32;address;aarch64;Fail +mod;int;64;64;address;aarch64;Fail +mod;int;64;128;address;aarch64;Fail +or;int;8;1;address;aarch64;Fail +or;int;8;2;address;aarch64;Fail +or;int;8;4;address;aarch64;Fail +or;int;8;8;address;aarch64;Success; +or;int;8;16;address;aarch64;Success; +or;int;8;32;address;aarch64;Fail +or;int;8;64;address;aarch64;Fail +or;int;8;128;address;aarch64;Fail +or;int;16;1;address;aarch64;Fail +or;int;16;2;address;aarch64;Fail +or;int;16;4;address;aarch64;Success; +or;int;16;8;address;aarch64;Success; +or;int;16;16;address;aarch64;Fail +or;int;16;32;address;aarch64;Fail +or;int;16;64;address;aarch64;Fail +or;int;16;128;address;aarch64;Fail +or;int;32;1;address;aarch64;Fail +or;int;32;2;address;aarch64;Success; +or;int;32;4;address;aarch64;Success; +or;int;32;8;address;aarch64;Fail +or;int;32;16;address;aarch64;Fail +or;int;32;32;address;aarch64;Fail +or;int;32;64;address;aarch64;Fail +or;int;32;128;address;aarch64;Fail +or;int;64;1;address;aarch64;Fail +or;int;64;2;address;aarch64;Fail +or;int;64;4;address;aarch64;Fail +or;int;64;8;address;aarch64;Fail +or;int;64;16;address;aarch64;Fail +or;int;64;32;address;aarch64;Fail +or;int;64;64;address;aarch64;Fail +or;int;64;128;address;aarch64;Fail +and;int;8;1;address;aarch64;Fail +and;int;8;2;address;aarch64;Fail +and;int;8;4;address;aarch64;Fail +and;int;8;8;address;aarch64;Success; +and;int;8;16;address;aarch64;Success; +and;int;8;32;address;aarch64;Fail +and;int;8;64;address;aarch64;Fail +and;int;8;128;address;aarch64;Fail +and;int;16;1;address;aarch64;Fail +and;int;16;2;address;aarch64;Fail +and;int;16;4;address;aarch64;Success; +and;int;16;8;address;aarch64;Success; +and;int;16;16;address;aarch64;Fail +and;int;16;32;address;aarch64;Fail +and;int;16;64;address;aarch64;Fail +and;int;16;128;address;aarch64;Fail +and;int;32;1;address;aarch64;Fail +and;int;32;2;address;aarch64;Success; +and;int;32;4;address;aarch64;Success; +and;int;32;8;address;aarch64;Fail +and;int;32;16;address;aarch64;Fail +and;int;32;32;address;aarch64;Fail +and;int;32;64;address;aarch64;Fail +and;int;32;128;address;aarch64;Fail +and;int;64;1;address;aarch64;Fail +and;int;64;2;address;aarch64;Fail +and;int;64;4;address;aarch64;Fail +and;int;64;8;address;aarch64;Fail +and;int;64;16;address;aarch64;Fail +and;int;64;32;address;aarch64;Fail +and;int;64;64;address;aarch64;Fail +and;int;64;128;address;aarch64;Fail +xor;int;8;1;address;aarch64;Fail +xor;int;8;2;address;aarch64;Fail +xor;int;8;4;address;aarch64;Fail +xor;int;8;8;address;aarch64;Success; +xor;int;8;16;address;aarch64;Success; +xor;int;8;32;address;aarch64;Fail +xor;int;8;64;address;aarch64;Fail +xor;int;8;128;address;aarch64;Fail +xor;int;16;1;address;aarch64;Fail +xor;int;16;2;address;aarch64;Fail +xor;int;16;4;address;aarch64;Success; +xor;int;16;8;address;aarch64;Success; +xor;int;16;16;address;aarch64;Fail +xor;int;16;32;address;aarch64;Fail +xor;int;16;64;address;aarch64;Fail +xor;int;16;128;address;aarch64;Fail +xor;int;32;1;address;aarch64;Fail +xor;int;32;2;address;aarch64;Success; +xor;int;32;4;address;aarch64;Success; +xor;int;32;8;address;aarch64;Fail +xor;int;32;16;address;aarch64;Fail +xor;int;32;32;address;aarch64;Fail +xor;int;32;64;address;aarch64;Fail +xor;int;32;128;address;aarch64;Fail +xor;int;64;1;address;aarch64;Fail +xor;int;64;2;address;aarch64;Fail +xor;int;64;4;address;aarch64;Fail +xor;int;64;8;address;aarch64;Fail +xor;int;64;16;address;aarch64;Fail +xor;int;64;32;address;aarch64;Fail +xor;int;64;64;address;aarch64;Fail +xor;int;64;128;address;aarch64;Fail +sl;int;8;1;address;aarch64;Fail +sl;int;8;2;address;aarch64;Fail +sl;int;8;4;address;aarch64;Fail +sl;int;8;8;address;aarch64;Fail +sl;int;8;16;address;aarch64;Fail +sl;int;8;32;address;aarch64;Fail +sl;int;8;64;address;aarch64;Fail +sl;int;8;128;address;aarch64;Fail +sl;int;16;1;address;aarch64;Fail +sl;int;16;2;address;aarch64;Fail +sl;int;16;4;address;aarch64;Fail +sl;int;16;8;address;aarch64;Fail +sl;int;16;16;address;aarch64;Fail +sl;int;16;32;address;aarch64;Fail +sl;int;16;64;address;aarch64;Fail +sl;int;16;128;address;aarch64;Fail +sl;int;32;1;address;aarch64;Fail +sl;int;32;2;address;aarch64;Fail +sl;int;32;4;address;aarch64;Fail +sl;int;32;8;address;aarch64;Fail +sl;int;32;16;address;aarch64;Fail +sl;int;32;32;address;aarch64;Fail +sl;int;32;64;address;aarch64;Fail +sl;int;32;128;address;aarch64;Fail +sl;int;64;1;address;aarch64;Fail +sl;int;64;2;address;aarch64;Fail +sl;int;64;4;address;aarch64;Fail +sl;int;64;8;address;aarch64;Fail +sl;int;64;16;address;aarch64;Fail +sl;int;64;32;address;aarch64;Fail +sl;int;64;64;address;aarch64;Fail +sl;int;64;128;address;aarch64;Fail +sr;int;8;1;address;aarch64;Fail +sr;int;8;2;address;aarch64;Fail +sr;int;8;4;address;aarch64;Fail +sr;int;8;8;address;aarch64;Fail +sr;int;8;16;address;aarch64;Fail +sr;int;8;32;address;aarch64;Fail +sr;int;8;64;address;aarch64;Fail +sr;int;8;128;address;aarch64;Fail +sr;int;16;1;address;aarch64;Fail +sr;int;16;2;address;aarch64;Fail +sr;int;16;4;address;aarch64;Fail +sr;int;16;8;address;aarch64;Fail +sr;int;16;16;address;aarch64;Fail +sr;int;16;32;address;aarch64;Fail +sr;int;16;64;address;aarch64;Fail +sr;int;16;128;address;aarch64;Fail +sr;int;32;1;address;aarch64;Fail +sr;int;32;2;address;aarch64;Fail +sr;int;32;4;address;aarch64;Fail +sr;int;32;8;address;aarch64;Fail +sr;int;32;16;address;aarch64;Fail +sr;int;32;32;address;aarch64;Fail +sr;int;32;64;address;aarch64;Fail +sr;int;32;128;address;aarch64;Fail +sr;int;64;1;address;aarch64;Fail +sr;int;64;2;address;aarch64;Fail +sr;int;64;4;address;aarch64;Fail +sr;int;64;8;address;aarch64;Fail +sr;int;64;16;address;aarch64;Fail +sr;int;64;32;address;aarch64;Fail +sr;int;64;64;address;aarch64;Fail +sr;int;64;128;address;aarch64;Fail +add;int;8;1;address;riscv;Fail +add;int;8;2;address;riscv;Fail +add;int;8;4;address;riscv;Fail +add;int;8;8;address;riscv;Fail +add;int;8;16;address;riscv;Fail +add;int;8;32;address;riscv;Fail +add;int;8;64;address;riscv;Fail +add;int;8;128;address;riscv;Fail +add;int;16;1;address;riscv;Fail +add;int;16;2;address;riscv;Fail +add;int;16;4;address;riscv;Fail +add;int;16;8;address;riscv;Fail +add;int;16;16;address;riscv;Fail +add;int;16;32;address;riscv;Fail +add;int;16;64;address;riscv;Fail +add;int;16;128;address;riscv;Fail +add;int;32;1;address;riscv;Fail +add;int;32;2;address;riscv;Fail +add;int;32;4;address;riscv;Fail +add;int;32;8;address;riscv;Fail +add;int;32;16;address;riscv;Fail +add;int;32;32;address;riscv;Fail +add;int;32;64;address;riscv;Fail +add;int;32;128;address;riscv;Fail +add;int;64;1;address;riscv;Fail +add;int;64;2;address;riscv;Fail +add;int;64;4;address;riscv;Fail +add;int;64;8;address;riscv;Fail +add;int;64;16;address;riscv;Fail +add;int;64;32;address;riscv;Fail +add;int;64;64;address;riscv;Fail +add;int;64;128;address;riscv;Fail +mul;int;8;1;address;riscv;Fail +mul;int;8;2;address;riscv;Fail +mul;int;8;4;address;riscv;Fail +mul;int;8;8;address;riscv;Fail +mul;int;8;16;address;riscv;Fail +mul;int;8;32;address;riscv;Fail +mul;int;8;64;address;riscv;Fail +mul;int;8;128;address;riscv;Fail +mul;int;16;1;address;riscv;Fail +mul;int;16;2;address;riscv;Fail +mul;int;16;4;address;riscv;Fail +mul;int;16;8;address;riscv;Fail +mul;int;16;16;address;riscv;Fail +mul;int;16;32;address;riscv;Fail +mul;int;16;64;address;riscv;Fail +mul;int;16;128;address;riscv;Fail +mul;int;32;1;address;riscv;Fail +mul;int;32;2;address;riscv;Fail +mul;int;32;4;address;riscv;Fail +mul;int;32;8;address;riscv;Fail +mul;int;32;16;address;riscv;Fail +mul;int;32;32;address;riscv;Fail +mul;int;32;64;address;riscv;Fail +mul;int;32;128;address;riscv;Fail +mul;int;64;1;address;riscv;Fail +mul;int;64;2;address;riscv;Fail +mul;int;64;4;address;riscv;Fail +mul;int;64;8;address;riscv;Fail +mul;int;64;16;address;riscv;Fail +mul;int;64;32;address;riscv;Fail +mul;int;64;64;address;riscv;Fail +mul;int;64;128;address;riscv;Fail +sub;int;8;1;address;riscv;Fail +sub;int;8;2;address;riscv;Fail +sub;int;8;4;address;riscv;Fail +sub;int;8;8;address;riscv;Fail +sub;int;8;16;address;riscv;Fail +sub;int;8;32;address;riscv;Fail +sub;int;8;64;address;riscv;Fail +sub;int;8;128;address;riscv;Fail +sub;int;16;1;address;riscv;Fail +sub;int;16;2;address;riscv;Fail +sub;int;16;4;address;riscv;Fail +sub;int;16;8;address;riscv;Fail +sub;int;16;16;address;riscv;Fail +sub;int;16;32;address;riscv;Fail +sub;int;16;64;address;riscv;Fail +sub;int;16;128;address;riscv;Fail +sub;int;32;1;address;riscv;Fail +sub;int;32;2;address;riscv;Fail +sub;int;32;4;address;riscv;Fail +sub;int;32;8;address;riscv;Fail +sub;int;32;16;address;riscv;Fail +sub;int;32;32;address;riscv;Fail +sub;int;32;64;address;riscv;Fail +sub;int;32;128;address;riscv;Fail +sub;int;64;1;address;riscv;Fail +sub;int;64;2;address;riscv;Fail +sub;int;64;4;address;riscv;Fail +sub;int;64;8;address;riscv;Fail +sub;int;64;16;address;riscv;Fail +sub;int;64;32;address;riscv;Fail +sub;int;64;64;address;riscv;Fail +sub;int;64;128;address;riscv;Fail +div;int;8;1;address;riscv;Fail +div;int;8;2;address;riscv;Fail +div;int;8;4;address;riscv;Fail +div;int;8;8;address;riscv;Fail +div;int;8;16;address;riscv;Fail +div;int;8;32;address;riscv;Fail +div;int;8;64;address;riscv;Fail +div;int;8;128;address;riscv;Fail +div;int;16;1;address;riscv;Fail +div;int;16;2;address;riscv;Fail +div;int;16;4;address;riscv;Fail +div;int;16;8;address;riscv;Fail +div;int;16;16;address;riscv;Fail +div;int;16;32;address;riscv;Fail +div;int;16;64;address;riscv;Fail +div;int;16;128;address;riscv;Fail +div;int;32;1;address;riscv;Fail +div;int;32;2;address;riscv;Fail +div;int;32;4;address;riscv;Fail +div;int;32;8;address;riscv;Fail +div;int;32;16;address;riscv;Fail +div;int;32;32;address;riscv;Fail +div;int;32;64;address;riscv;Fail +div;int;32;128;address;riscv;Fail +div;int;64;1;address;riscv;Fail +div;int;64;2;address;riscv;Fail +div;int;64;4;address;riscv;Fail +div;int;64;8;address;riscv;Fail +div;int;64;16;address;riscv;Fail +div;int;64;32;address;riscv;Fail +div;int;64;64;address;riscv;Fail +div;int;64;128;address;riscv;Fail +add;flt;32;1;address;riscv;Fail +add;flt;32;2;address;riscv;Fail +add;flt;32;4;address;riscv;Fail +add;flt;32;8;address;riscv;Fail +add;flt;32;16;address;riscv;Fail +add;flt;32;32;address;riscv;Fail +add;flt;32;64;address;riscv;Fail +add;flt;32;128;address;riscv;Fail +add;flt;64;1;address;riscv;Fail +add;flt;64;2;address;riscv;Fail +add;flt;64;4;address;riscv;Fail +add;flt;64;8;address;riscv;Fail +add;flt;64;16;address;riscv;Fail +add;flt;64;32;address;riscv;Fail +add;flt;64;64;address;riscv;Fail +add;flt;64;128;address;riscv;Fail +mul;flt;32;1;address;riscv;Fail +mul;flt;32;2;address;riscv;Fail +mul;flt;32;4;address;riscv;Fail +mul;flt;32;8;address;riscv;Fail +mul;flt;32;16;address;riscv;Fail +mul;flt;32;32;address;riscv;Fail +mul;flt;32;64;address;riscv;Fail +mul;flt;32;128;address;riscv;Fail +mul;flt;64;1;address;riscv;Fail +mul;flt;64;2;address;riscv;Fail +mul;flt;64;4;address;riscv;Fail +mul;flt;64;8;address;riscv;Fail +mul;flt;64;16;address;riscv;Fail +mul;flt;64;32;address;riscv;Fail +mul;flt;64;64;address;riscv;Fail +mul;flt;64;128;address;riscv;Fail +sub;flt;32;1;address;riscv;Fail +sub;flt;32;2;address;riscv;Fail +sub;flt;32;4;address;riscv;Fail +sub;flt;32;8;address;riscv;Fail +sub;flt;32;16;address;riscv;Fail +sub;flt;32;32;address;riscv;Fail +sub;flt;32;64;address;riscv;Fail +sub;flt;32;128;address;riscv;Fail +sub;flt;64;1;address;riscv;Fail +sub;flt;64;2;address;riscv;Fail +sub;flt;64;4;address;riscv;Fail +sub;flt;64;8;address;riscv;Fail +sub;flt;64;16;address;riscv;Fail +sub;flt;64;32;address;riscv;Fail +sub;flt;64;64;address;riscv;Fail +sub;flt;64;128;address;riscv;Fail +div;flt;32;1;address;riscv;Fail +div;flt;32;2;address;riscv;Fail +div;flt;32;4;address;riscv;Fail +div;flt;32;8;address;riscv;Fail +div;flt;32;16;address;riscv;Fail +div;flt;32;32;address;riscv;Fail +div;flt;32;64;address;riscv;Fail +div;flt;32;128;address;riscv;Fail +div;flt;64;1;address;riscv;Fail +div;flt;64;2;address;riscv;Fail +div;flt;64;4;address;riscv;Fail +div;flt;64;8;address;riscv;Fail +div;flt;64;16;address;riscv;Fail +div;flt;64;32;address;riscv;Fail +div;flt;64;64;address;riscv;Fail +div;flt;64;128;address;riscv;Fail +mod;int;8;1;address;riscv;Fail +mod;int;8;2;address;riscv;Fail +mod;int;8;4;address;riscv;Fail +mod;int;8;8;address;riscv;Fail +mod;int;8;16;address;riscv;Fail +mod;int;8;32;address;riscv;Fail +mod;int;8;64;address;riscv;Fail +mod;int;8;128;address;riscv;Fail +mod;int;16;1;address;riscv;Fail +mod;int;16;2;address;riscv;Fail +mod;int;16;4;address;riscv;Fail +mod;int;16;8;address;riscv;Fail +mod;int;16;16;address;riscv;Fail +mod;int;16;32;address;riscv;Fail +mod;int;16;64;address;riscv;Fail +mod;int;16;128;address;riscv;Fail +mod;int;32;1;address;riscv;Fail +mod;int;32;2;address;riscv;Fail +mod;int;32;4;address;riscv;Fail +mod;int;32;8;address;riscv;Fail +mod;int;32;16;address;riscv;Fail +mod;int;32;32;address;riscv;Fail +mod;int;32;64;address;riscv;Fail +mod;int;32;128;address;riscv;Fail +mod;int;64;1;address;riscv;Fail +mod;int;64;2;address;riscv;Fail +mod;int;64;4;address;riscv;Fail +mod;int;64;8;address;riscv;Fail +mod;int;64;16;address;riscv;Fail +mod;int;64;32;address;riscv;Fail +mod;int;64;64;address;riscv;Fail +mod;int;64;128;address;riscv;Fail +or;int;8;1;address;riscv;Fail +or;int;8;2;address;riscv;Fail +or;int;8;4;address;riscv;Fail +or;int;8;8;address;riscv;Fail +or;int;8;16;address;riscv;Fail +or;int;8;32;address;riscv;Fail +or;int;8;64;address;riscv;Fail +or;int;8;128;address;riscv;Fail +or;int;16;1;address;riscv;Fail +or;int;16;2;address;riscv;Fail +or;int;16;4;address;riscv;Fail +or;int;16;8;address;riscv;Fail +or;int;16;16;address;riscv;Fail +or;int;16;32;address;riscv;Fail +or;int;16;64;address;riscv;Fail +or;int;16;128;address;riscv;Fail +or;int;32;1;address;riscv;Fail +or;int;32;2;address;riscv;Fail +or;int;32;4;address;riscv;Fail +or;int;32;8;address;riscv;Fail +or;int;32;16;address;riscv;Fail +or;int;32;32;address;riscv;Fail +or;int;32;64;address;riscv;Fail +or;int;32;128;address;riscv;Fail +or;int;64;1;address;riscv;Fail +or;int;64;2;address;riscv;Fail +or;int;64;4;address;riscv;Fail +or;int;64;8;address;riscv;Fail +or;int;64;16;address;riscv;Fail +or;int;64;32;address;riscv;Fail +or;int;64;64;address;riscv;Fail +or;int;64;128;address;riscv;Fail +and;int;8;1;address;riscv;Fail +and;int;8;2;address;riscv;Fail +and;int;8;4;address;riscv;Fail +and;int;8;8;address;riscv;Fail +and;int;8;16;address;riscv;Fail +and;int;8;32;address;riscv;Fail +and;int;8;64;address;riscv;Fail +and;int;8;128;address;riscv;Fail +and;int;16;1;address;riscv;Fail +and;int;16;2;address;riscv;Fail +and;int;16;4;address;riscv;Fail +and;int;16;8;address;riscv;Fail +and;int;16;16;address;riscv;Fail +and;int;16;32;address;riscv;Fail +and;int;16;64;address;riscv;Fail +and;int;16;128;address;riscv;Fail +and;int;32;1;address;riscv;Fail +and;int;32;2;address;riscv;Fail +and;int;32;4;address;riscv;Fail +and;int;32;8;address;riscv;Fail +and;int;32;16;address;riscv;Fail +and;int;32;32;address;riscv;Fail +and;int;32;64;address;riscv;Fail +and;int;32;128;address;riscv;Fail +and;int;64;1;address;riscv;Fail +and;int;64;2;address;riscv;Fail +and;int;64;4;address;riscv;Fail +and;int;64;8;address;riscv;Fail +and;int;64;16;address;riscv;Fail +and;int;64;32;address;riscv;Fail +and;int;64;64;address;riscv;Fail +and;int;64;128;address;riscv;Fail +xor;int;8;1;address;riscv;Fail +xor;int;8;2;address;riscv;Fail +xor;int;8;4;address;riscv;Fail +xor;int;8;8;address;riscv;Fail +xor;int;8;16;address;riscv;Fail +xor;int;8;32;address;riscv;Fail +xor;int;8;64;address;riscv;Fail +xor;int;8;128;address;riscv;Fail +xor;int;16;1;address;riscv;Fail +xor;int;16;2;address;riscv;Fail +xor;int;16;4;address;riscv;Fail +xor;int;16;8;address;riscv;Fail +xor;int;16;16;address;riscv;Fail +xor;int;16;32;address;riscv;Fail +xor;int;16;64;address;riscv;Fail +xor;int;16;128;address;riscv;Fail +xor;int;32;1;address;riscv;Fail +xor;int;32;2;address;riscv;Fail +xor;int;32;4;address;riscv;Fail +xor;int;32;8;address;riscv;Fail +xor;int;32;16;address;riscv;Fail +xor;int;32;32;address;riscv;Fail +xor;int;32;64;address;riscv;Fail +xor;int;32;128;address;riscv;Fail +xor;int;64;1;address;riscv;Fail +xor;int;64;2;address;riscv;Fail +xor;int;64;4;address;riscv;Fail +xor;int;64;8;address;riscv;Fail +xor;int;64;16;address;riscv;Fail +xor;int;64;32;address;riscv;Fail +xor;int;64;64;address;riscv;Fail +xor;int;64;128;address;riscv;Fail +sl;int;8;1;address;riscv;Fail +sl;int;8;2;address;riscv;Fail +sl;int;8;4;address;riscv;Fail +sl;int;8;8;address;riscv;Fail +sl;int;8;16;address;riscv;Fail +sl;int;8;32;address;riscv;Fail +sl;int;8;64;address;riscv;Fail +sl;int;8;128;address;riscv;Fail +sl;int;16;1;address;riscv;Fail +sl;int;16;2;address;riscv;Fail +sl;int;16;4;address;riscv;Fail +sl;int;16;8;address;riscv;Fail +sl;int;16;16;address;riscv;Fail +sl;int;16;32;address;riscv;Fail +sl;int;16;64;address;riscv;Fail +sl;int;16;128;address;riscv;Fail +sl;int;32;1;address;riscv;Fail +sl;int;32;2;address;riscv;Fail +sl;int;32;4;address;riscv;Fail +sl;int;32;8;address;riscv;Fail +sl;int;32;16;address;riscv;Fail +sl;int;32;32;address;riscv;Fail +sl;int;32;64;address;riscv;Fail +sl;int;32;128;address;riscv;Fail +sl;int;64;1;address;riscv;Fail +sl;int;64;2;address;riscv;Fail +sl;int;64;4;address;riscv;Fail +sl;int;64;8;address;riscv;Fail +sl;int;64;16;address;riscv;Fail +sl;int;64;32;address;riscv;Fail +sl;int;64;64;address;riscv;Fail +sl;int;64;128;address;riscv;Fail +sr;int;8;1;address;riscv;Fail +sr;int;8;2;address;riscv;Fail +sr;int;8;4;address;riscv;Fail +sr;int;8;8;address;riscv;Fail +sr;int;8;16;address;riscv;Fail +sr;int;8;32;address;riscv;Fail +sr;int;8;64;address;riscv;Fail +sr;int;8;128;address;riscv;Fail +sr;int;16;1;address;riscv;Fail +sr;int;16;2;address;riscv;Fail +sr;int;16;4;address;riscv;Fail +sr;int;16;8;address;riscv;Fail +sr;int;16;16;address;riscv;Fail +sr;int;16;32;address;riscv;Fail +sr;int;16;64;address;riscv;Fail +sr;int;16;128;address;riscv;Fail +sr;int;32;1;address;riscv;Fail +sr;int;32;2;address;riscv;Fail +sr;int;32;4;address;riscv;Fail +sr;int;32;8;address;riscv;Fail +sr;int;32;16;address;riscv;Fail +sr;int;32;32;address;riscv;Fail +sr;int;32;64;address;riscv;Fail +sr;int;32;128;address;riscv;Fail +sr;int;64;1;address;riscv;Fail +sr;int;64;2;address;riscv;Fail +sr;int;64;4;address;riscv;Fail +sr;int;64;8;address;riscv;Fail +sr;int;64;16;address;riscv;Fail +sr;int;64;32;address;riscv;Fail +sr;int;64;64;address;riscv;Fail +sr;int;64;128;address;riscv;Fail +add;int;8;1;address;power;Fail +add;int;8;2;address;power;Fail +add;int;8;4;address;power;Fail +add;int;8;8;address;power;Fail +add;int;8;16;address;power;Fail +add;int;8;32;address;power;Fail +add;int;8;64;address;power;Fail +add;int;8;128;address;power;Fail +add;int;16;1;address;power;Fail +add;int;16;2;address;power;Fail +add;int;16;4;address;power;Fail +add;int;16;8;address;power;Fail +add;int;16;16;address;power;Fail +add;int;16;32;address;power;Fail +add;int;16;64;address;power;Fail +add;int;16;128;address;power;Fail +add;int;32;1;address;power;Fail +add;int;32;2;address;power;Fail +add;int;32;4;address;power;Fail +add;int;32;8;address;power;Fail +add;int;32;16;address;power;Fail +add;int;32;32;address;power;Fail +add;int;32;64;address;power;Fail +add;int;32;128;address;power;Fail +add;int;64;1;address;power;Fail +add;int;64;2;address;power;Fail +add;int;64;4;address;power;Fail +add;int;64;8;address;power;Fail +add;int;64;16;address;power;Fail +add;int;64;32;address;power;Fail +add;int;64;64;address;power;Fail +add;int;64;128;address;power;Fail +mul;int;8;1;address;power;Fail +mul;int;8;2;address;power;Fail +mul;int;8;4;address;power;Fail +mul;int;8;8;address;power;Fail +mul;int;8;16;address;power;Fail +mul;int;8;32;address;power;Fail +mul;int;8;64;address;power;Fail +mul;int;8;128;address;power;Fail +mul;int;16;1;address;power;Fail +mul;int;16;2;address;power;Fail +mul;int;16;4;address;power;Fail +mul;int;16;8;address;power;Fail +mul;int;16;16;address;power;Fail +mul;int;16;32;address;power;Fail +mul;int;16;64;address;power;Fail +mul;int;16;128;address;power;Fail +mul;int;32;1;address;power;Fail +mul;int;32;2;address;power;Fail +mul;int;32;4;address;power;Fail +mul;int;32;8;address;power;Fail +mul;int;32;16;address;power;Fail +mul;int;32;32;address;power;Fail +mul;int;32;64;address;power;Fail +mul;int;32;128;address;power;Fail +mul;int;64;1;address;power;Fail +mul;int;64;2;address;power;Fail +mul;int;64;4;address;power;Fail +mul;int;64;8;address;power;Fail +mul;int;64;16;address;power;Fail +mul;int;64;32;address;power;Fail +mul;int;64;64;address;power;Fail +mul;int;64;128;address;power;Fail +sub;int;8;1;address;power;Fail +sub;int;8;2;address;power;Fail +sub;int;8;4;address;power;Fail +sub;int;8;8;address;power;Fail +sub;int;8;16;address;power;Fail +sub;int;8;32;address;power;Fail +sub;int;8;64;address;power;Fail +sub;int;8;128;address;power;Fail +sub;int;16;1;address;power;Fail +sub;int;16;2;address;power;Fail +sub;int;16;4;address;power;Fail +sub;int;16;8;address;power;Fail +sub;int;16;16;address;power;Fail +sub;int;16;32;address;power;Fail +sub;int;16;64;address;power;Fail +sub;int;16;128;address;power;Fail +sub;int;32;1;address;power;Fail +sub;int;32;2;address;power;Fail +sub;int;32;4;address;power;Fail +sub;int;32;8;address;power;Fail +sub;int;32;16;address;power;Fail +sub;int;32;32;address;power;Fail +sub;int;32;64;address;power;Fail +sub;int;32;128;address;power;Fail +sub;int;64;1;address;power;Fail +sub;int;64;2;address;power;Fail +sub;int;64;4;address;power;Fail +sub;int;64;8;address;power;Fail +sub;int;64;16;address;power;Fail +sub;int;64;32;address;power;Fail +sub;int;64;64;address;power;Fail +sub;int;64;128;address;power;Fail +div;int;8;1;address;power;Fail +div;int;8;2;address;power;Fail +div;int;8;4;address;power;Fail +div;int;8;8;address;power;Fail +div;int;8;16;address;power;Fail +div;int;8;32;address;power;Fail +div;int;8;64;address;power;Fail +div;int;8;128;address;power;Fail +div;int;16;1;address;power;Fail +div;int;16;2;address;power;Fail +div;int;16;4;address;power;Fail +div;int;16;8;address;power;Fail +div;int;16;16;address;power;Fail +div;int;16;32;address;power;Fail +div;int;16;64;address;power;Fail +div;int;16;128;address;power;Fail +div;int;32;1;address;power;Fail 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+xor;int;64;128;address;power;Fail +sl;int;8;1;address;power;Fail +sl;int;8;2;address;power;Fail +sl;int;8;4;address;power;Fail +sl;int;8;8;address;power;Fail +sl;int;8;16;address;power;Fail +sl;int;8;32;address;power;Fail +sl;int;8;64;address;power;Fail +sl;int;8;128;address;power;Fail +sl;int;16;1;address;power;Fail +sl;int;16;2;address;power;Fail +sl;int;16;4;address;power;Fail +sl;int;16;8;address;power;Fail +sl;int;16;16;address;power;Fail +sl;int;16;32;address;power;Fail +sl;int;16;64;address;power;Fail +sl;int;16;128;address;power;Fail +sl;int;32;1;address;power;Fail +sl;int;32;2;address;power;Fail +sl;int;32;4;address;power;Fail +sl;int;32;8;address;power;Fail +sl;int;32;16;address;power;Fail +sl;int;32;32;address;power;Fail +sl;int;32;64;address;power;Fail +sl;int;32;128;address;power;Fail +sl;int;64;1;address;power;Fail +sl;int;64;2;address;power;Fail +sl;int;64;4;address;power;Fail +sl;int;64;8;address;power;Fail +sl;int;64;16;address;power;Fail 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+sr;int;64;8;address;power;Fail +sr;int;64;16;address;power;Fail +sr;int;64;32;address;power;Fail +sr;int;64;64;address;power;Fail +sr;int;64;128;address;power;Fail diff --git a/Demos/Makefile b/Demos/Makefile index 5d42c6e..10ec8cb 100644 --- a/Demos/Makefile +++ b/Demos/Makefile @@ -1,3 +1,17 @@ +buildAll: + -(cd Stencil; make buildAll) + -(cd VectorMatrix; make buildAll) + -(cd Newton-SquareRoot-VariablePrecision; make buildAll) + -(cd AudioFilter ; make buildAll) + -(cd C-SRAM_Applications; make buildAll) + -(cd CelciusFarenheitConversions; make buildAll) + -(cd ImagePixelSum; make buildAll) + -(cd IOTWorkerSpecialization; make buildAll) + -(cd Kahan3Sum; make buildAll) + -(cd ReversePolishNotation; make buildAll) + -(cd Stencil1D; make buildAll) + + clean: -(cd Stencil; make clean) -(cd VectorMatrix; make clean) diff --git a/Demos/Newton-SquareRoot-VariablePrecision/Newton.c b/Demos/Newton-SquareRoot-VariablePrecision/Newton.c new file mode 100644 index 0000000..d18ae26 --- /dev/null +++ b/Demos/Newton-SquareRoot-VariablePrecision/Newton.c @@ -0,0 +1,925 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +void RV32I_RET__I_32_1(){ /* RET */ + riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_RET__I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_ADDI_RRI_I_32_1(int r1,int r0,int i0){ /* ADD */ + riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_ADDI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_ADD_RRR_I_32_1(int r3,int r1,int r2){ /* ADD */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_ADD_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SUB_RRR_I_32_1(int r3,int r1,int r2){ /* SUB */ + riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SUB_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_MV_RR_I_32_1(int r0,int r1){ /* MV */ + riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_MV_RR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_MV_RI_I_32_1(int r3,int i1){ /* MV */ + riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_MV_RI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32F_FMV_S_RR_F_32_1(int r3,int r1){ /* MV */ + riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32F_FMV_S_RR_F_32_1\n", h2_asm_pc); +#endif +} +void RV32D_FMV_D_RR_F_64_1(int r3,int r1){ /* MV */ + riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32D_FMV_D_RR_F_64_1\n", h2_asm_pc); +#endif +} +void RV32I_LB_RRI_I_8_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void RV32I_LH_RRI_I_16_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void RV32I_LW_RRI_I_32_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LW_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32F_FADD_S_RRR_F_32_1(int r3,int r1,int r2){ /* ADD */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32F_FADD_S_RRR_F_32_1\n", h2_asm_pc); +#endif +} +void RV32D_FADD_D_RRR_F_64_1(int r3,int r1,int r2){ /* ADD */ + riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32D_FADD_D_RRR_F_64_1\n", h2_asm_pc); +#endif +} +void RV32I_SLLI_RRI_I_32_1(int r3,int r1,int i0){ /* SL */ + riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SLLI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SLL_RRR_I_32_1(int r3,int r1,int r2){ /* SL */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SLL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32F_FDIV_S_RRR_F_32_1(int r3,int r1,int r2){ /* DIV */ + riscv_G32(((0xc & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32F_FDIV_S_RRR_F_32_1\n", h2_asm_pc); +#endif +} +void RV32D_FDIV_D_RRR_F_64_1(int r3,int r1,int r2){ /* DIV */ + riscv_G32(((0xd & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32D_FDIV_D_RRR_F_64_1\n", h2_asm_pc); +#endif +} +void RV32I_SRLI_RRI_I_32_1(int r3,int r1,int i0){ /* SR */ + riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SRLI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SRL_RRR_I_32_1(int r3,int r1,int r2){ /* SR */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SRL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SB_RRI_I_8_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void RV32I_SH_RRI_I_16_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void RV32I_SW_RRI_I_32_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SW_RRI_I_32_1\n", h2_asm_pc); +#endif +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FDIV_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32D_FDIV_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +/* -*- c -*- */ + +#include +#include +#include + + +#define True 1 +#define False 0 +#define FLOAT 32 +#define DOUBLE 64 + +typedef float (*piff)(float, float, float); +typedef double (*pidd)(double, double, double); +/* Newton square root demonstration with variable precision */ +h2_insn_t * genIterate(h2_insn_t * ptr, int FloatWidth) +{ + /* Code Generation of 4 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t u = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; + h2_sValue_t val = {H2REGISTER, 'f', 1, (FloatWidth), 11, true}; + h2_sValue_t div = {H2REGISTER, 'f', 1, (FloatWidth), 12, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; + h2_sValue_t tmp1 = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; + h2_sValue_t tmp2 = {H2REGISTER, 'f', 1, (FloatWidth), 2, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x31F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp1 = riscv_genDIV_4(tmp1, val, u, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp2 = riscv_genADD_3(tmp2, u, tmp1); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = riscv_genDIV_4(tmp0000, tmp2, div, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + /* r = (u + (#(value) / u)) / 2.0*/ + + return (h2_insn_t *) ptr; +} + +#define ABS(x) ((x < 0) ? -(x) : (x)) + +int main(int argc, char **argv) +{ + int isFloat, iterationNumber; + double af, precf, precd, value, next, diff; + piff fPtr1; + pidd fPtr2; + h2_insn_t * ptr; + char input; + if (argc < 3) + { + printf ("Newton \n"); + exit(-1); + } + iterationNumber = 0; + af = atof (argv[1]); + precd = atof (argv[2]); + precf = 1; // precd * 1.e14; + ptr = h2_malloc (1024); + isFloat = True; + printf ("Compute square root of %f\n", af); + printf ("With precision of %e (float)\n", precf); + printf ("With precision of %e (double)\n", precd); + next = 1.0; + diff = af; + + fPtr1 = (piff) genIterate (ptr, FLOAT); + do + { + if ((diff < precf) && isFloat) + { /* Code re-generation with double for better precision */ + fPtr2 = (pidd) genIterate (ptr, DOUBLE); + isFloat = False; + } + value = next; + next = (isFloat)?fPtr1(value, af, 2.0):fPtr2(value, af, 2.0); + diff = ABS(next - value); + printf("%3d %s : %.20f, %e\n", + iterationNumber++, + isFloat?"float ":"double", + next, isFloat?precf:precd); + + if(iterationNumber > 100){ + return -1; + } + } while ( diff > precd); + if(isFloat){ + return (next != sqrtf(af)) ? -1 : 0; + } + else{ + return (next != sqrt(af)) ? -1 : 0; + } +} diff --git a/Demos/Newton-SquareRoot-VariablePrecision/Newton.riscv b/Demos/Newton-SquareRoot-VariablePrecision/Newton.riscv new file mode 100755 index 0000000000000000000000000000000000000000..671c4acab69894ef561e7a5042da5600c1936973 GIT binary patch literal 65000 zcmeFa349b~@;=@@Jy#AwAV2^)h8&Za4dDo0s2Fe{;1`kQ^ZP^agCS71rsD*EH`wV3Hq7Pjh6#>UPjr#?}{^450|9X!)0+j4_aPE z`R`E<@^k(uAJt2PP#&nCnY=nb5~)*8_I;glGCJmD=Z$@+V_|kt`ncq-9kX)^lDlRk z73C*&0S)V-EYhbA7>c{r4#e}1K5l|56c_C!E&m$fvg0Bj^$Edc{E^3oD+m|mG{(ih zU|jTV7%tNAVmWCgbFVI@lm&mAK%o<)*I7ontS9`B<&UoWZfacHYyMR9{?E^BTJgI- zH1F~Fi;w;s_UfZI{q=@MEguh_QhTtZS<--;k9GUW9iDg7^N&_MbK_R9*7>8Z#-9T~ zTO)&%`2n~pEgDr*z%Sr(AU^rWd@o#`1M+UfnYgS-?V zZyWPdwfe%PUuqezqXNo{kY5tOe;xAS0p+8SPYKAEB0n%7FS+{-x!s+SS(rIGyQny` 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z?-dI6OCF4oSLOXuR;FOU(Z(wa3Cw#GqD-UZPgqe!aLnT}|CA9T<0K?B qN2u&a#br`Yl!$qT{zanv8xqu?BjH5k +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include +#include +#include "ReadPgmImage.h" + +typedef int (*pifc)(int[], int, int, int); + + +void printImage(imgStruct_t *img, char *imageName) +{ + printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width ; column++) + { + printf("%03d ", img->pixelsArray[line*img->width+column]); + } + printf("\n"); + } + printf("\n"); +} + +int imgSum (imgStruct_t *img) +{ + int line, column, sum; + sum = 0; + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width; column++) + { + sum += img->pixelsArray[line*img->width+column]; + } + } + return (0 == sum)?1:sum; +} + +#if 0 +unsigned char clamp(int value) +{ + return (unsigned char)(0 > value)?0:(255 < value)?255:value; +} +#else +#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) +#endif + +pifc genKernel1x1(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF030F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, line, imgWidth); + tmp0001 = aarch64_genADD_3(tmp0001, tmp0000, column); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genMUL_3(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = aarch64_genADD_3(tmp0003, In, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = aarch64_genR_3(tmp0004, tmp0003, immValueZero); + sum = aarch64_genMUL_3(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); + if (!sum.dontFree) h2_freeReg(tmp0004.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0005 = aarch64_genDIV_3(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0005, immValueZero); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel3x3(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 19 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 13, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF3F0F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + njp1 = aarch64_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = aarch64_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = aarch64_genADD_3(tmp0000, stride, njm1); + tmp0001 = aarch64_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = aarch64_genR_3(tmp0003, tmp0002, immValueZero); + sum = aarch64_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = aarch64_genADD_3(tmp0004, stride, column); + tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = aarch64_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = aarch64_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = aarch64_genADD_3(tmp0009, stride, njp1); + tmp0010 = aarch64_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = aarch64_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = aarch64_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = aarch64_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genMV_3(ni, line, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0015 = aarch64_genADD_3(tmp0015, stride, njm1); + tmp0016 = aarch64_genMUL_3(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = aarch64_genADD_3(tmp0017, In, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = aarch64_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = aarch64_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0019); + if (!sum.dontFree) h2_freeReg(tmp0019.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0020 = aarch64_genADD_3(tmp0020, stride, column); + tmp0021 = aarch64_genMUL_3(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = aarch64_genADD_3(tmp0022, In, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = aarch64_genR_3(tmp0023, tmp0022, immValueZero); + tmp0024 = aarch64_genMUL_3(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0024); + if (!sum.dontFree) h2_freeReg(tmp0024.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0025 = aarch64_genADD_3(tmp0025, stride, njp1); + tmp0026 = aarch64_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = aarch64_genADD_3(tmp0027, In, tmp0026); + if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); + tmp0028 = aarch64_genR_3(tmp0028, tmp0027, immValueZero); + tmp0029 = aarch64_genMUL_3(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}); + if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0029); + if (!sum.dontFree) h2_freeReg(tmp0029.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0030 = aarch64_genADD_3(tmp0030, stride, njm1); + tmp0031 = aarch64_genMUL_3(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = aarch64_genADD_3(tmp0032, In, tmp0031); + if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); + tmp0033 = aarch64_genR_3(tmp0033, tmp0032, immValueZero); + tmp0034 = aarch64_genMUL_3(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}); + if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0034); + if (!sum.dontFree) h2_freeReg(tmp0034.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0035 = aarch64_genADD_3(tmp0035, stride, column); + tmp0036 = aarch64_genMUL_3(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = aarch64_genADD_3(tmp0037, In, tmp0036); + if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); + tmp0038 = aarch64_genR_3(tmp0038, tmp0037, immValueZero); + tmp0039 = aarch64_genMUL_3(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}); + if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0039); + if (!sum.dontFree) h2_freeReg(tmp0039.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0040 = aarch64_genADD_3(tmp0040, stride, njp1); + tmp0041 = aarch64_genMUL_3(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = aarch64_genADD_3(tmp0042, In, tmp0041); + if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); + tmp0043 = aarch64_genR_3(tmp0043, tmp0042, immValueZero); + tmp0044 = aarch64_genMUL_3(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}); + if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0044); + if (!sum.dontFree) h2_freeReg(tmp0044.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0045 = aarch64_genDIV_3(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0045, immValueZero); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel5x5(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 41 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 13, true}; + h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFFFF0F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + njm2 = aarch64_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = aarch64_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp1 = aarch64_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp2 = aarch64_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = aarch64_genADD_3(tmp0000, stride, njm2); + tmp0001 = aarch64_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = aarch64_genR_3(tmp0003, tmp0002, immValueZero); + sum = aarch64_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = aarch64_genADD_3(tmp0004, stride, njm1); + tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = aarch64_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = aarch64_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = aarch64_genADD_3(tmp0009, stride, column); + tmp0010 = aarch64_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = aarch64_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = aarch64_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = aarch64_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0014 = aarch64_genADD_3(tmp0014, stride, njp1); + tmp0015 = aarch64_genMUL_3(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = aarch64_genADD_3(tmp0016, In, tmp0015); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = aarch64_genR_3(tmp0017, tmp0016, immValueZero); + tmp0018 = aarch64_genMUL_3(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}); + if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0018); + if (!sum.dontFree) h2_freeReg(tmp0018.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0019 = aarch64_genADD_3(tmp0019, stride, njp2); + tmp0020 = aarch64_genMUL_3(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + tmp0021 = aarch64_genADD_3(tmp0021, In, tmp0020); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = aarch64_genR_3(tmp0022, tmp0021, immValueZero); + tmp0023 = aarch64_genMUL_3(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}); + if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0023); + if (!sum.dontFree) h2_freeReg(tmp0023.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0024 = aarch64_genADD_3(tmp0024, stride, njm2); + tmp0025 = aarch64_genMUL_3(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); + tmp0026 = aarch64_genADD_3(tmp0026, In, tmp0025); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = aarch64_genR_3(tmp0027, tmp0026, immValueZero); + tmp0028 = aarch64_genMUL_3(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0028); + if (!sum.dontFree) h2_freeReg(tmp0028.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0029 = aarch64_genADD_3(tmp0029, stride, njm1); + tmp0030 = aarch64_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = aarch64_genADD_3(tmp0031, In, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = aarch64_genR_3(tmp0032, tmp0031, immValueZero); + tmp0033 = aarch64_genMUL_3(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0033); + if (!sum.dontFree) h2_freeReg(tmp0033.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0034 = aarch64_genADD_3(tmp0034, stride, column); + tmp0035 = aarch64_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = aarch64_genADD_3(tmp0036, In, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = aarch64_genR_3(tmp0037, tmp0036, immValueZero); + tmp0038 = aarch64_genMUL_3(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0038); + if (!sum.dontFree) h2_freeReg(tmp0038.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0039 = aarch64_genADD_3(tmp0039, stride, njp1); + tmp0040 = aarch64_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = aarch64_genADD_3(tmp0041, In, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = aarch64_genR_3(tmp0042, tmp0041, immValueZero); + tmp0043 = aarch64_genMUL_3(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0043); + if (!sum.dontFree) h2_freeReg(tmp0043.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0044 = aarch64_genADD_3(tmp0044, stride, njp2); + tmp0045 = aarch64_genMUL_3(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = aarch64_genADD_3(tmp0046, In, tmp0045); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + tmp0047 = aarch64_genR_3(tmp0047, tmp0046, immValueZero); + tmp0048 = aarch64_genMUL_3(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}); + if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0048); + if (!sum.dontFree) h2_freeReg(tmp0048.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genMV_3(ni, line, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0050 = aarch64_genADD_3(tmp0050, stride, njm2); + tmp0051 = aarch64_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = aarch64_genADD_3(tmp0052, In, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = aarch64_genR_3(tmp0053, tmp0052, immValueZero); + tmp0054 = aarch64_genMUL_3(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0054); + if (!sum.dontFree) h2_freeReg(tmp0054.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0055 = aarch64_genADD_3(tmp0055, stride, njm1); + tmp0056 = aarch64_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = aarch64_genADD_3(tmp0057, In, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = aarch64_genR_3(tmp0058, tmp0057, immValueZero); + tmp0059 = aarch64_genMUL_3(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0059); + if (!sum.dontFree) h2_freeReg(tmp0059.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0060 = aarch64_genADD_3(tmp0060, stride, column); + tmp0061 = aarch64_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = aarch64_genADD_3(tmp0062, In, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + tmp0063 = aarch64_genR_3(tmp0063, tmp0062, immValueZero); + tmp0064 = aarch64_genMUL_3(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0064); + if (!sum.dontFree) h2_freeReg(tmp0064.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0065 = aarch64_genADD_3(tmp0065, stride, njp1); + tmp0066 = aarch64_genMUL_3(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = aarch64_genADD_3(tmp0067, In, tmp0066); + if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); + tmp0068 = aarch64_genR_3(tmp0068, tmp0067, immValueZero); + tmp0069 = aarch64_genMUL_3(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}); + if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0069); + if (!sum.dontFree) h2_freeReg(tmp0069.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0070 = aarch64_genADD_3(tmp0070, stride, njp2); + tmp0071 = aarch64_genMUL_3(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); + tmp0072 = aarch64_genADD_3(tmp0072, In, tmp0071); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = aarch64_genR_3(tmp0073, tmp0072, immValueZero); + tmp0074 = aarch64_genMUL_3(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}); + if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0074); + if (!sum.dontFree) h2_freeReg(tmp0074.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0075 = aarch64_genADD_3(tmp0075, stride, njm2); + tmp0076 = aarch64_genMUL_3(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); + tmp0077 = aarch64_genADD_3(tmp0077, In, tmp0076); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = aarch64_genR_3(tmp0078, tmp0077, immValueZero); + tmp0079 = aarch64_genMUL_3(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}); + if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0079); + if (!sum.dontFree) h2_freeReg(tmp0079.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0080 = aarch64_genADD_3(tmp0080, stride, njm1); + tmp0081 = aarch64_genMUL_3(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); + tmp0082 = aarch64_genADD_3(tmp0082, In, tmp0081); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = aarch64_genR_3(tmp0083, tmp0082, immValueZero); + tmp0084 = aarch64_genMUL_3(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}); + if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0084); + if (!sum.dontFree) h2_freeReg(tmp0084.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0085 = aarch64_genADD_3(tmp0085, stride, column); + tmp0086 = aarch64_genMUL_3(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); + tmp0087 = aarch64_genADD_3(tmp0087, In, tmp0086); + if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); + tmp0088 = aarch64_genR_3(tmp0088, tmp0087, immValueZero); + tmp0089 = aarch64_genMUL_3(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}); + if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0089); + if (!sum.dontFree) h2_freeReg(tmp0089.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0090 = aarch64_genADD_3(tmp0090, stride, njp1); + tmp0091 = aarch64_genMUL_3(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); + tmp0092 = aarch64_genADD_3(tmp0092, In, tmp0091); + if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); + tmp0093 = aarch64_genR_3(tmp0093, tmp0092, immValueZero); + tmp0094 = aarch64_genMUL_3(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}); + if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0094); + if (!sum.dontFree) h2_freeReg(tmp0094.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0095 = aarch64_genADD_3(tmp0095, stride, njp2); + tmp0096 = aarch64_genMUL_3(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); + tmp0097 = aarch64_genADD_3(tmp0097, In, tmp0096); + if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); + tmp0098 = aarch64_genR_3(tmp0098, tmp0097, immValueZero); + tmp0099 = aarch64_genMUL_3(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}); + if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0099); + if (!sum.dontFree) h2_freeReg(tmp0099.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = aarch64_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0100 = aarch64_genADD_3(tmp0100, stride, njm2); + tmp0101 = aarch64_genMUL_3(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); + tmp0102 = aarch64_genADD_3(tmp0102, In, tmp0101); + if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); + tmp0103 = aarch64_genR_3(tmp0103, tmp0102, immValueZero); + tmp0104 = aarch64_genMUL_3(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}); + if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0104); + if (!sum.dontFree) h2_freeReg(tmp0104.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0105 = aarch64_genADD_3(tmp0105, stride, njm1); + tmp0106 = aarch64_genMUL_3(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); + tmp0107 = aarch64_genADD_3(tmp0107, In, tmp0106); + if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); + tmp0108 = aarch64_genR_3(tmp0108, tmp0107, immValueZero); + tmp0109 = aarch64_genMUL_3(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}); + if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0109); + if (!sum.dontFree) h2_freeReg(tmp0109.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0110 = aarch64_genADD_3(tmp0110, stride, column); + tmp0111 = aarch64_genMUL_3(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); + tmp0112 = aarch64_genADD_3(tmp0112, In, tmp0111); + if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); + tmp0113 = aarch64_genR_3(tmp0113, tmp0112, immValueZero); + tmp0114 = aarch64_genMUL_3(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}); + if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0114); + if (!sum.dontFree) h2_freeReg(tmp0114.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0115 = aarch64_genADD_3(tmp0115, stride, njp1); + tmp0116 = aarch64_genMUL_3(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); + tmp0117 = aarch64_genADD_3(tmp0117, In, tmp0116); + if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); + tmp0118 = aarch64_genR_3(tmp0118, tmp0117, immValueZero); + tmp0119 = aarch64_genMUL_3(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}); + if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0119); + if (!sum.dontFree) h2_freeReg(tmp0119.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0120 = aarch64_genADD_3(tmp0120, stride, njp2); + tmp0121 = aarch64_genMUL_3(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); + tmp0122 = aarch64_genADD_3(tmp0122, In, tmp0121); + if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); + tmp0123 = aarch64_genR_3(tmp0123, tmp0122, immValueZero); + tmp0124 = aarch64_genMUL_3(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}); + if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); + sum = aarch64_genADD_3(sum, sum, tmp0124); + if (!sum.dontFree) h2_freeReg(tmp0124.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0125 = aarch64_genDIV_3(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0125, immValueZero); + if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +#if 0 +#endif +} + +// Compute a stencil for 1 point +int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) +{ + int line, column, sum = 0; + int offset = (Filter->width)/2; + + for (line = 0; line < Filter->height; line++) + { + for (column = 0; column < Filter->width; column++) + { + int ni = (l + line) - offset; + int nj = (c + column) - offset; + sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; + } + } + return sum / coeff; +} + + +void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelStatic(In, line, column, Filter, coeff); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelHL(In->pixelsArray, line, column, In->width); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) +{ + int errors = 0; + for(int line = 0 ; line < staticImg->height ; line++) + { + for(int column = 0 ; column < staticImg->width ; column++) + { + if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) + { + if (0 == errors) + { + printf("Alert : first difference at line %i column %i\n", line, column); + } + errors++; + } + } + } + return errors; +} + +int main(int argc, char *argv[]) +{ + int error, coeff, nXperiment = 20; + imgStruct_t *In, *OutH4, *OutStatic, *Filter; + char *filterImageName, *inputImageName; + if (argc < 5) + { + printf ("./Stencil \n"); + exit(-1); + } + + inputImageName = argv[1]; + filterImageName = argv[4]; + In = readPgmImage(inputImageName); + Filter = readPgmImage(filterImageName); + coeff = imgSum (Filter); +#ifdef VERBOSE + printf ("%s: coeff %d\n", filterImageName, coeff); + printImage (Filter, "Filter"); +#endif + assert (Filter->width == Filter->height); // Only square filters + OutStatic = createImage (In->height, In->width); + OutH4 = createImage (In->height, In->width); +#ifdef VERBOSE + printf ("after init\n"); + printImage(In, "In"); +#endif + ticks_t timeStatic = h2_getticks(); // Static convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionStatic(In, OutStatic, Filter, coeff); + } + timeStatic = h2_getticks() - timeStatic; +#ifdef VERBOSE + printf ("after static\n"); + printImage(OutStatic, "Out"); +#endif + + pifc kernelHL = (pifc)h2_malloc(8192); + ticks_t timeCodeGen = h2_getticks(); + switch (Filter->width) + { + case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; + case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; + case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; + default: printf ("Unknown filter size\n"); exit(-1); + } + timeCodeGen = h2_getticks() - timeCodeGen; + +#ifdef VERBOSE + printf ("after codegen\n"); +#endif + + ticks_t timeH4 = h2_getticks(); // Compilette convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionH4(In, OutH4, Filter, kernelHL); + } + timeH4 = h2_getticks() - timeH4; +#ifdef VERBOSE + printf ("after h2\n"); + printImage(OutH4, "Out H4"); +#endif + error = compareImages(OutH4, OutStatic); + printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", + filterImageName, + Filter->width, Filter->height, In->width, In->height, + timeStatic/nXperiment, timeH4/nXperiment, + h2_codeGenTime, h2_insnGenerated, + error); + +#if VERBOSE + writePgmImage(OutStatic, argv[2]); + writePgmImage(OutH4, argv[3]); +#endif + + return (0 == error)?0:-1; +} diff --git a/Demos/Stencil/Stencil.power b/Demos/Stencil/Stencil.power new file mode 100755 index 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zN5WhGIa&WXso$prB~|q*_VY+k{q2e&snVb8q!zDDRD^w^}NAAhnZBqs~@%@^EqgWxX$ up`RtI@uSu+3bQ_lxWco|LO&tnFlXZ7_n+Pmrqh2%o6x5}?eJc{Ec<^RwnugV literal 0 HcmV?d00001 diff --git a/Demos/Stencil/Stencil.power.c b/Demos/Stencil/Stencil.power.c new file mode 100644 index 0000000..826cc9f --- /dev/null +++ b/Demos/Stencil/Stencil.power.c @@ -0,0 +1,1955 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); +#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (power)\\n"); + #endif + P2 = power_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include +#include +#include "ReadPgmImage.h" + +typedef int (*pifc)(int[], int, int, int); + + +void printImage(imgStruct_t *img, char *imageName) +{ + printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width ; column++) + { + printf("%03d ", img->pixelsArray[line*img->width+column]); + } + printf("\n"); + } + printf("\n"); +} + +int imgSum (imgStruct_t *img) +{ + int line, column, sum; + sum = 0; + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width; column++) + { + sum += img->pixelsArray[line*img->width+column]; + } + } + return (0 == sum)?1:sum; +} + +#if 0 +unsigned char clamp(int value) +{ + return (unsigned char)(0 > value)?0:(255 < value)?255:value; +} +#else +#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) +#endif + +pifc genKernel1x1(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x787F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, line, imgWidth); + tmp0001 = power_genADD_3(tmp0001, tmp0000, column); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genMUL_3(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = power_genADD_3(tmp0003, In, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = power_genR_3(tmp0004, tmp0003, immValueZero); + sum = power_genMUL_3(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); + if (!sum.dontFree) h2_freeReg(tmp0004.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0005 = power_genDIV_3(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel3x3(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 19 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 17, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 18, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7F87F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + njp1 = power_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = power_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = power_genADD_3(tmp0000, stride, njm1); + tmp0001 = power_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = power_genR_3(tmp0003, tmp0002, immValueZero); + sum = power_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = power_genADD_3(tmp0004, stride, column); + tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = power_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = power_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = power_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = power_genADD_3(tmp0009, stride, njp1); + tmp0010 = power_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = power_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = power_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = power_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = power_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genMV_2(ni, line); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0015 = power_genADD_3(tmp0015, stride, njm1); + tmp0016 = power_genMUL_3(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = power_genADD_3(tmp0017, In, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = power_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = power_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + sum = power_genADD_3(sum, sum, tmp0019); + if (!sum.dontFree) h2_freeReg(tmp0019.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0020 = power_genADD_3(tmp0020, stride, column); + tmp0021 = power_genMUL_3(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = power_genADD_3(tmp0022, In, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = power_genR_3(tmp0023, tmp0022, immValueZero); + tmp0024 = power_genMUL_3(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + sum = power_genADD_3(sum, sum, tmp0024); + if (!sum.dontFree) h2_freeReg(tmp0024.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0025 = power_genADD_3(tmp0025, stride, njp1); + tmp0026 = power_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = power_genADD_3(tmp0027, In, tmp0026); + if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); + tmp0028 = power_genR_3(tmp0028, tmp0027, immValueZero); + tmp0029 = power_genMUL_3(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}); + if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); + sum = power_genADD_3(sum, sum, tmp0029); + if (!sum.dontFree) h2_freeReg(tmp0029.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0030 = power_genADD_3(tmp0030, stride, njm1); + tmp0031 = power_genMUL_3(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = power_genADD_3(tmp0032, In, tmp0031); + if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); + tmp0033 = power_genR_3(tmp0033, tmp0032, immValueZero); + tmp0034 = power_genMUL_3(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}); + if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); + sum = power_genADD_3(sum, sum, tmp0034); + if (!sum.dontFree) h2_freeReg(tmp0034.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0035 = power_genADD_3(tmp0035, stride, column); + tmp0036 = power_genMUL_3(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = power_genADD_3(tmp0037, In, tmp0036); + if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); + tmp0038 = power_genR_3(tmp0038, tmp0037, immValueZero); + tmp0039 = power_genMUL_3(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}); + if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); + sum = power_genADD_3(sum, sum, tmp0039); + if (!sum.dontFree) h2_freeReg(tmp0039.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0040 = power_genADD_3(tmp0040, stride, njp1); + tmp0041 = power_genMUL_3(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = power_genADD_3(tmp0042, In, tmp0041); + if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); + tmp0043 = power_genR_3(tmp0043, tmp0042, immValueZero); + tmp0044 = power_genMUL_3(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}); + if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); + sum = power_genADD_3(sum, sum, tmp0044); + if (!sum.dontFree) h2_freeReg(tmp0044.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0045 = power_genDIV_3(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0045); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel5x5(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 41 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 17, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 18, true}; + h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 19, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 20, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1FF87F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + njm2 = power_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = power_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp1 = power_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp2 = power_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = power_genADD_3(tmp0000, stride, njm2); + tmp0001 = power_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = power_genR_3(tmp0003, tmp0002, immValueZero); + sum = power_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = power_genADD_3(tmp0004, stride, njm1); + tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = power_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = power_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = power_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = power_genADD_3(tmp0009, stride, column); + tmp0010 = power_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = power_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = power_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = power_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = power_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0014 = power_genADD_3(tmp0014, stride, njp1); + tmp0015 = power_genMUL_3(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = power_genADD_3(tmp0016, In, tmp0015); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = power_genR_3(tmp0017, tmp0016, immValueZero); + tmp0018 = power_genMUL_3(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}); + if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); + sum = power_genADD_3(sum, sum, tmp0018); + if (!sum.dontFree) h2_freeReg(tmp0018.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0019 = power_genADD_3(tmp0019, stride, njp2); + tmp0020 = power_genMUL_3(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + tmp0021 = power_genADD_3(tmp0021, In, tmp0020); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = power_genR_3(tmp0022, tmp0021, immValueZero); + tmp0023 = power_genMUL_3(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}); + if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); + sum = power_genADD_3(sum, sum, tmp0023); + if (!sum.dontFree) h2_freeReg(tmp0023.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0024 = power_genADD_3(tmp0024, stride, njm2); + tmp0025 = power_genMUL_3(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); + tmp0026 = power_genADD_3(tmp0026, In, tmp0025); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = power_genR_3(tmp0027, tmp0026, immValueZero); + tmp0028 = power_genMUL_3(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + sum = power_genADD_3(sum, sum, tmp0028); + if (!sum.dontFree) h2_freeReg(tmp0028.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0029 = power_genADD_3(tmp0029, stride, njm1); + tmp0030 = power_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = power_genADD_3(tmp0031, In, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = power_genR_3(tmp0032, tmp0031, immValueZero); + tmp0033 = power_genMUL_3(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + sum = power_genADD_3(sum, sum, tmp0033); + if (!sum.dontFree) h2_freeReg(tmp0033.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0034 = power_genADD_3(tmp0034, stride, column); + tmp0035 = power_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = power_genADD_3(tmp0036, In, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = power_genR_3(tmp0037, tmp0036, immValueZero); + tmp0038 = power_genMUL_3(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + sum = power_genADD_3(sum, sum, tmp0038); + if (!sum.dontFree) h2_freeReg(tmp0038.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0039 = power_genADD_3(tmp0039, stride, njp1); + tmp0040 = power_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = power_genADD_3(tmp0041, In, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = power_genR_3(tmp0042, tmp0041, immValueZero); + tmp0043 = power_genMUL_3(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + sum = power_genADD_3(sum, sum, tmp0043); + if (!sum.dontFree) h2_freeReg(tmp0043.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0044 = power_genADD_3(tmp0044, stride, njp2); + tmp0045 = power_genMUL_3(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = power_genADD_3(tmp0046, In, tmp0045); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + tmp0047 = power_genR_3(tmp0047, tmp0046, immValueZero); + tmp0048 = power_genMUL_3(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}); + if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); + sum = power_genADD_3(sum, sum, tmp0048); + if (!sum.dontFree) h2_freeReg(tmp0048.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genMV_2(ni, line); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0050 = power_genADD_3(tmp0050, stride, njm2); + tmp0051 = power_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = power_genADD_3(tmp0052, In, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = power_genR_3(tmp0053, tmp0052, immValueZero); + tmp0054 = power_genMUL_3(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + sum = power_genADD_3(sum, sum, tmp0054); + if (!sum.dontFree) h2_freeReg(tmp0054.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0055 = power_genADD_3(tmp0055, stride, njm1); + tmp0056 = power_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = power_genADD_3(tmp0057, In, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = power_genR_3(tmp0058, tmp0057, immValueZero); + tmp0059 = power_genMUL_3(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + sum = power_genADD_3(sum, sum, tmp0059); + if (!sum.dontFree) h2_freeReg(tmp0059.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0060 = power_genADD_3(tmp0060, stride, column); + tmp0061 = power_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = power_genADD_3(tmp0062, In, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + tmp0063 = power_genR_3(tmp0063, tmp0062, immValueZero); + tmp0064 = power_genMUL_3(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + sum = power_genADD_3(sum, sum, tmp0064); + if (!sum.dontFree) h2_freeReg(tmp0064.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0065 = power_genADD_3(tmp0065, stride, njp1); + tmp0066 = power_genMUL_3(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = power_genADD_3(tmp0067, In, tmp0066); + if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); + tmp0068 = power_genR_3(tmp0068, tmp0067, immValueZero); + tmp0069 = power_genMUL_3(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}); + if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); + sum = power_genADD_3(sum, sum, tmp0069); + if (!sum.dontFree) h2_freeReg(tmp0069.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0070 = power_genADD_3(tmp0070, stride, njp2); + tmp0071 = power_genMUL_3(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); + tmp0072 = power_genADD_3(tmp0072, In, tmp0071); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = power_genR_3(tmp0073, tmp0072, immValueZero); + tmp0074 = power_genMUL_3(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}); + if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); + sum = power_genADD_3(sum, sum, tmp0074); + if (!sum.dontFree) h2_freeReg(tmp0074.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0075 = power_genADD_3(tmp0075, stride, njm2); + tmp0076 = power_genMUL_3(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); + tmp0077 = power_genADD_3(tmp0077, In, tmp0076); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = power_genR_3(tmp0078, tmp0077, immValueZero); + tmp0079 = power_genMUL_3(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}); + if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); + sum = power_genADD_3(sum, sum, tmp0079); + if (!sum.dontFree) h2_freeReg(tmp0079.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0080 = power_genADD_3(tmp0080, stride, njm1); + tmp0081 = power_genMUL_3(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); + tmp0082 = power_genADD_3(tmp0082, In, tmp0081); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = power_genR_3(tmp0083, tmp0082, immValueZero); + tmp0084 = power_genMUL_3(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}); + if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); + sum = power_genADD_3(sum, sum, tmp0084); + if (!sum.dontFree) h2_freeReg(tmp0084.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0085 = power_genADD_3(tmp0085, stride, column); + tmp0086 = power_genMUL_3(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); + tmp0087 = power_genADD_3(tmp0087, In, tmp0086); + if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); + tmp0088 = power_genR_3(tmp0088, tmp0087, immValueZero); + tmp0089 = power_genMUL_3(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}); + if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); + sum = power_genADD_3(sum, sum, tmp0089); + if (!sum.dontFree) h2_freeReg(tmp0089.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0090 = power_genADD_3(tmp0090, stride, njp1); + tmp0091 = power_genMUL_3(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); + tmp0092 = power_genADD_3(tmp0092, In, tmp0091); + if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); + tmp0093 = power_genR_3(tmp0093, tmp0092, immValueZero); + tmp0094 = power_genMUL_3(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}); + if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); + sum = power_genADD_3(sum, sum, tmp0094); + if (!sum.dontFree) h2_freeReg(tmp0094.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0095 = power_genADD_3(tmp0095, stride, njp2); + tmp0096 = power_genMUL_3(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); + tmp0097 = power_genADD_3(tmp0097, In, tmp0096); + if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); + tmp0098 = power_genR_3(tmp0098, tmp0097, immValueZero); + tmp0099 = power_genMUL_3(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}); + if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); + sum = power_genADD_3(sum, sum, tmp0099); + if (!sum.dontFree) h2_freeReg(tmp0099.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = power_genMUL_3(stride, ni, imgWidth); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0100 = power_genADD_3(tmp0100, stride, njm2); + tmp0101 = power_genMUL_3(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); + tmp0102 = power_genADD_3(tmp0102, In, tmp0101); + if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); + tmp0103 = power_genR_3(tmp0103, tmp0102, immValueZero); + tmp0104 = power_genMUL_3(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}); + if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); + sum = power_genADD_3(sum, sum, tmp0104); + if (!sum.dontFree) h2_freeReg(tmp0104.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0105 = power_genADD_3(tmp0105, stride, njm1); + tmp0106 = power_genMUL_3(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); + tmp0107 = power_genADD_3(tmp0107, In, tmp0106); + if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); + tmp0108 = power_genR_3(tmp0108, tmp0107, immValueZero); + tmp0109 = power_genMUL_3(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}); + if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); + sum = power_genADD_3(sum, sum, tmp0109); + if (!sum.dontFree) h2_freeReg(tmp0109.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0110 = power_genADD_3(tmp0110, stride, column); + tmp0111 = power_genMUL_3(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); + tmp0112 = power_genADD_3(tmp0112, In, tmp0111); + if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); + tmp0113 = power_genR_3(tmp0113, tmp0112, immValueZero); + tmp0114 = power_genMUL_3(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}); + if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); + sum = power_genADD_3(sum, sum, tmp0114); + if (!sum.dontFree) h2_freeReg(tmp0114.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0115 = power_genADD_3(tmp0115, stride, njp1); + tmp0116 = power_genMUL_3(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); + tmp0117 = power_genADD_3(tmp0117, In, tmp0116); + if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); + tmp0118 = power_genR_3(tmp0118, tmp0117, immValueZero); + tmp0119 = power_genMUL_3(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}); + if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); + sum = power_genADD_3(sum, sum, tmp0119); + if (!sum.dontFree) h2_freeReg(tmp0119.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0120 = power_genADD_3(tmp0120, stride, njp2); + tmp0121 = power_genMUL_3(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); + tmp0122 = power_genADD_3(tmp0122, In, tmp0121); + if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); + tmp0123 = power_genR_3(tmp0123, tmp0122, immValueZero); + tmp0124 = power_genMUL_3(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}); + if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); + sum = power_genADD_3(sum, sum, tmp0124); + if (!sum.dontFree) h2_freeReg(tmp0124.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0125 = power_genDIV_3(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); + h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0125); + if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +#if 0 +#endif +} + +// Compute a stencil for 1 point +int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) +{ + int line, column, sum = 0; + int offset = (Filter->width)/2; + + for (line = 0; line < Filter->height; line++) + { + for (column = 0; column < Filter->width; column++) + { + int ni = (l + line) - offset; + int nj = (c + column) - offset; + sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; + } + } + return sum / coeff; +} + + +void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelStatic(In, line, column, Filter, coeff); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelHL(In->pixelsArray, line, column, In->width); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) +{ + int errors = 0; + for(int line = 0 ; line < staticImg->height ; line++) + { + for(int column = 0 ; column < staticImg->width ; column++) + { + if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) + { + if (0 == errors) + { + printf("Alert : first difference at line %i column %i\n", line, column); + } + errors++; + } + } + } + return errors; +} + +int main(int argc, char *argv[]) +{ + int error, coeff, nXperiment = 20; + imgStruct_t *In, *OutH4, *OutStatic, *Filter; + char *filterImageName, *inputImageName; + if (argc < 5) + { + printf ("./Stencil \n"); + exit(-1); + } + + inputImageName = argv[1]; + filterImageName = argv[4]; + In = readPgmImage(inputImageName); + Filter = readPgmImage(filterImageName); + coeff = imgSum (Filter); +#ifdef VERBOSE + printf ("%s: coeff %d\n", filterImageName, coeff); + printImage (Filter, "Filter"); +#endif + assert (Filter->width == Filter->height); // Only square filters + OutStatic = createImage (In->height, In->width); + OutH4 = createImage (In->height, In->width); +#ifdef VERBOSE + printf ("after init\n"); + printImage(In, "In"); +#endif + ticks_t timeStatic = h2_getticks(); // Static convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionStatic(In, OutStatic, Filter, coeff); + } + timeStatic = h2_getticks() - timeStatic; +#ifdef VERBOSE + printf ("after static\n"); + printImage(OutStatic, "Out"); +#endif + + pifc kernelHL = (pifc)h2_malloc(8192); + ticks_t timeCodeGen = h2_getticks(); + switch (Filter->width) + { + case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; + case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; + case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; + default: printf ("Unknown filter size\n"); exit(-1); + } + timeCodeGen = h2_getticks() - timeCodeGen; + +#ifdef VERBOSE + printf ("after codegen\n"); +#endif + + ticks_t timeH4 = h2_getticks(); // Compilette convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionH4(In, OutH4, Filter, kernelHL); + } + timeH4 = h2_getticks() - timeH4; +#ifdef VERBOSE + printf ("after h2\n"); + printImage(OutH4, "Out H4"); +#endif + error = compareImages(OutH4, OutStatic); + printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", + filterImageName, + Filter->width, Filter->height, In->width, In->height, + timeStatic/nXperiment, timeH4/nXperiment, + h2_codeGenTime, h2_insnGenerated, + error); + +#if VERBOSE + writePgmImage(OutStatic, argv[2]); + writePgmImage(OutH4, argv[3]); +#endif + + return (0 == error)?0:-1; +} diff --git a/Demos/Stencil/Stencil.riscv b/Demos/Stencil/Stencil.riscv new file mode 100755 index 0000000000000000000000000000000000000000..60c93461d991da91012ba0558f9cc14c29dff531 GIT binary patch literal 171700 zcmeFa3wTt;{l~q@S=q>+0*V!Dy{x;*VVkD$T5GM0? z)t0}>b7E{M0A#WAyDS=IH0{yQmBmF{7I}=H)W zV)O$mu8Xy;xK2}L5a-Hb9{(-JIsIFIl0MzrZs&O9_!{|57Kw+9?c!mN-hc712Yxo} z(Z~Nf_Gcp>9W`{!<(K{J(P1MlzwCkJQNxojHO`f^zT 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zb5IA57jUxvJQ6slkH68(K_1VSaiYzVDZdwTJ%&JTY~V|l29upQ-xgOB=)<(j_b{V! z*Fvr`&Pav4X=CIZ-xi;iPFJ!<$J{Y;_x9N$ryg}mK_j<7%bEU8F4$rT7aV<1j_2Yr za+`;3F*TeXQigKtw4AOkN|)H;bCE|hl;Oc=RtA%v`yN~HD?H{fka?sT@$7qHA0FwR pi1M{K83zqG`II-}2GMezEw)DHk +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) + { // RISCV has no DIVI + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { // X * NPowerOf2 = X >> N (immediate shift left) + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSR_3(P0, P1, P2); + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include +#include +#include +#include "ReadPgmImage.h" + +typedef int (*pifc)(int[], int, int, int); + + +void printImage(imgStruct_t *img, char *imageName) +{ + printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width ; column++) + { + printf("%03d ", img->pixelsArray[line*img->width+column]); + } + printf("\n"); + } + printf("\n"); +} + +int imgSum (imgStruct_t *img) +{ + int line, column, sum; + sum = 0; + for(int line = 0 ; line < img->height ; line++) + { + for(int column = 0 ; column < img->width; column++) + { + sum += img->pixelsArray[line*img->width+column]; + } + } + return (0 == sum)?1:sum; +} + +#if 0 +unsigned char clamp(int value) +{ + return (unsigned char)(0 > value)?0:(255 < value)?255:value; +} +#else +#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) +#endif + +pifc genKernel1x1(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x3F3F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, line, imgWidth, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, tmp0000, column); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genMUL_4(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = riscv_genADD_3(tmp0003, In, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = riscv_genR_3(tmp0004, tmp0003, immValueZero); + sum = riscv_genMUL_4(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}, immValueZero); + if (!sum.dontFree) h2_freeReg(tmp0004.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0005 = riscv_genDIV_4(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel3x3(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 19 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 28, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 29, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x30003FFF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + njp1 = riscv_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = riscv_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = riscv_genADD_3(tmp0000, stride, njm1); + tmp0001 = riscv_genMUL_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = riscv_genR_3(tmp0003, tmp0002, immValueZero); + sum = riscv_genMUL_4(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}, immValueZero); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = riscv_genADD_3(tmp0004, stride, column); + tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = riscv_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = riscv_genMUL_4(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}, immValueZero); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = riscv_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = riscv_genADD_3(tmp0009, stride, njp1); + tmp0010 = riscv_genMUL_4(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = riscv_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = riscv_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = riscv_genMUL_4(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}, immValueZero); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = riscv_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genMV_2(ni, line); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0015 = riscv_genADD_3(tmp0015, stride, njm1); + tmp0016 = riscv_genMUL_4(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = riscv_genADD_3(tmp0017, In, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = riscv_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = riscv_genMUL_4(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}, immValueZero); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + sum = riscv_genADD_3(sum, sum, tmp0019); + if (!sum.dontFree) h2_freeReg(tmp0019.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0020 = riscv_genADD_3(tmp0020, stride, column); + tmp0021 = riscv_genMUL_4(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = riscv_genADD_3(tmp0022, In, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = riscv_genR_3(tmp0023, tmp0022, immValueZero); + tmp0024 = riscv_genMUL_4(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}, immValueZero); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + sum = riscv_genADD_3(sum, sum, tmp0024); + if (!sum.dontFree) h2_freeReg(tmp0024.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0025 = riscv_genADD_3(tmp0025, stride, njp1); + tmp0026 = riscv_genMUL_4(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = riscv_genADD_3(tmp0027, In, tmp0026); + if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); + tmp0028 = riscv_genR_3(tmp0028, tmp0027, immValueZero); + tmp0029 = riscv_genMUL_4(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}, immValueZero); + if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); + sum = riscv_genADD_3(sum, sum, tmp0029); + if (!sum.dontFree) h2_freeReg(tmp0029.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0030 = riscv_genADD_3(tmp0030, stride, njm1); + tmp0031 = riscv_genMUL_4(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = riscv_genADD_3(tmp0032, In, tmp0031); + if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); + tmp0033 = riscv_genR_3(tmp0033, tmp0032, immValueZero); + tmp0034 = riscv_genMUL_4(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}, immValueZero); + if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); + sum = riscv_genADD_3(sum, sum, tmp0034); + if (!sum.dontFree) h2_freeReg(tmp0034.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0035 = riscv_genADD_3(tmp0035, stride, column); + tmp0036 = riscv_genMUL_4(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = riscv_genADD_3(tmp0037, In, tmp0036); + if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); + tmp0038 = riscv_genR_3(tmp0038, tmp0037, immValueZero); + tmp0039 = riscv_genMUL_4(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}, immValueZero); + if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); + sum = riscv_genADD_3(sum, sum, tmp0039); + if (!sum.dontFree) h2_freeReg(tmp0039.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0040 = riscv_genADD_3(tmp0040, stride, njp1); + tmp0041 = riscv_genMUL_4(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = riscv_genADD_3(tmp0042, In, tmp0041); + if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); + tmp0043 = riscv_genR_3(tmp0043, tmp0042, immValueZero); + tmp0044 = riscv_genMUL_4(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}, immValueZero); + if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); + sum = riscv_genADD_3(sum, sum, tmp0044); + if (!sum.dontFree) h2_freeReg(tmp0044.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0045 = riscv_genDIV_4(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0045); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +pifc genKernel5x5(pifc ptr, int* Filter, int coeff) +{ + /* Code Generation of 41 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; + h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 28, true}; + h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 29, true}; + h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 30, true}; + h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 31, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF0003FFF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + njm2 = riscv_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njm1 = riscv_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp1 = riscv_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + njp2 = riscv_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0000 = riscv_genADD_3(tmp0000, stride, njm2); + tmp0001 = riscv_genMUL_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genADD_3(tmp0002, In, tmp0001); + if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); + tmp0003 = riscv_genR_3(tmp0003, tmp0002, immValueZero); + sum = riscv_genMUL_4(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}, immValueZero); + if (!sum.dontFree) h2_freeReg(tmp0003.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0004 = riscv_genADD_3(tmp0004, stride, njm1); + tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = riscv_genADD_3(tmp0006, In, tmp0005); + if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); + tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); + tmp0008 = riscv_genMUL_4(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}, immValueZero); + if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); + sum = riscv_genADD_3(sum, sum, tmp0008); + if (!sum.dontFree) h2_freeReg(tmp0008.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0009 = riscv_genADD_3(tmp0009, stride, column); + tmp0010 = riscv_genMUL_4(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = riscv_genADD_3(tmp0011, In, tmp0010); + if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); + tmp0012 = riscv_genR_3(tmp0012, tmp0011, immValueZero); + tmp0013 = riscv_genMUL_4(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}, immValueZero); + if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); + sum = riscv_genADD_3(sum, sum, tmp0013); + if (!sum.dontFree) h2_freeReg(tmp0013.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0014 = riscv_genADD_3(tmp0014, stride, njp1); + tmp0015 = riscv_genMUL_4(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = riscv_genADD_3(tmp0016, In, tmp0015); + if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); + tmp0017 = riscv_genR_3(tmp0017, tmp0016, immValueZero); + tmp0018 = riscv_genMUL_4(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}, immValueZero); + if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); + sum = riscv_genADD_3(sum, sum, tmp0018); + if (!sum.dontFree) h2_freeReg(tmp0018.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0019 = riscv_genADD_3(tmp0019, stride, njp2); + tmp0020 = riscv_genMUL_4(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + tmp0021 = riscv_genADD_3(tmp0021, In, tmp0020); + if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); + tmp0022 = riscv_genR_3(tmp0022, tmp0021, immValueZero); + tmp0023 = riscv_genMUL_4(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}, immValueZero); + if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); + sum = riscv_genADD_3(sum, sum, tmp0023); + if (!sum.dontFree) h2_freeReg(tmp0023.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0024 = riscv_genADD_3(tmp0024, stride, njm2); + tmp0025 = riscv_genMUL_4(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); + tmp0026 = riscv_genADD_3(tmp0026, In, tmp0025); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = riscv_genR_3(tmp0027, tmp0026, immValueZero); + tmp0028 = riscv_genMUL_4(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}, immValueZero); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + sum = riscv_genADD_3(sum, sum, tmp0028); + if (!sum.dontFree) h2_freeReg(tmp0028.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0029 = riscv_genADD_3(tmp0029, stride, njm1); + tmp0030 = riscv_genMUL_4(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = riscv_genADD_3(tmp0031, In, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = riscv_genR_3(tmp0032, tmp0031, immValueZero); + tmp0033 = riscv_genMUL_4(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}, immValueZero); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + sum = riscv_genADD_3(sum, sum, tmp0033); + if (!sum.dontFree) h2_freeReg(tmp0033.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0034 = riscv_genADD_3(tmp0034, stride, column); + tmp0035 = riscv_genMUL_4(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = riscv_genADD_3(tmp0036, In, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = riscv_genR_3(tmp0037, tmp0036, immValueZero); + tmp0038 = riscv_genMUL_4(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}, immValueZero); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + sum = riscv_genADD_3(sum, sum, tmp0038); + if (!sum.dontFree) h2_freeReg(tmp0038.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0039 = riscv_genADD_3(tmp0039, stride, njp1); + tmp0040 = riscv_genMUL_4(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = riscv_genADD_3(tmp0041, In, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + tmp0042 = riscv_genR_3(tmp0042, tmp0041, immValueZero); + tmp0043 = riscv_genMUL_4(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}, immValueZero); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + sum = riscv_genADD_3(sum, sum, tmp0043); + if (!sum.dontFree) h2_freeReg(tmp0043.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0044 = riscv_genADD_3(tmp0044, stride, njp2); + tmp0045 = riscv_genMUL_4(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = riscv_genADD_3(tmp0046, In, tmp0045); + if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); + tmp0047 = riscv_genR_3(tmp0047, tmp0046, immValueZero); + tmp0048 = riscv_genMUL_4(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}, immValueZero); + if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); + sum = riscv_genADD_3(sum, sum, tmp0048); + if (!sum.dontFree) h2_freeReg(tmp0048.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genMV_2(ni, line); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0050 = riscv_genADD_3(tmp0050, stride, njm2); + tmp0051 = riscv_genMUL_4(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = riscv_genADD_3(tmp0052, In, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = riscv_genR_3(tmp0053, tmp0052, immValueZero); + tmp0054 = riscv_genMUL_4(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}, immValueZero); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + sum = riscv_genADD_3(sum, sum, tmp0054); + if (!sum.dontFree) h2_freeReg(tmp0054.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0055 = riscv_genADD_3(tmp0055, stride, njm1); + tmp0056 = riscv_genMUL_4(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = riscv_genADD_3(tmp0057, In, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = riscv_genR_3(tmp0058, tmp0057, immValueZero); + tmp0059 = riscv_genMUL_4(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}, immValueZero); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + sum = riscv_genADD_3(sum, sum, tmp0059); + if (!sum.dontFree) h2_freeReg(tmp0059.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0060 = riscv_genADD_3(tmp0060, stride, column); + tmp0061 = riscv_genMUL_4(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = riscv_genADD_3(tmp0062, In, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + tmp0063 = riscv_genR_3(tmp0063, tmp0062, immValueZero); + tmp0064 = riscv_genMUL_4(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}, immValueZero); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + sum = riscv_genADD_3(sum, sum, tmp0064); + if (!sum.dontFree) h2_freeReg(tmp0064.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0065 = riscv_genADD_3(tmp0065, stride, njp1); + tmp0066 = riscv_genMUL_4(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = riscv_genADD_3(tmp0067, In, tmp0066); + if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); + tmp0068 = riscv_genR_3(tmp0068, tmp0067, immValueZero); + tmp0069 = riscv_genMUL_4(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}, immValueZero); + if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); + sum = riscv_genADD_3(sum, sum, tmp0069); + if (!sum.dontFree) h2_freeReg(tmp0069.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0070 = riscv_genADD_3(tmp0070, stride, njp2); + tmp0071 = riscv_genMUL_4(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); + tmp0072 = riscv_genADD_3(tmp0072, In, tmp0071); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = riscv_genR_3(tmp0073, tmp0072, immValueZero); + tmp0074 = riscv_genMUL_4(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}, immValueZero); + if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); + sum = riscv_genADD_3(sum, sum, tmp0074); + if (!sum.dontFree) h2_freeReg(tmp0074.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0075 = riscv_genADD_3(tmp0075, stride, njm2); + tmp0076 = riscv_genMUL_4(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); + tmp0077 = riscv_genADD_3(tmp0077, In, tmp0076); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = riscv_genR_3(tmp0078, tmp0077, immValueZero); + tmp0079 = riscv_genMUL_4(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}, immValueZero); + if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); + sum = riscv_genADD_3(sum, sum, tmp0079); + if (!sum.dontFree) h2_freeReg(tmp0079.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0080 = riscv_genADD_3(tmp0080, stride, njm1); + tmp0081 = riscv_genMUL_4(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); + tmp0082 = riscv_genADD_3(tmp0082, In, tmp0081); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = riscv_genR_3(tmp0083, tmp0082, immValueZero); + tmp0084 = riscv_genMUL_4(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}, immValueZero); + if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); + sum = riscv_genADD_3(sum, sum, tmp0084); + if (!sum.dontFree) h2_freeReg(tmp0084.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0085 = riscv_genADD_3(tmp0085, stride, column); + tmp0086 = riscv_genMUL_4(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); + tmp0087 = riscv_genADD_3(tmp0087, In, tmp0086); + if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); + tmp0088 = riscv_genR_3(tmp0088, tmp0087, immValueZero); + tmp0089 = riscv_genMUL_4(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}, immValueZero); + if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); + sum = riscv_genADD_3(sum, sum, tmp0089); + if (!sum.dontFree) h2_freeReg(tmp0089.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0090 = riscv_genADD_3(tmp0090, stride, njp1); + tmp0091 = riscv_genMUL_4(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); + tmp0092 = riscv_genADD_3(tmp0092, In, tmp0091); + if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); + tmp0093 = riscv_genR_3(tmp0093, tmp0092, immValueZero); + tmp0094 = riscv_genMUL_4(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}, immValueZero); + if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); + sum = riscv_genADD_3(sum, sum, tmp0094); + if (!sum.dontFree) h2_freeReg(tmp0094.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0095 = riscv_genADD_3(tmp0095, stride, njp2); + tmp0096 = riscv_genMUL_4(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); + tmp0097 = riscv_genADD_3(tmp0097, In, tmp0096); + if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); + tmp0098 = riscv_genR_3(tmp0098, tmp0097, immValueZero); + tmp0099 = riscv_genMUL_4(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}, immValueZero); + if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); + sum = riscv_genADD_3(sum, sum, tmp0099); + if (!sum.dontFree) h2_freeReg(tmp0099.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0100 = riscv_genADD_3(tmp0100, stride, njm2); + tmp0101 = riscv_genMUL_4(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); + tmp0102 = riscv_genADD_3(tmp0102, In, tmp0101); + if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); + tmp0103 = riscv_genR_3(tmp0103, tmp0102, immValueZero); + tmp0104 = riscv_genMUL_4(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}, immValueZero); + if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); + sum = riscv_genADD_3(sum, sum, tmp0104); + if (!sum.dontFree) h2_freeReg(tmp0104.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0105 = riscv_genADD_3(tmp0105, stride, njm1); + tmp0106 = riscv_genMUL_4(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); + tmp0107 = riscv_genADD_3(tmp0107, In, tmp0106); + if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); + tmp0108 = riscv_genR_3(tmp0108, tmp0107, immValueZero); + tmp0109 = riscv_genMUL_4(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}, immValueZero); + if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); + sum = riscv_genADD_3(sum, sum, tmp0109); + if (!sum.dontFree) h2_freeReg(tmp0109.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0110 = riscv_genADD_3(tmp0110, stride, column); + tmp0111 = riscv_genMUL_4(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); + tmp0112 = riscv_genADD_3(tmp0112, In, tmp0111); + if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); + tmp0113 = riscv_genR_3(tmp0113, tmp0112, immValueZero); + tmp0114 = riscv_genMUL_4(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}, immValueZero); + if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); + sum = riscv_genADD_3(sum, sum, tmp0114); + if (!sum.dontFree) h2_freeReg(tmp0114.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0115 = riscv_genADD_3(tmp0115, stride, njp1); + tmp0116 = riscv_genMUL_4(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); + tmp0117 = riscv_genADD_3(tmp0117, In, tmp0116); + if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); + tmp0118 = riscv_genR_3(tmp0118, tmp0117, immValueZero); + tmp0119 = riscv_genMUL_4(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}, immValueZero); + if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); + sum = riscv_genADD_3(sum, sum, tmp0119); + if (!sum.dontFree) h2_freeReg(tmp0119.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0120 = riscv_genADD_3(tmp0120, stride, njp2); + tmp0121 = riscv_genMUL_4(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); + tmp0122 = riscv_genADD_3(tmp0122, In, tmp0121); + if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); + tmp0123 = riscv_genR_3(tmp0123, tmp0122, immValueZero); + tmp0124 = riscv_genMUL_4(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}, immValueZero); + if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); + sum = riscv_genADD_3(sum, sum, tmp0124); + if (!sum.dontFree) h2_freeReg(tmp0124.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0125 = riscv_genDIV_4(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0125); + if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +#if 0 +#endif +} + +// Compute a stencil for 1 point +int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) +{ + int line, column, sum = 0; + int offset = (Filter->width)/2; + + for (line = 0; line < Filter->height; line++) + { + for (column = 0; column < Filter->width; column++) + { + int ni = (l + line) - offset; + int nj = (c + column) - offset; + sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; + } + } + return sum / coeff; +} + + +void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelStatic(In, line, column, Filter, coeff); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) +{ + int offset = Filter->width/2; + int result; + for (int line = offset; line < In->height - offset; line++) + { + for (int column = offset; column < In->width - offset; column++) + { + result = kernelHL(In->pixelsArray, line, column, In->width); + Out->pixelsArray[line*Out->width+column] = clamp(result); + } + } +} + +int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) +{ + int errors = 0; + for(int line = 0 ; line < staticImg->height ; line++) + { + for(int column = 0 ; column < staticImg->width ; column++) + { + if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) + { + if (0 == errors) + { + printf("Alert : first difference at line %i column %i\n", line, column); + } + errors++; + } + } + } + return errors; +} + +int main(int argc, char *argv[]) +{ + int error, coeff, nXperiment = 20; + imgStruct_t *In, *OutH4, *OutStatic, *Filter; + char *filterImageName, *inputImageName; + if (argc < 5) + { + printf ("./Stencil \n"); + exit(-1); + } + + inputImageName = argv[1]; + filterImageName = argv[4]; + In = readPgmImage(inputImageName); + Filter = readPgmImage(filterImageName); + coeff = imgSum (Filter); +#ifdef VERBOSE + printf ("%s: coeff %d\n", filterImageName, coeff); + printImage (Filter, "Filter"); +#endif + assert (Filter->width == Filter->height); // Only square filters + OutStatic = createImage (In->height, In->width); + OutH4 = createImage (In->height, In->width); +#ifdef VERBOSE + printf ("after init\n"); + printImage(In, "In"); +#endif + ticks_t timeStatic = h2_getticks(); // Static convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionStatic(In, OutStatic, Filter, coeff); + } + timeStatic = h2_getticks() - timeStatic; +#ifdef VERBOSE + printf ("after static\n"); + printImage(OutStatic, "Out"); +#endif + + pifc kernelHL = (pifc)h2_malloc(8192); + ticks_t timeCodeGen = h2_getticks(); + switch (Filter->width) + { + case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; + case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; + case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; + default: printf ("Unknown filter size\n"); exit(-1); + } + timeCodeGen = h2_getticks() - timeCodeGen; + +#ifdef VERBOSE + printf ("after codegen\n"); +#endif + + ticks_t timeH4 = h2_getticks(); // Compilette convolution + for (int i = 0; i < nXperiment; i++) + { + convolutionH4(In, OutH4, Filter, kernelHL); + } + timeH4 = h2_getticks() - timeH4; +#ifdef VERBOSE + printf ("after h2\n"); + printImage(OutH4, "Out H4"); +#endif + error = compareImages(OutH4, OutStatic); + printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", + filterImageName, + Filter->width, Filter->height, In->width, In->height, + timeStatic/nXperiment, timeH4/nXperiment, + h2_codeGenTime, h2_insnGenerated, + error); + +#if VERBOSE + writePgmImage(OutStatic, argv[2]); + writePgmImage(OutH4, argv[3]); +#endif + + return (0 == error)?0:-1; +} diff --git a/Demos/VectorMatrix/VectorMatrix.aarch64 b/Demos/VectorMatrix/VectorMatrix.aarch64 new file mode 100755 index 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zgh9_0q2zA-T>ei0Bb$(Z6m;Fs7IG>CwX;oGT{TYE^Z3R2b$w7y_~`(Fc+l@Riv1=c zaen~#J zuW7x01vIo~NBMQ#)b;nt|F_^J-%);DUv)$HuTkL;LjST!qjvm9q=`iNbsg3_e_;ug zPT0cosQ%w__;tP34~2hK8Re>cdi}P;uj{&2u2_bR@>j9nMTBIj{`!6HvhdF+p=)5r1@Wg +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +void A64_RET__I_64_1(){ /* ret */ + aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + +#ifdef H2_DEBUG_INSN +printf("%p : A64_RET__I_64_1\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_8_8(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_8_16(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_16_8(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_16_4(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_16_4\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_32_1(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_SUB_RRI_I_32_1(int r0,int r1,int i0){ /* sub */ + aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_32_2(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_32_4(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_64_2(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_64_2\n", h2_asm_pc); +#endif +} +void A64_SUB_RRI_I_64_1(int r0,int r1,int i0){ /* sub */ + aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_SUB_RRR_I_64_1(int r0,int r1,int r2){ /* sub */ + aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_SUB_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_MOV_RRR_I_8_8(int r0,int r1,int r2){ /* mv */ + aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RRR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_MOV_RRR_I_16_8(int r0,int r1,int r2){ /* mv */ + aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_MV_RR_I_32_4(int r0,int r1){ /* mv */ + aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MV_RR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_MOV_RR_I_32_1(int r0,int r1){ /* mv */ + aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_MOVI_RI_I_32_4(int r0,int i0){ /* mv */ + aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOVI_RI_I_32_4\n", h2_asm_pc); +#endif +} +void A64_MOVI_RI_I_32_2(int r0,int i0){ /* mv */ + aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOVI_RI_I_32_2\n", h2_asm_pc); +#endif +} +void A64_DUP_RR_I_32_4(int r0,int r1){ /* mv */ + aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_DUP_RR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_MOV_RI_I_32_1(int r0,int i0){ /* mv */ + aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_MOV_RR_I_32_2(int r0,int r1){ /* mv */ + aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_DUP_RR_I_32_1(int r0,int r1){ /* mv */ + aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_DUP_RR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_DUP_RR_I_32_2(int r0,int r1){ /* mv */ + aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_DUP_RR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_MOV_RR_I_64_1(int r0,int r1){ /* mv */ + aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_MOV_RI_I_64_1(int r0,int i0){ /* mv */ + aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MOV_RI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_DUP_RR_I_64_1(int r0,int r1){ /* mv */ + aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_DUP_RR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_DUP_RR_I_64_2(int r0,int r1){ /* mv */ + aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_DUP_RR_I_64_2\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_8_8(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_8_16(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_16_4(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_16_4\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_16_8(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_32_4(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_32_1(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_32_2(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_MUL_RRR_I_64_1(int r0,int r1,int r2){ /* mul */ + aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_MUL_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_8_8(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_8_16(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_16_8(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_16_4(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_16_4\n", h2_asm_pc); +#endif +} +void A64_ADD_RRI_I_32_1(int r0,int r1,int i0){ /* add */ + aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_32_1(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_32_2(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_32_4(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_64_2(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_64_2\n", h2_asm_pc); +#endif +} +void A64_ADD_RRR_I_64_1(int r0,int r1,int r2){ /* add */ + aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_ADD_RRI_I_64_1(int r0,int r1,int i0){ /* add */ + aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ADD_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_LSR_RRI_I_32_1(int r0,int r1,int i0){ /* sr */ + aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSR_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_LSR_RRR_I_32_1(int r0,int r1,int r2){ /* sr */ + aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSR_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_LSR_RRI_I_64_1(int r0,int r1,int i0){ /* sr */ + aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSR_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_LSR_RRR_I_64_1(int r0,int r1,int r2){ /* sr */ + aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSR_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_8_8(int r0,int r1){ /* w */ + aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_8_16(int r0,int r1){ /* w */ + aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_8_16\n", h2_asm_pc); +#endif +} +void A64_STRB_RRI_I_8_1(int r0,int r1,int i0){ /* w */ + aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STRB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_16_8(int r0,int r1){ /* w */ + aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_16_4(int r0,int r1){ /* w */ + aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_16_4\n", h2_asm_pc); +#endif +} +void A64_STRH_RRI_I_16_1(int r0,int r1,int i0){ /* w */ + aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STRH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void A64_STR_RRR_I_32_1(int r0,int r1,int r2){ /* w */ + aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STR_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_STR_RRI_I_32_1(int r0,int r1,int i0){ /* w */ + aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STR_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_STR_RRI_I_32_2(int r0,int r1,int i0){ /* w */ + aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STR_RRI_I_32_2\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_32_4(int r0,int r1){ /* w */ + aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_STR_RRR_I_64_1(int r0,int r1,int r2){ /* w */ + aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STR_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_ST1_RR_I_64_2(int r0,int r1){ /* w */ + aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_ST1_RR_I_64_2\n", h2_asm_pc); +#endif +} +void A64_STR_RRI_I_64_1(int r0,int r1,int i0){ /* w */ + aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_STR_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_8_16(int r0,int r1){ /* r */ + aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_8_16\n", h2_asm_pc); +#endif +} +void A64_LDRB_RRI_I_8_1(int r0,int r1,int i0){ /* r */ + aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LDRB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_8_8(int r0,int r1){ /* r */ + aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_8_8\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_16_4(int r0,int r1){ /* r */ + aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_16_4\n", h2_asm_pc); +#endif +} +void A64_LDRH_RRI_I_16_1(int r0,int r1,int i0){ /* r */ + aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LDRH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_16_8(int r0,int r1){ /* r */ + aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_16_8\n", h2_asm_pc); +#endif +} +void A64_LDR_RRI_I_32_1(int r0,int r1,int i0){ /* r */ + aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LDR_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_LDP_RRI_I_32_2(int r0,int r1,int i0){ /* r */ + aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LDP_RRI_I_32_2\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_32_2(int r0,int r1){ /* r */ + aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_32_2\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_32_4(int r0,int r1){ /* r */ + aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_32_4\n", h2_asm_pc); +#endif +} +void A64_LDR_RRR_I_64_1(int r0,int r1,int r2){ /* r */ + aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LDR_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void A64_LD1_RR_I_64_2(int r0,int r1){ /* r */ + aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LD1_RR_I_64_2\n", h2_asm_pc); +#endif +} +void A64_LSL_RRI_I_32_1(int r0,int r1,int i0){ /* sl */ + aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSL_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void A64_LSL_RRR_I_32_1(int r0,int r1,int r2){ /* sl */ + aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void A64_LSL_RRI_I_64_1(int r0,int r1,int i0){ /* sl */ + aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSL_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void A64_LSL_RRR_I_64_1(int r0,int r1,int r2){ /* sl */ + aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : A64_LSL_RRR_I_64_1\n", h2_asm_pc); +#endif +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +/* -*- c -*- */ +// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c +#include +#include +#include +#include +#define T 4 +typedef int d_t; +typedef d_t matrix_t [T][T]; +typedef d_t vector_t [T]; +typedef d_t (*pifvv)(vector_t, vector_t); + +pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) +{ + /* Code Generation of 5 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = aarch64_genMUL_3(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0001 = aarch64_genADD_3(tmp0001, o, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = aarch64_genMUL_3(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0003 = aarch64_genADD_3(tmp0003, i, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = aarch64_genR_3(tmp0004, tmp0003, immValueZero); + tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = aarch64_genMUL_3(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0007 = aarch64_genADD_3(tmp0007, i, tmp0006); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + tmp0008 = aarch64_genR_3(tmp0008, tmp0007, immValueZero); + tmp0009 = aarch64_genMUL_3(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}); + if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); + tmp0010 = aarch64_genADD_3(tmp0010, tmp0005, tmp0009); + if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = aarch64_genMUL_3(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0012 = aarch64_genADD_3(tmp0012, i, tmp0011); + if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); + tmp0013 = aarch64_genR_3(tmp0013, tmp0012, immValueZero); + tmp0014 = aarch64_genMUL_3(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}); + if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); + tmp0015 = aarch64_genADD_3(tmp0015, tmp0010, tmp0014); + if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = aarch64_genMUL_3(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0017 = aarch64_genADD_3(tmp0017, i, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = aarch64_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = aarch64_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + tmp0020 = aarch64_genADD_3(tmp0020, tmp0015, tmp0019); + if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + aarch64_genW_3(tmp0001, tmp0020, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0021 = aarch64_genMUL_3(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0022 = aarch64_genADD_3(tmp0022, o, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = aarch64_genMUL_3(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0024 = aarch64_genADD_3(tmp0024, i, tmp0023); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + tmp0025 = aarch64_genR_3(tmp0025, tmp0024, immValueZero); + tmp0026 = aarch64_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = aarch64_genMUL_3(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0028 = aarch64_genADD_3(tmp0028, i, tmp0027); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + tmp0029 = aarch64_genR_3(tmp0029, tmp0028, immValueZero); + tmp0030 = aarch64_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = aarch64_genADD_3(tmp0031, tmp0026, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = aarch64_genMUL_3(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0033 = aarch64_genADD_3(tmp0033, i, tmp0032); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + tmp0034 = aarch64_genR_3(tmp0034, tmp0033, immValueZero); + tmp0035 = aarch64_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = aarch64_genADD_3(tmp0036, tmp0031, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = aarch64_genMUL_3(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0038 = aarch64_genADD_3(tmp0038, i, tmp0037); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + tmp0039 = aarch64_genR_3(tmp0039, tmp0038, immValueZero); + tmp0040 = aarch64_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = aarch64_genADD_3(tmp0041, tmp0036, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + aarch64_genW_3(tmp0022, tmp0041, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0042 = aarch64_genMUL_3(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0043 = aarch64_genADD_3(tmp0043, o, tmp0042); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + tmp0044 = aarch64_genMUL_3(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0045 = aarch64_genADD_3(tmp0045, i, tmp0044); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = aarch64_genR_3(tmp0046, tmp0045, immValueZero); + tmp0047 = aarch64_genMUL_3(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}); + if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); + tmp0048 = aarch64_genMUL_3(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0049 = aarch64_genADD_3(tmp0049, i, tmp0048); + if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); + tmp0050 = aarch64_genR_3(tmp0050, tmp0049, immValueZero); + tmp0051 = aarch64_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = aarch64_genADD_3(tmp0052, tmp0047, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = aarch64_genMUL_3(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0054 = aarch64_genADD_3(tmp0054, i, tmp0053); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + tmp0055 = aarch64_genR_3(tmp0055, tmp0054, immValueZero); + tmp0056 = aarch64_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = aarch64_genADD_3(tmp0057, tmp0052, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = aarch64_genMUL_3(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0059 = aarch64_genADD_3(tmp0059, i, tmp0058); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + tmp0060 = aarch64_genR_3(tmp0060, tmp0059, immValueZero); + tmp0061 = aarch64_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = aarch64_genADD_3(tmp0062, tmp0057, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + aarch64_genW_3(tmp0043, tmp0062, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0063 = aarch64_genMUL_3(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0064 = aarch64_genADD_3(tmp0064, o, tmp0063); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + tmp0065 = aarch64_genMUL_3(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0066 = aarch64_genADD_3(tmp0066, i, tmp0065); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = aarch64_genR_3(tmp0067, tmp0066, immValueZero); + tmp0068 = aarch64_genMUL_3(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}); + if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); + tmp0069 = aarch64_genMUL_3(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0070 = aarch64_genADD_3(tmp0070, i, tmp0069); + if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); + tmp0071 = aarch64_genR_3(tmp0071, tmp0070, immValueZero); + tmp0072 = aarch64_genMUL_3(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = aarch64_genADD_3(tmp0073, tmp0068, tmp0072); + if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); + if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); + tmp0074 = aarch64_genMUL_3(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0075 = aarch64_genADD_3(tmp0075, i, tmp0074); + if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); + tmp0076 = aarch64_genR_3(tmp0076, tmp0075, immValueZero); + tmp0077 = aarch64_genMUL_3(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = aarch64_genADD_3(tmp0078, tmp0073, tmp0077); + if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); + if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); + tmp0079 = aarch64_genMUL_3(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0080 = aarch64_genADD_3(tmp0080, i, tmp0079); + if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); + tmp0081 = aarch64_genR_3(tmp0081, tmp0080, immValueZero); + tmp0082 = aarch64_genMUL_3(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = aarch64_genADD_3(tmp0083, tmp0078, tmp0082); + if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); + if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); + aarch64_genW_3(tmp0064, tmp0083, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) +{ + o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; + o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; + o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; + o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; + return o[3]; +} + +#if 0 // What the binary code should be with a translation matrix +d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) +{ + + o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; + o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; + o[2] = m[2][2] * i[2] + m[3][2] * i[3]; + o[3] = + i[3]; + return o[3]; +} +#endif +d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) +{ + for (int column = 0; column < T; column++) + { + o[column] = 0; + for (int line = 0; line < T; line++) + { + o[column] += i[line] * m[line][column]; + + } + } + return o[3]; +} + + +int VectorMatrixProductCount(matrix_t mat) +{ + int op = 0; + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + switch (mat[line][column]) + { + case 0 : op += 0; break; + case 1 : op += 1; break; + default: op += 2; break; + } + } + } + return op; +} + + +void printMatrix (matrix_t m, char msg[]) +{ + printf ("%s:\n", msg); + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + printf ("%4d ", m[line][column]); + } + printf ("\n"); + } + printf ("\n"); +} + +void printVector (vector_t v, char msg[]) +{ + for (int i = 0; i < T; i++) + printf ("%4d ", v[i]); + printf ("%s\n", msg); +} + +bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) +{ + int has_differences = false; + for (int line = 0; line < nVector; line++) + for (int i = 0; i < T; i++) + { + if (ref[line][i] != other[line][i]) + has_differences = true; + if (doPrint) + printf("%4d ", other[line][i]); + } + /* printf("%s : ", msg); */ + /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ + return has_differences; +} + +int main (int argc, char *argv[]) +{ + matrix_t m; + char *matrixName; + // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; + vector_t *out, *cout, *in; + uint64_t timeGeneral, timeCompilette; + pifvv vmProduct; + int tmp, doPrint, nXperiment; + unsigned long acc; + bool resultValid; + + if (argc != 19) + { + printf ("Not enough arguments %d\n", argc); + printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); + exit (-1); + } + doPrint = 0; + acc = 0; + nXperiment = atoi (argv[1]); + matrixName = argv[2]; + for (int line = 0; line < 4; line++) + for (int column = 0; column < 4; column++) + { + m[line][column] = atoi (argv[3 + line*4+column]); + } +#ifdef VERBOSE + printMatrix(m, matrixName); +#endif + + in = calloc(nXperiment, sizeof (vector_t)); + out = calloc(nXperiment, sizeof (vector_t)); + cout = calloc(nXperiment, sizeof (vector_t)); + + for (int line = 0; line < nXperiment; line++) + for (int column = 0; column < 4; column++) + in[line][column] = random () % 1000; + + tmp = VectorMatrixProductCount (m); + printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); + +// Repeat one instruction and count ticks +#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} + +#ifdef VERBOSE + printVector (in[0], "Input vector #0"); +#endif + + acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ + DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) + +#ifdef VERBOSE + printVector (out[0], "Output vector #0 (general)"); +#endif + +#if 0 // Possible test with a source level unrolled version + uint64_t timeUnrolled; + vector_t uout0, uout1; + acc += VectorMatrixProductUnrolled (uout0, in0, m); + DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); + vectorCompare(out1, uout1, "Unrolled out0", doPrint); +#endif + + vmProduct = (pifvv) h2_malloc(1024); + vmProduct = genVectorMatrixProduct (vmProduct, m); + acc += vmProduct (cout[0], in[0]); + DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); + +#ifdef VERBOSE + printVector (cout[0], "Output vector #0 (compilette)"); +#endif + + resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); + + printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", + matrixName, nXperiment, + timeGeneral, timeCompilette, + h2_codeGenTime, h2_insnGenerated, + resultValid?"true":"false"); + return resultValid; +} diff --git a/Demos/VectorMatrix/VectorMatrix.power b/Demos/VectorMatrix/VectorMatrix.power new file mode 100755 index 0000000000000000000000000000000000000000..3cf332b703c4aebb261c30c4221ad8674f510874 GIT binary patch literal 80624 zcmeFa4R}=5wLiR1GRaIn86av@#0i2;YzP6VoqPZ@A!_)LrW%oYsmzcBlNv)zf*oW+ zW@6d~OT9_JHYjRn)#AO>m)o1(i?_5lQT`TN>P;)ssECQinh>r{TYEbJ^3!@R1>^*1e?S5+sZ$Ug8JShLv^W;zAjthi)E)ZUEf$%jK2)A7zJo^IS)(eE&FA(m! zKzPjs!qYDhUVNT#ef>{o(V5r#T2amZHU)ZMRg?hLPr9keVPR!Mz07&WbKT?Kc-CoW z%!j(aJ8wVhIo-{aGlyB)nLg$|vzDdhMKf34DC;?MfDN4PXZ|xoY|ohh8#uG+oTf*N zy>-%a^;U0}+2i&6Ccn}1`qvvxtUoV~H4I7G%S2pNU6PZ=mTWdL@6LX;$zfu7IX2`w zoyDbFSx%mfdhQiE^wZ!zv=a{Hpd~G zZ^>S^=d`NcllSZsyGt!!xO>Yh=G|Kok>4Hf@4ok}+K~5Of8Sl2^82qhQafO*z~y;+ z6X*TSPqebB>N@bdZgYEobi;$^D!uiK;~R>LGa81XGp;F4&1f*OFFkgY^SdR_(Up>0)mC&5y96bLy-`o3AeSW~XHw?ucq~Y+%=W&#CM4J^y-WtH)MqpDOZku|0Or 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XKfZptzwnlb`R^@Q%BvoO*9`szd0{3w literal 0 HcmV?d00001 diff --git a/Demos/VectorMatrix/VectorMatrix.power.c b/Demos/VectorMatrix/VectorMatrix.power.c new file mode 100644 index 0000000..ef2ed96 --- /dev/null +++ b/Demos/VectorMatrix/VectorMatrix.power.c @@ -0,0 +1,1457 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +void P1_BLR__I_32_1(){ /* ret */ + power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + +#ifdef H2_DEBUG_INSN +printf("%p : P1_BLR__I_32_1\n", h2_asm_pc); +#endif +} +void P1_SUBI_RRI_I_32_1(int r0,int r1,int i0){ /* sub */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_SUBI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void PPC_SUB_RRR_I_32_1(int r0,int r2,int r1){ /* sub */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : PPC_SUB_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_LI_RI_I_32_1(int r0,int i0){ /* mv */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LI_RI_I_32_1\n", h2_asm_pc); +#endif +} +void P1_MV_RR_I_32_1(int r0,int r1){ /* mv */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_MV_RR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_LI_RI_I_64_1(int r0,int i0){ /* mv */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LI_RI_I_64_1\n", h2_asm_pc); +#endif +} +void V2_03_VSRB_RRR_I_8_16(int r0,int r1,int r2){ /* sr */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSRB_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void V2_03_VSRH_RRR_I_16_8(int r0,int r1,int r2){ /* sr */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSRH_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void V2_03_VSRW_RRR_I_32_4(int r0,int r1,int r2){ /* sr */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSRW_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void V2_07_VSRD_RRR_I_64_2(int r0,int r1,int r2){ /* sr */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_07_VSRD_RRR_I_64_2\n", h2_asm_pc); +#endif +} +void V2_03_VSR_RRR_I_128_1(int r0,int r1,int r2){ /* sr */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSR_RRR_I_128_1\n", h2_asm_pc); +#endif +} +void P1_MULLW_RRR_I_32_1(int r0,int r1,int r2){ /* mul */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_MULLW_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_MULLI_RRI_I_64_1(int r0,int r1,int i0){ /* mul */ + power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_MULLI_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void V2_03_VADDSBS_RRR_I_8_16(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDSBS_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void V2_03_VADDUBS_RRR_I_8_16(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDUBS_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void V2_03_VADDSHS_RRR_I_16_8(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDSHS_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void V2_03_VADDUHS_RRR_I_16_8(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDUHS_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void V2_03_VADDUWS_RRR_I_32_4(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDUWS_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void P1_ADDI_RRI_I_32_1(int r0,int r1,int i0){ /* add */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_ADDI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void V2_03_VADDSWS_RRR_I_32_4(int r0,int r1,int r2){ /* add */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VADDSWS_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void P1_ADD_RRR_I_32_1(int r0,int r1,int r2){ /* add */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_ADD_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_ADD_RRR_I_64_1(int r0,int r1,int r2){ /* add */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_ADD_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void P1_ADDI_RRI_I_64_1(int r0,int r1,int i0){ /* add */ + power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_ADDI_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void P1_STB_RRI_I_8_1(int r1,int r0,int i0){ /* w */ + power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_STB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void P1_STBX_RRR_I_8_1(int r1,int r0,int r2){ /* w */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_STBX_RRR_I_8_1\n", h2_asm_pc); +#endif +} +void P1_STH_RRI_I_16_1(int r1,int r0,int i0){ /* w */ + power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_STH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void P1_STW_RRI_I_32_1(int r1,int r0,int i0){ /* w */ + power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_STW_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void P1_STWX_RRR_I_32_1(int r0,int r1,int r2){ /* w */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_STWX_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void PPC_STD_RRI_I_64_1(int r1,int r0,int i0){ /* w */ + power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : PPC_STD_RRI_I_64_1\n", h2_asm_pc); +#endif +} +void P1_LBZ_RRI_I_8_1(int r0,int r1,int i0){ /* r */ + power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LBZ_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void P1_LBZX_RRR_I_8_1(int r0,int r1,int r2){ /* r */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LBZX_RRR_I_8_1\n", h2_asm_pc); +#endif +} +void P1_LHZ_RRI_I_16_1(int r0,int r1,int i0){ /* r */ + power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LHZ_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void P1_LWZ_RRI_I_32_1(int r0,int r1,int i0){ /* r */ + power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LWZ_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void P1_LWZU_RRI_I_32_1(int r0,int r1,int i0){ /* r */ + power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LWZU_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void P1_LWZUX_RRR_I_32_1(int r0,int r1,int r2){ /* r */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LWZUX_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_LWZX_RRR_I_32_1(int r0,int r1,int r2){ /* r */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_LWZX_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void V2_03_VSLB_RRR_I_8_16(int r0,int r1,int r2){ /* sl */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSLB_RRR_I_8_16\n", h2_asm_pc); +#endif +} +void V2_03_VSLH_RRR_I_16_8(int r0,int r1,int r2){ /* sl */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSLH_RRR_I_16_8\n", h2_asm_pc); +#endif +} +void P1_SLW_RRR_I_32_1(int r1,int r0,int r2){ /* sl */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_SLW_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void P1_SLW__RRR_I_32_1(int r1,int r0,int r2){ /* sl */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : P1_SLW__RRR_I_32_1\n", h2_asm_pc); +#endif +} +void V2_03_VSLW_RRR_I_32_4(int r0,int r1,int r2){ /* sl */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSLW_RRR_I_32_4\n", h2_asm_pc); +#endif +} +void PPC_SLD_RRR_I_64_1(int r1,int r0,int r2){ /* sl */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : PPC_SLD_RRR_I_64_1\n", h2_asm_pc); +#endif +} +void PPC_SLD__RRR_I_64_1(int r1,int r0,int r2){ /* sl */ + power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : PPC_SLD__RRR_I_64_1\n", h2_asm_pc); +#endif +} +void V2_07_VSLD_RRR_I_64_2(int r0,int r1,int r2){ /* sl */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_07_VSLD_RRR_I_64_2\n", h2_asm_pc); +#endif +} +void V2_03_VSL_RRR_I_128_1(int r0,int r1,int r2){ /* sl */ + power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : V2_03_VSL_RRR_I_128_1\n", h2_asm_pc); +#endif +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} + +/* End Header autogenerated part */ +/* -*- c -*- */ +// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c +#include +#include +#include +#include +#define T 4 +typedef int d_t; +typedef d_t matrix_t [T][T]; +typedef d_t vector_t [T]; +typedef d_t (*pifvv)(vector_t, vector_t); + +pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) +{ + /* Code Generation of 5 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 4, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 64, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x381F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp0000 = power_genMUL_3(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0001 = power_genADD_3(tmp0001, o, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = power_genMUL_3(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0003 = power_genADD_3(tmp0003, i, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = power_genR_3(tmp0004, tmp0003, immValueZero); + tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = power_genMUL_3(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0007 = power_genADD_3(tmp0007, i, tmp0006); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + tmp0008 = power_genR_3(tmp0008, tmp0007, immValueZero); + tmp0009 = power_genMUL_3(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}); + if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); + tmp0010 = power_genADD_3(tmp0010, tmp0005, tmp0009); + if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = power_genMUL_3(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0012 = power_genADD_3(tmp0012, i, tmp0011); + if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); + tmp0013 = power_genR_3(tmp0013, tmp0012, immValueZero); + tmp0014 = power_genMUL_3(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}); + if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); + tmp0015 = power_genADD_3(tmp0015, tmp0010, tmp0014); + if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = power_genMUL_3(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0017 = power_genADD_3(tmp0017, i, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = power_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = power_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + tmp0020 = power_genADD_3(tmp0020, tmp0015, tmp0019); + if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + power_genW_3(tmp0001, tmp0020, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0021 = power_genMUL_3(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0022 = power_genADD_3(tmp0022, o, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = power_genMUL_3(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0024 = power_genADD_3(tmp0024, i, tmp0023); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + tmp0025 = power_genR_3(tmp0025, tmp0024, immValueZero); + tmp0026 = power_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = power_genMUL_3(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0028 = power_genADD_3(tmp0028, i, tmp0027); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + tmp0029 = power_genR_3(tmp0029, tmp0028, immValueZero); + tmp0030 = power_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = power_genADD_3(tmp0031, tmp0026, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = power_genMUL_3(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0033 = power_genADD_3(tmp0033, i, tmp0032); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + tmp0034 = power_genR_3(tmp0034, tmp0033, immValueZero); + tmp0035 = power_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = power_genADD_3(tmp0036, tmp0031, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = power_genMUL_3(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0038 = power_genADD_3(tmp0038, i, tmp0037); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + tmp0039 = power_genR_3(tmp0039, tmp0038, immValueZero); + tmp0040 = power_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = power_genADD_3(tmp0041, tmp0036, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + power_genW_3(tmp0022, tmp0041, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0042 = power_genMUL_3(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0043 = power_genADD_3(tmp0043, o, tmp0042); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + tmp0044 = power_genMUL_3(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0045 = power_genADD_3(tmp0045, i, tmp0044); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = power_genR_3(tmp0046, tmp0045, immValueZero); + tmp0047 = power_genMUL_3(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}); + if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); + tmp0048 = power_genMUL_3(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0049 = power_genADD_3(tmp0049, i, tmp0048); + if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); + tmp0050 = power_genR_3(tmp0050, tmp0049, immValueZero); + tmp0051 = power_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = power_genADD_3(tmp0052, tmp0047, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = power_genMUL_3(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0054 = power_genADD_3(tmp0054, i, tmp0053); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + tmp0055 = power_genR_3(tmp0055, tmp0054, immValueZero); + tmp0056 = power_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = power_genADD_3(tmp0057, tmp0052, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = power_genMUL_3(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0059 = power_genADD_3(tmp0059, i, tmp0058); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + tmp0060 = power_genR_3(tmp0060, tmp0059, immValueZero); + tmp0061 = power_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = power_genADD_3(tmp0062, tmp0057, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + power_genW_3(tmp0043, tmp0062, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0063 = power_genMUL_3(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0064 = power_genADD_3(tmp0064, o, tmp0063); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + tmp0065 = power_genMUL_3(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0066 = power_genADD_3(tmp0066, i, tmp0065); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = power_genR_3(tmp0067, tmp0066, immValueZero); + tmp0068 = power_genMUL_3(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}); + if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); + tmp0069 = power_genMUL_3(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0070 = power_genADD_3(tmp0070, i, tmp0069); + if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); + tmp0071 = power_genR_3(tmp0071, tmp0070, immValueZero); + tmp0072 = power_genMUL_3(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = power_genADD_3(tmp0073, tmp0068, tmp0072); + if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); + if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); + tmp0074 = power_genMUL_3(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0075 = power_genADD_3(tmp0075, i, tmp0074); + if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); + tmp0076 = power_genR_3(tmp0076, tmp0075, immValueZero); + tmp0077 = power_genMUL_3(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = power_genADD_3(tmp0078, tmp0073, tmp0077); + if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); + if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); + tmp0079 = power_genMUL_3(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); + tmp0080 = power_genADD_3(tmp0080, i, tmp0079); + if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); + tmp0081 = power_genR_3(tmp0081, tmp0080, immValueZero); + tmp0082 = power_genMUL_3(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = power_genADD_3(tmp0083, tmp0078, tmp0082); + if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); + if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); + power_genW_3(tmp0064, tmp0083, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) +{ + o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; + o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; + o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; + o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; + return o[3]; +} + +#if 0 // What the binary code should be with a translation matrix +d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) +{ + + o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; + o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; + o[2] = m[2][2] * i[2] + m[3][2] * i[3]; + o[3] = + i[3]; + return o[3]; +} +#endif +d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) +{ + for (int column = 0; column < T; column++) + { + o[column] = 0; + for (int line = 0; line < T; line++) + { + o[column] += i[line] * m[line][column]; + + } + } + return o[3]; +} + + +int VectorMatrixProductCount(matrix_t mat) +{ + int op = 0; + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + switch (mat[line][column]) + { + case 0 : op += 0; break; + case 1 : op += 1; break; + default: op += 2; break; + } + } + } + return op; +} + + +void printMatrix (matrix_t m, char msg[]) +{ + printf ("%s:\n", msg); + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + printf ("%4d ", m[line][column]); + } + printf ("\n"); + } + printf ("\n"); +} + +void printVector (vector_t v, char msg[]) +{ + for (int i = 0; i < T; i++) + printf ("%4d ", v[i]); + printf ("%s\n", msg); +} + +bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) +{ + int has_differences = false; + for (int line = 0; line < nVector; line++) + for (int i = 0; i < T; i++) + { + if (ref[line][i] != other[line][i]) + has_differences = true; + if (doPrint) + printf("%4d ", other[line][i]); + } + /* printf("%s : ", msg); */ + /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ + return has_differences; +} + +int main (int argc, char *argv[]) +{ + matrix_t m; + char *matrixName; + // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; + vector_t *out, *cout, *in; + uint64_t timeGeneral, timeCompilette; + pifvv vmProduct; + int tmp, doPrint, nXperiment; + unsigned long acc; + bool resultValid; + + if (argc != 19) + { + printf ("Not enough arguments %d\n", argc); + printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); + exit (-1); + } + doPrint = 0; + acc = 0; + nXperiment = atoi (argv[1]); + matrixName = argv[2]; + for (int line = 0; line < 4; line++) + for (int column = 0; column < 4; column++) + { + m[line][column] = atoi (argv[3 + line*4+column]); + } +#ifdef VERBOSE + printMatrix(m, matrixName); +#endif + + in = calloc(nXperiment, sizeof (vector_t)); + out = calloc(nXperiment, sizeof (vector_t)); + cout = calloc(nXperiment, sizeof (vector_t)); + + for (int line = 0; line < nXperiment; line++) + for (int column = 0; column < 4; column++) + in[line][column] = random () % 1000; + + tmp = VectorMatrixProductCount (m); + printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); + +// Repeat one instruction and count ticks +#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} + +#ifdef VERBOSE + printVector (in[0], "Input vector #0"); +#endif + + acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ + DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) + +#ifdef VERBOSE + printVector (out[0], "Output vector #0 (general)"); +#endif + +#if 0 // Possible test with a source level unrolled version + uint64_t timeUnrolled; + vector_t uout0, uout1; + acc += VectorMatrixProductUnrolled (uout0, in0, m); + DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); + vectorCompare(out1, uout1, "Unrolled out0", doPrint); +#endif + + vmProduct = (pifvv) h2_malloc(1024); + vmProduct = genVectorMatrixProduct (vmProduct, m); + acc += vmProduct (cout[0], in[0]); + DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); + +#ifdef VERBOSE + printVector (cout[0], "Output vector #0 (compilette)"); +#endif + + resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); + + printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", + matrixName, nXperiment, + timeGeneral, timeCompilette, + h2_codeGenTime, h2_insnGenerated, + resultValid?"true":"false"); + return resultValid; +} diff --git a/Demos/VectorMatrix/VectorMatrix.riscv b/Demos/VectorMatrix/VectorMatrix.riscv new file mode 100755 index 0000000000000000000000000000000000000000..8eea702214e5f50c8ce2d86440163b9568f12d15 GIT binary patch literal 62544 zcmdSC3tSXOwm;rO%`l4i*o=v6es03jFpkI$cQL_T?_FbXWE5Y!u8MCrqM{}~gD55_ z(lazZ5aKBKNR%J~K>|8NNlbj<$RH{rF=$xh3nRuvQ4^Dxjr#wd?im>n6gOt?{p)9{ zyQ`|Z>zq3EJ*Up8Y8Lk$7^+YxIOjh%?puzoR<}}cFHmM3$Ek35f%E1(I34H1{ho7| zt|^b|D7fCZfqqKl(~sd7h3hChmwrCDrXQ6do62X8ufU1p-`^caXF1i8|IwL(^E|*w zKWYcpL4Jnv7@l`lA^rNHS|WbbE-H7U1Ijy~oPO7FO+PAkws9@$uSMJF=Z$>&Im`a~ zWz?jpyEty@E`{`yX{j&&8_H4rfq(RTyq+71a@Y3#j6C`|=?i>q+Qh)uCjH^HX*1_7 z_`}?3uSZ085BkHj*JgJQnxubymi~{9y7VkGlQRw;j#TakdItR?9=FG@HGcG75B%t# zCw^3?6z`apDf_V7t55e@l=|lXy#MF6UW+`$yWf~PUOi*!tRMWB?{7YH z>6UiZMX$n?|NfL7>-vx0`wta8nd6?qZxVj#F4t7D&E@(zTzk7*kHhs}U9NwN>)9^X zf53H|%k?^3bC>1!b>ME?qjy%glxuN)&gGiq|G!+WN8q}*%k>akr?^~);(DLUH5WNK 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zbC2b*WIW0rg(UjYJgZhWG&TBbRa_rbp$c9l7&irKZ!i+e7A_ENE2=6R)pozy*4C&t zs*BVLi`3NAXcBQ@P%&<-vS@pgT4jnfuTXU*I=`y=+uO~4IF7-!{563H>Az~p+EXPG zNo=eU7{A6Q{IjW`~Fjcj^uBM|#^#>XnTiE037}RWCQxjU!hUSfJNgFKJol6nXdz-e}Y*5n@vj=b+QehQ#w_^vcv7=LVGe;F&0cyOwT*Ct4#n#_G}Tvv&dXrQ&K& zFc!vzNAI5v!nlK}J|@P`M64>>#ySTkN;q3&uPKQ-;=T5k8RpZEku&GG`5TjE7nw@v zNq;_G@B#F#sv2Fb|Byz-FHb@}nq9wY&G|$euB0XBX1f}{J<d zuP2!55x(%67=#U&P8ubvwPXsvNE?HwD8uPA=u1R#oK9=~NU=!qI>@K>n9C<`Rz@-5 zOC+`IQYw7*e0DX~tHw({OZ^jOyd_%oqcJ17Wl$i zXJ0p#>R=2bZ=w3#r&ZM1nZ(35G2Xsed32DKB^mC(&EsDgW`d8q5o{L(&*f<#b8NE4 zPDS8faKXK@$;b2D5DL6DK5lCmK97ixcwHaQ@sEP9)uaLF`#AFQ8|;tp-9GE(`QD98 z7Me7p}>1>`~CRv<6KMTmS`px29g z0XGzI?`PFZI^#-2zC~c3_Xnlmn~%J`UZA2Ikv8}d`JQ1Vkh_qlKAzrL#xrmfkv33X zaQ_1aw!;c+1LM_*79aOaEz zz9PikR-uiL=T941y!R^J$=C>1)@Sm~H|?oHNAZ=470AbU&N#kB=qTQ8Si#~Wq%T`x v^J_wQ(MT@{7a+2q3lVv +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +void RV32I_RET__I_32_1(){ /* RET */ + riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_RET__I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SUB_RRR_I_32_1(int r3,int r1,int r2){ /* SUB */ + riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SUB_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_MV_RR_I_32_1(int r0,int r1){ /* MV */ + riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_MV_RR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_MV_RI_I_32_1(int r3,int i1){ /* MV */ + riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_MV_RI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SLLI_RRI_I_32_1(int r3,int r1,int i0){ /* SL */ + riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SLLI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SLL_RRR_I_32_1(int r3,int r1,int r2){ /* SL */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SLL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32M_MUL_RRR_I_32_1(int r3,int r1,int r2){ /* MUL */ + riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32M_MUL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_ADDI_RRI_I_32_1(int r1,int r0,int i0){ /* ADD */ + riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_ADDI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_ADD_RRR_I_32_1(int r3,int r1,int r2){ /* ADD */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_ADD_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_LB_RRI_I_8_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void RV32I_LH_RRI_I_16_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void RV32I_LW_RRI_I_32_1(int r3,int r1,int i1){ /* R */ + riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_LW_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SRLI_RRI_I_32_1(int r3,int r1,int i0){ /* SR */ + riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SRLI_RRI_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SRL_RRR_I_32_1(int r3,int r1,int r2){ /* SR */ + riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SRL_RRR_I_32_1\n", h2_asm_pc); +#endif +} +void RV32I_SB_RRI_I_8_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SB_RRI_I_8_1\n", h2_asm_pc); +#endif +} +void RV32I_SH_RRI_I_16_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SH_RRI_I_16_1\n", h2_asm_pc); +#endif +} +void RV32I_SW_RRI_I_32_1(int r1,int r2,int i1){ /* W */ + riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); +#ifdef H2_DEBUG_INSN +printf("%p : RV32I_SW_RRI_I_32_1\n", h2_asm_pc); +#endif +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +/* -*- c -*- */ +// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c +#include +#include +#include +#include +#define T 4 +typedef int d_t; +typedef d_t matrix_t [T][T]; +typedef d_t vector_t [T]; +typedef d_t (*pifvv)(vector_t, vector_t); + +pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) +{ + /* Code Generation of 5 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xF1F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp0000 = riscv_genMUL_4(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0001 = riscv_genADD_3(tmp0001, o, tmp0000); + if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); + tmp0002 = riscv_genMUL_4(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0003 = riscv_genADD_3(tmp0003, i, tmp0002); + if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); + tmp0004 = riscv_genR_3(tmp0004, tmp0003, immValueZero); + tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}, immValueZero); + if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); + tmp0006 = riscv_genMUL_4(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0007 = riscv_genADD_3(tmp0007, i, tmp0006); + if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); + tmp0008 = riscv_genR_3(tmp0008, tmp0007, immValueZero); + tmp0009 = riscv_genMUL_4(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}, immValueZero); + if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); + tmp0010 = riscv_genADD_3(tmp0010, tmp0005, tmp0009); + if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); + if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); + tmp0011 = riscv_genMUL_4(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0012 = riscv_genADD_3(tmp0012, i, tmp0011); + if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); + tmp0013 = riscv_genR_3(tmp0013, tmp0012, immValueZero); + tmp0014 = riscv_genMUL_4(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}, immValueZero); + if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); + tmp0015 = riscv_genADD_3(tmp0015, tmp0010, tmp0014); + if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); + if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); + tmp0016 = riscv_genMUL_4(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0017 = riscv_genADD_3(tmp0017, i, tmp0016); + if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); + tmp0018 = riscv_genR_3(tmp0018, tmp0017, immValueZero); + tmp0019 = riscv_genMUL_4(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}, immValueZero); + if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); + tmp0020 = riscv_genADD_3(tmp0020, tmp0015, tmp0019); + if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); + if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); + riscv_genW_3(tmp0001, tmp0020, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0021 = riscv_genMUL_4(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0022 = riscv_genADD_3(tmp0022, o, tmp0021); + if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); + tmp0023 = riscv_genMUL_4(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0024 = riscv_genADD_3(tmp0024, i, tmp0023); + if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); + tmp0025 = riscv_genR_3(tmp0025, tmp0024, immValueZero); + tmp0026 = riscv_genMUL_4(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}, immValueZero); + if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); + tmp0027 = riscv_genMUL_4(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0028 = riscv_genADD_3(tmp0028, i, tmp0027); + if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); + tmp0029 = riscv_genR_3(tmp0029, tmp0028, immValueZero); + tmp0030 = riscv_genMUL_4(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}, immValueZero); + if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); + tmp0031 = riscv_genADD_3(tmp0031, tmp0026, tmp0030); + if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); + if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); + tmp0032 = riscv_genMUL_4(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0033 = riscv_genADD_3(tmp0033, i, tmp0032); + if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); + tmp0034 = riscv_genR_3(tmp0034, tmp0033, immValueZero); + tmp0035 = riscv_genMUL_4(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}, immValueZero); + if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); + tmp0036 = riscv_genADD_3(tmp0036, tmp0031, tmp0035); + if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); + if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); + tmp0037 = riscv_genMUL_4(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0038 = riscv_genADD_3(tmp0038, i, tmp0037); + if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); + tmp0039 = riscv_genR_3(tmp0039, tmp0038, immValueZero); + tmp0040 = riscv_genMUL_4(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}, immValueZero); + if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); + tmp0041 = riscv_genADD_3(tmp0041, tmp0036, tmp0040); + if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); + if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); + riscv_genW_3(tmp0022, tmp0041, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0042 = riscv_genMUL_4(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0043 = riscv_genADD_3(tmp0043, o, tmp0042); + if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); + tmp0044 = riscv_genMUL_4(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0045 = riscv_genADD_3(tmp0045, i, tmp0044); + if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); + tmp0046 = riscv_genR_3(tmp0046, tmp0045, immValueZero); + tmp0047 = riscv_genMUL_4(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}, immValueZero); + if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); + tmp0048 = riscv_genMUL_4(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0049 = riscv_genADD_3(tmp0049, i, tmp0048); + if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); + tmp0050 = riscv_genR_3(tmp0050, tmp0049, immValueZero); + tmp0051 = riscv_genMUL_4(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}, immValueZero); + if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); + tmp0052 = riscv_genADD_3(tmp0052, tmp0047, tmp0051); + if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); + if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); + tmp0053 = riscv_genMUL_4(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0054 = riscv_genADD_3(tmp0054, i, tmp0053); + if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); + tmp0055 = riscv_genR_3(tmp0055, tmp0054, immValueZero); + tmp0056 = riscv_genMUL_4(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}, immValueZero); + if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); + tmp0057 = riscv_genADD_3(tmp0057, tmp0052, tmp0056); + if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); + if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); + tmp0058 = riscv_genMUL_4(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0059 = riscv_genADD_3(tmp0059, i, tmp0058); + if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); + tmp0060 = riscv_genR_3(tmp0060, tmp0059, immValueZero); + tmp0061 = riscv_genMUL_4(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}, immValueZero); + if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); + tmp0062 = riscv_genADD_3(tmp0062, tmp0057, tmp0061); + if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); + if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); + riscv_genW_3(tmp0043, tmp0062, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp0063 = riscv_genMUL_4(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0064 = riscv_genADD_3(tmp0064, o, tmp0063); + if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); + tmp0065 = riscv_genMUL_4(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0066 = riscv_genADD_3(tmp0066, i, tmp0065); + if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); + tmp0067 = riscv_genR_3(tmp0067, tmp0066, immValueZero); + tmp0068 = riscv_genMUL_4(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}, immValueZero); + if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); + tmp0069 = riscv_genMUL_4(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0070 = riscv_genADD_3(tmp0070, i, tmp0069); + if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); + tmp0071 = riscv_genR_3(tmp0071, tmp0070, immValueZero); + tmp0072 = riscv_genMUL_4(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}, immValueZero); + if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); + tmp0073 = riscv_genADD_3(tmp0073, tmp0068, tmp0072); + if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); + if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); + tmp0074 = riscv_genMUL_4(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0075 = riscv_genADD_3(tmp0075, i, tmp0074); + if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); + tmp0076 = riscv_genR_3(tmp0076, tmp0075, immValueZero); + tmp0077 = riscv_genMUL_4(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}, immValueZero); + if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); + tmp0078 = riscv_genADD_3(tmp0078, tmp0073, tmp0077); + if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); + if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); + tmp0079 = riscv_genMUL_4(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); + tmp0080 = riscv_genADD_3(tmp0080, i, tmp0079); + if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); + tmp0081 = riscv_genR_3(tmp0081, tmp0080, immValueZero); + tmp0082 = riscv_genMUL_4(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}, immValueZero); + if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); + tmp0083 = riscv_genADD_3(tmp0083, tmp0078, tmp0082); + if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); + if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); + riscv_genW_3(tmp0064, tmp0083, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return ptr; +} + +d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) +{ + o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; + o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; + o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; + o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; + return o[3]; +} + +#if 0 // What the binary code should be with a translation matrix +d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) +{ + + o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; + o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; + o[2] = m[2][2] * i[2] + m[3][2] * i[3]; + o[3] = + i[3]; + return o[3]; +} +#endif +d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) +{ + for (int column = 0; column < T; column++) + { + o[column] = 0; + for (int line = 0; line < T; line++) + { + o[column] += i[line] * m[line][column]; + + } + } + return o[3]; +} + + +int VectorMatrixProductCount(matrix_t mat) +{ + int op = 0; + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + switch (mat[line][column]) + { + case 0 : op += 0; break; + case 1 : op += 1; break; + default: op += 2; break; + } + } + } + return op; +} + + +void printMatrix (matrix_t m, char msg[]) +{ + printf ("%s:\n", msg); + for (int column = 0; column < T; column++) + { + for (int line = 0; line < T; line++) + { + printf ("%4d ", m[line][column]); + } + printf ("\n"); + } + printf ("\n"); +} + +void printVector (vector_t v, char msg[]) +{ + for (int i = 0; i < T; i++) + printf ("%4d ", v[i]); + printf ("%s\n", msg); +} + +bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) +{ + int has_differences = false; + for (int line = 0; line < nVector; line++) + for (int i = 0; i < T; i++) + { + if (ref[line][i] != other[line][i]) + has_differences = true; + if (doPrint) + printf("%4d ", other[line][i]); + } + /* printf("%s : ", msg); */ + /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ + return has_differences; +} + +int main (int argc, char *argv[]) +{ + matrix_t m; + char *matrixName; + // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; + vector_t *out, *cout, *in; + uint64_t timeGeneral, timeCompilette; + pifvv vmProduct; + int tmp, doPrint, nXperiment; + unsigned long acc; + bool resultValid; + + if (argc != 19) + { + printf ("Not enough arguments %d\n", argc); + printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); + exit (-1); + } + doPrint = 0; + acc = 0; + nXperiment = atoi (argv[1]); + matrixName = argv[2]; + for (int line = 0; line < 4; line++) + for (int column = 0; column < 4; column++) + { + m[line][column] = atoi (argv[3 + line*4+column]); + } +#ifdef VERBOSE + printMatrix(m, matrixName); +#endif + + in = calloc(nXperiment, sizeof (vector_t)); + out = calloc(nXperiment, sizeof (vector_t)); + cout = calloc(nXperiment, sizeof (vector_t)); + + for (int line = 0; line < nXperiment; line++) + for (int column = 0; column < 4; column++) + in[line][column] = random () % 1000; + + tmp = VectorMatrixProductCount (m); + printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); + +// Repeat one instruction and count ticks +#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} + +#ifdef VERBOSE + printVector (in[0], "Input vector #0"); +#endif + + acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ + DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) + +#ifdef VERBOSE + printVector (out[0], "Output vector #0 (general)"); +#endif + +#if 0 // Possible test with a source level unrolled version + uint64_t timeUnrolled; + vector_t uout0, uout1; + acc += VectorMatrixProductUnrolled (uout0, in0, m); + DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); + vectorCompare(out1, uout1, "Unrolled out0", doPrint); +#endif + + vmProduct = (pifvv) h2_malloc(1024); + vmProduct = genVectorMatrixProduct (vmProduct, m); + acc += vmProduct (cout[0], in[0]); + DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); + +#ifdef VERBOSE + printVector (cout[0], "Output vector #0 (compilette)"); +#endif + + resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); + + printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", + matrixName, nXperiment, + timeGeneral, timeCompilette, + h2_codeGenTime, h2_insnGenerated, + resultValid?"true":"false"); + return resultValid; +} diff --git a/HybroGen/IsaDescription.interp b/HybroGen/IsaDescription.interp new file mode 100644 index 0000000..c1157f7 --- /dev/null +++ b/HybroGen/IsaDescription.interp @@ -0,0 +1,58 @@ +token literal names: +null +'ARCH' +'|' +'[' +']' +'i' +'u' +'f' +null +null +null +null +null +':' +null + +token symbolic names: +null +null +null +null +null +null +null +null +WS +COMMENT +INT +NAME +NEWLINE +SEMICOL +CINLINE + +rule names: +isadescription +headerlines +archline +isalines +commentline +isaline +emptyline +bindescr +binelem +binvalue +regbin +expbin +asmdescr +extname +arith +opname +regName +semname +reglist + + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 16, 133, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 6, 3, 47, 10, 3, 13, 3, 14, 3, 48, 3, 4, 3, 4, 3, 4, 6, 4, 54, 10, 4, 13, 4, 14, 4, 55, 3, 4, 3, 4, 3, 5, 3, 5, 3, 5, 7, 5, 63, 10, 5, 12, 5, 14, 5, 66, 11, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 6, 9, 78, 10, 9, 13, 9, 14, 9, 79, 3, 10, 3, 10, 3, 10, 5, 10, 85, 10, 10, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 5, 12, 94, 10, 12, 3, 12, 3, 12, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 5, 13, 103, 10, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 5, 14, 114, 10, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 3, 20, 3, 20, 7, 20, 128, 10, 20, 12, 20, 14, 20, 131, 11, 20, 3, 20, 2, 2, 21, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 2, 3, 3, 2, 7, 9, 2, 127, 2, 40, 3, 2, 2, 2, 4, 46, 3, 2, 2, 2, 6, 50, 3, 2, 2, 2, 8, 64, 3, 2, 2, 2, 10, 67, 3, 2, 2, 2, 12, 69, 3, 2, 2, 2, 14, 74, 3, 2, 2, 2, 16, 77, 3, 2, 2, 2, 18, 84, 3, 2, 2, 2, 20, 86, 3, 2, 2, 2, 22, 88, 3, 2, 2, 2, 24, 97, 3, 2, 2, 2, 26, 106, 3, 2, 2, 2, 28, 115, 3, 2, 2, 2, 30, 117, 3, 2, 2, 2, 32, 119, 3, 2, 2, 2, 34, 121, 3, 2, 2, 2, 36, 123, 3, 2, 2, 2, 38, 125, 3, 2, 2, 2, 40, 41, 5, 4, 3, 2, 41, 42, 5, 8, 5, 2, 42, 3, 3, 2, 2, 2, 43, 47, 5, 10, 6, 2, 44, 47, 5, 6, 4, 2, 45, 47, 5, 14, 8, 2, 46, 43, 3, 2, 2, 2, 46, 44, 3, 2, 2, 2, 46, 45, 3, 2, 2, 2, 47, 48, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 48, 49, 3, 2, 2, 2, 49, 5, 3, 2, 2, 2, 50, 51, 7, 3, 2, 2, 51, 53, 7, 13, 2, 2, 52, 54, 7, 12, 2, 2, 53, 52, 3, 2, 2, 2, 54, 55, 3, 2, 2, 2, 55, 53, 3, 2, 2, 2, 55, 56, 3, 2, 2, 2, 56, 57, 3, 2, 2, 2, 57, 58, 7, 14, 2, 2, 58, 7, 3, 2, 2, 2, 59, 63, 5, 10, 6, 2, 60, 63, 5, 14, 8, 2, 61, 63, 5, 12, 7, 2, 62, 59, 3, 2, 2, 2, 62, 60, 3, 2, 2, 2, 62, 61, 3, 2, 2, 2, 63, 66, 3, 2, 2, 2, 64, 62, 3, 2, 2, 2, 64, 65, 3, 2, 2, 2, 65, 9, 3, 2, 2, 2, 66, 64, 3, 2, 2, 2, 67, 68, 7, 11, 2, 2, 68, 11, 3, 2, 2, 2, 69, 70, 5, 16, 9, 2, 70, 71, 7, 4, 2, 2, 71, 72, 5, 26, 14, 2, 72, 73, 7, 14, 2, 2, 73, 13, 3, 2, 2, 2, 74, 75, 7, 14, 2, 2, 75, 15, 3, 2, 2, 2, 76, 78, 5, 18, 10, 2, 77, 76, 3, 2, 2, 2, 78, 79, 3, 2, 2, 2, 79, 77, 3, 2, 2, 2, 79, 80, 3, 2, 2, 2, 80, 17, 3, 2, 2, 2, 81, 85, 5, 20, 11, 2, 82, 85, 5, 22, 12, 2, 83, 85, 5, 24, 13, 2, 84, 81, 3, 2, 2, 2, 84, 82, 3, 2, 2, 2, 84, 83, 3, 2, 2, 2, 85, 19, 3, 2, 2, 2, 86, 87, 7, 12, 2, 2, 87, 21, 3, 2, 2, 2, 88, 89, 7, 13, 2, 2, 89, 90, 7, 5, 2, 2, 90, 93, 7, 12, 2, 2, 91, 92, 7, 15, 2, 2, 92, 94, 7, 12, 2, 2, 93, 91, 3, 2, 2, 2, 93, 94, 3, 2, 2, 2, 94, 95, 3, 2, 2, 2, 95, 96, 7, 6, 2, 2, 96, 23, 3, 2, 2, 2, 97, 98, 7, 16, 2, 2, 98, 99, 7, 5, 2, 2, 99, 102, 7, 12, 2, 2, 100, 101, 7, 15, 2, 2, 101, 103, 7, 12, 2, 2, 102, 100, 3, 2, 2, 2, 102, 103, 3, 2, 2, 2, 103, 104, 3, 2, 2, 2, 104, 105, 7, 6, 2, 2, 105, 25, 3, 2, 2, 2, 106, 107, 5, 28, 15, 2, 107, 108, 5, 30, 16, 2, 108, 109, 7, 12, 2, 2, 109, 110, 7, 12, 2, 2, 110, 111, 5, 36, 19, 2, 111, 113, 5, 32, 17, 2, 112, 114, 5, 38, 20, 2, 113, 112, 3, 2, 2, 2, 113, 114, 3, 2, 2, 2, 114, 27, 3, 2, 2, 2, 115, 116, 7, 13, 2, 2, 116, 29, 3, 2, 2, 2, 117, 118, 9, 2, 2, 2, 118, 31, 3, 2, 2, 2, 119, 120, 7, 13, 2, 2, 120, 33, 3, 2, 2, 2, 121, 122, 7, 13, 2, 2, 122, 35, 3, 2, 2, 2, 123, 124, 7, 13, 2, 2, 124, 37, 3, 2, 2, 2, 125, 129, 5, 34, 18, 2, 126, 128, 5, 34, 18, 2, 127, 126, 3, 2, 2, 2, 128, 131, 3, 2, 2, 2, 129, 127, 3, 2, 2, 2, 129, 130, 3, 2, 2, 2, 130, 39, 3, 2, 2, 2, 131, 129, 3, 2, 2, 2, 13, 46, 48, 55, 62, 64, 79, 84, 93, 102, 113, 129] \ No newline at end of file diff --git a/HybroGen/IsaDescription.tokens b/HybroGen/IsaDescription.tokens new file mode 100644 index 0000000..2dcd920 --- /dev/null +++ b/HybroGen/IsaDescription.tokens @@ -0,0 +1,22 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +WS=8 +COMMENT=9 +INT=10 +NAME=11 +NEWLINE=12 +SEMICOL=13 +CINLINE=14 +'ARCH'=1 +'|'=2 +'['=3 +']'=4 +'i'=5 +'u'=6 +'f'=7 +':'=13 diff --git a/HybroGen/IsaDescriptionLexer.interp b/HybroGen/IsaDescriptionLexer.interp new file mode 100644 index 0000000..23a6756 --- /dev/null +++ b/HybroGen/IsaDescriptionLexer.interp @@ -0,0 +1,59 @@ +token literal names: +null +'ARCH' +'|' +'[' +']' +'i' +'u' +'f' +null +null +null +null +null +':' +null + +token symbolic names: +null +null +null +null +null +null +null +null +WS +COMMENT +INT +NAME +NEWLINE +SEMICOL +CINLINE + +rule names: +T__0 +T__1 +T__2 +T__3 +T__4 +T__5 +T__6 +WS +COMMENT +INT +NAME +NEWLINE +SEMICOL +CINLINE + +channel names: +DEFAULT_TOKEN_CHANNEL +HIDDEN + +mode names: +DEFAULT_MODE + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 16, 91, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 6, 9, 50, 10, 9, 13, 9, 14, 9, 51, 3, 9, 3, 9, 3, 10, 3, 10, 7, 10, 58, 10, 10, 12, 10, 14, 10, 61, 11, 10, 3, 10, 3, 10, 3, 11, 6, 11, 66, 10, 11, 13, 11, 14, 11, 67, 3, 12, 3, 12, 7, 12, 72, 10, 12, 12, 12, 14, 12, 75, 11, 12, 3, 13, 5, 13, 78, 10, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 15, 3, 15, 6, 15, 86, 10, 15, 13, 15, 14, 15, 87, 3, 15, 3, 15, 3, 59, 2, 16, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 27, 15, 29, 16, 3, 2, 7, 4, 2, 11, 11, 34, 34, 3, 2, 50, 59, 4, 2, 67, 92, 99, 124, 7, 2, 48, 48, 50, 59, 67, 92, 97, 97, 99, 124, 3, 2, 127, 127, 2, 96, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 2, 27, 3, 2, 2, 2, 2, 29, 3, 2, 2, 2, 3, 31, 3, 2, 2, 2, 5, 36, 3, 2, 2, 2, 7, 38, 3, 2, 2, 2, 9, 40, 3, 2, 2, 2, 11, 42, 3, 2, 2, 2, 13, 44, 3, 2, 2, 2, 15, 46, 3, 2, 2, 2, 17, 49, 3, 2, 2, 2, 19, 55, 3, 2, 2, 2, 21, 65, 3, 2, 2, 2, 23, 69, 3, 2, 2, 2, 25, 77, 3, 2, 2, 2, 27, 81, 3, 2, 2, 2, 29, 83, 3, 2, 2, 2, 31, 32, 7, 67, 2, 2, 32, 33, 7, 84, 2, 2, 33, 34, 7, 69, 2, 2, 34, 35, 7, 74, 2, 2, 35, 4, 3, 2, 2, 2, 36, 37, 7, 126, 2, 2, 37, 6, 3, 2, 2, 2, 38, 39, 7, 93, 2, 2, 39, 8, 3, 2, 2, 2, 40, 41, 7, 95, 2, 2, 41, 10, 3, 2, 2, 2, 42, 43, 7, 107, 2, 2, 43, 12, 3, 2, 2, 2, 44, 45, 7, 119, 2, 2, 45, 14, 3, 2, 2, 2, 46, 47, 7, 104, 2, 2, 47, 16, 3, 2, 2, 2, 48, 50, 9, 2, 2, 2, 49, 48, 3, 2, 2, 2, 50, 51, 3, 2, 2, 2, 51, 49, 3, 2, 2, 2, 51, 52, 3, 2, 2, 2, 52, 53, 3, 2, 2, 2, 53, 54, 8, 9, 2, 2, 54, 18, 3, 2, 2, 2, 55, 59, 7, 37, 2, 2, 56, 58, 11, 2, 2, 2, 57, 56, 3, 2, 2, 2, 58, 61, 3, 2, 2, 2, 59, 60, 3, 2, 2, 2, 59, 57, 3, 2, 2, 2, 60, 62, 3, 2, 2, 2, 61, 59, 3, 2, 2, 2, 62, 63, 5, 25, 13, 2, 63, 20, 3, 2, 2, 2, 64, 66, 9, 3, 2, 2, 65, 64, 3, 2, 2, 2, 66, 67, 3, 2, 2, 2, 67, 65, 3, 2, 2, 2, 67, 68, 3, 2, 2, 2, 68, 22, 3, 2, 2, 2, 69, 73, 9, 4, 2, 2, 70, 72, 9, 5, 2, 2, 71, 70, 3, 2, 2, 2, 72, 75, 3, 2, 2, 2, 73, 71, 3, 2, 2, 2, 73, 74, 3, 2, 2, 2, 74, 24, 3, 2, 2, 2, 75, 73, 3, 2, 2, 2, 76, 78, 7, 15, 2, 2, 77, 76, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 79, 3, 2, 2, 2, 79, 80, 7, 12, 2, 2, 80, 26, 3, 2, 2, 2, 81, 82, 7, 60, 2, 2, 82, 28, 3, 2, 2, 2, 83, 85, 7, 125, 2, 2, 84, 86, 10, 6, 2, 2, 85, 84, 3, 2, 2, 2, 86, 87, 3, 2, 2, 2, 87, 85, 3, 2, 2, 2, 87, 88, 3, 2, 2, 2, 88, 89, 3, 2, 2, 2, 89, 90, 7, 127, 2, 2, 90, 30, 3, 2, 2, 2, 9, 2, 51, 59, 67, 73, 77, 87, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroGen/IsaDescriptionLexer.py b/HybroGen/IsaDescriptionLexer.py new file mode 100644 index 0000000..1ace933 --- /dev/null +++ b/HybroGen/IsaDescriptionLexer.py @@ -0,0 +1,92 @@ +# Generated from IsaDescription.g4 by ANTLR 4.9.2 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\20") + buf.write("[\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") + buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") + buf.write("\t\16\4\17\t\17\3\2\3\2\3\2\3\2\3\2\3\3\3\3\3\4\3\4\3") + buf.write("\5\3\5\3\6\3\6\3\7\3\7\3\b\3\b\3\t\6\t\62\n\t\r\t\16\t") + buf.write("\63\3\t\3\t\3\n\3\n\7\n:\n\n\f\n\16\n=\13\n\3\n\3\n\3") + buf.write("\13\6\13B\n\13\r\13\16\13C\3\f\3\f\7\fH\n\f\f\f\16\fK") + buf.write("\13\f\3\r\5\rN\n\r\3\r\3\r\3\16\3\16\3\17\3\17\6\17V\n") + buf.write("\17\r\17\16\17W\3\17\3\17\3;\2\20\3\3\5\4\7\5\t\6\13\7") + buf.write("\r\b\17\t\21\n\23\13\25\f\27\r\31\16\33\17\35\20\3\2\7") + buf.write("\4\2\13\13\"\"\3\2\62;\4\2C\\c|\7\2\60\60\62;C\\aac|\3") + buf.write("\2\177\177\2`\2\3\3\2\2\2\2\5\3\2\2\2\2\7\3\2\2\2\2\t") + buf.write("\3\2\2\2\2\13\3\2\2\2\2\r\3\2\2\2\2\17\3\2\2\2\2\21\3") + buf.write("\2\2\2\2\23\3\2\2\2\2\25\3\2\2\2\2\27\3\2\2\2\2\31\3\2") + buf.write("\2\2\2\33\3\2\2\2\2\35\3\2\2\2\3\37\3\2\2\2\5$\3\2\2\2") + buf.write("\7&\3\2\2\2\t(\3\2\2\2\13*\3\2\2\2\r,\3\2\2\2\17.\3\2") + buf.write("\2\2\21\61\3\2\2\2\23\67\3\2\2\2\25A\3\2\2\2\27E\3\2\2") + buf.write("\2\31M\3\2\2\2\33Q\3\2\2\2\35S\3\2\2\2\37 \7C\2\2 !\7") + buf.write("T\2\2!\"\7E\2\2\"#\7J\2\2#\4\3\2\2\2$%\7~\2\2%\6\3\2\2") + buf.write("\2&\'\7]\2\2\'\b\3\2\2\2()\7_\2\2)\n\3\2\2\2*+\7k\2\2") + buf.write("+\f\3\2\2\2,-\7w\2\2-\16\3\2\2\2./\7h\2\2/\20\3\2\2\2") + buf.write("\60\62\t\2\2\2\61\60\3\2\2\2\62\63\3\2\2\2\63\61\3\2\2") + buf.write("\2\63\64\3\2\2\2\64\65\3\2\2\2\65\66\b\t\2\2\66\22\3\2") + buf.write("\2\2\67;\7%\2\28:\13\2\2\298\3\2\2\2:=\3\2\2\2;<\3\2\2") + buf.write("\2;9\3\2\2\2<>\3\2\2\2=;\3\2\2\2>?\5\31\r\2?\24\3\2\2") + buf.write("\2@B\t\3\2\2A@\3\2\2\2BC\3\2\2\2CA\3\2\2\2CD\3\2\2\2D") + buf.write("\26\3\2\2\2EI\t\4\2\2FH\t\5\2\2GF\3\2\2\2HK\3\2\2\2IG") + buf.write("\3\2\2\2IJ\3\2\2\2J\30\3\2\2\2KI\3\2\2\2LN\7\17\2\2ML") + buf.write("\3\2\2\2MN\3\2\2\2NO\3\2\2\2OP\7\f\2\2P\32\3\2\2\2QR\7") + buf.write("<\2\2R\34\3\2\2\2SU\7}\2\2TV\n\6\2\2UT\3\2\2\2VW\3\2\2") + buf.write("\2WU\3\2\2\2WX\3\2\2\2XY\3\2\2\2YZ\7\177\2\2Z\36\3\2\2") + buf.write("\2\t\2\63;CIMW\3\b\2\2") + return buf.getvalue() + + +class IsaDescriptionLexer(Lexer): + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + T__0 = 1 + T__1 = 2 + T__2 = 3 + T__3 = 4 + T__4 = 5 + T__5 = 6 + T__6 = 7 + WS = 8 + COMMENT = 9 + INT = 10 + NAME = 11 + NEWLINE = 12 + SEMICOL = 13 + CINLINE = 14 + + channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] + + modeNames = [ "DEFAULT_MODE" ] + + literalNames = [ "", + "'ARCH'", "'|'", "'['", "']'", "'i'", "'u'", "'f'", "':'" ] + + symbolicNames = [ "", + "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", "CINLINE" ] + + ruleNames = [ "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", + "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", + "CINLINE" ] + + grammarFileName = "IsaDescription.g4" + + def __init__(self, input=None, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) + self._actions = None + self._predicates = None + + diff --git a/HybroGen/IsaDescriptionLexer.tokens b/HybroGen/IsaDescriptionLexer.tokens new file mode 100644 index 0000000..2dcd920 --- /dev/null +++ b/HybroGen/IsaDescriptionLexer.tokens @@ -0,0 +1,22 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +WS=8 +COMMENT=9 +INT=10 +NAME=11 +NEWLINE=12 +SEMICOL=13 +CINLINE=14 +'ARCH'=1 +'|'=2 +'['=3 +']'=4 +'i'=5 +'u'=6 +'f'=7 +':'=13 diff --git a/HybroGen/IsaDescriptionListener.py b/HybroGen/IsaDescriptionListener.py new file mode 100644 index 0000000..f1a6b6f --- /dev/null +++ b/HybroGen/IsaDescriptionListener.py @@ -0,0 +1,183 @@ +# Generated from IsaDescription.g4 by ANTLR 4.9.2 +from antlr4 import * +if __name__ is not None and "." in __name__: + from .IsaDescriptionParser import IsaDescriptionParser +else: + from IsaDescriptionParser import IsaDescriptionParser + +# This class defines a complete listener for a parse tree produced by IsaDescriptionParser. +class IsaDescriptionListener(ParseTreeListener): + + # Enter a parse tree produced by IsaDescriptionParser#isadescription. + def enterIsadescription(self, ctx:IsaDescriptionParser.IsadescriptionContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#isadescription. + def exitIsadescription(self, ctx:IsaDescriptionParser.IsadescriptionContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#headerlines. + def enterHeaderlines(self, ctx:IsaDescriptionParser.HeaderlinesContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#headerlines. + def exitHeaderlines(self, ctx:IsaDescriptionParser.HeaderlinesContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#archline. + def enterArchline(self, ctx:IsaDescriptionParser.ArchlineContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#archline. + def exitArchline(self, ctx:IsaDescriptionParser.ArchlineContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#isalines. + def enterIsalines(self, ctx:IsaDescriptionParser.IsalinesContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#isalines. + def exitIsalines(self, ctx:IsaDescriptionParser.IsalinesContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#commentline. + def enterCommentline(self, ctx:IsaDescriptionParser.CommentlineContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#commentline. + def exitCommentline(self, ctx:IsaDescriptionParser.CommentlineContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#isaline. + def enterIsaline(self, ctx:IsaDescriptionParser.IsalineContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#isaline. + def exitIsaline(self, ctx:IsaDescriptionParser.IsalineContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#emptyline. + def enterEmptyline(self, ctx:IsaDescriptionParser.EmptylineContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#emptyline. + def exitEmptyline(self, ctx:IsaDescriptionParser.EmptylineContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#bindescr. + def enterBindescr(self, ctx:IsaDescriptionParser.BindescrContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#bindescr. + def exitBindescr(self, ctx:IsaDescriptionParser.BindescrContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#binelem. + def enterBinelem(self, ctx:IsaDescriptionParser.BinelemContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#binelem. + def exitBinelem(self, ctx:IsaDescriptionParser.BinelemContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#binvalue. + def enterBinvalue(self, ctx:IsaDescriptionParser.BinvalueContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#binvalue. + def exitBinvalue(self, ctx:IsaDescriptionParser.BinvalueContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#regbin. + def enterRegbin(self, ctx:IsaDescriptionParser.RegbinContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#regbin. + def exitRegbin(self, ctx:IsaDescriptionParser.RegbinContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#expbin. + def enterExpbin(self, ctx:IsaDescriptionParser.ExpbinContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#expbin. + def exitExpbin(self, ctx:IsaDescriptionParser.ExpbinContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#asmdescr. + def enterAsmdescr(self, ctx:IsaDescriptionParser.AsmdescrContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#asmdescr. + def exitAsmdescr(self, ctx:IsaDescriptionParser.AsmdescrContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#extname. + def enterExtname(self, ctx:IsaDescriptionParser.ExtnameContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#extname. + def exitExtname(self, ctx:IsaDescriptionParser.ExtnameContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#arith. + def enterArith(self, ctx:IsaDescriptionParser.ArithContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#arith. + def exitArith(self, ctx:IsaDescriptionParser.ArithContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#opname. + def enterOpname(self, ctx:IsaDescriptionParser.OpnameContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#opname. + def exitOpname(self, ctx:IsaDescriptionParser.OpnameContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#regName. + def enterRegName(self, ctx:IsaDescriptionParser.RegNameContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#regName. + def exitRegName(self, ctx:IsaDescriptionParser.RegNameContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#semname. + def enterSemname(self, ctx:IsaDescriptionParser.SemnameContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#semname. + def exitSemname(self, ctx:IsaDescriptionParser.SemnameContext): + pass + + + # Enter a parse tree produced by IsaDescriptionParser#reglist. + def enterReglist(self, ctx:IsaDescriptionParser.ReglistContext): + pass + + # Exit a parse tree produced by IsaDescriptionParser#reglist. + def exitReglist(self, ctx:IsaDescriptionParser.ReglistContext): + pass + + + +del IsaDescriptionParser \ No newline at end of file diff --git a/HybroGen/IsaDescriptionParser.py b/HybroGen/IsaDescriptionParser.py new file mode 100644 index 0000000..cd79c81 --- /dev/null +++ b/HybroGen/IsaDescriptionParser.py @@ -0,0 +1,1179 @@ +# Generated from IsaDescription.g4 by ANTLR 4.9.2 +# encoding: utf-8 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\20") + buf.write("\u0085\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") + buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") + buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23") + buf.write("\4\24\t\24\3\2\3\2\3\2\3\3\3\3\3\3\6\3/\n\3\r\3\16\3\60") + buf.write("\3\4\3\4\3\4\6\4\66\n\4\r\4\16\4\67\3\4\3\4\3\5\3\5\3") + buf.write("\5\7\5?\n\5\f\5\16\5B\13\5\3\6\3\6\3\7\3\7\3\7\3\7\3\7") + buf.write("\3\b\3\b\3\t\6\tN\n\t\r\t\16\tO\3\n\3\n\3\n\5\nU\n\n\3") + buf.write("\13\3\13\3\f\3\f\3\f\3\f\3\f\5\f^\n\f\3\f\3\f\3\r\3\r") + buf.write("\3\r\3\r\3\r\5\rg\n\r\3\r\3\r\3\16\3\16\3\16\3\16\3\16") + buf.write("\3\16\3\16\5\16r\n\16\3\17\3\17\3\20\3\20\3\21\3\21\3") + buf.write("\22\3\22\3\23\3\23\3\24\3\24\7\24\u0080\n\24\f\24\16\24") + buf.write("\u0083\13\24\3\24\2\2\25\2\4\6\b\n\f\16\20\22\24\26\30") + buf.write("\32\34\36 \"$&\2\3\3\2\7\t\2\177\2(\3\2\2\2\4.\3\2\2\2") + buf.write("\6\62\3\2\2\2\b@\3\2\2\2\nC\3\2\2\2\fE\3\2\2\2\16J\3\2") + buf.write("\2\2\20M\3\2\2\2\22T\3\2\2\2\24V\3\2\2\2\26X\3\2\2\2\30") + buf.write("a\3\2\2\2\32j\3\2\2\2\34s\3\2\2\2\36u\3\2\2\2 w\3\2\2") + buf.write("\2\"y\3\2\2\2${\3\2\2\2&}\3\2\2\2()\5\4\3\2)*\5\b\5\2") + buf.write("*\3\3\2\2\2+/\5\n\6\2,/\5\6\4\2-/\5\16\b\2.+\3\2\2\2.") + buf.write(",\3\2\2\2.-\3\2\2\2/\60\3\2\2\2\60.\3\2\2\2\60\61\3\2") + buf.write("\2\2\61\5\3\2\2\2\62\63\7\3\2\2\63\65\7\r\2\2\64\66\7") + buf.write("\f\2\2\65\64\3\2\2\2\66\67\3\2\2\2\67\65\3\2\2\2\678\3") + buf.write("\2\2\289\3\2\2\29:\7\16\2\2:\7\3\2\2\2;?\5\n\6\2;\3\2\2\2><\3\2\2\2>=\3\2\2\2?B\3\2\2\2") + buf.write("@>\3\2\2\2@A\3\2\2\2A\t\3\2\2\2B@\3\2\2\2CD\7\13\2\2D") + buf.write("\13\3\2\2\2EF\5\20\t\2FG\7\4\2\2GH\5\32\16\2HI\7\16\2") + buf.write("\2I\r\3\2\2\2JK\7\16\2\2K\17\3\2\2\2LN\5\22\n\2ML\3\2") + buf.write("\2\2NO\3\2\2\2OM\3\2\2\2OP\3\2\2\2P\21\3\2\2\2QU\5\24") + buf.write("\13\2RU\5\26\f\2SU\5\30\r\2TQ\3\2\2\2TR\3\2\2\2TS\3\2") + buf.write("\2\2U\23\3\2\2\2VW\7\f\2\2W\25\3\2\2\2XY\7\r\2\2YZ\7\5") + buf.write("\2\2Z]\7\f\2\2[\\\7\17\2\2\\^\7\f\2\2][\3\2\2\2]^\3\2") + buf.write("\2\2^_\3\2\2\2_`\7\6\2\2`\27\3\2\2\2ab\7\20\2\2bc\7\5") + buf.write("\2\2cf\7\f\2\2de\7\17\2\2eg\7\f\2\2fd\3\2\2\2fg\3\2\2") + buf.write("\2gh\3\2\2\2hi\7\6\2\2i\31\3\2\2\2jk\5\34\17\2kl\5\36") + buf.write("\20\2lm\7\f\2\2mn\7\f\2\2no\5$\23\2oq\5 \21\2pr\5&\24") + buf.write("\2qp\3\2\2\2qr\3\2\2\2r\33\3\2\2\2st\7\r\2\2t\35\3\2\2") + buf.write("\2uv\t\2\2\2v\37\3\2\2\2wx\7\r\2\2x!\3\2\2\2yz\7\r\2\2") + buf.write("z#\3\2\2\2{|\7\r\2\2|%\3\2\2\2}\u0081\5\"\22\2~\u0080") + buf.write("\5\"\22\2\177~\3\2\2\2\u0080\u0083\3\2\2\2\u0081\177\3") + buf.write("\2\2\2\u0081\u0082\3\2\2\2\u0082\'\3\2\2\2\u0083\u0081") + buf.write("\3\2\2\2\r.\60\67>@OT]fq\u0081") + return buf.getvalue() + + +class IsaDescriptionParser ( Parser ): + + grammarFileName = "IsaDescription.g4" + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + sharedContextCache = PredictionContextCache() + + literalNames = [ "", "'ARCH'", "'|'", "'['", "']'", "'i'", + "'u'", "'f'", "", "", "", + "", "", "':'" ] + + symbolicNames = [ "", "", "", "", + "", "", "", "", + "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", + "CINLINE" ] + + RULE_isadescription = 0 + RULE_headerlines = 1 + RULE_archline = 2 + RULE_isalines = 3 + RULE_commentline = 4 + RULE_isaline = 5 + RULE_emptyline = 6 + RULE_bindescr = 7 + RULE_binelem = 8 + RULE_binvalue = 9 + RULE_regbin = 10 + RULE_expbin = 11 + RULE_asmdescr = 12 + RULE_extname = 13 + RULE_arith = 14 + RULE_opname = 15 + RULE_regName = 16 + RULE_semname = 17 + RULE_reglist = 18 + + ruleNames = [ "isadescription", "headerlines", "archline", "isalines", + "commentline", "isaline", "emptyline", "bindescr", "binelem", + "binvalue", "regbin", "expbin", "asmdescr", "extname", + "arith", "opname", "regName", "semname", "reglist" ] + + EOF = Token.EOF + T__0=1 + T__1=2 + T__2=3 + T__3=4 + T__4=5 + T__5=6 + T__6=7 + WS=8 + COMMENT=9 + INT=10 + NAME=11 + NEWLINE=12 + SEMICOL=13 + CINLINE=14 + + def __init__(self, input:TokenStream, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) + self._predicates = None + + + + class IsadescriptionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def headerlines(self): + return self.getTypedRuleContext(IsaDescriptionParser.HeaderlinesContext,0) + + + def isalines(self): + return self.getTypedRuleContext(IsaDescriptionParser.IsalinesContext,0) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_isadescription + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterIsadescription" ): + listener.enterIsadescription(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitIsadescription" ): + listener.exitIsadescription(self) + + + + + def isadescription(self): + + localctx = IsaDescriptionParser.IsadescriptionContext(self, self._ctx, self.state) + self.enterRule(localctx, 0, self.RULE_isadescription) + try: + self.enterOuterAlt(localctx, 1) + self.state = 38 + self.headerlines() + self.state = 39 + self.isalines() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class HeaderlinesContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def commentline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.CommentlineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.CommentlineContext,i) + + + def archline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.ArchlineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.ArchlineContext,i) + + + def emptyline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.EmptylineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.EmptylineContext,i) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_headerlines + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterHeaderlines" ): + listener.enterHeaderlines(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitHeaderlines" ): + listener.exitHeaderlines(self) + + + + + def headerlines(self): + + localctx = IsaDescriptionParser.HeaderlinesContext(self, self._ctx, self.state) + self.enterRule(localctx, 2, self.RULE_headerlines) + try: + self.enterOuterAlt(localctx, 1) + self.state = 44 + self._errHandler.sync(self) + _alt = 1 + while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: + if _alt == 1: + self.state = 44 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [IsaDescriptionParser.COMMENT]: + self.state = 41 + self.commentline() + pass + elif token in [IsaDescriptionParser.T__0]: + self.state = 42 + self.archline() + pass + elif token in [IsaDescriptionParser.NEWLINE]: + self.state = 43 + self.emptyline() + pass + else: + raise NoViableAltException(self) + + + else: + raise NoViableAltException(self) + self.state = 46 + self._errHandler.sync(self) + _alt = self._interp.adaptivePredict(self._input,1,self._ctx) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ArchlineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def NEWLINE(self): + return self.getToken(IsaDescriptionParser.NEWLINE, 0) + + def INT(self, i:int=None): + if i is None: + return self.getTokens(IsaDescriptionParser.INT) + else: + return self.getToken(IsaDescriptionParser.INT, i) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_archline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterArchline" ): + listener.enterArchline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitArchline" ): + listener.exitArchline(self) + + + + + def archline(self): + + localctx = IsaDescriptionParser.ArchlineContext(self, self._ctx, self.state) + self.enterRule(localctx, 4, self.RULE_archline) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 48 + self.match(IsaDescriptionParser.T__0) + self.state = 49 + self.match(IsaDescriptionParser.NAME) + self.state = 51 + self._errHandler.sync(self) + _la = self._input.LA(1) + while True: + self.state = 50 + self.match(IsaDescriptionParser.INT) + self.state = 53 + self._errHandler.sync(self) + _la = self._input.LA(1) + if not (_la==IsaDescriptionParser.INT): + break + + self.state = 55 + self.match(IsaDescriptionParser.NEWLINE) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class IsalinesContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def commentline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.CommentlineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.CommentlineContext,i) + + + def emptyline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.EmptylineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.EmptylineContext,i) + + + def isaline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.IsalineContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.IsalineContext,i) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_isalines + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterIsalines" ): + listener.enterIsalines(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitIsalines" ): + listener.exitIsalines(self) + + + + + def isalines(self): + + localctx = IsaDescriptionParser.IsalinesContext(self, self._ctx, self.state) + self.enterRule(localctx, 6, self.RULE_isalines) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 62 + self._errHandler.sync(self) + _la = self._input.LA(1) + while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.COMMENT) | (1 << IsaDescriptionParser.INT) | (1 << IsaDescriptionParser.NAME) | (1 << IsaDescriptionParser.NEWLINE) | (1 << IsaDescriptionParser.CINLINE))) != 0): + self.state = 60 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [IsaDescriptionParser.COMMENT]: + self.state = 57 + self.commentline() + pass + elif token in [IsaDescriptionParser.NEWLINE]: + self.state = 58 + self.emptyline() + pass + elif token in [IsaDescriptionParser.INT, IsaDescriptionParser.NAME, IsaDescriptionParser.CINLINE]: + self.state = 59 + self.isaline() + pass + else: + raise NoViableAltException(self) + + self.state = 64 + self._errHandler.sync(self) + _la = self._input.LA(1) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class CommentlineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def COMMENT(self): + return self.getToken(IsaDescriptionParser.COMMENT, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_commentline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterCommentline" ): + listener.enterCommentline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitCommentline" ): + listener.exitCommentline(self) + + + + + def commentline(self): + + localctx = IsaDescriptionParser.CommentlineContext(self, self._ctx, self.state) + self.enterRule(localctx, 8, self.RULE_commentline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 65 + self.match(IsaDescriptionParser.COMMENT) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class IsalineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def bindescr(self): + return self.getTypedRuleContext(IsaDescriptionParser.BindescrContext,0) + + + def asmdescr(self): + return self.getTypedRuleContext(IsaDescriptionParser.AsmdescrContext,0) + + + def NEWLINE(self): + return self.getToken(IsaDescriptionParser.NEWLINE, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_isaline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterIsaline" ): + listener.enterIsaline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitIsaline" ): + listener.exitIsaline(self) + + + + + def isaline(self): + + localctx = IsaDescriptionParser.IsalineContext(self, self._ctx, self.state) + self.enterRule(localctx, 10, self.RULE_isaline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 67 + self.bindescr() + self.state = 68 + self.match(IsaDescriptionParser.T__1) + self.state = 69 + self.asmdescr() + self.state = 70 + self.match(IsaDescriptionParser.NEWLINE) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class EmptylineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NEWLINE(self): + return self.getToken(IsaDescriptionParser.NEWLINE, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_emptyline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterEmptyline" ): + listener.enterEmptyline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitEmptyline" ): + listener.exitEmptyline(self) + + + + + def emptyline(self): + + localctx = IsaDescriptionParser.EmptylineContext(self, self._ctx, self.state) + self.enterRule(localctx, 12, self.RULE_emptyline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 72 + self.match(IsaDescriptionParser.NEWLINE) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class BindescrContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def binelem(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.BinelemContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.BinelemContext,i) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_bindescr + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterBindescr" ): + listener.enterBindescr(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitBindescr" ): + listener.exitBindescr(self) + + + + + def bindescr(self): + + localctx = IsaDescriptionParser.BindescrContext(self, self._ctx, self.state) + self.enterRule(localctx, 14, self.RULE_bindescr) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 75 + self._errHandler.sync(self) + _la = self._input.LA(1) + while True: + self.state = 74 + self.binelem() + self.state = 77 + self._errHandler.sync(self) + _la = self._input.LA(1) + if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.INT) | (1 << IsaDescriptionParser.NAME) | (1 << IsaDescriptionParser.CINLINE))) != 0)): + break + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class BinelemContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def binvalue(self): + return self.getTypedRuleContext(IsaDescriptionParser.BinvalueContext,0) + + + def regbin(self): + return self.getTypedRuleContext(IsaDescriptionParser.RegbinContext,0) + + + def expbin(self): + return self.getTypedRuleContext(IsaDescriptionParser.ExpbinContext,0) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_binelem + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterBinelem" ): + listener.enterBinelem(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitBinelem" ): + listener.exitBinelem(self) + + + + + def binelem(self): + + localctx = IsaDescriptionParser.BinelemContext(self, self._ctx, self.state) + self.enterRule(localctx, 16, self.RULE_binelem) + try: + self.state = 82 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [IsaDescriptionParser.INT]: + self.enterOuterAlt(localctx, 1) + self.state = 79 + self.binvalue() + pass + elif token in [IsaDescriptionParser.NAME]: + self.enterOuterAlt(localctx, 2) + self.state = 80 + self.regbin() + pass + elif token in [IsaDescriptionParser.CINLINE]: + self.enterOuterAlt(localctx, 3) + self.state = 81 + self.expbin() + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class BinvalueContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def INT(self): + return self.getToken(IsaDescriptionParser.INT, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_binvalue + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterBinvalue" ): + listener.enterBinvalue(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitBinvalue" ): + listener.exitBinvalue(self) + + + + + def binvalue(self): + + localctx = IsaDescriptionParser.BinvalueContext(self, self._ctx, self.state) + self.enterRule(localctx, 18, self.RULE_binvalue) + try: + self.enterOuterAlt(localctx, 1) + self.state = 84 + self.match(IsaDescriptionParser.INT) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegbinContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def INT(self, i:int=None): + if i is None: + return self.getTokens(IsaDescriptionParser.INT) + else: + return self.getToken(IsaDescriptionParser.INT, i) + + def SEMICOL(self): + return self.getToken(IsaDescriptionParser.SEMICOL, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_regbin + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegbin" ): + listener.enterRegbin(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegbin" ): + listener.exitRegbin(self) + + + + + def regbin(self): + + localctx = IsaDescriptionParser.RegbinContext(self, self._ctx, self.state) + self.enterRule(localctx, 20, self.RULE_regbin) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 86 + self.match(IsaDescriptionParser.NAME) + self.state = 87 + self.match(IsaDescriptionParser.T__2) + self.state = 88 + self.match(IsaDescriptionParser.INT) + self.state = 91 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==IsaDescriptionParser.SEMICOL: + self.state = 89 + self.match(IsaDescriptionParser.SEMICOL) + self.state = 90 + self.match(IsaDescriptionParser.INT) + + + self.state = 93 + self.match(IsaDescriptionParser.T__3) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ExpbinContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def CINLINE(self): + return self.getToken(IsaDescriptionParser.CINLINE, 0) + + def INT(self, i:int=None): + if i is None: + return self.getTokens(IsaDescriptionParser.INT) + else: + return self.getToken(IsaDescriptionParser.INT, i) + + def SEMICOL(self): + return self.getToken(IsaDescriptionParser.SEMICOL, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_expbin + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterExpbin" ): + listener.enterExpbin(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitExpbin" ): + listener.exitExpbin(self) + + + + + def expbin(self): + + localctx = IsaDescriptionParser.ExpbinContext(self, self._ctx, self.state) + self.enterRule(localctx, 22, self.RULE_expbin) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 95 + self.match(IsaDescriptionParser.CINLINE) + self.state = 96 + self.match(IsaDescriptionParser.T__2) + self.state = 97 + self.match(IsaDescriptionParser.INT) + self.state = 100 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==IsaDescriptionParser.SEMICOL: + self.state = 98 + self.match(IsaDescriptionParser.SEMICOL) + self.state = 99 + self.match(IsaDescriptionParser.INT) + + + self.state = 102 + self.match(IsaDescriptionParser.T__3) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class AsmdescrContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def extname(self): + return self.getTypedRuleContext(IsaDescriptionParser.ExtnameContext,0) + + + def arith(self): + return self.getTypedRuleContext(IsaDescriptionParser.ArithContext,0) + + + def INT(self, i:int=None): + if i is None: + return self.getTokens(IsaDescriptionParser.INT) + else: + return self.getToken(IsaDescriptionParser.INT, i) + + def semname(self): + return self.getTypedRuleContext(IsaDescriptionParser.SemnameContext,0) + + + def opname(self): + return self.getTypedRuleContext(IsaDescriptionParser.OpnameContext,0) + + + def reglist(self): + return self.getTypedRuleContext(IsaDescriptionParser.ReglistContext,0) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_asmdescr + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterAsmdescr" ): + listener.enterAsmdescr(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitAsmdescr" ): + listener.exitAsmdescr(self) + + + + + def asmdescr(self): + + localctx = IsaDescriptionParser.AsmdescrContext(self, self._ctx, self.state) + self.enterRule(localctx, 24, self.RULE_asmdescr) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 104 + self.extname() + self.state = 105 + self.arith() + self.state = 106 + self.match(IsaDescriptionParser.INT) + self.state = 107 + self.match(IsaDescriptionParser.INT) + self.state = 108 + self.semname() + self.state = 109 + self.opname() + self.state = 111 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==IsaDescriptionParser.NAME: + self.state = 110 + self.reglist() + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ExtnameContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_extname + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterExtname" ): + listener.enterExtname(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitExtname" ): + listener.exitExtname(self) + + + + + def extname(self): + + localctx = IsaDescriptionParser.ExtnameContext(self, self._ctx, self.state) + self.enterRule(localctx, 26, self.RULE_extname) + try: + self.enterOuterAlt(localctx, 1) + self.state = 113 + self.match(IsaDescriptionParser.NAME) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ArithContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_arith + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterArith" ): + listener.enterArith(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitArith" ): + listener.exitArith(self) + + + + + def arith(self): + + localctx = IsaDescriptionParser.ArithContext(self, self._ctx, self.state) + self.enterRule(localctx, 28, self.RULE_arith) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 115 + _la = self._input.LA(1) + if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.T__4) | (1 << IsaDescriptionParser.T__5) | (1 << IsaDescriptionParser.T__6))) != 0)): + self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class OpnameContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_opname + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterOpname" ): + listener.enterOpname(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitOpname" ): + listener.exitOpname(self) + + + + + def opname(self): + + localctx = IsaDescriptionParser.OpnameContext(self, self._ctx, self.state) + self.enterRule(localctx, 30, self.RULE_opname) + try: + self.enterOuterAlt(localctx, 1) + self.state = 117 + self.match(IsaDescriptionParser.NAME) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegNameContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_regName + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegName" ): + listener.enterRegName(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegName" ): + listener.exitRegName(self) + + + + + def regName(self): + + localctx = IsaDescriptionParser.RegNameContext(self, self._ctx, self.state) + self.enterRule(localctx, 32, self.RULE_regName) + try: + self.enterOuterAlt(localctx, 1) + self.state = 119 + self.match(IsaDescriptionParser.NAME) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class SemnameContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(IsaDescriptionParser.NAME, 0) + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_semname + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterSemname" ): + listener.enterSemname(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitSemname" ): + listener.exitSemname(self) + + + + + def semname(self): + + localctx = IsaDescriptionParser.SemnameContext(self, self._ctx, self.state) + self.enterRule(localctx, 34, self.RULE_semname) + try: + self.enterOuterAlt(localctx, 1) + self.state = 121 + self.match(IsaDescriptionParser.NAME) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ReglistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def regName(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(IsaDescriptionParser.RegNameContext) + else: + return self.getTypedRuleContext(IsaDescriptionParser.RegNameContext,i) + + + def getRuleIndex(self): + return IsaDescriptionParser.RULE_reglist + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterReglist" ): + listener.enterReglist(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitReglist" ): + listener.exitReglist(self) + + + + + def reglist(self): + + localctx = IsaDescriptionParser.ReglistContext(self, self._ctx, self.state) + self.enterRule(localctx, 36, self.RULE_reglist) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 123 + self.regName() + self.state = 127 + self._errHandler.sync(self) + _la = self._input.LA(1) + while _la==IsaDescriptionParser.NAME: + self.state = 124 + self.regName() + self.state = 129 + self._errHandler.sync(self) + _la = self._input.LA(1) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + + + + diff --git a/HybroGen/RegisterDescription.interp b/HybroGen/RegisterDescription.interp new file mode 100644 index 0000000..63bbb83 --- /dev/null +++ b/HybroGen/RegisterDescription.interp @@ -0,0 +1,50 @@ +token literal names: +null +'-' +'v' +'i' +'f' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +WS +COMMENT +INT +FUNCNAME +REGWN +NEWLINE +PREFIX +NAME + +rule names: +registerdescription +headerlines +commentline +emptyline +registerlines +registerline +registerlist +registerprefix +registerfunctionlist +registerfunction +registerfunctionwn +regbankvec +regbank +registerwidth +extension + + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 14, 89, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 6, 3, 38, 10, 3, 13, 3, 14, 3, 39, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 6, 6, 6, 49, 10, 6, 13, 6, 14, 6, 50, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 5, 7, 60, 10, 7, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 5, 9, 67, 10, 9, 3, 10, 3, 10, 5, 10, 71, 10, 10, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 5, 12, 78, 10, 12, 3, 13, 5, 13, 81, 10, 13, 3, 14, 3, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 16, 2, 2, 17, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 2, 3, 3, 2, 5, 6, 2, 83, 2, 32, 3, 2, 2, 2, 4, 37, 3, 2, 2, 2, 6, 41, 3, 2, 2, 2, 8, 43, 3, 2, 2, 2, 10, 48, 3, 2, 2, 2, 12, 52, 3, 2, 2, 2, 14, 61, 3, 2, 2, 2, 16, 63, 3, 2, 2, 2, 18, 70, 3, 2, 2, 2, 20, 72, 3, 2, 2, 2, 22, 74, 3, 2, 2, 2, 24, 80, 3, 2, 2, 2, 26, 82, 3, 2, 2, 2, 28, 84, 3, 2, 2, 2, 30, 86, 3, 2, 2, 2, 32, 33, 5, 4, 3, 2, 33, 34, 5, 10, 6, 2, 34, 3, 3, 2, 2, 2, 35, 38, 5, 6, 4, 2, 36, 38, 5, 8, 5, 2, 37, 35, 3, 2, 2, 2, 37, 36, 3, 2, 2, 2, 38, 39, 3, 2, 2, 2, 39, 37, 3, 2, 2, 2, 39, 40, 3, 2, 2, 2, 40, 5, 3, 2, 2, 2, 41, 42, 7, 8, 2, 2, 42, 7, 3, 2, 2, 2, 43, 44, 7, 12, 2, 2, 44, 9, 3, 2, 2, 2, 45, 49, 5, 6, 4, 2, 46, 49, 5, 12, 7, 2, 47, 49, 5, 8, 5, 2, 48, 45, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 48, 47, 3, 2, 2, 2, 49, 50, 3, 2, 2, 2, 50, 48, 3, 2, 2, 2, 50, 51, 3, 2, 2, 2, 51, 11, 3, 2, 2, 2, 52, 53, 5, 30, 16, 2, 53, 54, 5, 24, 13, 2, 54, 55, 5, 26, 14, 2, 55, 56, 5, 14, 8, 2, 56, 57, 5, 28, 15, 2, 57, 59, 5, 18, 10, 2, 58, 60, 7, 12, 2, 2, 59, 58, 3, 2, 2, 2, 59, 60, 3, 2, 2, 2, 60, 13, 3, 2, 2, 2, 61, 62, 5, 16, 9, 2, 62, 15, 3, 2, 2, 2, 63, 66, 7, 13, 2, 2, 64, 65, 7, 3, 2, 2, 65, 67, 7, 9, 2, 2, 66, 64, 3, 2, 2, 2, 66, 67, 3, 2, 2, 2, 67, 17, 3, 2, 2, 2, 68, 71, 5, 20, 11, 2, 69, 71, 5, 22, 12, 2, 70, 68, 3, 2, 2, 2, 70, 69, 3, 2, 2, 2, 71, 19, 3, 2, 2, 2, 72, 73, 7, 10, 2, 2, 73, 21, 3, 2, 2, 2, 74, 77, 7, 11, 2, 2, 75, 76, 7, 3, 2, 2, 76, 78, 7, 9, 2, 2, 77, 75, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 23, 3, 2, 2, 2, 79, 81, 7, 4, 2, 2, 80, 79, 3, 2, 2, 2, 80, 81, 3, 2, 2, 2, 81, 25, 3, 2, 2, 2, 82, 83, 9, 2, 2, 2, 83, 27, 3, 2, 2, 2, 84, 85, 7, 9, 2, 2, 85, 29, 3, 2, 2, 2, 86, 87, 7, 14, 2, 2, 87, 31, 3, 2, 2, 2, 11, 37, 39, 48, 50, 59, 66, 70, 77, 80] \ No newline at end of file diff --git a/HybroGen/RegisterDescription.tokens b/HybroGen/RegisterDescription.tokens new file mode 100644 index 0000000..7db056c --- /dev/null +++ b/HybroGen/RegisterDescription.tokens @@ -0,0 +1,16 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +WS=5 +COMMENT=6 +INT=7 +FUNCNAME=8 +REGWN=9 +NEWLINE=10 +PREFIX=11 +NAME=12 +'-'=1 +'v'=2 +'i'=3 +'f'=4 diff --git a/HybroGen/RegisterDescriptionLexer.interp b/HybroGen/RegisterDescriptionLexer.interp new file mode 100644 index 0000000..29a9957 --- /dev/null +++ b/HybroGen/RegisterDescriptionLexer.interp @@ -0,0 +1,53 @@ +token literal names: +null +'-' +'v' +'i' +'f' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +WS +COMMENT +INT +FUNCNAME +REGWN +NEWLINE +PREFIX +NAME + +rule names: +T__0 +T__1 +T__2 +T__3 +WS +COMMENT +INT +FUNCNAME +REGWN +NEWLINE +PREFIX +NAME + +channel names: +DEFAULT_TOKEN_CHANNEL +HIDDEN + +mode names: +DEFAULT_MODE + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 14, 96, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 3, 2, 3, 2, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 6, 6, 37, 10, 6, 13, 6, 14, 6, 38, 3, 6, 3, 6, 3, 7, 3, 7, 7, 7, 45, 10, 7, 12, 7, 14, 7, 48, 11, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 6, 8, 55, 10, 8, 13, 8, 14, 8, 56, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 5, 9, 71, 10, 9, 3, 10, 3, 10, 3, 10, 3, 11, 5, 11, 77, 10, 11, 3, 11, 3, 11, 3, 12, 3, 12, 7, 12, 83, 10, 12, 12, 12, 14, 12, 86, 11, 12, 3, 12, 3, 12, 3, 13, 3, 13, 7, 13, 92, 10, 13, 12, 13, 14, 13, 95, 11, 13, 3, 46, 2, 14, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 3, 2, 7, 4, 2, 11, 11, 34, 34, 3, 2, 50, 59, 5, 2, 75, 75, 81, 81, 86, 86, 4, 2, 67, 92, 99, 124, 7, 2, 48, 48, 50, 59, 67, 92, 97, 97, 99, 124, 2, 107, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 3, 27, 3, 2, 2, 2, 5, 29, 3, 2, 2, 2, 7, 31, 3, 2, 2, 2, 9, 33, 3, 2, 2, 2, 11, 36, 3, 2, 2, 2, 13, 42, 3, 2, 2, 2, 15, 54, 3, 2, 2, 2, 17, 70, 3, 2, 2, 2, 19, 72, 3, 2, 2, 2, 21, 76, 3, 2, 2, 2, 23, 80, 3, 2, 2, 2, 25, 89, 3, 2, 2, 2, 27, 28, 7, 47, 2, 2, 28, 4, 3, 2, 2, 2, 29, 30, 7, 120, 2, 2, 30, 6, 3, 2, 2, 2, 31, 32, 7, 107, 2, 2, 32, 8, 3, 2, 2, 2, 33, 34, 7, 104, 2, 2, 34, 10, 3, 2, 2, 2, 35, 37, 9, 2, 2, 2, 36, 35, 3, 2, 2, 2, 37, 38, 3, 2, 2, 2, 38, 36, 3, 2, 2, 2, 38, 39, 3, 2, 2, 2, 39, 40, 3, 2, 2, 2, 40, 41, 8, 6, 2, 2, 41, 12, 3, 2, 2, 2, 42, 46, 7, 37, 2, 2, 43, 45, 11, 2, 2, 2, 44, 43, 3, 2, 2, 2, 45, 48, 3, 2, 2, 2, 46, 47, 3, 2, 2, 2, 46, 44, 3, 2, 2, 2, 47, 49, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 49, 50, 5, 21, 11, 2, 50, 51, 3, 2, 2, 2, 51, 52, 8, 7, 2, 2, 52, 14, 3, 2, 2, 2, 53, 55, 9, 3, 2, 2, 54, 53, 3, 2, 2, 2, 55, 56, 3, 2, 2, 2, 56, 54, 3, 2, 2, 2, 56, 57, 3, 2, 2, 2, 57, 16, 3, 2, 2, 2, 58, 71, 7, 92, 2, 2, 59, 60, 7, 84, 2, 2, 60, 71, 7, 67, 2, 2, 61, 62, 7, 72, 2, 2, 62, 71, 7, 82, 2, 2, 63, 64, 7, 85, 2, 2, 64, 71, 7, 82, 2, 2, 65, 66, 7, 73, 2, 2, 66, 71, 7, 82, 2, 2, 67, 68, 7, 86, 2, 2, 68, 71, 7, 82, 2, 2, 69, 71, 7, 90, 2, 2, 70, 58, 3, 2, 2, 2, 70, 59, 3, 2, 2, 2, 70, 61, 3, 2, 2, 2, 70, 63, 3, 2, 2, 2, 70, 65, 3, 2, 2, 2, 70, 67, 3, 2, 2, 2, 70, 69, 3, 2, 2, 2, 71, 18, 3, 2, 2, 2, 72, 73, 9, 4, 2, 2, 73, 74, 5, 15, 8, 2, 74, 20, 3, 2, 2, 2, 75, 77, 7, 15, 2, 2, 76, 75, 3, 2, 2, 2, 76, 77, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 79, 7, 12, 2, 2, 79, 22, 3, 2, 2, 2, 80, 84, 7, 38, 2, 2, 81, 83, 9, 5, 2, 2, 82, 81, 3, 2, 2, 2, 83, 86, 3, 2, 2, 2, 84, 82, 3, 2, 2, 2, 84, 85, 3, 2, 2, 2, 85, 87, 3, 2, 2, 2, 86, 84, 3, 2, 2, 2, 87, 88, 5, 15, 8, 2, 88, 24, 3, 2, 2, 2, 89, 93, 9, 5, 2, 2, 90, 92, 9, 6, 2, 2, 91, 90, 3, 2, 2, 2, 92, 95, 3, 2, 2, 2, 93, 91, 3, 2, 2, 2, 93, 94, 3, 2, 2, 2, 94, 26, 3, 2, 2, 2, 95, 93, 3, 2, 2, 2, 10, 2, 38, 46, 56, 70, 76, 84, 93, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroGen/RegisterDescriptionLexer.py b/HybroGen/RegisterDescriptionLexer.py new file mode 100644 index 0000000..7915d78 --- /dev/null +++ b/HybroGen/RegisterDescriptionLexer.py @@ -0,0 +1,92 @@ +# Generated from RegisterDescription.g4 by ANTLR 4.9.2 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\16") + buf.write("`\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") + buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\3\2") + buf.write("\3\2\3\3\3\3\3\4\3\4\3\5\3\5\3\6\6\6%\n\6\r\6\16\6&\3") + buf.write("\6\3\6\3\7\3\7\7\7-\n\7\f\7\16\7\60\13\7\3\7\3\7\3\7\3") + buf.write("\7\3\b\6\b\67\n\b\r\b\16\b8\3\t\3\t\3\t\3\t\3\t\3\t\3") + buf.write("\t\3\t\3\t\3\t\3\t\3\t\5\tG\n\t\3\n\3\n\3\n\3\13\5\13") + buf.write("M\n\13\3\13\3\13\3\f\3\f\7\fS\n\f\f\f\16\fV\13\f\3\f\3") + buf.write("\f\3\r\3\r\7\r\\\n\r\f\r\16\r_\13\r\3.\2\16\3\3\5\4\7") + buf.write("\5\t\6\13\7\r\b\17\t\21\n\23\13\25\f\27\r\31\16\3\2\7") + buf.write("\4\2\13\13\"\"\3\2\62;\5\2KKQQVV\4\2C\\c|\7\2\60\60\62") + buf.write(";C\\aac|\2k\2\3\3\2\2\2\2\5\3\2\2\2\2\7\3\2\2\2\2\t\3") + buf.write("\2\2\2\2\13\3\2\2\2\2\r\3\2\2\2\2\17\3\2\2\2\2\21\3\2") + buf.write("\2\2\2\23\3\2\2\2\2\25\3\2\2\2\2\27\3\2\2\2\2\31\3\2\2") + buf.write("\2\3\33\3\2\2\2\5\35\3\2\2\2\7\37\3\2\2\2\t!\3\2\2\2\13") + buf.write("$\3\2\2\2\r*\3\2\2\2\17\66\3\2\2\2\21F\3\2\2\2\23H\3\2") + buf.write("\2\2\25L\3\2\2\2\27P\3\2\2\2\31Y\3\2\2\2\33\34\7/\2\2") + buf.write("\34\4\3\2\2\2\35\36\7x\2\2\36\6\3\2\2\2\37 \7k\2\2 \b") + buf.write("\3\2\2\2!\"\7h\2\2\"\n\3\2\2\2#%\t\2\2\2$#\3\2\2\2%&\3") + buf.write("\2\2\2&$\3\2\2\2&\'\3\2\2\2\'(\3\2\2\2()\b\6\2\2)\f\3") + buf.write("\2\2\2*.\7%\2\2+-\13\2\2\2,+\3\2\2\2-\60\3\2\2\2./\3\2") + buf.write("\2\2.,\3\2\2\2/\61\3\2\2\2\60.\3\2\2\2\61\62\5\25\13\2") + buf.write("\62\63\3\2\2\2\63\64\b\7\2\2\64\16\3\2\2\2\65\67\t\3\2") + buf.write("\2\66\65\3\2\2\2\678\3\2\2\28\66\3\2\2\289\3\2\2\29\20") + buf.write("\3\2\2\2:G\7\\\2\2;<\7T\2\2\7H\2\2>G\7R\2\2") + buf.write("?@\7U\2\2@G\7R\2\2AB\7I\2\2BG\7R\2\2CD\7V\2\2DG\7R\2\2") + buf.write("EG\7Z\2\2F:\3\2\2\2F;\3\2\2\2F=\3\2\2\2F?\3\2\2\2FA\3") + buf.write("\2\2\2FC\3\2\2\2FE\3\2\2\2G\22\3\2\2\2HI\t\4\2\2IJ\5\17") + buf.write("\b\2J\24\3\2\2\2KM\7\17\2\2LK\3\2\2\2LM\3\2\2\2MN\3\2") + buf.write("\2\2NO\7\f\2\2O\26\3\2\2\2PT\7&\2\2QS\t\5\2\2RQ\3\2\2") + buf.write("\2SV\3\2\2\2TR\3\2\2\2TU\3\2\2\2UW\3\2\2\2VT\3\2\2\2W") + buf.write("X\5\17\b\2X\30\3\2\2\2Y]\t\5\2\2Z\\\t\6\2\2[Z\3\2\2\2") + buf.write("\\_\3\2\2\2][\3\2\2\2]^\3\2\2\2^\32\3\2\2\2_]\3\2\2\2") + buf.write("\n\2&.8FLT]\3\b\2\2") + return buf.getvalue() + + +class RegisterDescriptionLexer(Lexer): + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + T__0 = 1 + T__1 = 2 + T__2 = 3 + T__3 = 4 + WS = 5 + COMMENT = 6 + INT = 7 + FUNCNAME = 8 + REGWN = 9 + NEWLINE = 10 + PREFIX = 11 + NAME = 12 + + channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] + + modeNames = [ "DEFAULT_MODE" ] + + literalNames = [ "", + "'-'", "'v'", "'i'", "'f'" ] + + symbolicNames = [ "", + "WS", "COMMENT", "INT", "FUNCNAME", "REGWN", "NEWLINE", "PREFIX", + "NAME" ] + + ruleNames = [ "T__0", "T__1", "T__2", "T__3", "WS", "COMMENT", "INT", + "FUNCNAME", "REGWN", "NEWLINE", "PREFIX", "NAME" ] + + grammarFileName = "RegisterDescription.g4" + + def __init__(self, input=None, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) + self._actions = None + self._predicates = None + + diff --git a/HybroGen/RegisterDescriptionLexer.tokens b/HybroGen/RegisterDescriptionLexer.tokens new file mode 100644 index 0000000..7db056c --- /dev/null +++ b/HybroGen/RegisterDescriptionLexer.tokens @@ -0,0 +1,16 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +WS=5 +COMMENT=6 +INT=7 +FUNCNAME=8 +REGWN=9 +NEWLINE=10 +PREFIX=11 +NAME=12 +'-'=1 +'v'=2 +'i'=3 +'f'=4 diff --git a/HybroGen/RegisterDescriptionListener.py b/HybroGen/RegisterDescriptionListener.py new file mode 100644 index 0000000..dcd9a40 --- /dev/null +++ b/HybroGen/RegisterDescriptionListener.py @@ -0,0 +1,147 @@ +# Generated from RegisterDescription.g4 by ANTLR 4.9.2 +from antlr4 import * +if __name__ is not None and "." in __name__: + from .RegisterDescriptionParser import RegisterDescriptionParser +else: + from RegisterDescriptionParser import RegisterDescriptionParser + +# This class defines a complete listener for a parse tree produced by RegisterDescriptionParser. +class RegisterDescriptionListener(ParseTreeListener): + + # Enter a parse tree produced by RegisterDescriptionParser#registerdescription. + def enterRegisterdescription(self, ctx:RegisterDescriptionParser.RegisterdescriptionContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerdescription. + def exitRegisterdescription(self, ctx:RegisterDescriptionParser.RegisterdescriptionContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#headerlines. + def enterHeaderlines(self, ctx:RegisterDescriptionParser.HeaderlinesContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#headerlines. + def exitHeaderlines(self, ctx:RegisterDescriptionParser.HeaderlinesContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#commentline. + def enterCommentline(self, ctx:RegisterDescriptionParser.CommentlineContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#commentline. + def exitCommentline(self, ctx:RegisterDescriptionParser.CommentlineContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#emptyline. + def enterEmptyline(self, ctx:RegisterDescriptionParser.EmptylineContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#emptyline. + def exitEmptyline(self, ctx:RegisterDescriptionParser.EmptylineContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerlines. + def enterRegisterlines(self, ctx:RegisterDescriptionParser.RegisterlinesContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerlines. + def exitRegisterlines(self, ctx:RegisterDescriptionParser.RegisterlinesContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerline. + def enterRegisterline(self, ctx:RegisterDescriptionParser.RegisterlineContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerline. + def exitRegisterline(self, ctx:RegisterDescriptionParser.RegisterlineContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerlist. + def enterRegisterlist(self, ctx:RegisterDescriptionParser.RegisterlistContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerlist. + def exitRegisterlist(self, ctx:RegisterDescriptionParser.RegisterlistContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerprefix. + def enterRegisterprefix(self, ctx:RegisterDescriptionParser.RegisterprefixContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerprefix. + def exitRegisterprefix(self, ctx:RegisterDescriptionParser.RegisterprefixContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerfunctionlist. + def enterRegisterfunctionlist(self, ctx:RegisterDescriptionParser.RegisterfunctionlistContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerfunctionlist. + def exitRegisterfunctionlist(self, ctx:RegisterDescriptionParser.RegisterfunctionlistContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerfunction. + def enterRegisterfunction(self, ctx:RegisterDescriptionParser.RegisterfunctionContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerfunction. + def exitRegisterfunction(self, ctx:RegisterDescriptionParser.RegisterfunctionContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerfunctionwn. + def enterRegisterfunctionwn(self, ctx:RegisterDescriptionParser.RegisterfunctionwnContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerfunctionwn. + def exitRegisterfunctionwn(self, ctx:RegisterDescriptionParser.RegisterfunctionwnContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#regbankvec. + def enterRegbankvec(self, ctx:RegisterDescriptionParser.RegbankvecContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#regbankvec. + def exitRegbankvec(self, ctx:RegisterDescriptionParser.RegbankvecContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#regbank. + def enterRegbank(self, ctx:RegisterDescriptionParser.RegbankContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#regbank. + def exitRegbank(self, ctx:RegisterDescriptionParser.RegbankContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#registerwidth. + def enterRegisterwidth(self, ctx:RegisterDescriptionParser.RegisterwidthContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#registerwidth. + def exitRegisterwidth(self, ctx:RegisterDescriptionParser.RegisterwidthContext): + pass + + + # Enter a parse tree produced by RegisterDescriptionParser#extension. + def enterExtension(self, ctx:RegisterDescriptionParser.ExtensionContext): + pass + + # Exit a parse tree produced by RegisterDescriptionParser#extension. + def exitExtension(self, ctx:RegisterDescriptionParser.ExtensionContext): + pass + + + +del RegisterDescriptionParser \ No newline at end of file diff --git a/HybroGen/RegisterDescriptionParser.py b/HybroGen/RegisterDescriptionParser.py new file mode 100644 index 0000000..cde839d --- /dev/null +++ b/HybroGen/RegisterDescriptionParser.py @@ -0,0 +1,891 @@ +# Generated from RegisterDescription.g4 by ANTLR 4.9.2 +# encoding: utf-8 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\16") + buf.write("Y\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7\4\b") + buf.write("\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16\t") + buf.write("\16\4\17\t\17\4\20\t\20\3\2\3\2\3\2\3\3\3\3\6\3&\n\3\r") + buf.write("\3\16\3\'\3\4\3\4\3\5\3\5\3\6\3\6\3\6\6\6\61\n\6\r\6\16") + buf.write("\6\62\3\7\3\7\3\7\3\7\3\7\3\7\3\7\5\7<\n\7\3\b\3\b\3\t") + buf.write("\3\t\3\t\5\tC\n\t\3\n\3\n\5\nG\n\n\3\13\3\13\3\f\3\f\3") + buf.write("\f\5\fN\n\f\3\r\5\rQ\n\r\3\16\3\16\3\17\3\17\3\20\3\20") + buf.write("\3\20\2\2\21\2\4\6\b\n\f\16\20\22\24\26\30\32\34\36\2") + buf.write("\3\3\2\5\6\2S\2 \3\2\2\2\4%\3\2\2\2\6)\3\2\2\2\b+\3\2") + buf.write("\2\2\n\60\3\2\2\2\f\64\3\2\2\2\16=\3\2\2\2\20?\3\2\2\2") + buf.write("\22F\3\2\2\2\24H\3\2\2\2\26J\3\2\2\2\30P\3\2\2\2\32R\3") + buf.write("\2\2\2\34T\3\2\2\2\36V\3\2\2\2 !\5\4\3\2!\"\5\n\6\2\"") + buf.write("\3\3\2\2\2#&\5\6\4\2$&\5\b\5\2%#\3\2\2\2%$\3\2\2\2&\'") + buf.write("\3\2\2\2\'%\3\2\2\2\'(\3\2\2\2(\5\3\2\2\2)*\7\b\2\2*\7") + buf.write("\3\2\2\2+,\7\f\2\2,\t\3\2\2\2-\61\5\6\4\2.\61\5\f\7\2") + buf.write("/\61\5\b\5\2\60-\3\2\2\2\60.\3\2\2\2\60/\3\2\2\2\61\62") + buf.write("\3\2\2\2\62\60\3\2\2\2\62\63\3\2\2\2\63\13\3\2\2\2\64") + buf.write("\65\5\36\20\2\65\66\5\30\r\2\66\67\5\32\16\2\678\5\16") + buf.write("\b\289\5\34\17\29;\5\22\n\2:<\7\f\2\2;:\3\2\2\2;<\3\2") + buf.write("\2\2<\r\3\2\2\2=>\5\20\t\2>\17\3\2\2\2?B\7\r\2\2@A\7\3") + buf.write("\2\2AC\7\t\2\2B@\3\2\2\2BC\3\2\2\2C\21\3\2\2\2DG\5\24") + buf.write("\13\2EG\5\26\f\2FD\3\2\2\2FE\3\2\2\2G\23\3\2\2\2HI\7\n") + buf.write("\2\2I\25\3\2\2\2JM\7\13\2\2KL\7\3\2\2LN\7\t\2\2MK\3\2") + buf.write("\2\2MN\3\2\2\2N\27\3\2\2\2OQ\7\4\2\2PO\3\2\2\2PQ\3\2\2") + buf.write("\2Q\31\3\2\2\2RS\t\2\2\2S\33\3\2\2\2TU\7\t\2\2U\35\3\2") + buf.write("\2\2VW\7\16\2\2W\37\3\2\2\2\13%\'\60\62;BFMP") + return buf.getvalue() + + +class RegisterDescriptionParser ( Parser ): + + grammarFileName = "RegisterDescription.g4" + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + sharedContextCache = PredictionContextCache() + + literalNames = [ "", "'-'", "'v'", "'i'", "'f'" ] + + symbolicNames = [ "", "", "", "", + "", "WS", "COMMENT", "INT", "FUNCNAME", "REGWN", + "NEWLINE", "PREFIX", "NAME" ] + + RULE_registerdescription = 0 + RULE_headerlines = 1 + RULE_commentline = 2 + RULE_emptyline = 3 + RULE_registerlines = 4 + RULE_registerline = 5 + RULE_registerlist = 6 + RULE_registerprefix = 7 + RULE_registerfunctionlist = 8 + RULE_registerfunction = 9 + RULE_registerfunctionwn = 10 + RULE_regbankvec = 11 + RULE_regbank = 12 + RULE_registerwidth = 13 + RULE_extension = 14 + + ruleNames = [ "registerdescription", "headerlines", "commentline", + "emptyline", "registerlines", "registerline", "registerlist", + "registerprefix", "registerfunctionlist", "registerfunction", + "registerfunctionwn", "regbankvec", "regbank", "registerwidth", + "extension" ] + + EOF = Token.EOF + T__0=1 + T__1=2 + T__2=3 + T__3=4 + WS=5 + COMMENT=6 + INT=7 + FUNCNAME=8 + REGWN=9 + NEWLINE=10 + PREFIX=11 + NAME=12 + + def __init__(self, input:TokenStream, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) + self._predicates = None + + + + class RegisterdescriptionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def headerlines(self): + return self.getTypedRuleContext(RegisterDescriptionParser.HeaderlinesContext,0) + + + def registerlines(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlinesContext,0) + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerdescription + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterdescription" ): + listener.enterRegisterdescription(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterdescription" ): + listener.exitRegisterdescription(self) + + + + + def registerdescription(self): + + localctx = RegisterDescriptionParser.RegisterdescriptionContext(self, self._ctx, self.state) + self.enterRule(localctx, 0, self.RULE_registerdescription) + try: + self.enterOuterAlt(localctx, 1) + self.state = 30 + self.headerlines() + self.state = 31 + self.registerlines() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class HeaderlinesContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def commentline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(RegisterDescriptionParser.CommentlineContext) + else: + return self.getTypedRuleContext(RegisterDescriptionParser.CommentlineContext,i) + + + def emptyline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(RegisterDescriptionParser.EmptylineContext) + else: + return self.getTypedRuleContext(RegisterDescriptionParser.EmptylineContext,i) + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_headerlines + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterHeaderlines" ): + listener.enterHeaderlines(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitHeaderlines" ): + listener.exitHeaderlines(self) + + + + + def headerlines(self): + + localctx = RegisterDescriptionParser.HeaderlinesContext(self, self._ctx, self.state) + self.enterRule(localctx, 2, self.RULE_headerlines) + try: + self.enterOuterAlt(localctx, 1) + self.state = 35 + self._errHandler.sync(self) + _alt = 1 + while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: + if _alt == 1: + self.state = 35 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [RegisterDescriptionParser.COMMENT]: + self.state = 33 + self.commentline() + pass + elif token in [RegisterDescriptionParser.NEWLINE]: + self.state = 34 + self.emptyline() + pass + else: + raise NoViableAltException(self) + + + else: + raise NoViableAltException(self) + self.state = 37 + self._errHandler.sync(self) + _alt = self._interp.adaptivePredict(self._input,1,self._ctx) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class CommentlineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def COMMENT(self): + return self.getToken(RegisterDescriptionParser.COMMENT, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_commentline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterCommentline" ): + listener.enterCommentline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitCommentline" ): + listener.exitCommentline(self) + + + + + def commentline(self): + + localctx = RegisterDescriptionParser.CommentlineContext(self, self._ctx, self.state) + self.enterRule(localctx, 4, self.RULE_commentline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 39 + self.match(RegisterDescriptionParser.COMMENT) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class EmptylineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NEWLINE(self): + return self.getToken(RegisterDescriptionParser.NEWLINE, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_emptyline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterEmptyline" ): + listener.enterEmptyline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitEmptyline" ): + listener.exitEmptyline(self) + + + + + def emptyline(self): + + localctx = RegisterDescriptionParser.EmptylineContext(self, self._ctx, self.state) + self.enterRule(localctx, 6, self.RULE_emptyline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 41 + self.match(RegisterDescriptionParser.NEWLINE) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterlinesContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def commentline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(RegisterDescriptionParser.CommentlineContext) + else: + return self.getTypedRuleContext(RegisterDescriptionParser.CommentlineContext,i) + + + def registerline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(RegisterDescriptionParser.RegisterlineContext) + else: + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlineContext,i) + + + def emptyline(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(RegisterDescriptionParser.EmptylineContext) + else: + return self.getTypedRuleContext(RegisterDescriptionParser.EmptylineContext,i) + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerlines + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterlines" ): + listener.enterRegisterlines(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterlines" ): + listener.exitRegisterlines(self) + + + + + def registerlines(self): + + localctx = RegisterDescriptionParser.RegisterlinesContext(self, self._ctx, self.state) + self.enterRule(localctx, 8, self.RULE_registerlines) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 46 + self._errHandler.sync(self) + _la = self._input.LA(1) + while True: + self.state = 46 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [RegisterDescriptionParser.COMMENT]: + self.state = 43 + self.commentline() + pass + elif token in [RegisterDescriptionParser.NAME]: + self.state = 44 + self.registerline() + pass + elif token in [RegisterDescriptionParser.NEWLINE]: + self.state = 45 + self.emptyline() + pass + else: + raise NoViableAltException(self) + + self.state = 48 + self._errHandler.sync(self) + _la = self._input.LA(1) + if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << RegisterDescriptionParser.COMMENT) | (1 << RegisterDescriptionParser.NEWLINE) | (1 << RegisterDescriptionParser.NAME))) != 0)): + break + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterlineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def extension(self): + return self.getTypedRuleContext(RegisterDescriptionParser.ExtensionContext,0) + + + def regbankvec(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegbankvecContext,0) + + + def regbank(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegbankContext,0) + + + def registerlist(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlistContext,0) + + + def registerwidth(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterwidthContext,0) + + + def registerfunctionlist(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionlistContext,0) + + + def NEWLINE(self): + return self.getToken(RegisterDescriptionParser.NEWLINE, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerline + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterline" ): + listener.enterRegisterline(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterline" ): + listener.exitRegisterline(self) + + + + + def registerline(self): + + localctx = RegisterDescriptionParser.RegisterlineContext(self, self._ctx, self.state) + self.enterRule(localctx, 10, self.RULE_registerline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 50 + self.extension() + self.state = 51 + self.regbankvec() + self.state = 52 + self.regbank() + self.state = 53 + self.registerlist() + self.state = 54 + self.registerwidth() + self.state = 55 + self.registerfunctionlist() + self.state = 57 + self._errHandler.sync(self) + la_ = self._interp.adaptivePredict(self._input,4,self._ctx) + if la_ == 1: + self.state = 56 + self.match(RegisterDescriptionParser.NEWLINE) + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterlistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def registerprefix(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterprefixContext,0) + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerlist + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterlist" ): + listener.enterRegisterlist(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterlist" ): + listener.exitRegisterlist(self) + + + + + def registerlist(self): + + localctx = RegisterDescriptionParser.RegisterlistContext(self, self._ctx, self.state) + self.enterRule(localctx, 12, self.RULE_registerlist) + try: + self.enterOuterAlt(localctx, 1) + self.state = 59 + self.registerprefix() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterprefixContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def PREFIX(self): + return self.getToken(RegisterDescriptionParser.PREFIX, 0) + + def INT(self): + return self.getToken(RegisterDescriptionParser.INT, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerprefix + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterprefix" ): + listener.enterRegisterprefix(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterprefix" ): + listener.exitRegisterprefix(self) + + + + + def registerprefix(self): + + localctx = RegisterDescriptionParser.RegisterprefixContext(self, self._ctx, self.state) + self.enterRule(localctx, 14, self.RULE_registerprefix) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 61 + self.match(RegisterDescriptionParser.PREFIX) + self.state = 64 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==RegisterDescriptionParser.T__0: + self.state = 62 + self.match(RegisterDescriptionParser.T__0) + self.state = 63 + self.match(RegisterDescriptionParser.INT) + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterfunctionlistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def registerfunction(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionContext,0) + + + def registerfunctionwn(self): + return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionwnContext,0) + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerfunctionlist + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterfunctionlist" ): + listener.enterRegisterfunctionlist(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterfunctionlist" ): + listener.exitRegisterfunctionlist(self) + + + + + def registerfunctionlist(self): + + localctx = RegisterDescriptionParser.RegisterfunctionlistContext(self, self._ctx, self.state) + self.enterRule(localctx, 16, self.RULE_registerfunctionlist) + try: + self.state = 68 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [RegisterDescriptionParser.FUNCNAME]: + self.enterOuterAlt(localctx, 1) + self.state = 66 + self.registerfunction() + pass + elif token in [RegisterDescriptionParser.REGWN]: + self.enterOuterAlt(localctx, 2) + self.state = 67 + self.registerfunctionwn() + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterfunctionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def FUNCNAME(self): + return self.getToken(RegisterDescriptionParser.FUNCNAME, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerfunction + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterfunction" ): + listener.enterRegisterfunction(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterfunction" ): + listener.exitRegisterfunction(self) + + + + + def registerfunction(self): + + localctx = RegisterDescriptionParser.RegisterfunctionContext(self, self._ctx, self.state) + self.enterRule(localctx, 18, self.RULE_registerfunction) + try: + self.enterOuterAlt(localctx, 1) + self.state = 70 + self.match(RegisterDescriptionParser.FUNCNAME) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterfunctionwnContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def REGWN(self): + return self.getToken(RegisterDescriptionParser.REGWN, 0) + + def INT(self): + return self.getToken(RegisterDescriptionParser.INT, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerfunctionwn + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterfunctionwn" ): + listener.enterRegisterfunctionwn(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterfunctionwn" ): + listener.exitRegisterfunctionwn(self) + + + + + def registerfunctionwn(self): + + localctx = RegisterDescriptionParser.RegisterfunctionwnContext(self, self._ctx, self.state) + self.enterRule(localctx, 20, self.RULE_registerfunctionwn) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 72 + self.match(RegisterDescriptionParser.REGWN) + self.state = 75 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==RegisterDescriptionParser.T__0: + self.state = 73 + self.match(RegisterDescriptionParser.T__0) + self.state = 74 + self.match(RegisterDescriptionParser.INT) + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegbankvecContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_regbankvec + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegbankvec" ): + listener.enterRegbankvec(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegbankvec" ): + listener.exitRegbankvec(self) + + + + + def regbankvec(self): + + localctx = RegisterDescriptionParser.RegbankvecContext(self, self._ctx, self.state) + self.enterRule(localctx, 22, self.RULE_regbankvec) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 78 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==RegisterDescriptionParser.T__1: + self.state = 77 + self.match(RegisterDescriptionParser.T__1) + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegbankContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_regbank + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegbank" ): + listener.enterRegbank(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegbank" ): + listener.exitRegbank(self) + + + + + def regbank(self): + + localctx = RegisterDescriptionParser.RegbankContext(self, self._ctx, self.state) + self.enterRule(localctx, 24, self.RULE_regbank) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 80 + _la = self._input.LA(1) + if not(_la==RegisterDescriptionParser.T__2 or _la==RegisterDescriptionParser.T__3): + self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class RegisterwidthContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def INT(self): + return self.getToken(RegisterDescriptionParser.INT, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_registerwidth + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterRegisterwidth" ): + listener.enterRegisterwidth(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitRegisterwidth" ): + listener.exitRegisterwidth(self) + + + + + def registerwidth(self): + + localctx = RegisterDescriptionParser.RegisterwidthContext(self, self._ctx, self.state) + self.enterRule(localctx, 26, self.RULE_registerwidth) + try: + self.enterOuterAlt(localctx, 1) + self.state = 82 + self.match(RegisterDescriptionParser.INT) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ExtensionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def NAME(self): + return self.getToken(RegisterDescriptionParser.NAME, 0) + + def getRuleIndex(self): + return RegisterDescriptionParser.RULE_extension + + def enterRule(self, listener:ParseTreeListener): + if hasattr( listener, "enterExtension" ): + listener.enterExtension(self) + + def exitRule(self, listener:ParseTreeListener): + if hasattr( listener, "exitExtension" ): + listener.exitExtension(self) + + + + + def extension(self): + + localctx = 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a/HybroLang/.antlr/HybroLang.interp b/HybroLang/.antlr/HybroLang.interp new file mode 100644 index 0000000..8ea5afa --- /dev/null +++ b/HybroLang/.antlr/HybroLang.interp @@ -0,0 +1,125 @@ +token literal names: +null +'(' +')' +'{' +'}' +',' +';' +'for' +'if' +'else' +'return' +'=' +'[' +']' +'*' +'/' +'+' +'-' +'<<' +'>>' +'&' +'|' +'^' +'int' +'uint' +'sint' +'suint' +'flt' +'cpl' +'pix' +'ipv4' +'ipv6' +'[]' +'==' +'!=' +'<' +'>' +'<=' +'>=' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +DecimalFloatingConstant +IntegerConstant +DecimalConstant +Name +INLINE +WhiteSpace +LineComment +NewLine + +rule names: +compilationunit +function +fndcl +fnprototype +fnbody +paramdcllist +localvardef +vardcllist +vardcl +actionlist +condexpr +action +returnexpr +affectexpr +unaryexpr +varorvalue +datatype +intconstvalue +constvalue +constinline +typebase +condOperator + + +atn: +[4, 1, 46, 204, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 1, 0, 4, 0, 46, 8, 0, 11, 0, 12, 0, 47, 1, 1, 1, 1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 3, 1, 3, 1, 3, 1, 3, 1, 4, 1, 4, 5, 4, 63, 8, 4, 10, 4, 12, 4, 66, 9, 4, 1, 4, 1, 4, 3, 4, 70, 8, 4, 1, 4, 1, 4, 1, 5, 1, 5, 1, 5, 5, 5, 77, 8, 5, 10, 5, 12, 5, 80, 9, 5, 1, 5, 3, 5, 83, 8, 5, 1, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 5, 7, 91, 8, 7, 10, 7, 12, 7, 94, 9, 7, 1, 8, 1, 8, 1, 8, 1, 9, 5, 9, 100, 8, 9, 10, 9, 12, 9, 103, 9, 9, 1, 10, 1, 10, 1, 10, 1, 10, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 3, 11, 136, 8, 11, 1, 12, 1, 12, 1, 12, 1, 12, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 3, 13, 152, 8, 13, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 5, 14, 169, 8, 14, 10, 14, 12, 14, 172, 9, 14, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 3, 15, 181, 8, 15, 1, 16, 1, 16, 1, 16, 1, 16, 1, 17, 1, 17, 3, 17, 189, 8, 17, 1, 18, 1, 18, 1, 18, 3, 18, 194, 8, 18, 1, 19, 1, 19, 1, 20, 1, 20, 3, 20, 200, 8, 20, 1, 21, 1, 21, 1, 21, 0, 1, 28, 22, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 0, 6, 1, 0, 14, 15, 1, 0, 16, 17, 1, 0, 18, 19, 1, 0, 20, 22, 1, 0, 23, 31, 1, 0, 33, 38, 201, 0, 45, 1, 0, 0, 0, 2, 49, 1, 0, 0, 0, 4, 52, 1, 0, 0, 0, 6, 56, 1, 0, 0, 0, 8, 60, 1, 0, 0, 0, 10, 82, 1, 0, 0, 0, 12, 84, 1, 0, 0, 0, 14, 87, 1, 0, 0, 0, 16, 95, 1, 0, 0, 0, 18, 101, 1, 0, 0, 0, 20, 104, 1, 0, 0, 0, 22, 135, 1, 0, 0, 0, 24, 137, 1, 0, 0, 0, 26, 151, 1, 0, 0, 0, 28, 153, 1, 0, 0, 0, 30, 180, 1, 0, 0, 0, 32, 182, 1, 0, 0, 0, 34, 188, 1, 0, 0, 0, 36, 193, 1, 0, 0, 0, 38, 195, 1, 0, 0, 0, 40, 197, 1, 0, 0, 0, 42, 201, 1, 0, 0, 0, 44, 46, 3, 2, 1, 0, 45, 44, 1, 0, 0, 0, 46, 47, 1, 0, 0, 0, 47, 45, 1, 0, 0, 0, 47, 48, 1, 0, 0, 0, 48, 1, 1, 0, 0, 0, 49, 50, 3, 4, 2, 0, 50, 51, 3, 8, 4, 0, 51, 3, 1, 0, 0, 0, 52, 53, 3, 32, 16, 0, 53, 54, 5, 42, 0, 0, 54, 55, 3, 6, 3, 0, 55, 5, 1, 0, 0, 0, 56, 57, 5, 1, 0, 0, 57, 58, 3, 10, 5, 0, 58, 59, 5, 2, 0, 0, 59, 7, 1, 0, 0, 0, 60, 64, 5, 3, 0, 0, 61, 63, 3, 12, 6, 0, 62, 61, 1, 0, 0, 0, 63, 66, 1, 0, 0, 0, 64, 62, 1, 0, 0, 0, 64, 65, 1, 0, 0, 0, 65, 67, 1, 0, 0, 0, 66, 64, 1, 0, 0, 0, 67, 69, 3, 18, 9, 0, 68, 70, 3, 24, 12, 0, 69, 68, 1, 0, 0, 0, 69, 70, 1, 0, 0, 0, 70, 71, 1, 0, 0, 0, 71, 72, 5, 4, 0, 0, 72, 9, 1, 0, 0, 0, 73, 78, 3, 16, 8, 0, 74, 75, 5, 5, 0, 0, 75, 77, 3, 16, 8, 0, 76, 74, 1, 0, 0, 0, 77, 80, 1, 0, 0, 0, 78, 76, 1, 0, 0, 0, 78, 79, 1, 0, 0, 0, 79, 83, 1, 0, 0, 0, 80, 78, 1, 0, 0, 0, 81, 83, 1, 0, 0, 0, 82, 73, 1, 0, 0, 0, 82, 81, 1, 0, 0, 0, 83, 11, 1, 0, 0, 0, 84, 85, 3, 14, 7, 0, 85, 86, 5, 6, 0, 0, 86, 13, 1, 0, 0, 0, 87, 92, 3, 16, 8, 0, 88, 89, 5, 5, 0, 0, 89, 91, 5, 42, 0, 0, 90, 88, 1, 0, 0, 0, 91, 94, 1, 0, 0, 0, 92, 90, 1, 0, 0, 0, 92, 93, 1, 0, 0, 0, 93, 15, 1, 0, 0, 0, 94, 92, 1, 0, 0, 0, 95, 96, 3, 32, 16, 0, 96, 97, 5, 42, 0, 0, 97, 17, 1, 0, 0, 0, 98, 100, 3, 22, 11, 0, 99, 98, 1, 0, 0, 0, 100, 103, 1, 0, 0, 0, 101, 99, 1, 0, 0, 0, 101, 102, 1, 0, 0, 0, 102, 19, 1, 0, 0, 0, 103, 101, 1, 0, 0, 0, 104, 105, 3, 30, 15, 0, 105, 106, 3, 42, 21, 0, 106, 107, 3, 30, 15, 0, 107, 21, 1, 0, 0, 0, 108, 109, 3, 26, 13, 0, 109, 110, 5, 6, 0, 0, 110, 136, 1, 0, 0, 0, 111, 112, 5, 7, 0, 0, 112, 113, 5, 1, 0, 0, 113, 114, 3, 26, 13, 0, 114, 115, 5, 6, 0, 0, 115, 116, 3, 20, 10, 0, 116, 117, 5, 6, 0, 0, 117, 118, 3, 26, 13, 0, 118, 119, 5, 2, 0, 0, 119, 120, 5, 3, 0, 0, 120, 121, 3, 18, 9, 0, 121, 122, 5, 4, 0, 0, 122, 136, 1, 0, 0, 0, 123, 124, 5, 8, 0, 0, 124, 125, 5, 1, 0, 0, 125, 126, 3, 20, 10, 0, 126, 127, 5, 2, 0, 0, 127, 128, 5, 3, 0, 0, 128, 129, 3, 18, 9, 0, 129, 130, 5, 4, 0, 0, 130, 131, 5, 9, 0, 0, 131, 132, 5, 3, 0, 0, 132, 133, 3, 18, 9, 0, 133, 134, 5, 4, 0, 0, 134, 136, 1, 0, 0, 0, 135, 108, 1, 0, 0, 0, 135, 111, 1, 0, 0, 0, 135, 123, 1, 0, 0, 0, 136, 23, 1, 0, 0, 0, 137, 138, 5, 10, 0, 0, 138, 139, 3, 28, 14, 0, 139, 140, 5, 6, 0, 0, 140, 25, 1, 0, 0, 0, 141, 142, 5, 42, 0, 0, 142, 143, 5, 11, 0, 0, 143, 152, 3, 28, 14, 0, 144, 145, 5, 42, 0, 0, 145, 146, 5, 12, 0, 0, 146, 147, 3, 28, 14, 0, 147, 148, 5, 13, 0, 0, 148, 149, 5, 11, 0, 0, 149, 150, 3, 28, 14, 0, 150, 152, 1, 0, 0, 0, 151, 141, 1, 0, 0, 0, 151, 144, 1, 0, 0, 0, 152, 27, 1, 0, 0, 0, 153, 154, 6, 14, -1, 0, 154, 155, 3, 30, 15, 0, 155, 170, 1, 0, 0, 0, 156, 157, 10, 5, 0, 0, 157, 158, 7, 0, 0, 0, 158, 169, 3, 28, 14, 6, 159, 160, 10, 4, 0, 0, 160, 161, 7, 1, 0, 0, 161, 169, 3, 28, 14, 5, 162, 163, 10, 3, 0, 0, 163, 164, 7, 2, 0, 0, 164, 169, 3, 28, 14, 4, 165, 166, 10, 2, 0, 0, 166, 167, 7, 3, 0, 0, 167, 169, 3, 28, 14, 3, 168, 156, 1, 0, 0, 0, 168, 159, 1, 0, 0, 0, 168, 162, 1, 0, 0, 0, 168, 165, 1, 0, 0, 0, 169, 172, 1, 0, 0, 0, 170, 168, 1, 0, 0, 0, 170, 171, 1, 0, 0, 0, 171, 29, 1, 0, 0, 0, 172, 170, 1, 0, 0, 0, 173, 174, 5, 42, 0, 0, 174, 175, 5, 12, 0, 0, 175, 176, 3, 28, 14, 0, 176, 177, 5, 13, 0, 0, 177, 181, 1, 0, 0, 0, 178, 181, 3, 36, 18, 0, 179, 181, 5, 42, 0, 0, 180, 173, 1, 0, 0, 0, 180, 178, 1, 0, 0, 0, 180, 179, 1, 0, 0, 0, 181, 31, 1, 0, 0, 0, 182, 183, 3, 40, 20, 0, 183, 184, 3, 34, 17, 0, 184, 185, 3, 34, 17, 0, 185, 33, 1, 0, 0, 0, 186, 189, 5, 40, 0, 0, 187, 189, 3, 38, 19, 0, 188, 186, 1, 0, 0, 0, 188, 187, 1, 0, 0, 0, 189, 35, 1, 0, 0, 0, 190, 194, 5, 40, 0, 0, 191, 194, 5, 39, 0, 0, 192, 194, 3, 38, 19, 0, 193, 190, 1, 0, 0, 0, 193, 191, 1, 0, 0, 0, 193, 192, 1, 0, 0, 0, 194, 37, 1, 0, 0, 0, 195, 196, 5, 43, 0, 0, 196, 39, 1, 0, 0, 0, 197, 199, 7, 4, 0, 0, 198, 200, 5, 32, 0, 0, 199, 198, 1, 0, 0, 0, 199, 200, 1, 0, 0, 0, 200, 41, 1, 0, 0, 0, 201, 202, 7, 5, 0, 0, 202, 43, 1, 0, 0, 0, 15, 47, 64, 69, 78, 82, 92, 101, 135, 151, 168, 170, 180, 188, 193, 199] \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLang.tokens b/HybroLang/.antlr/HybroLang.tokens new file mode 100644 index 0000000..574a34a --- /dev/null +++ b/HybroLang/.antlr/HybroLang.tokens @@ -0,0 +1,84 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +T__7=8 +T__8=9 +T__9=10 +T__10=11 +T__11=12 +T__12=13 +T__13=14 +T__14=15 +T__15=16 +T__16=17 +T__17=18 +T__18=19 +T__19=20 +T__20=21 +T__21=22 +T__22=23 +T__23=24 +T__24=25 +T__25=26 +T__26=27 +T__27=28 +T__28=29 +T__29=30 +T__30=31 +T__31=32 +T__32=33 +T__33=34 +T__34=35 +T__35=36 +T__36=37 +T__37=38 +DecimalFloatingConstant=39 +IntegerConstant=40 +DecimalConstant=41 +Name=42 +INLINE=43 +WhiteSpace=44 +LineComment=45 +NewLine=46 +'('=1 +')'=2 +'{'=3 +'}'=4 +','=5 +';'=6 +'for'=7 +'if'=8 +'else'=9 +'return'=10 +'='=11 +'['=12 +']'=13 +'*'=14 +'/'=15 +'+'=16 +'-'=17 +'<<'=18 +'>>'=19 +'&'=20 +'|'=21 +'^'=22 +'int'=23 +'uint'=24 +'sint'=25 +'suint'=26 +'flt'=27 +'cpl'=28 +'pix'=29 +'ipv4'=30 +'ipv6'=31 +'[]'=32 +'=='=33 +'!='=34 +'<'=35 +'>'=36 +'<='=37 +'>='=38 diff --git a/HybroLang/.antlr/HybroLangBaseListener.java b/HybroLang/.antlr/HybroLangBaseListener.java new file mode 100644 index 0000000..1196c27 --- /dev/null +++ b/HybroLang/.antlr/HybroLangBaseListener.java @@ -0,0 +1,327 @@ +// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 + +import org.antlr.v4.runtime.ParserRuleContext; +import org.antlr.v4.runtime.tree.ErrorNode; +import org.antlr.v4.runtime.tree.TerminalNode; + +/** + * This class provides an empty implementation of {@link HybroLangListener}, + * which can be extended to create a listener which only needs to handle a subset + * of the available methods. + */ +@SuppressWarnings("CheckReturnValue") +public class HybroLangBaseListener implements HybroLangListener { + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterCompilationunit(HybroLangParser.CompilationunitContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitCompilationunit(HybroLangParser.CompilationunitContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterFunction(HybroLangParser.FunctionContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitFunction(HybroLangParser.FunctionContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterFndcl(HybroLangParser.FndclContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitFndcl(HybroLangParser.FndclContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterFnprototype(HybroLangParser.FnprototypeContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitFnprototype(HybroLangParser.FnprototypeContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterFnbody(HybroLangParser.FnbodyContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitFnbody(HybroLangParser.FnbodyContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterParamdcllist(HybroLangParser.ParamdcllistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitParamdcllist(HybroLangParser.ParamdcllistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterLocalvardef(HybroLangParser.LocalvardefContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitLocalvardef(HybroLangParser.LocalvardefContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterVardcllist(HybroLangParser.VardcllistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitVardcllist(HybroLangParser.VardcllistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterVardcl(HybroLangParser.VardclContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitVardcl(HybroLangParser.VardclContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterActionlist(HybroLangParser.ActionlistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitActionlist(HybroLangParser.ActionlistContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterCondexpr(HybroLangParser.CondexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitCondexpr(HybroLangParser.CondexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterAction(HybroLangParser.ActionContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitAction(HybroLangParser.ActionContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterReturnexpr(HybroLangParser.ReturnexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitReturnexpr(HybroLangParser.ReturnexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterAffectexpr(HybroLangParser.AffectexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitAffectexpr(HybroLangParser.AffectexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterUnaryexpr(HybroLangParser.UnaryexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitUnaryexpr(HybroLangParser.UnaryexprContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterDatatype(HybroLangParser.DatatypeContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitDatatype(HybroLangParser.DatatypeContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterIntconstvalue(HybroLangParser.IntconstvalueContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitIntconstvalue(HybroLangParser.IntconstvalueContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterConstvalue(HybroLangParser.ConstvalueContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitConstvalue(HybroLangParser.ConstvalueContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterConstinline(HybroLangParser.ConstinlineContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitConstinline(HybroLangParser.ConstinlineContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterTypebase(HybroLangParser.TypebaseContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitTypebase(HybroLangParser.TypebaseContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterCondOperator(HybroLangParser.CondOperatorContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitCondOperator(HybroLangParser.CondOperatorContext ctx) { } + + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void enterEveryRule(ParserRuleContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void exitEveryRule(ParserRuleContext ctx) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void visitTerminal(TerminalNode node) { } + /** + * {@inheritDoc} + * + *

The default implementation does nothing.

+ */ + @Override public void visitErrorNode(ErrorNode node) { } +} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.interp b/HybroLang/.antlr/HybroLangLexer.interp new file mode 100644 index 0000000..9840595 --- /dev/null +++ b/HybroLang/.antlr/HybroLangLexer.interp @@ -0,0 +1,162 @@ +token literal names: +null +'(' +')' +'{' +'}' +',' +';' +'for' +'if' +'else' +'return' +'=' +'[' +']' +'*' +'/' +'+' +'-' +'<<' +'>>' +'&' +'|' +'^' +'int' +'uint' +'sint' +'suint' +'flt' +'cpl' +'pix' +'ipv4' +'ipv6' +'[]' +'==' +'!=' +'<' +'>' +'<=' +'>=' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +DecimalFloatingConstant +IntegerConstant +DecimalConstant +Name +INLINE +WhiteSpace +LineComment +NewLine + +rule names: +T__0 +T__1 +T__2 +T__3 +T__4 +T__5 +T__6 +T__7 +T__8 +T__9 +T__10 +T__11 +T__12 +T__13 +T__14 +T__15 +T__16 +T__17 +T__18 +T__19 +T__20 +T__21 +T__22 +T__23 +T__24 +T__25 +T__26 +T__27 +T__28 +T__29 +T__30 +T__31 +T__32 +T__33 +T__34 +T__35 +T__36 +T__37 +DecimalFloatingConstant +ExponentPart +FloatingSuffix +FractionalConstant +IntegerConstant +DecimalConstant +DigitSequence +Digit +NonzeroDigit +Sign +Name +INLINE +WhiteSpace +LineComment +NewLine + +channel names: +DEFAULT_TOKEN_CHANNEL +HIDDEN + +mode names: +DEFAULT_MODE + +atn: +[4, 0, 46, 320, 6, -1, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 2, 22, 7, 22, 2, 23, 7, 23, 2, 24, 7, 24, 2, 25, 7, 25, 2, 26, 7, 26, 2, 27, 7, 27, 2, 28, 7, 28, 2, 29, 7, 29, 2, 30, 7, 30, 2, 31, 7, 31, 2, 32, 7, 32, 2, 33, 7, 33, 2, 34, 7, 34, 2, 35, 7, 35, 2, 36, 7, 36, 2, 37, 7, 37, 2, 38, 7, 38, 2, 39, 7, 39, 2, 40, 7, 40, 2, 41, 7, 41, 2, 42, 7, 42, 2, 43, 7, 43, 2, 44, 7, 44, 2, 45, 7, 45, 2, 46, 7, 46, 2, 47, 7, 47, 2, 48, 7, 48, 2, 49, 7, 49, 2, 50, 7, 50, 2, 51, 7, 51, 2, 52, 7, 52, 1, 0, 1, 0, 1, 1, 1, 1, 1, 2, 1, 2, 1, 3, 1, 3, 1, 4, 1, 4, 1, 5, 1, 5, 1, 6, 1, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 1, 8, 1, 8, 1, 8, 1, 8, 1, 8, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 10, 1, 10, 1, 11, 1, 11, 1, 12, 1, 12, 1, 13, 1, 13, 1, 14, 1, 14, 1, 15, 1, 15, 1, 16, 1, 16, 1, 17, 1, 17, 1, 17, 1, 18, 1, 18, 1, 18, 1, 19, 1, 19, 1, 20, 1, 20, 1, 21, 1, 21, 1, 22, 1, 22, 1, 22, 1, 22, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 25, 1, 25, 1, 25, 1, 25, 1, 25, 1, 25, 1, 26, 1, 26, 1, 26, 1, 26, 1, 27, 1, 27, 1, 27, 1, 27, 1, 28, 1, 28, 1, 28, 1, 28, 1, 29, 1, 29, 1, 29, 1, 29, 1, 29, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 31, 1, 31, 1, 31, 1, 32, 1, 32, 1, 32, 1, 33, 1, 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0, 256, 257, 3, 89, 44, 0, 257, 86, 1, 0, 0, 0, 258, 262, 3, 93, 46, 0, 259, 261, 3, 91, 45, 0, 260, 259, 1, 0, 0, 0, 261, 264, 1, 0, 0, 0, 262, 260, 1, 0, 0, 0, 262, 263, 1, 0, 0, 0, 263, 88, 1, 0, 0, 0, 264, 262, 1, 0, 0, 0, 265, 267, 3, 91, 45, 0, 266, 265, 1, 0, 0, 0, 267, 268, 1, 0, 0, 0, 268, 266, 1, 0, 0, 0, 268, 269, 1, 0, 0, 0, 269, 90, 1, 0, 0, 0, 270, 271, 7, 1, 0, 0, 271, 92, 1, 0, 0, 0, 272, 273, 7, 2, 0, 0, 273, 94, 1, 0, 0, 0, 274, 275, 7, 3, 0, 0, 275, 96, 1, 0, 0, 0, 276, 280, 7, 4, 0, 0, 277, 279, 7, 5, 0, 0, 278, 277, 1, 0, 0, 0, 279, 282, 1, 0, 0, 0, 280, 278, 1, 0, 0, 0, 280, 281, 1, 0, 0, 0, 281, 98, 1, 0, 0, 0, 282, 280, 1, 0, 0, 0, 283, 284, 5, 35, 0, 0, 284, 285, 5, 40, 0, 0, 285, 287, 1, 0, 0, 0, 286, 288, 8, 6, 0, 0, 287, 286, 1, 0, 0, 0, 288, 289, 1, 0, 0, 0, 289, 287, 1, 0, 0, 0, 289, 290, 1, 0, 0, 0, 290, 291, 1, 0, 0, 0, 291, 292, 5, 41, 0, 0, 292, 100, 1, 0, 0, 0, 293, 295, 7, 7, 0, 0, 294, 293, 1, 0, 0, 0, 295, 296, 1, 0, 0, 0, 296, 294, 1, 0, 0, 0, 296, 297, 1, 0, 0, 0, 297, 298, 1, 0, 0, 0, 298, 299, 6, 50, 0, 0, 299, 102, 1, 0, 0, 0, 300, 301, 5, 47, 0, 0, 301, 302, 5, 47, 0, 0, 302, 306, 1, 0, 0, 0, 303, 305, 9, 0, 0, 0, 304, 303, 1, 0, 0, 0, 305, 308, 1, 0, 0, 0, 306, 307, 1, 0, 0, 0, 306, 304, 1, 0, 0, 0, 307, 309, 1, 0, 0, 0, 308, 306, 1, 0, 0, 0, 309, 310, 3, 105, 52, 0, 310, 311, 1, 0, 0, 0, 311, 312, 6, 51, 0, 0, 312, 104, 1, 0, 0, 0, 313, 315, 5, 13, 0, 0, 314, 313, 1, 0, 0, 0, 314, 315, 1, 0, 0, 0, 315, 316, 1, 0, 0, 0, 316, 317, 5, 10, 0, 0, 317, 318, 1, 0, 0, 0, 318, 319, 6, 52, 0, 0, 319, 106, 1, 0, 0, 0, 15, 0, 227, 230, 234, 239, 242, 247, 254, 262, 268, 280, 289, 296, 306, 314, 1, 6, 0, 0] \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.java b/HybroLang/.antlr/HybroLangLexer.java new file mode 100644 index 0000000..fe6b304 --- /dev/null +++ b/HybroLang/.antlr/HybroLangLexer.java @@ -0,0 +1,329 @@ +// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 +import org.antlr.v4.runtime.Lexer; +import org.antlr.v4.runtime.CharStream; +import org.antlr.v4.runtime.Token; +import org.antlr.v4.runtime.TokenStream; +import org.antlr.v4.runtime.*; +import org.antlr.v4.runtime.atn.*; +import org.antlr.v4.runtime.dfa.DFA; +import org.antlr.v4.runtime.misc.*; + +@SuppressWarnings({"all", "warnings", "unchecked", "unused", "cast", "CheckReturnValue", "this-escape"}) +public class HybroLangLexer extends Lexer { + static { RuntimeMetaData.checkVersion("4.13.1", RuntimeMetaData.VERSION); } + + protected static final DFA[] _decisionToDFA; + protected static final PredictionContextCache _sharedContextCache = + new PredictionContextCache(); + public static final int + T__0=1, T__1=2, T__2=3, T__3=4, T__4=5, T__5=6, T__6=7, T__7=8, T__8=9, + T__9=10, T__10=11, T__11=12, T__12=13, T__13=14, T__14=15, T__15=16, T__16=17, + T__17=18, T__18=19, T__19=20, T__20=21, T__21=22, T__22=23, T__23=24, + T__24=25, T__25=26, T__26=27, T__27=28, T__28=29, T__29=30, T__30=31, + T__31=32, T__32=33, T__33=34, T__34=35, T__35=36, T__36=37, T__37=38, + DecimalFloatingConstant=39, IntegerConstant=40, DecimalConstant=41, Name=42, + INLINE=43, WhiteSpace=44, LineComment=45, NewLine=46; + public static String[] channelNames = { + "DEFAULT_TOKEN_CHANNEL", "HIDDEN" + }; + + public static String[] modeNames = { + "DEFAULT_MODE" + }; + + private static String[] makeRuleNames() { + return new String[] { + "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", "T__7", "T__8", + "T__9", "T__10", "T__11", "T__12", "T__13", "T__14", "T__15", "T__16", + "T__17", "T__18", "T__19", "T__20", "T__21", "T__22", "T__23", "T__24", + "T__25", "T__26", "T__27", "T__28", "T__29", "T__30", "T__31", "T__32", + "T__33", "T__34", "T__35", "T__36", "T__37", "DecimalFloatingConstant", + "ExponentPart", "FloatingSuffix", "FractionalConstant", "IntegerConstant", + "DecimalConstant", "DigitSequence", "Digit", "NonzeroDigit", "Sign", + "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" + }; + } + public static final String[] ruleNames = makeRuleNames(); + + private static String[] makeLiteralNames() { + return new String[] { + null, "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", + "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", + "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", + "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", "'=='", "'!='", + "'<'", "'>'", "'<='", "'>='" + }; + } + private static final String[] _LITERAL_NAMES = makeLiteralNames(); + private static String[] makeSymbolicNames() { + return new String[] { + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", + "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" + }; + } + private static final String[] _SYMBOLIC_NAMES = makeSymbolicNames(); + public static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES); + + /** + * @deprecated Use {@link #VOCABULARY} instead. + */ + @Deprecated + public static final String[] tokenNames; + static { + tokenNames = new String[_SYMBOLIC_NAMES.length]; + for (int i = 0; i < tokenNames.length; i++) { + tokenNames[i] = VOCABULARY.getLiteralName(i); + if (tokenNames[i] == null) { + tokenNames[i] = VOCABULARY.getSymbolicName(i); + } + + if (tokenNames[i] == null) { + tokenNames[i] = ""; + } + } + } + + @Override + @Deprecated + public String[] getTokenNames() { + return tokenNames; + } + + @Override + + public Vocabulary getVocabulary() { + return VOCABULARY; + } + + + public HybroLangLexer(CharStream input) { + super(input); + _interp = new LexerATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache); + } + + @Override + public String getGrammarFileName() { return "HybroLang.g4"; } + + @Override + public String[] getRuleNames() { return ruleNames; } + + @Override + public String getSerializedATN() { return _serializedATN; } + + @Override + public String[] getChannelNames() { return channelNames; } + + @Override + public String[] getModeNames() { return modeNames; } + + @Override + public ATN getATN() { return _ATN; } + + public static final String _serializedATN = + "\u0004\u0000.\u0140\u0006\uffff\uffff\u0002\u0000\u0007\u0000\u0002\u0001"+ + "\u0007\u0001\u0002\u0002\u0007\u0002\u0002\u0003\u0007\u0003\u0002\u0004"+ + "\u0007\u0004\u0002\u0005\u0007\u0005\u0002\u0006\u0007\u0006\u0002\u0007"+ + "\u0007\u0007\u0002\b\u0007\b\u0002\t\u0007\t\u0002\n\u0007\n\u0002\u000b"+ + "\u0007\u000b\u0002\f\u0007\f\u0002\r\u0007\r\u0002\u000e\u0007\u000e\u0002"+ + "\u000f\u0007\u000f\u0002\u0010\u0007\u0010\u0002\u0011\u0007\u0011\u0002"+ + "\u0012\u0007\u0012\u0002\u0013\u0007\u0013\u0002\u0014\u0007\u0014\u0002"+ + "\u0015\u0007\u0015\u0002\u0016\u0007\u0016\u0002\u0017\u0007\u0017\u0002"+ + "\u0018\u0007\u0018\u0002\u0019\u0007\u0019\u0002\u001a\u0007\u001a\u0002"+ + "\u001b\u0007\u001b\u0002\u001c\u0007\u001c\u0002\u001d\u0007\u001d\u0002"+ + "\u001e\u0007\u001e\u0002\u001f\u0007\u001f\u0002 \u0007 \u0002!\u0007"+ + "!\u0002\"\u0007\"\u0002#\u0007#\u0002$\u0007$\u0002%\u0007%\u0002&\u0007"+ + "&\u0002\'\u0007\'\u0002(\u0007(\u0002)\u0007)\u0002*\u0007*\u0002+\u0007"+ + "+\u0002,\u0007,\u0002-\u0007-\u0002.\u0007.\u0002/\u0007/\u00020\u0007"+ + "0\u00021\u00071\u00022\u00072\u00023\u00073\u00024\u00074\u0001\u0000"+ + "\u0001\u0000\u0001\u0001\u0001\u0001\u0001\u0002\u0001\u0002\u0001\u0003"+ + "\u0001\u0003\u0001\u0004\u0001\u0004\u0001\u0005\u0001\u0005\u0001\u0006"+ + "\u0001\u0006\u0001\u0006\u0001\u0006\u0001\u0007\u0001\u0007\u0001\u0007"+ + "\u0001\b\u0001\b\u0001\b\u0001\b\u0001\b\u0001\t\u0001\t\u0001\t\u0001"+ + "\t\u0001\t\u0001\t\u0001\t\u0001\n\u0001\n\u0001\u000b\u0001\u000b\u0001"+ + "\f\u0001\f\u0001\r\u0001\r\u0001\u000e\u0001\u000e\u0001\u000f\u0001\u000f"+ + "\u0001\u0010\u0001\u0010\u0001\u0011\u0001\u0011\u0001\u0011\u0001\u0012"+ + "\u0001\u0012\u0001\u0012\u0001\u0013\u0001\u0013\u0001\u0014\u0001\u0014"+ + "\u0001\u0015\u0001\u0015\u0001\u0016\u0001\u0016\u0001\u0016\u0001\u0016"+ + "\u0001\u0017\u0001\u0017\u0001\u0017\u0001\u0017\u0001\u0017\u0001\u0018"+ + "\u0001\u0018\u0001\u0018\u0001\u0018\u0001\u0018\u0001\u0019\u0001\u0019"+ + "\u0001\u0019\u0001\u0019\u0001\u0019\u0001\u0019\u0001\u001a\u0001\u001a"+ + "\u0001\u001a\u0001\u001a\u0001\u001b\u0001\u001b\u0001\u001b\u0001\u001b"+ + "\u0001\u001c\u0001\u001c\u0001\u001c\u0001\u001c\u0001\u001d\u0001\u001d"+ + "\u0001\u001d\u0001\u001d\u0001\u001d\u0001\u001e\u0001\u001e\u0001\u001e"+ + "\u0001\u001e\u0001\u001e\u0001\u001f\u0001\u001f\u0001\u001f\u0001 \u0001"+ + " \u0001 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"p\u0000\u0000\u00c6\u00c7\u0005v\u0000\u0000\u00c7\u00c8\u00054\u0000"+ + "\u0000\u00c8<\u0001\u0000\u0000\u0000\u00c9\u00ca\u0005i\u0000\u0000\u00ca"+ + "\u00cb\u0005p\u0000\u0000\u00cb\u00cc\u0005v\u0000\u0000\u00cc\u00cd\u0005"+ + "6\u0000\u0000\u00cd>\u0001\u0000\u0000\u0000\u00ce\u00cf\u0005[\u0000"+ + "\u0000\u00cf\u00d0\u0005]\u0000\u0000\u00d0@\u0001\u0000\u0000\u0000\u00d1"+ + "\u00d2\u0005=\u0000\u0000\u00d2\u00d3\u0005=\u0000\u0000\u00d3B\u0001"+ + "\u0000\u0000\u0000\u00d4\u00d5\u0005!\u0000\u0000\u00d5\u00d6\u0005=\u0000"+ + "\u0000\u00d6D\u0001\u0000\u0000\u0000\u00d7\u00d8\u0005<\u0000\u0000\u00d8"+ + "F\u0001\u0000\u0000\u0000\u00d9\u00da\u0005>\u0000\u0000\u00daH\u0001"+ + "\u0000\u0000\u0000\u00db\u00dc\u0005<\u0000\u0000\u00dc\u00dd\u0005=\u0000"+ + "\u0000\u00ddJ\u0001\u0000\u0000\u0000\u00de\u00df\u0005>\u0000\u0000\u00df"+ + "\u00e0\u0005=\u0000\u0000\u00e0L\u0001\u0000\u0000\u0000\u00e1\u00e3\u0003"+ + "S)\u0000\u00e2\u00e4\u0003O\'\u0000\u00e3\u00e2\u0001\u0000\u0000\u0000"+ + "\u00e3\u00e4\u0001\u0000\u0000\u0000\u00e4\u00e6\u0001\u0000\u0000\u0000"+ + "\u00e5\u00e7\u0003Q(\u0000\u00e6\u00e5\u0001\u0000\u0000\u0000\u00e6\u00e7"+ + "\u0001\u0000\u0000\u0000\u00e7N\u0001\u0000\u0000\u0000\u00e8\u00ea\u0005"+ + "e\u0000\u0000\u00e9\u00eb\u0003_/\u0000\u00ea\u00e9\u0001\u0000\u0000"+ + "\u0000\u00ea\u00eb\u0001\u0000\u0000\u0000\u00eb\u00ec\u0001\u0000\u0000"+ + "\u0000\u00ec\u00f3\u0003Y,\u0000\u00ed\u00ef\u0005E\u0000\u0000\u00ee"+ + "\u00f0\u0003_/\u0000\u00ef\u00ee\u0001\u0000\u0000\u0000\u00ef\u00f0\u0001"+ + "\u0000\u0000\u0000\u00f0\u00f1\u0001\u0000\u0000\u0000\u00f1\u00f3\u0003"+ + "Y,\u0000\u00f2\u00e8\u0001\u0000\u0000\u0000\u00f2\u00ed\u0001\u0000\u0000"+ + "\u0000\u00f3P\u0001\u0000\u0000\u0000\u00f4\u00f5\u0007\u0000\u0000\u0000"+ + "\u00f5R\u0001\u0000\u0000\u0000\u00f6\u00f8\u0003Y,\u0000\u00f7\u00f6"+ + "\u0001\u0000\u0000\u0000\u00f7\u00f8\u0001\u0000\u0000\u0000\u00f8\u00f9"+ + "\u0001\u0000\u0000\u0000\u00f9\u00fa\u0005.\u0000\u0000\u00fa\u00ff\u0003"+ + "Y,\u0000\u00fb\u00fc\u0003Y,\u0000\u00fc\u00fd\u0005.\u0000\u0000\u00fd"+ + "\u00ff\u0001\u0000\u0000\u0000\u00fe\u00f7\u0001\u0000\u0000\u0000\u00fe"+ + "\u00fb\u0001\u0000\u0000\u0000\u00ffT\u0001\u0000\u0000\u0000\u0100\u0101"+ + "\u0003Y,\u0000\u0101V\u0001\u0000\u0000\u0000\u0102\u0106\u0003].\u0000"+ + "\u0103\u0105\u0003[-\u0000\u0104\u0103\u0001\u0000\u0000\u0000\u0105\u0108"+ + "\u0001\u0000\u0000\u0000\u0106\u0104\u0001\u0000\u0000\u0000\u0106\u0107"+ + "\u0001\u0000\u0000\u0000\u0107X\u0001\u0000\u0000\u0000\u0108\u0106\u0001"+ + "\u0000\u0000\u0000\u0109\u010b\u0003[-\u0000\u010a\u0109\u0001\u0000\u0000"+ + "\u0000\u010b\u010c\u0001\u0000\u0000\u0000\u010c\u010a\u0001\u0000\u0000"+ + "\u0000\u010c\u010d\u0001\u0000\u0000\u0000\u010dZ\u0001\u0000\u0000\u0000"+ + "\u010e\u010f\u0007\u0001\u0000\u0000\u010f\\\u0001\u0000\u0000\u0000\u0110"+ + "\u0111\u0007\u0002\u0000\u0000\u0111^\u0001\u0000\u0000\u0000\u0112\u0113"+ + "\u0007\u0003\u0000\u0000\u0113`\u0001\u0000\u0000\u0000\u0114\u0118\u0007"+ + "\u0004\u0000\u0000\u0115\u0117\u0007\u0005\u0000\u0000\u0116\u0115\u0001"+ + "\u0000\u0000\u0000\u0117\u011a\u0001\u0000\u0000\u0000\u0118\u0116\u0001"+ + "\u0000\u0000\u0000\u0118\u0119\u0001\u0000\u0000\u0000\u0119b\u0001\u0000"+ + "\u0000\u0000\u011a\u0118\u0001\u0000\u0000\u0000\u011b\u011c\u0005#\u0000"+ + "\u0000\u011c\u011d\u0005(\u0000\u0000\u011d\u011f\u0001\u0000\u0000\u0000"+ + "\u011e\u0120\b\u0006\u0000\u0000\u011f\u011e\u0001\u0000\u0000\u0000\u0120"+ + "\u0121\u0001\u0000\u0000\u0000\u0121\u011f\u0001\u0000\u0000\u0000\u0121"+ + "\u0122\u0001\u0000\u0000\u0000\u0122\u0123\u0001\u0000\u0000\u0000\u0123"+ + "\u0124\u0005)\u0000\u0000\u0124d\u0001\u0000\u0000\u0000\u0125\u0127\u0007"+ + "\u0007\u0000\u0000\u0126\u0125\u0001\u0000\u0000\u0000\u0127\u0128\u0001"+ + "\u0000\u0000\u0000\u0128\u0126\u0001\u0000\u0000\u0000\u0128\u0129\u0001"+ + "\u0000\u0000\u0000\u0129\u012a\u0001\u0000\u0000\u0000\u012a\u012b\u0006"+ + "2\u0000\u0000\u012bf\u0001\u0000\u0000\u0000\u012c\u012d\u0005/\u0000"+ + "\u0000\u012d\u012e\u0005/\u0000\u0000\u012e\u0132\u0001\u0000\u0000\u0000"+ + "\u012f\u0131\t\u0000\u0000\u0000\u0130\u012f\u0001\u0000\u0000\u0000\u0131"+ + "\u0134\u0001\u0000\u0000\u0000\u0132\u0133\u0001\u0000\u0000\u0000\u0132"+ + "\u0130\u0001\u0000\u0000\u0000\u0133\u0135\u0001\u0000\u0000\u0000\u0134"+ + "\u0132\u0001\u0000\u0000\u0000\u0135\u0136\u0003i4\u0000\u0136\u0137\u0001"+ + "\u0000\u0000\u0000\u0137\u0138\u00063\u0000\u0000\u0138h\u0001\u0000\u0000"+ + "\u0000\u0139\u013b\u0005\r\u0000\u0000\u013a\u0139\u0001\u0000\u0000\u0000"+ + "\u013a\u013b\u0001\u0000\u0000\u0000\u013b\u013c\u0001\u0000\u0000\u0000"+ + "\u013c\u013d\u0005\n\u0000\u0000\u013d\u013e\u0001\u0000\u0000\u0000\u013e"+ + "\u013f\u00064\u0000\u0000\u013fj\u0001\u0000\u0000\u0000\u000f\u0000\u00e3"+ + "\u00e6\u00ea\u00ef\u00f2\u00f7\u00fe\u0106\u010c\u0118\u0121\u0128\u0132"+ + "\u013a\u0001\u0006\u0000\u0000"; + public static final ATN _ATN = + new ATNDeserializer().deserialize(_serializedATN.toCharArray()); + static { + _decisionToDFA = new DFA[_ATN.getNumberOfDecisions()]; + for (int i = 0; i < _ATN.getNumberOfDecisions(); i++) { + _decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i); + } + } +} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.tokens b/HybroLang/.antlr/HybroLangLexer.tokens new file mode 100644 index 0000000..574a34a --- /dev/null +++ b/HybroLang/.antlr/HybroLangLexer.tokens @@ -0,0 +1,84 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +T__7=8 +T__8=9 +T__9=10 +T__10=11 +T__11=12 +T__12=13 +T__13=14 +T__14=15 +T__15=16 +T__16=17 +T__17=18 +T__18=19 +T__19=20 +T__20=21 +T__21=22 +T__22=23 +T__23=24 +T__24=25 +T__25=26 +T__26=27 +T__27=28 +T__28=29 +T__29=30 +T__30=31 +T__31=32 +T__32=33 +T__33=34 +T__34=35 +T__35=36 +T__36=37 +T__37=38 +DecimalFloatingConstant=39 +IntegerConstant=40 +DecimalConstant=41 +Name=42 +INLINE=43 +WhiteSpace=44 +LineComment=45 +NewLine=46 +'('=1 +')'=2 +'{'=3 +'}'=4 +','=5 +';'=6 +'for'=7 +'if'=8 +'else'=9 +'return'=10 +'='=11 +'['=12 +']'=13 +'*'=14 +'/'=15 +'+'=16 +'-'=17 +'<<'=18 +'>>'=19 +'&'=20 +'|'=21 +'^'=22 +'int'=23 +'uint'=24 +'sint'=25 +'suint'=26 +'flt'=27 +'cpl'=28 +'pix'=29 +'ipv4'=30 +'ipv6'=31 +'[]'=32 +'=='=33 +'!='=34 +'<'=35 +'>'=36 +'<='=37 +'>='=38 diff --git a/HybroLang/.antlr/HybroLangListener.java b/HybroLang/.antlr/HybroLangListener.java new file mode 100644 index 0000000..17c0a14 --- /dev/null +++ b/HybroLang/.antlr/HybroLangListener.java @@ -0,0 +1,255 @@ +// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 +import org.antlr.v4.runtime.tree.ParseTreeListener; + +/** + * This interface defines a complete listener for a parse tree produced by + * {@link HybroLangParser}. + */ +public interface HybroLangListener extends ParseTreeListener { + /** + * Enter a parse tree produced by {@link HybroLangParser#compilationunit}. + * @param ctx the parse tree + */ + void enterCompilationunit(HybroLangParser.CompilationunitContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#compilationunit}. + * @param ctx the parse tree + */ + void exitCompilationunit(HybroLangParser.CompilationunitContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#function}. + * @param ctx the parse tree + */ + void enterFunction(HybroLangParser.FunctionContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#function}. + * @param ctx the parse tree + */ + void exitFunction(HybroLangParser.FunctionContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#fndcl}. + * @param ctx the parse tree + */ + void enterFndcl(HybroLangParser.FndclContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#fndcl}. + * @param ctx the parse tree + */ + void exitFndcl(HybroLangParser.FndclContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#fnprototype}. + * @param ctx the parse tree + */ + void enterFnprototype(HybroLangParser.FnprototypeContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#fnprototype}. + * @param ctx the parse tree + */ + void exitFnprototype(HybroLangParser.FnprototypeContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#fnbody}. + * @param ctx the parse tree + */ + void enterFnbody(HybroLangParser.FnbodyContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#fnbody}. + * @param ctx the parse tree + */ + void exitFnbody(HybroLangParser.FnbodyContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#paramdcllist}. + * @param ctx the parse tree + */ + void enterParamdcllist(HybroLangParser.ParamdcllistContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#paramdcllist}. + * @param ctx the parse tree + */ + void exitParamdcllist(HybroLangParser.ParamdcllistContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#localvardef}. + * @param ctx the parse tree + */ + void enterLocalvardef(HybroLangParser.LocalvardefContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#localvardef}. + * @param ctx the parse tree + */ + void exitLocalvardef(HybroLangParser.LocalvardefContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#vardcllist}. + * @param ctx the parse tree + */ + void enterVardcllist(HybroLangParser.VardcllistContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#vardcllist}. + * @param ctx the parse tree + */ + void exitVardcllist(HybroLangParser.VardcllistContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#vardcl}. + * @param ctx the parse tree + */ + void enterVardcl(HybroLangParser.VardclContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#vardcl}. + * @param ctx the parse tree + */ + void exitVardcl(HybroLangParser.VardclContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#actionlist}. + * @param ctx the parse tree + */ + void enterActionlist(HybroLangParser.ActionlistContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#actionlist}. + * @param ctx the parse tree + */ + void exitActionlist(HybroLangParser.ActionlistContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#condexpr}. + * @param ctx the parse tree + */ + void enterCondexpr(HybroLangParser.CondexprContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#condexpr}. + * @param ctx the parse tree + */ + void exitCondexpr(HybroLangParser.CondexprContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#action}. + * @param ctx the parse tree + */ + void enterAction(HybroLangParser.ActionContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#action}. + * @param ctx the parse tree + */ + void exitAction(HybroLangParser.ActionContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#returnexpr}. + * @param ctx the parse tree + */ + void enterReturnexpr(HybroLangParser.ReturnexprContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#returnexpr}. + * @param ctx the parse tree + */ + void exitReturnexpr(HybroLangParser.ReturnexprContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#affectexpr}. + * @param ctx the parse tree + */ + void enterAffectexpr(HybroLangParser.AffectexprContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#affectexpr}. + * @param ctx the parse tree + */ + void exitAffectexpr(HybroLangParser.AffectexprContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#unaryexpr}. + * @param ctx the parse tree + */ + void enterUnaryexpr(HybroLangParser.UnaryexprContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#unaryexpr}. + * @param ctx the parse tree + */ + void exitUnaryexpr(HybroLangParser.UnaryexprContext ctx); + /** + * Enter a parse tree produced by the {@code varorvalueArray} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void enterVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx); + /** + * Exit a parse tree produced by the {@code varorvalueArray} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void exitVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx); + /** + * Enter a parse tree produced by the {@code varorvalueConst} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void enterVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx); + /** + * Exit a parse tree produced by the {@code varorvalueConst} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void exitVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx); + /** + * Enter a parse tree produced by the {@code varorvalueVar} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void enterVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx); + /** + * Exit a parse tree produced by the {@code varorvalueVar} + * labeled alternative in {@link HybroLangParser#varorvalue}. + * @param ctx the parse tree + */ + void exitVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#datatype}. + * @param ctx the parse tree + */ + void enterDatatype(HybroLangParser.DatatypeContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#datatype}. + * @param ctx the parse tree + */ + void exitDatatype(HybroLangParser.DatatypeContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#intconstvalue}. + * @param ctx the parse tree + */ + void enterIntconstvalue(HybroLangParser.IntconstvalueContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#intconstvalue}. + * @param ctx the parse tree + */ + void exitIntconstvalue(HybroLangParser.IntconstvalueContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#constvalue}. + * @param ctx the parse tree + */ + void enterConstvalue(HybroLangParser.ConstvalueContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#constvalue}. + * @param ctx the parse tree + */ + void exitConstvalue(HybroLangParser.ConstvalueContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#constinline}. + * @param ctx the parse tree + */ + void enterConstinline(HybroLangParser.ConstinlineContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#constinline}. + * @param ctx the parse tree + */ + void exitConstinline(HybroLangParser.ConstinlineContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#typebase}. + * @param ctx the parse tree + */ + void enterTypebase(HybroLangParser.TypebaseContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#typebase}. + * @param ctx the parse tree + */ + void exitTypebase(HybroLangParser.TypebaseContext ctx); + /** + * Enter a parse tree produced by {@link HybroLangParser#condOperator}. + * @param ctx the parse tree + */ + void enterCondOperator(HybroLangParser.CondOperatorContext ctx); + /** + * Exit a parse tree produced by {@link HybroLangParser#condOperator}. + * @param ctx the parse tree + */ + void exitCondOperator(HybroLangParser.CondOperatorContext ctx); +} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangParser.java b/HybroLang/.antlr/HybroLangParser.java new file mode 100644 index 0000000..784d4f0 --- /dev/null +++ b/HybroLang/.antlr/HybroLangParser.java @@ -0,0 +1,1680 @@ +// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 +import org.antlr.v4.runtime.atn.*; +import org.antlr.v4.runtime.dfa.DFA; +import org.antlr.v4.runtime.*; +import org.antlr.v4.runtime.misc.*; +import org.antlr.v4.runtime.tree.*; +import java.util.List; +import java.util.Iterator; +import java.util.ArrayList; + +@SuppressWarnings({"all", "warnings", "unchecked", "unused", "cast", "CheckReturnValue"}) +public class HybroLangParser extends Parser { + static { RuntimeMetaData.checkVersion("4.13.1", RuntimeMetaData.VERSION); } + + protected static final DFA[] _decisionToDFA; + protected static final PredictionContextCache _sharedContextCache = + new PredictionContextCache(); + public static final int + T__0=1, T__1=2, T__2=3, T__3=4, T__4=5, T__5=6, T__6=7, T__7=8, T__8=9, + T__9=10, T__10=11, T__11=12, T__12=13, T__13=14, T__14=15, T__15=16, T__16=17, + T__17=18, T__18=19, T__19=20, T__20=21, T__21=22, T__22=23, T__23=24, + T__24=25, T__25=26, T__26=27, T__27=28, T__28=29, T__29=30, T__30=31, + T__31=32, T__32=33, T__33=34, T__34=35, T__35=36, T__36=37, T__37=38, + DecimalFloatingConstant=39, IntegerConstant=40, DecimalConstant=41, Name=42, + INLINE=43, WhiteSpace=44, LineComment=45, NewLine=46; + public static final int + RULE_compilationunit = 0, RULE_function = 1, RULE_fndcl = 2, RULE_fnprototype = 3, + RULE_fnbody = 4, RULE_paramdcllist = 5, RULE_localvardef = 6, RULE_vardcllist = 7, + RULE_vardcl = 8, RULE_actionlist = 9, RULE_condexpr = 10, RULE_action = 11, + RULE_returnexpr = 12, RULE_affectexpr = 13, RULE_unaryexpr = 14, RULE_varorvalue = 15, + RULE_datatype = 16, RULE_intconstvalue = 17, RULE_constvalue = 18, RULE_constinline = 19, + RULE_typebase = 20, RULE_condOperator = 21; + private static String[] makeRuleNames() { + return new String[] { + "compilationunit", "function", "fndcl", "fnprototype", "fnbody", "paramdcllist", + "localvardef", "vardcllist", "vardcl", "actionlist", "condexpr", "action", + "returnexpr", "affectexpr", "unaryexpr", "varorvalue", "datatype", "intconstvalue", + "constvalue", "constinline", "typebase", "condOperator" + }; + } + public static final String[] ruleNames = makeRuleNames(); + + private static String[] makeLiteralNames() { + return new String[] { + null, "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", + "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", + "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", + "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", "'=='", "'!='", + "'<'", "'>'", "'<='", "'>='" + }; + } + private static final String[] _LITERAL_NAMES = makeLiteralNames(); + private static String[] makeSymbolicNames() { + return new String[] { + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, null, null, null, null, null, null, null, null, null, + null, null, null, "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", + "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" + }; + } + private static final String[] _SYMBOLIC_NAMES = makeSymbolicNames(); + public static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES); + + /** + * @deprecated Use {@link #VOCABULARY} instead. + */ + @Deprecated + public static final String[] tokenNames; + static { + tokenNames = new String[_SYMBOLIC_NAMES.length]; + for (int i = 0; i < tokenNames.length; i++) { + tokenNames[i] = VOCABULARY.getLiteralName(i); + if (tokenNames[i] == null) { + tokenNames[i] = VOCABULARY.getSymbolicName(i); + } + + if (tokenNames[i] == null) { + tokenNames[i] = ""; + } + } + } + + @Override + @Deprecated + public String[] getTokenNames() { + return tokenNames; + } + + @Override + + public Vocabulary getVocabulary() { + return VOCABULARY; + } + + @Override + public String getGrammarFileName() { return "HybroLang.g4"; } + + @Override + public String[] getRuleNames() { return ruleNames; } + + @Override + public String getSerializedATN() { return _serializedATN; } + + @Override + public ATN getATN() { return _ATN; } + + public HybroLangParser(TokenStream input) { + super(input); + _interp = new ParserATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache); + } + + @SuppressWarnings("CheckReturnValue") + public static class CompilationunitContext extends ParserRuleContext { + public List function() { + return getRuleContexts(FunctionContext.class); + } + public FunctionContext function(int i) { + return getRuleContext(FunctionContext.class,i); + } + public CompilationunitContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_compilationunit; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCompilationunit(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCompilationunit(this); + } + } + + public final CompilationunitContext compilationunit() throws RecognitionException { + CompilationunitContext _localctx = new CompilationunitContext(_ctx, getState()); + enterRule(_localctx, 0, RULE_compilationunit); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(45); + _errHandler.sync(this); + _la = _input.LA(1); + do { + { + { + setState(44); + function(); + } + } + setState(47); + _errHandler.sync(this); + _la = _input.LA(1); + } while ( (((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0) ); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class FunctionContext extends ParserRuleContext { + public FndclContext fndcl() { + return getRuleContext(FndclContext.class,0); + } + public FnbodyContext fnbody() { + return getRuleContext(FnbodyContext.class,0); + } + public FunctionContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_function; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFunction(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFunction(this); + } + } + + public final FunctionContext function() throws RecognitionException { + FunctionContext _localctx = new FunctionContext(_ctx, getState()); + enterRule(_localctx, 2, RULE_function); + try { + enterOuterAlt(_localctx, 1); + { + setState(49); + fndcl(); + setState(50); + fnbody(); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class FndclContext extends ParserRuleContext { + public DatatypeContext datatype() { + return getRuleContext(DatatypeContext.class,0); + } + public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } + public FnprototypeContext fnprototype() { + return getRuleContext(FnprototypeContext.class,0); + } + public FndclContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_fndcl; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFndcl(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFndcl(this); + } + } + + public final FndclContext fndcl() throws RecognitionException { + FndclContext _localctx = new FndclContext(_ctx, getState()); + enterRule(_localctx, 4, RULE_fndcl); + try { + enterOuterAlt(_localctx, 1); + { + setState(52); + datatype(); + setState(53); + match(Name); + setState(54); + fnprototype(); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class FnprototypeContext extends ParserRuleContext { + public ParamdcllistContext paramdcllist() { + return getRuleContext(ParamdcllistContext.class,0); + } + public FnprototypeContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_fnprototype; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFnprototype(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFnprototype(this); + } + } + + public final FnprototypeContext fnprototype() throws RecognitionException { + FnprototypeContext _localctx = new FnprototypeContext(_ctx, getState()); + enterRule(_localctx, 6, RULE_fnprototype); + try { + enterOuterAlt(_localctx, 1); + { + setState(56); + match(T__0); + setState(57); + paramdcllist(); + setState(58); + match(T__1); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class FnbodyContext extends ParserRuleContext { + public ActionlistContext actionlist() { + return getRuleContext(ActionlistContext.class,0); + } + public List localvardef() { + return getRuleContexts(LocalvardefContext.class); + } + public LocalvardefContext localvardef(int i) { + return getRuleContext(LocalvardefContext.class,i); + } + public ReturnexprContext returnexpr() { + return getRuleContext(ReturnexprContext.class,0); + } + public FnbodyContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_fnbody; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFnbody(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFnbody(this); + } + } + + public final FnbodyContext fnbody() throws RecognitionException { + FnbodyContext _localctx = new FnbodyContext(_ctx, getState()); + enterRule(_localctx, 8, RULE_fnbody); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(60); + match(T__2); + setState(64); + _errHandler.sync(this); + _la = _input.LA(1); + while ((((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0)) { + { + { + setState(61); + localvardef(); + } + } + setState(66); + _errHandler.sync(this); + _la = _input.LA(1); + } + setState(67); + actionlist(); + setState(69); + _errHandler.sync(this); + _la = _input.LA(1); + if (_la==T__9) { + { + setState(68); + returnexpr(); + } + } + + setState(71); + match(T__3); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ParamdcllistContext extends ParserRuleContext { + public List vardcl() { + return getRuleContexts(VardclContext.class); + } + public VardclContext vardcl(int i) { + return getRuleContext(VardclContext.class,i); + } + public ParamdcllistContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_paramdcllist; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterParamdcllist(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitParamdcllist(this); + } + } + + public final ParamdcllistContext paramdcllist() throws RecognitionException { + ParamdcllistContext _localctx = new ParamdcllistContext(_ctx, getState()); + enterRule(_localctx, 10, RULE_paramdcllist); + int _la; + try { + setState(82); + _errHandler.sync(this); + switch (_input.LA(1)) { + case T__22: + case T__23: + case T__24: + case T__25: + case T__26: + case T__27: + case T__28: + case T__29: + case T__30: + enterOuterAlt(_localctx, 1); + { + setState(73); + vardcl(); + setState(78); + _errHandler.sync(this); + _la = _input.LA(1); + while (_la==T__4) { + { + { + setState(74); + match(T__4); + setState(75); + vardcl(); + } + } + setState(80); + _errHandler.sync(this); + _la = _input.LA(1); + } + } + break; + case T__1: + enterOuterAlt(_localctx, 2); + { + } + break; + default: + throw new NoViableAltException(this); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class LocalvardefContext extends ParserRuleContext { + public VardcllistContext vardcllist() { + return getRuleContext(VardcllistContext.class,0); + } + public LocalvardefContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_localvardef; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterLocalvardef(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitLocalvardef(this); + } + } + + public final LocalvardefContext localvardef() throws RecognitionException { + LocalvardefContext _localctx = new LocalvardefContext(_ctx, getState()); + enterRule(_localctx, 12, RULE_localvardef); + try { + enterOuterAlt(_localctx, 1); + { + setState(84); + vardcllist(); + setState(85); + match(T__5); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class VardcllistContext extends ParserRuleContext { + public VardclContext vardcl() { + return getRuleContext(VardclContext.class,0); + } + public List Name() { return getTokens(HybroLangParser.Name); } + public TerminalNode Name(int i) { + return getToken(HybroLangParser.Name, i); + } + public VardcllistContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_vardcllist; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVardcllist(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVardcllist(this); + } + } + + public final VardcllistContext vardcllist() throws RecognitionException { + VardcllistContext _localctx = new VardcllistContext(_ctx, getState()); + enterRule(_localctx, 14, RULE_vardcllist); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(87); + vardcl(); + setState(92); + _errHandler.sync(this); + _la = _input.LA(1); + while (_la==T__4) { + { + { + setState(88); + match(T__4); + setState(89); + match(Name); + } + } + setState(94); + _errHandler.sync(this); + _la = _input.LA(1); + } + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class VardclContext extends ParserRuleContext { + public DatatypeContext datatype() { + return getRuleContext(DatatypeContext.class,0); + } + public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } + public VardclContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_vardcl; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVardcl(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVardcl(this); + } + } + + public final VardclContext vardcl() throws RecognitionException { + VardclContext _localctx = new VardclContext(_ctx, getState()); + enterRule(_localctx, 16, RULE_vardcl); + try { + enterOuterAlt(_localctx, 1); + { + setState(95); + datatype(); + setState(96); + match(Name); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ActionlistContext extends ParserRuleContext { + public List action() { + return getRuleContexts(ActionContext.class); + } + public ActionContext action(int i) { + return getRuleContext(ActionContext.class,i); + } + public ActionlistContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_actionlist; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterActionlist(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitActionlist(this); + } + } + + public final ActionlistContext actionlist() throws RecognitionException { + ActionlistContext _localctx = new ActionlistContext(_ctx, getState()); + enterRule(_localctx, 18, RULE_actionlist); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(101); + _errHandler.sync(this); + _la = _input.LA(1); + while ((((_la) & ~0x3f) == 0 && ((1L << _la) & 4398046511488L) != 0)) { + { + { + setState(98); + action(); + } + } + setState(103); + _errHandler.sync(this); + _la = _input.LA(1); + } + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class CondexprContext extends ParserRuleContext { + public List varorvalue() { + return getRuleContexts(VarorvalueContext.class); + } + public VarorvalueContext varorvalue(int i) { + return getRuleContext(VarorvalueContext.class,i); + } + public CondOperatorContext condOperator() { + return getRuleContext(CondOperatorContext.class,0); + } + public CondexprContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_condexpr; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCondexpr(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCondexpr(this); + } + } + + public final CondexprContext condexpr() throws RecognitionException { + CondexprContext _localctx = new CondexprContext(_ctx, getState()); + enterRule(_localctx, 20, RULE_condexpr); + try { + enterOuterAlt(_localctx, 1); + { + setState(104); + varorvalue(); + setState(105); + condOperator(); + setState(106); + varorvalue(); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ActionContext extends ParserRuleContext { + public List affectexpr() { + return getRuleContexts(AffectexprContext.class); + } + public AffectexprContext affectexpr(int i) { + return getRuleContext(AffectexprContext.class,i); + } + public CondexprContext condexpr() { + return getRuleContext(CondexprContext.class,0); + } + public List actionlist() { + return getRuleContexts(ActionlistContext.class); + } + public ActionlistContext actionlist(int i) { + return getRuleContext(ActionlistContext.class,i); + } + public ActionContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_action; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterAction(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitAction(this); + } + } + + public final ActionContext action() throws RecognitionException { + ActionContext _localctx = new ActionContext(_ctx, getState()); + enterRule(_localctx, 22, RULE_action); + try { + setState(135); + _errHandler.sync(this); + switch (_input.LA(1)) { + case Name: + enterOuterAlt(_localctx, 1); + { + setState(108); + affectexpr(); + setState(109); + match(T__5); + } + break; + case T__6: + enterOuterAlt(_localctx, 2); + { + setState(111); + match(T__6); + setState(112); + match(T__0); + setState(113); + affectexpr(); + setState(114); + match(T__5); + setState(115); + condexpr(); + setState(116); + match(T__5); + setState(117); + affectexpr(); + setState(118); + match(T__1); + setState(119); + match(T__2); + setState(120); + actionlist(); + setState(121); + match(T__3); + } + break; + case T__7: + enterOuterAlt(_localctx, 3); + { + setState(123); + match(T__7); + setState(124); + match(T__0); + setState(125); + condexpr(); + setState(126); + match(T__1); + setState(127); + match(T__2); + setState(128); + actionlist(); + setState(129); + match(T__3); + setState(130); + match(T__8); + setState(131); + match(T__2); + setState(132); + actionlist(); + setState(133); + match(T__3); + } + break; + default: + throw new NoViableAltException(this); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ReturnexprContext extends ParserRuleContext { + public UnaryexprContext unaryexpr() { + return getRuleContext(UnaryexprContext.class,0); + } + public ReturnexprContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_returnexpr; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterReturnexpr(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitReturnexpr(this); + } + } + + public final ReturnexprContext returnexpr() throws RecognitionException { + ReturnexprContext _localctx = new ReturnexprContext(_ctx, getState()); + enterRule(_localctx, 24, RULE_returnexpr); + try { + enterOuterAlt(_localctx, 1); + { + setState(137); + match(T__9); + setState(138); + unaryexpr(0); + setState(139); + match(T__5); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class AffectexprContext extends ParserRuleContext { + public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } + public List unaryexpr() { + return getRuleContexts(UnaryexprContext.class); + } + public UnaryexprContext unaryexpr(int i) { + return getRuleContext(UnaryexprContext.class,i); + } + public AffectexprContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_affectexpr; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterAffectexpr(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitAffectexpr(this); + } + } + + public final AffectexprContext affectexpr() throws RecognitionException { + AffectexprContext _localctx = new AffectexprContext(_ctx, getState()); + enterRule(_localctx, 26, RULE_affectexpr); + try { + setState(151); + _errHandler.sync(this); + switch ( getInterpreter().adaptivePredict(_input,8,_ctx) ) { + case 1: + enterOuterAlt(_localctx, 1); + { + setState(141); + match(Name); + setState(142); + match(T__10); + setState(143); + unaryexpr(0); + } + break; + case 2: + enterOuterAlt(_localctx, 2); + { + setState(144); + match(Name); + setState(145); + match(T__11); + setState(146); + unaryexpr(0); + setState(147); + match(T__12); + setState(148); + match(T__10); + setState(149); + unaryexpr(0); + } + break; + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class UnaryexprContext extends ParserRuleContext { + public Token op; + public VarorvalueContext varorvalue() { + return getRuleContext(VarorvalueContext.class,0); + } + public List unaryexpr() { + return getRuleContexts(UnaryexprContext.class); + } + public UnaryexprContext unaryexpr(int i) { + return getRuleContext(UnaryexprContext.class,i); + } + public UnaryexprContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_unaryexpr; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterUnaryexpr(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitUnaryexpr(this); + } + } + + public final UnaryexprContext unaryexpr() throws RecognitionException { + return unaryexpr(0); + } + + private UnaryexprContext unaryexpr(int _p) throws RecognitionException { + ParserRuleContext _parentctx = _ctx; + int _parentState = getState(); + UnaryexprContext _localctx = new UnaryexprContext(_ctx, _parentState); + UnaryexprContext _prevctx = _localctx; + int _startState = 28; + enterRecursionRule(_localctx, 28, RULE_unaryexpr, _p); + int _la; + try { + int _alt; + enterOuterAlt(_localctx, 1); + { + { + setState(154); + varorvalue(); + } + _ctx.stop = _input.LT(-1); + setState(170); + _errHandler.sync(this); + _alt = getInterpreter().adaptivePredict(_input,10,_ctx); + while ( _alt!=2 && _alt!=org.antlr.v4.runtime.atn.ATN.INVALID_ALT_NUMBER ) { + if ( _alt==1 ) { + if ( _parseListeners!=null ) triggerExitRuleEvent(); + _prevctx = _localctx; + { + setState(168); + _errHandler.sync(this); + switch ( getInterpreter().adaptivePredict(_input,9,_ctx) ) { + case 1: + { + _localctx = new UnaryexprContext(_parentctx, _parentState); + pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); + setState(156); + if (!(precpred(_ctx, 5))) throw new FailedPredicateException(this, "precpred(_ctx, 5)"); + setState(157); + ((UnaryexprContext)_localctx).op = _input.LT(1); + _la = _input.LA(1); + if ( !(_la==T__13 || _la==T__14) ) { + ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + setState(158); + unaryexpr(6); + } + break; + case 2: + { + _localctx = new UnaryexprContext(_parentctx, _parentState); + pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); + setState(159); + if (!(precpred(_ctx, 4))) throw new FailedPredicateException(this, "precpred(_ctx, 4)"); + setState(160); + ((UnaryexprContext)_localctx).op = _input.LT(1); + _la = _input.LA(1); + if ( !(_la==T__15 || _la==T__16) ) { + ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + setState(161); + unaryexpr(5); + } + break; + case 3: + { + _localctx = new UnaryexprContext(_parentctx, _parentState); + pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); + setState(162); + if (!(precpred(_ctx, 3))) throw new FailedPredicateException(this, "precpred(_ctx, 3)"); + setState(163); + ((UnaryexprContext)_localctx).op = _input.LT(1); + _la = _input.LA(1); + if ( !(_la==T__17 || _la==T__18) ) { + ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + setState(164); + unaryexpr(4); + } + break; + case 4: + { + _localctx = new UnaryexprContext(_parentctx, _parentState); + pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); + setState(165); + if (!(precpred(_ctx, 2))) throw new FailedPredicateException(this, "precpred(_ctx, 2)"); + setState(166); + ((UnaryexprContext)_localctx).op = _input.LT(1); + _la = _input.LA(1); + if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 7340032L) != 0)) ) { + ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + setState(167); + unaryexpr(3); + } + break; + } + } + } + setState(172); + _errHandler.sync(this); + _alt = getInterpreter().adaptivePredict(_input,10,_ctx); + } + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + unrollRecursionContexts(_parentctx); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class VarorvalueContext extends ParserRuleContext { + public VarorvalueContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_varorvalue; } + + public VarorvalueContext() { } + public void copyFrom(VarorvalueContext ctx) { + super.copyFrom(ctx); + } + } + @SuppressWarnings("CheckReturnValue") + public static class VarorvalueVarContext extends VarorvalueContext { + public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } + public VarorvalueVarContext(VarorvalueContext ctx) { copyFrom(ctx); } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueVar(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueVar(this); + } + } + @SuppressWarnings("CheckReturnValue") + public static class VarorvalueArrayContext extends VarorvalueContext { + public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } + public UnaryexprContext unaryexpr() { + return getRuleContext(UnaryexprContext.class,0); + } + public VarorvalueArrayContext(VarorvalueContext ctx) { copyFrom(ctx); } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueArray(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueArray(this); + } + } + @SuppressWarnings("CheckReturnValue") + public static class VarorvalueConstContext extends VarorvalueContext { + public ConstvalueContext constvalue() { + return getRuleContext(ConstvalueContext.class,0); + } + public VarorvalueConstContext(VarorvalueContext ctx) { copyFrom(ctx); } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueConst(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueConst(this); + } + } + + public final VarorvalueContext varorvalue() throws RecognitionException { + VarorvalueContext _localctx = new VarorvalueContext(_ctx, getState()); + enterRule(_localctx, 30, RULE_varorvalue); + try { + setState(180); + _errHandler.sync(this); + switch ( getInterpreter().adaptivePredict(_input,11,_ctx) ) { + case 1: + _localctx = new VarorvalueArrayContext(_localctx); + enterOuterAlt(_localctx, 1); + { + setState(173); + match(Name); + setState(174); + match(T__11); + setState(175); + unaryexpr(0); + setState(176); + match(T__12); + } + break; + case 2: + _localctx = new VarorvalueConstContext(_localctx); + enterOuterAlt(_localctx, 2); + { + setState(178); + constvalue(); + } + break; + case 3: + _localctx = new VarorvalueVarContext(_localctx); + enterOuterAlt(_localctx, 3); + { + setState(179); + match(Name); + } + break; + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class DatatypeContext extends ParserRuleContext { + public IntconstvalueContext wordlen; + public IntconstvalueContext vectorlen; + public TypebaseContext typebase() { + return getRuleContext(TypebaseContext.class,0); + } + public List intconstvalue() { + return getRuleContexts(IntconstvalueContext.class); + } + public IntconstvalueContext intconstvalue(int i) { + return getRuleContext(IntconstvalueContext.class,i); + } + public DatatypeContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_datatype; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterDatatype(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitDatatype(this); + } + } + + public final DatatypeContext datatype() throws RecognitionException { + DatatypeContext _localctx = new DatatypeContext(_ctx, getState()); + enterRule(_localctx, 32, RULE_datatype); + try { + enterOuterAlt(_localctx, 1); + { + setState(182); + typebase(); + setState(183); + ((DatatypeContext)_localctx).wordlen = intconstvalue(); + setState(184); + ((DatatypeContext)_localctx).vectorlen = intconstvalue(); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class IntconstvalueContext extends ParserRuleContext { + public TerminalNode IntegerConstant() { return getToken(HybroLangParser.IntegerConstant, 0); } + public ConstinlineContext constinline() { + return getRuleContext(ConstinlineContext.class,0); + } + public IntconstvalueContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_intconstvalue; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterIntconstvalue(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitIntconstvalue(this); + } + } + + public final IntconstvalueContext intconstvalue() throws RecognitionException { + IntconstvalueContext _localctx = new IntconstvalueContext(_ctx, getState()); + enterRule(_localctx, 34, RULE_intconstvalue); + try { + setState(188); + _errHandler.sync(this); + switch (_input.LA(1)) { + case IntegerConstant: + enterOuterAlt(_localctx, 1); + { + setState(186); + match(IntegerConstant); + } + break; + case INLINE: + enterOuterAlt(_localctx, 2); + { + setState(187); + constinline(); + } + break; + default: + throw new NoViableAltException(this); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ConstvalueContext extends ParserRuleContext { + public TerminalNode IntegerConstant() { return getToken(HybroLangParser.IntegerConstant, 0); } + public TerminalNode DecimalFloatingConstant() { return getToken(HybroLangParser.DecimalFloatingConstant, 0); } + public ConstinlineContext constinline() { + return getRuleContext(ConstinlineContext.class,0); + } + public ConstvalueContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_constvalue; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterConstvalue(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitConstvalue(this); + } + } + + public final ConstvalueContext constvalue() throws RecognitionException { + ConstvalueContext _localctx = new ConstvalueContext(_ctx, getState()); + enterRule(_localctx, 36, RULE_constvalue); + try { + setState(193); + _errHandler.sync(this); + switch (_input.LA(1)) { + case IntegerConstant: + enterOuterAlt(_localctx, 1); + { + setState(190); + match(IntegerConstant); + } + break; + case DecimalFloatingConstant: + enterOuterAlt(_localctx, 2); + { + setState(191); + match(DecimalFloatingConstant); + } + break; + case INLINE: + enterOuterAlt(_localctx, 3); + { + setState(192); + constinline(); + } + break; + default: + throw new NoViableAltException(this); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class ConstinlineContext extends ParserRuleContext { + public TerminalNode INLINE() { return getToken(HybroLangParser.INLINE, 0); } + public ConstinlineContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_constinline; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterConstinline(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitConstinline(this); + } + } + + public final ConstinlineContext constinline() throws RecognitionException { + ConstinlineContext _localctx = new ConstinlineContext(_ctx, getState()); + enterRule(_localctx, 38, RULE_constinline); + try { + enterOuterAlt(_localctx, 1); + { + setState(195); + match(INLINE); + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class TypebaseContext extends ParserRuleContext { + public TypebaseContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_typebase; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterTypebase(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitTypebase(this); + } + } + + public final TypebaseContext typebase() throws RecognitionException { + TypebaseContext _localctx = new TypebaseContext(_ctx, getState()); + enterRule(_localctx, 40, RULE_typebase); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(197); + _la = _input.LA(1); + if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0)) ) { + _errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + setState(199); + _errHandler.sync(this); + _la = _input.LA(1); + if (_la==T__31) { + { + setState(198); + match(T__31); + } + } + + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + @SuppressWarnings("CheckReturnValue") + public static class CondOperatorContext extends ParserRuleContext { + public CondOperatorContext(ParserRuleContext parent, int invokingState) { + super(parent, invokingState); + } + @Override public int getRuleIndex() { return RULE_condOperator; } + @Override + public void enterRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCondOperator(this); + } + @Override + public void exitRule(ParseTreeListener listener) { + if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCondOperator(this); + } + } + + public final CondOperatorContext condOperator() throws RecognitionException { + CondOperatorContext _localctx = new CondOperatorContext(_ctx, getState()); + enterRule(_localctx, 42, RULE_condOperator); + int _la; + try { + enterOuterAlt(_localctx, 1); + { + setState(201); + _la = _input.LA(1); + if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 541165879296L) != 0)) ) { + _errHandler.recoverInline(this); + } + else { + if ( _input.LA(1)==Token.EOF ) matchedEOF = true; + _errHandler.reportMatch(this); + consume(); + } + } + } + catch (RecognitionException re) { + _localctx.exception = re; + _errHandler.reportError(this, re); + _errHandler.recover(this, re); + } + finally { + exitRule(); + } + return _localctx; + } + + public boolean sempred(RuleContext _localctx, int ruleIndex, int predIndex) { + switch (ruleIndex) { + case 14: + return unaryexpr_sempred((UnaryexprContext)_localctx, predIndex); + } + return true; + } + private boolean unaryexpr_sempred(UnaryexprContext _localctx, int predIndex) { + switch (predIndex) { + case 0: + return precpred(_ctx, 5); + case 1: + return precpred(_ctx, 4); + case 2: + return precpred(_ctx, 3); + case 3: + return precpred(_ctx, 2); + } + return true; + } + + public static final String _serializedATN = + "\u0004\u0001.\u00cc\u0002\u0000\u0007\u0000\u0002\u0001\u0007\u0001\u0002"+ + "\u0002\u0007\u0002\u0002\u0003\u0007\u0003\u0002\u0004\u0007\u0004\u0002"+ + "\u0005\u0007\u0005\u0002\u0006\u0007\u0006\u0002\u0007\u0007\u0007\u0002"+ + "\b\u0007\b\u0002\t\u0007\t\u0002\n\u0007\n\u0002\u000b\u0007\u000b\u0002"+ + "\f\u0007\f\u0002\r\u0007\r\u0002\u000e\u0007\u000e\u0002\u000f\u0007\u000f"+ + "\u0002\u0010\u0007\u0010\u0002\u0011\u0007\u0011\u0002\u0012\u0007\u0012"+ + "\u0002\u0013\u0007\u0013\u0002\u0014\u0007\u0014\u0002\u0015\u0007\u0015"+ + "\u0001\u0000\u0004\u0000.\b\u0000\u000b\u0000\f\u0000/\u0001\u0001\u0001"+ + "\u0001\u0001\u0001\u0001\u0002\u0001\u0002\u0001\u0002\u0001\u0002\u0001"+ + "\u0003\u0001\u0003\u0001\u0003\u0001\u0003\u0001\u0004\u0001\u0004\u0005"+ + "\u0004?\b\u0004\n\u0004\f\u0004B\t\u0004\u0001\u0004\u0001\u0004\u0003"+ + "\u0004F\b\u0004\u0001\u0004\u0001\u0004\u0001\u0005\u0001\u0005\u0001"+ + "\u0005\u0005\u0005M\b\u0005\n\u0005\f\u0005P\t\u0005\u0001\u0005\u0003"+ + "\u0005S\b\u0005\u0001\u0006\u0001\u0006\u0001\u0006\u0001\u0007\u0001"+ + "\u0007\u0001\u0007\u0005\u0007[\b\u0007\n\u0007\f\u0007^\t\u0007\u0001"+ + "\b\u0001\b\u0001\b\u0001\t\u0005\td\b\t\n\t\f\tg\t\t\u0001\n\u0001\n\u0001"+ + "\n\u0001\n\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ + "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ + "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ + "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ + "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0003\u000b\u0088\b\u000b"+ + "\u0001\f\u0001\f\u0001\f\u0001\f\u0001\r\u0001\r\u0001\r\u0001\r\u0001"+ + "\r\u0001\r\u0001\r\u0001\r\u0001\r\u0001\r\u0003\r\u0098\b\r\u0001\u000e"+ + "\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e"+ + "\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e\u0001\u000e"+ + "\u0001\u000e\u0001\u000e\u0005\u000e\u00a9\b\u000e\n\u000e\f\u000e\u00ac"+ + "\t\u000e\u0001\u000f\u0001\u000f\u0001\u000f\u0001\u000f\u0001\u000f\u0001"+ + "\u000f\u0001\u000f\u0003\u000f\u00b5\b\u000f\u0001\u0010\u0001\u0010\u0001"+ + "\u0010\u0001\u0010\u0001\u0011\u0001\u0011\u0003\u0011\u00bd\b\u0011\u0001"+ + "\u0012\u0001\u0012\u0001\u0012\u0003\u0012\u00c2\b\u0012\u0001\u0013\u0001"+ + "\u0013\u0001\u0014\u0001\u0014\u0003\u0014\u00c8\b\u0014\u0001\u0015\u0001"+ + "\u0015\u0001\u0015\u0000\u0001\u001c\u0016\u0000\u0002\u0004\u0006\b\n"+ + "\f\u000e\u0010\u0012\u0014\u0016\u0018\u001a\u001c\u001e \"$&(*\u0000"+ + "\u0006\u0001\u0000\u000e\u000f\u0001\u0000\u0010\u0011\u0001\u0000\u0012"+ + "\u0013\u0001\u0000\u0014\u0016\u0001\u0000\u0017\u001f\u0001\u0000!&\u00c9"+ + "\u0000-\u0001\u0000\u0000\u0000\u00021\u0001\u0000\u0000\u0000\u00044"+ + "\u0001\u0000\u0000\u0000\u00068\u0001\u0000\u0000\u0000\b<\u0001\u0000"+ + "\u0000\u0000\nR\u0001\u0000\u0000\u0000\fT\u0001\u0000\u0000\u0000\u000e"+ + "W\u0001\u0000\u0000\u0000\u0010_\u0001\u0000\u0000\u0000\u0012e\u0001"+ + "\u0000\u0000\u0000\u0014h\u0001\u0000\u0000\u0000\u0016\u0087\u0001\u0000"+ + "\u0000\u0000\u0018\u0089\u0001\u0000\u0000\u0000\u001a\u0097\u0001\u0000"+ + "\u0000\u0000\u001c\u0099\u0001\u0000\u0000\u0000\u001e\u00b4\u0001\u0000"+ + "\u0000\u0000 \u00b6\u0001\u0000\u0000\u0000\"\u00bc\u0001\u0000\u0000"+ + "\u0000$\u00c1\u0001\u0000\u0000\u0000&\u00c3\u0001\u0000\u0000\u0000("+ + "\u00c5\u0001\u0000\u0000\u0000*\u00c9\u0001\u0000\u0000\u0000,.\u0003"+ + "\u0002\u0001\u0000-,\u0001\u0000\u0000\u0000./\u0001\u0000\u0000\u0000"+ + "/-\u0001\u0000\u0000\u0000/0\u0001\u0000\u0000\u00000\u0001\u0001\u0000"+ + "\u0000\u000012\u0003\u0004\u0002\u000023\u0003\b\u0004\u00003\u0003\u0001"+ + "\u0000\u0000\u000045\u0003 \u0010\u000056\u0005*\u0000\u000067\u0003\u0006"+ + "\u0003\u00007\u0005\u0001\u0000\u0000\u000089\u0005\u0001\u0000\u0000"+ + "9:\u0003\n\u0005\u0000:;\u0005\u0002\u0000\u0000;\u0007\u0001\u0000\u0000"+ + "\u0000<@\u0005\u0003\u0000\u0000=?\u0003\f\u0006\u0000>=\u0001\u0000\u0000"+ + "\u0000?B\u0001\u0000\u0000\u0000@>\u0001\u0000\u0000\u0000@A\u0001\u0000"+ + "\u0000\u0000AC\u0001\u0000\u0000\u0000B@\u0001\u0000\u0000\u0000CE\u0003"+ + "\u0012\t\u0000DF\u0003\u0018\f\u0000ED\u0001\u0000\u0000\u0000EF\u0001"+ + "\u0000\u0000\u0000FG\u0001\u0000\u0000\u0000GH\u0005\u0004\u0000\u0000"+ + "H\t\u0001\u0000\u0000\u0000IN\u0003\u0010\b\u0000JK\u0005\u0005\u0000"+ + "\u0000KM\u0003\u0010\b\u0000LJ\u0001\u0000\u0000\u0000MP\u0001\u0000\u0000"+ + "\u0000NL\u0001\u0000\u0000\u0000NO\u0001\u0000\u0000\u0000OS\u0001\u0000"+ + "\u0000\u0000PN\u0001\u0000\u0000\u0000QS\u0001\u0000\u0000\u0000RI\u0001"+ + "\u0000\u0000\u0000RQ\u0001\u0000\u0000\u0000S\u000b\u0001\u0000\u0000"+ + "\u0000TU\u0003\u000e\u0007\u0000UV\u0005\u0006\u0000\u0000V\r\u0001\u0000"+ + "\u0000\u0000W\\\u0003\u0010\b\u0000XY\u0005\u0005\u0000\u0000Y[\u0005"+ + "*\u0000\u0000ZX\u0001\u0000\u0000\u0000[^\u0001\u0000\u0000\u0000\\Z\u0001"+ + "\u0000\u0000\u0000\\]\u0001\u0000\u0000\u0000]\u000f\u0001\u0000\u0000"+ + "\u0000^\\\u0001\u0000\u0000\u0000_`\u0003 \u0010\u0000`a\u0005*\u0000"+ + "\u0000a\u0011\u0001\u0000\u0000\u0000bd\u0003\u0016\u000b\u0000cb\u0001"+ + "\u0000\u0000\u0000dg\u0001\u0000\u0000\u0000ec\u0001\u0000\u0000\u0000"+ + "ef\u0001\u0000\u0000\u0000f\u0013\u0001\u0000\u0000\u0000ge\u0001\u0000"+ + "\u0000\u0000hi\u0003\u001e\u000f\u0000ij\u0003*\u0015\u0000jk\u0003\u001e"+ + "\u000f\u0000k\u0015\u0001\u0000\u0000\u0000lm\u0003\u001a\r\u0000mn\u0005"+ + "\u0006\u0000\u0000n\u0088\u0001\u0000\u0000\u0000op\u0005\u0007\u0000"+ + "\u0000pq\u0005\u0001\u0000\u0000qr\u0003\u001a\r\u0000rs\u0005\u0006\u0000"+ + "\u0000st\u0003\u0014\n\u0000tu\u0005\u0006\u0000\u0000uv\u0003\u001a\r"+ + "\u0000vw\u0005\u0002\u0000\u0000wx\u0005\u0003\u0000\u0000xy\u0003\u0012"+ + "\t\u0000yz\u0005\u0004\u0000\u0000z\u0088\u0001\u0000\u0000\u0000{|\u0005"+ + "\b\u0000\u0000|}\u0005\u0001\u0000\u0000}~\u0003\u0014\n\u0000~\u007f"+ + "\u0005\u0002\u0000\u0000\u007f\u0080\u0005\u0003\u0000\u0000\u0080\u0081"+ + "\u0003\u0012\t\u0000\u0081\u0082\u0005\u0004\u0000\u0000\u0082\u0083\u0005"+ + "\t\u0000\u0000\u0083\u0084\u0005\u0003\u0000\u0000\u0084\u0085\u0003\u0012"+ + "\t\u0000\u0085\u0086\u0005\u0004\u0000\u0000\u0086\u0088\u0001\u0000\u0000"+ + "\u0000\u0087l\u0001\u0000\u0000\u0000\u0087o\u0001\u0000\u0000\u0000\u0087"+ + "{\u0001\u0000\u0000\u0000\u0088\u0017\u0001\u0000\u0000\u0000\u0089\u008a"+ + "\u0005\n\u0000\u0000\u008a\u008b\u0003\u001c\u000e\u0000\u008b\u008c\u0005"+ + "\u0006\u0000\u0000\u008c\u0019\u0001\u0000\u0000\u0000\u008d\u008e\u0005"+ + "*\u0000\u0000\u008e\u008f\u0005\u000b\u0000\u0000\u008f\u0098\u0003\u001c"+ + "\u000e\u0000\u0090\u0091\u0005*\u0000\u0000\u0091\u0092\u0005\f\u0000"+ + "\u0000\u0092\u0093\u0003\u001c\u000e\u0000\u0093\u0094\u0005\r\u0000\u0000"+ + "\u0094\u0095\u0005\u000b\u0000\u0000\u0095\u0096\u0003\u001c\u000e\u0000"+ + "\u0096\u0098\u0001\u0000\u0000\u0000\u0097\u008d\u0001\u0000\u0000\u0000"+ + "\u0097\u0090\u0001\u0000\u0000\u0000\u0098\u001b\u0001\u0000\u0000\u0000"+ + "\u0099\u009a\u0006\u000e\uffff\uffff\u0000\u009a\u009b\u0003\u001e\u000f"+ + "\u0000\u009b\u00aa\u0001\u0000\u0000\u0000\u009c\u009d\n\u0005\u0000\u0000"+ + "\u009d\u009e\u0007\u0000\u0000\u0000\u009e\u00a9\u0003\u001c\u000e\u0006"+ + "\u009f\u00a0\n\u0004\u0000\u0000\u00a0\u00a1\u0007\u0001\u0000\u0000\u00a1"+ + "\u00a9\u0003\u001c\u000e\u0005\u00a2\u00a3\n\u0003\u0000\u0000\u00a3\u00a4"+ + "\u0007\u0002\u0000\u0000\u00a4\u00a9\u0003\u001c\u000e\u0004\u00a5\u00a6"+ + "\n\u0002\u0000\u0000\u00a6\u00a7\u0007\u0003\u0000\u0000\u00a7\u00a9\u0003"+ + "\u001c\u000e\u0003\u00a8\u009c\u0001\u0000\u0000\u0000\u00a8\u009f\u0001"+ + "\u0000\u0000\u0000\u00a8\u00a2\u0001\u0000\u0000\u0000\u00a8\u00a5\u0001"+ + "\u0000\u0000\u0000\u00a9\u00ac\u0001\u0000\u0000\u0000\u00aa\u00a8\u0001"+ + "\u0000\u0000\u0000\u00aa\u00ab\u0001\u0000\u0000\u0000\u00ab\u001d\u0001"+ + "\u0000\u0000\u0000\u00ac\u00aa\u0001\u0000\u0000\u0000\u00ad\u00ae\u0005"+ + "*\u0000\u0000\u00ae\u00af\u0005\f\u0000\u0000\u00af\u00b0\u0003\u001c"+ + "\u000e\u0000\u00b0\u00b1\u0005\r\u0000\u0000\u00b1\u00b5\u0001\u0000\u0000"+ + "\u0000\u00b2\u00b5\u0003$\u0012\u0000\u00b3\u00b5\u0005*\u0000\u0000\u00b4"+ + "\u00ad\u0001\u0000\u0000\u0000\u00b4\u00b2\u0001\u0000\u0000\u0000\u00b4"+ + "\u00b3\u0001\u0000\u0000\u0000\u00b5\u001f\u0001\u0000\u0000\u0000\u00b6"+ + "\u00b7\u0003(\u0014\u0000\u00b7\u00b8\u0003\"\u0011\u0000\u00b8\u00b9"+ + "\u0003\"\u0011\u0000\u00b9!\u0001\u0000\u0000\u0000\u00ba\u00bd\u0005"+ + "(\u0000\u0000\u00bb\u00bd\u0003&\u0013\u0000\u00bc\u00ba\u0001\u0000\u0000"+ + "\u0000\u00bc\u00bb\u0001\u0000\u0000\u0000\u00bd#\u0001\u0000\u0000\u0000"+ + "\u00be\u00c2\u0005(\u0000\u0000\u00bf\u00c2\u0005\'\u0000\u0000\u00c0"+ + "\u00c2\u0003&\u0013\u0000\u00c1\u00be\u0001\u0000\u0000\u0000\u00c1\u00bf"+ + "\u0001\u0000\u0000\u0000\u00c1\u00c0\u0001\u0000\u0000\u0000\u00c2%\u0001"+ + "\u0000\u0000\u0000\u00c3\u00c4\u0005+\u0000\u0000\u00c4\'\u0001\u0000"+ + "\u0000\u0000\u00c5\u00c7\u0007\u0004\u0000\u0000\u00c6\u00c8\u0005 \u0000"+ + "\u0000\u00c7\u00c6\u0001\u0000\u0000\u0000\u00c7\u00c8\u0001\u0000\u0000"+ + "\u0000\u00c8)\u0001\u0000\u0000\u0000\u00c9\u00ca\u0007\u0005\u0000\u0000"+ + "\u00ca+\u0001\u0000\u0000\u0000\u000f/@ENR\\e\u0087\u0097\u00a8\u00aa"+ + "\u00b4\u00bc\u00c1\u00c7"; + public static final ATN _ATN = + new ATNDeserializer().deserialize(_serializedATN.toCharArray()); + static { + _decisionToDFA = new DFA[_ATN.getNumberOfDecisions()]; + for (int i = 0; i < _ATN.getNumberOfDecisions(); i++) { + _decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i); + } + } +} \ No newline at end of file diff --git a/HybroLang/HybroLang.interp b/HybroLang/HybroLang.interp new file mode 100644 index 0000000..4f98fb4 --- /dev/null +++ b/HybroLang/HybroLang.interp @@ -0,0 +1,125 @@ +token literal names: +null +'(' +')' +'{' +'}' +',' +';' +'for' +'if' +'else' +'return' +'=' +'[' +']' +'*' +'/' +'+' +'-' +'<<' +'>>' +'&' +'|' +'^' +'int' +'uint' +'sint' +'suint' +'flt' +'cpl' +'pix' +'ipv4' +'ipv6' +'[]' +'==' +'!=' +'<' +'>' +'<=' +'>=' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +DecimalFloatingConstant +IntegerConstant +DecimalConstant +Name +INLINE +WhiteSpace +LineComment +NewLine + +rule names: +compilationunit +function +fndcl +fnprototype +fnbody +paramdcllist +localvardef +vardcllist +vardcl +actionlist +condexpr +action +returnexpr +affectexpr +unaryexpr +varorvalue +datatype +intconstvalue +constvalue +constinline +typebase +condOperator + + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 48, 206, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 3, 2, 6, 2, 48, 10, 2, 13, 2, 14, 2, 49, 3, 3, 3, 3, 3, 3, 3, 4, 3, 4, 3, 4, 3, 4, 3, 5, 3, 5, 3, 5, 3, 5, 3, 6, 3, 6, 7, 6, 65, 10, 6, 12, 6, 14, 6, 68, 11, 6, 3, 6, 3, 6, 5, 6, 72, 10, 6, 3, 6, 3, 6, 3, 7, 3, 7, 3, 7, 7, 7, 79, 10, 7, 12, 7, 14, 7, 82, 11, 7, 3, 7, 5, 7, 85, 10, 7, 3, 8, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 7, 9, 93, 10, 9, 12, 9, 14, 9, 96, 11, 9, 3, 10, 3, 10, 3, 10, 3, 11, 7, 11, 102, 10, 11, 12, 11, 14, 11, 105, 11, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 5, 13, 138, 10, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 3, 15, 5, 15, 154, 10, 15, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 3, 16, 7, 16, 171, 10, 16, 12, 16, 14, 16, 174, 11, 16, 3, 17, 3, 17, 3, 17, 3, 17, 3, 17, 3, 17, 3, 17, 5, 17, 183, 10, 17, 3, 18, 3, 18, 3, 18, 3, 18, 3, 19, 3, 19, 5, 19, 191, 10, 19, 3, 20, 3, 20, 3, 20, 5, 20, 196, 10, 20, 3, 21, 3, 21, 3, 22, 3, 22, 5, 22, 202, 10, 22, 3, 23, 3, 23, 3, 23, 2, 3, 30, 24, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 2, 8, 3, 2, 16, 17, 3, 2, 18, 19, 3, 2, 20, 21, 3, 2, 22, 24, 3, 2, 25, 33, 3, 2, 35, 40, 2, 203, 2, 47, 3, 2, 2, 2, 4, 51, 3, 2, 2, 2, 6, 54, 3, 2, 2, 2, 8, 58, 3, 2, 2, 2, 10, 62, 3, 2, 2, 2, 12, 84, 3, 2, 2, 2, 14, 86, 3, 2, 2, 2, 16, 89, 3, 2, 2, 2, 18, 97, 3, 2, 2, 2, 20, 103, 3, 2, 2, 2, 22, 106, 3, 2, 2, 2, 24, 137, 3, 2, 2, 2, 26, 139, 3, 2, 2, 2, 28, 153, 3, 2, 2, 2, 30, 155, 3, 2, 2, 2, 32, 182, 3, 2, 2, 2, 34, 184, 3, 2, 2, 2, 36, 190, 3, 2, 2, 2, 38, 195, 3, 2, 2, 2, 40, 197, 3, 2, 2, 2, 42, 199, 3, 2, 2, 2, 44, 203, 3, 2, 2, 2, 46, 48, 5, 4, 3, 2, 47, 46, 3, 2, 2, 2, 48, 49, 3, 2, 2, 2, 49, 47, 3, 2, 2, 2, 49, 50, 3, 2, 2, 2, 50, 3, 3, 2, 2, 2, 51, 52, 5, 6, 4, 2, 52, 53, 5, 10, 6, 2, 53, 5, 3, 2, 2, 2, 54, 55, 5, 34, 18, 2, 55, 56, 7, 44, 2, 2, 56, 57, 5, 8, 5, 2, 57, 7, 3, 2, 2, 2, 58, 59, 7, 3, 2, 2, 59, 60, 5, 12, 7, 2, 60, 61, 7, 4, 2, 2, 61, 9, 3, 2, 2, 2, 62, 66, 7, 5, 2, 2, 63, 65, 5, 14, 8, 2, 64, 63, 3, 2, 2, 2, 65, 68, 3, 2, 2, 2, 66, 64, 3, 2, 2, 2, 66, 67, 3, 2, 2, 2, 67, 69, 3, 2, 2, 2, 68, 66, 3, 2, 2, 2, 69, 71, 5, 20, 11, 2, 70, 72, 5, 26, 14, 2, 71, 70, 3, 2, 2, 2, 71, 72, 3, 2, 2, 2, 72, 73, 3, 2, 2, 2, 73, 74, 7, 6, 2, 2, 74, 11, 3, 2, 2, 2, 75, 80, 5, 18, 10, 2, 76, 77, 7, 7, 2, 2, 77, 79, 5, 18, 10, 2, 78, 76, 3, 2, 2, 2, 79, 82, 3, 2, 2, 2, 80, 78, 3, 2, 2, 2, 80, 81, 3, 2, 2, 2, 81, 85, 3, 2, 2, 2, 82, 80, 3, 2, 2, 2, 83, 85, 3, 2, 2, 2, 84, 75, 3, 2, 2, 2, 84, 83, 3, 2, 2, 2, 85, 13, 3, 2, 2, 2, 86, 87, 5, 16, 9, 2, 87, 88, 7, 8, 2, 2, 88, 15, 3, 2, 2, 2, 89, 94, 5, 18, 10, 2, 90, 91, 7, 7, 2, 2, 91, 93, 7, 44, 2, 2, 92, 90, 3, 2, 2, 2, 93, 96, 3, 2, 2, 2, 94, 92, 3, 2, 2, 2, 94, 95, 3, 2, 2, 2, 95, 17, 3, 2, 2, 2, 96, 94, 3, 2, 2, 2, 97, 98, 5, 34, 18, 2, 98, 99, 7, 44, 2, 2, 99, 19, 3, 2, 2, 2, 100, 102, 5, 24, 13, 2, 101, 100, 3, 2, 2, 2, 102, 105, 3, 2, 2, 2, 103, 101, 3, 2, 2, 2, 103, 104, 3, 2, 2, 2, 104, 21, 3, 2, 2, 2, 105, 103, 3, 2, 2, 2, 106, 107, 5, 32, 17, 2, 107, 108, 5, 44, 23, 2, 108, 109, 5, 32, 17, 2, 109, 23, 3, 2, 2, 2, 110, 111, 5, 28, 15, 2, 111, 112, 7, 8, 2, 2, 112, 138, 3, 2, 2, 2, 113, 114, 7, 9, 2, 2, 114, 115, 7, 3, 2, 2, 115, 116, 5, 28, 15, 2, 116, 117, 7, 8, 2, 2, 117, 118, 5, 22, 12, 2, 118, 119, 7, 8, 2, 2, 119, 120, 5, 28, 15, 2, 120, 121, 7, 4, 2, 2, 121, 122, 7, 5, 2, 2, 122, 123, 5, 20, 11, 2, 123, 124, 7, 6, 2, 2, 124, 138, 3, 2, 2, 2, 125, 126, 7, 10, 2, 2, 126, 127, 7, 3, 2, 2, 127, 128, 5, 22, 12, 2, 128, 129, 7, 4, 2, 2, 129, 130, 7, 5, 2, 2, 130, 131, 5, 20, 11, 2, 131, 132, 7, 6, 2, 2, 132, 133, 7, 11, 2, 2, 133, 134, 7, 5, 2, 2, 134, 135, 5, 20, 11, 2, 135, 136, 7, 6, 2, 2, 136, 138, 3, 2, 2, 2, 137, 110, 3, 2, 2, 2, 137, 113, 3, 2, 2, 2, 137, 125, 3, 2, 2, 2, 138, 25, 3, 2, 2, 2, 139, 140, 7, 12, 2, 2, 140, 141, 5, 30, 16, 2, 141, 142, 7, 8, 2, 2, 142, 27, 3, 2, 2, 2, 143, 144, 7, 44, 2, 2, 144, 145, 7, 13, 2, 2, 145, 154, 5, 30, 16, 2, 146, 147, 7, 44, 2, 2, 147, 148, 7, 14, 2, 2, 148, 149, 5, 30, 16, 2, 149, 150, 7, 15, 2, 2, 150, 151, 7, 13, 2, 2, 151, 152, 5, 30, 16, 2, 152, 154, 3, 2, 2, 2, 153, 143, 3, 2, 2, 2, 153, 146, 3, 2, 2, 2, 154, 29, 3, 2, 2, 2, 155, 156, 8, 16, 1, 2, 156, 157, 5, 32, 17, 2, 157, 172, 3, 2, 2, 2, 158, 159, 12, 7, 2, 2, 159, 160, 9, 2, 2, 2, 160, 171, 5, 30, 16, 8, 161, 162, 12, 6, 2, 2, 162, 163, 9, 3, 2, 2, 163, 171, 5, 30, 16, 7, 164, 165, 12, 5, 2, 2, 165, 166, 9, 4, 2, 2, 166, 171, 5, 30, 16, 6, 167, 168, 12, 4, 2, 2, 168, 169, 9, 5, 2, 2, 169, 171, 5, 30, 16, 5, 170, 158, 3, 2, 2, 2, 170, 161, 3, 2, 2, 2, 170, 164, 3, 2, 2, 2, 170, 167, 3, 2, 2, 2, 171, 174, 3, 2, 2, 2, 172, 170, 3, 2, 2, 2, 172, 173, 3, 2, 2, 2, 173, 31, 3, 2, 2, 2, 174, 172, 3, 2, 2, 2, 175, 176, 7, 44, 2, 2, 176, 177, 7, 14, 2, 2, 177, 178, 5, 30, 16, 2, 178, 179, 7, 15, 2, 2, 179, 183, 3, 2, 2, 2, 180, 183, 5, 38, 20, 2, 181, 183, 7, 44, 2, 2, 182, 175, 3, 2, 2, 2, 182, 180, 3, 2, 2, 2, 182, 181, 3, 2, 2, 2, 183, 33, 3, 2, 2, 2, 184, 185, 5, 42, 22, 2, 185, 186, 5, 36, 19, 2, 186, 187, 5, 36, 19, 2, 187, 35, 3, 2, 2, 2, 188, 191, 7, 42, 2, 2, 189, 191, 5, 40, 21, 2, 190, 188, 3, 2, 2, 2, 190, 189, 3, 2, 2, 2, 191, 37, 3, 2, 2, 2, 192, 196, 7, 42, 2, 2, 193, 196, 7, 41, 2, 2, 194, 196, 5, 40, 21, 2, 195, 192, 3, 2, 2, 2, 195, 193, 3, 2, 2, 2, 195, 194, 3, 2, 2, 2, 196, 39, 3, 2, 2, 2, 197, 198, 7, 45, 2, 2, 198, 41, 3, 2, 2, 2, 199, 201, 9, 6, 2, 2, 200, 202, 7, 34, 2, 2, 201, 200, 3, 2, 2, 2, 201, 202, 3, 2, 2, 2, 202, 43, 3, 2, 2, 2, 203, 204, 9, 7, 2, 2, 204, 45, 3, 2, 2, 2, 17, 49, 66, 71, 80, 84, 94, 103, 137, 153, 170, 172, 182, 190, 195, 201] \ No newline at end of file diff --git a/HybroLang/HybroLang.tokens b/HybroLang/HybroLang.tokens new file mode 100644 index 0000000..574a34a --- /dev/null +++ b/HybroLang/HybroLang.tokens @@ -0,0 +1,84 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +T__7=8 +T__8=9 +T__9=10 +T__10=11 +T__11=12 +T__12=13 +T__13=14 +T__14=15 +T__15=16 +T__16=17 +T__17=18 +T__18=19 +T__19=20 +T__20=21 +T__21=22 +T__22=23 +T__23=24 +T__24=25 +T__25=26 +T__26=27 +T__27=28 +T__28=29 +T__29=30 +T__30=31 +T__31=32 +T__32=33 +T__33=34 +T__34=35 +T__35=36 +T__36=37 +T__37=38 +DecimalFloatingConstant=39 +IntegerConstant=40 +DecimalConstant=41 +Name=42 +INLINE=43 +WhiteSpace=44 +LineComment=45 +NewLine=46 +'('=1 +')'=2 +'{'=3 +'}'=4 +','=5 +';'=6 +'for'=7 +'if'=8 +'else'=9 +'return'=10 +'='=11 +'['=12 +']'=13 +'*'=14 +'/'=15 +'+'=16 +'-'=17 +'<<'=18 +'>>'=19 +'&'=20 +'|'=21 +'^'=22 +'int'=23 +'uint'=24 +'sint'=25 +'suint'=26 +'flt'=27 +'cpl'=28 +'pix'=29 +'ipv4'=30 +'ipv6'=31 +'[]'=32 +'=='=33 +'!='=34 +'<'=35 +'>'=36 +'<='=37 +'>='=38 diff --git a/HybroLang/HybroLangLexer.interp b/HybroLang/HybroLangLexer.interp new file mode 100644 index 0000000..49e7b7c --- /dev/null +++ b/HybroLang/HybroLangLexer.interp @@ -0,0 +1,162 @@ +token literal names: +null +'(' +')' +'{' +'}' +',' +';' +'for' +'if' +'else' +'return' +'=' +'[' +']' +'*' +'/' +'+' +'-' +'<<' +'>>' +'&' +'|' +'^' +'int' +'uint' +'sint' +'suint' +'flt' +'cpl' +'pix' +'ipv4' +'ipv6' +'[]' +'==' +'!=' +'<' +'>' +'<=' +'>=' +null +null +null +null +null +null +null +null + +token symbolic names: +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +null +DecimalFloatingConstant +IntegerConstant +DecimalConstant +Name +INLINE +WhiteSpace +LineComment +NewLine + +rule names: +T__0 +T__1 +T__2 +T__3 +T__4 +T__5 +T__6 +T__7 +T__8 +T__9 +T__10 +T__11 +T__12 +T__13 +T__14 +T__15 +T__16 +T__17 +T__18 +T__19 +T__20 +T__21 +T__22 +T__23 +T__24 +T__25 +T__26 +T__27 +T__28 +T__29 +T__30 +T__31 +T__32 +T__33 +T__34 +T__35 +T__36 +T__37 +DecimalFloatingConstant +ExponentPart +FloatingSuffix +FractionalConstant +IntegerConstant +DecimalConstant +DigitSequence +Digit +NonzeroDigit +Sign +Name +INLINE +WhiteSpace +LineComment +NewLine + +channel names: +DEFAULT_TOKEN_CHANNEL +HIDDEN + +mode names: +DEFAULT_MODE + +atn: +[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 48, 322, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 4, 21, 9, 21, 4, 22, 9, 22, 4, 23, 9, 23, 4, 24, 9, 24, 4, 25, 9, 25, 4, 26, 9, 26, 4, 27, 9, 27, 4, 28, 9, 28, 4, 29, 9, 29, 4, 30, 9, 30, 4, 31, 9, 31, 4, 32, 9, 32, 4, 33, 9, 33, 4, 34, 9, 34, 4, 35, 9, 35, 4, 36, 9, 36, 4, 37, 9, 37, 4, 38, 9, 38, 4, 39, 9, 39, 4, 40, 9, 40, 4, 41, 9, 41, 4, 42, 9, 42, 4, 43, 9, 43, 4, 44, 9, 44, 4, 45, 9, 45, 4, 46, 9, 46, 4, 47, 9, 47, 4, 48, 9, 48, 4, 49, 9, 49, 4, 50, 9, 50, 4, 51, 9, 51, 4, 52, 9, 52, 4, 53, 9, 53, 4, 54, 9, 54, 3, 2, 3, 2, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 8, 3, 8, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 12, 3, 12, 3, 13, 3, 13, 3, 14, 3, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 3, 19, 3, 20, 3, 20, 3, 20, 3, 21, 3, 21, 3, 22, 3, 22, 3, 23, 3, 23, 3, 24, 3, 24, 3, 24, 3, 24, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 28, 3, 28, 3, 28, 3, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 30, 3, 30, 3, 30, 3, 30, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 33, 3, 33, 3, 33, 3, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 35, 3, 36, 3, 36, 3, 37, 3, 37, 3, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 39, 3, 40, 3, 40, 5, 40, 230, 10, 40, 3, 40, 5, 40, 233, 10, 40, 3, 41, 3, 41, 5, 41, 237, 10, 41, 3, 41, 3, 41, 3, 41, 5, 41, 242, 10, 41, 3, 41, 5, 41, 245, 10, 41, 3, 42, 3, 42, 3, 43, 5, 43, 250, 10, 43, 3, 43, 3, 43, 3, 43, 3, 43, 3, 43, 5, 43, 257, 10, 43, 3, 44, 3, 44, 3, 45, 3, 45, 7, 45, 263, 10, 45, 12, 45, 14, 45, 266, 11, 45, 3, 46, 6, 46, 269, 10, 46, 13, 46, 14, 46, 270, 3, 47, 3, 47, 3, 48, 3, 48, 3, 49, 3, 49, 3, 50, 3, 50, 7, 50, 281, 10, 50, 12, 50, 14, 50, 284, 11, 50, 3, 51, 3, 51, 3, 51, 3, 51, 6, 51, 290, 10, 51, 13, 51, 14, 51, 291, 3, 51, 3, 51, 3, 52, 6, 52, 297, 10, 52, 13, 52, 14, 52, 298, 3, 52, 3, 52, 3, 53, 3, 53, 3, 53, 3, 53, 7, 53, 307, 10, 53, 12, 53, 14, 53, 310, 11, 53, 3, 53, 3, 53, 3, 53, 3, 53, 3, 54, 5, 54, 317, 10, 54, 3, 54, 3, 54, 3, 54, 3, 54, 3, 308, 2, 55, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 27, 15, 29, 16, 31, 17, 33, 18, 35, 19, 37, 20, 39, 21, 41, 22, 43, 23, 45, 24, 47, 25, 49, 26, 51, 27, 53, 28, 55, 29, 57, 30, 59, 31, 61, 32, 63, 33, 65, 34, 67, 35, 69, 36, 71, 37, 73, 38, 75, 39, 77, 40, 79, 41, 81, 2, 83, 2, 85, 2, 87, 42, 89, 43, 91, 2, 93, 2, 95, 2, 97, 2, 99, 44, 101, 45, 103, 46, 105, 47, 107, 48, 3, 2, 10, 6, 2, 72, 72, 78, 78, 104, 104, 110, 110, 3, 2, 50, 59, 3, 2, 51, 59, 4, 2, 45, 45, 47, 47, 4, 2, 67, 92, 99, 124, 6, 2, 50, 59, 67, 92, 97, 97, 99, 124, 3, 2, 43, 43, 4, 2, 11, 11, 34, 34, 2, 328, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 2, 27, 3, 2, 2, 2, 2, 29, 3, 2, 2, 2, 2, 31, 3, 2, 2, 2, 2, 33, 3, 2, 2, 2, 2, 35, 3, 2, 2, 2, 2, 37, 3, 2, 2, 2, 2, 39, 3, 2, 2, 2, 2, 41, 3, 2, 2, 2, 2, 43, 3, 2, 2, 2, 2, 45, 3, 2, 2, 2, 2, 47, 3, 2, 2, 2, 2, 49, 3, 2, 2, 2, 2, 51, 3, 2, 2, 2, 2, 53, 3, 2, 2, 2, 2, 55, 3, 2, 2, 2, 2, 57, 3, 2, 2, 2, 2, 59, 3, 2, 2, 2, 2, 61, 3, 2, 2, 2, 2, 63, 3, 2, 2, 2, 2, 65, 3, 2, 2, 2, 2, 67, 3, 2, 2, 2, 2, 69, 3, 2, 2, 2, 2, 71, 3, 2, 2, 2, 2, 73, 3, 2, 2, 2, 2, 75, 3, 2, 2, 2, 2, 77, 3, 2, 2, 2, 2, 79, 3, 2, 2, 2, 2, 87, 3, 2, 2, 2, 2, 89, 3, 2, 2, 2, 2, 99, 3, 2, 2, 2, 2, 101, 3, 2, 2, 2, 2, 103, 3, 2, 2, 2, 2, 105, 3, 2, 2, 2, 2, 107, 3, 2, 2, 2, 3, 109, 3, 2, 2, 2, 5, 111, 3, 2, 2, 2, 7, 113, 3, 2, 2, 2, 9, 115, 3, 2, 2, 2, 11, 117, 3, 2, 2, 2, 13, 119, 3, 2, 2, 2, 15, 121, 3, 2, 2, 2, 17, 125, 3, 2, 2, 2, 19, 128, 3, 2, 2, 2, 21, 133, 3, 2, 2, 2, 23, 140, 3, 2, 2, 2, 25, 142, 3, 2, 2, 2, 27, 144, 3, 2, 2, 2, 29, 146, 3, 2, 2, 2, 31, 148, 3, 2, 2, 2, 33, 150, 3, 2, 2, 2, 35, 152, 3, 2, 2, 2, 37, 154, 3, 2, 2, 2, 39, 157, 3, 2, 2, 2, 41, 160, 3, 2, 2, 2, 43, 162, 3, 2, 2, 2, 45, 164, 3, 2, 2, 2, 47, 166, 3, 2, 2, 2, 49, 170, 3, 2, 2, 2, 51, 175, 3, 2, 2, 2, 53, 180, 3, 2, 2, 2, 55, 186, 3, 2, 2, 2, 57, 190, 3, 2, 2, 2, 59, 194, 3, 2, 2, 2, 61, 198, 3, 2, 2, 2, 63, 203, 3, 2, 2, 2, 65, 208, 3, 2, 2, 2, 67, 211, 3, 2, 2, 2, 69, 214, 3, 2, 2, 2, 71, 217, 3, 2, 2, 2, 73, 219, 3, 2, 2, 2, 75, 221, 3, 2, 2, 2, 77, 224, 3, 2, 2, 2, 79, 227, 3, 2, 2, 2, 81, 244, 3, 2, 2, 2, 83, 246, 3, 2, 2, 2, 85, 256, 3, 2, 2, 2, 87, 258, 3, 2, 2, 2, 89, 260, 3, 2, 2, 2, 91, 268, 3, 2, 2, 2, 93, 272, 3, 2, 2, 2, 95, 274, 3, 2, 2, 2, 97, 276, 3, 2, 2, 2, 99, 278, 3, 2, 2, 2, 101, 285, 3, 2, 2, 2, 103, 296, 3, 2, 2, 2, 105, 302, 3, 2, 2, 2, 107, 316, 3, 2, 2, 2, 109, 110, 7, 42, 2, 2, 110, 4, 3, 2, 2, 2, 111, 112, 7, 43, 2, 2, 112, 6, 3, 2, 2, 2, 113, 114, 7, 125, 2, 2, 114, 8, 3, 2, 2, 2, 115, 116, 7, 127, 2, 2, 116, 10, 3, 2, 2, 2, 117, 118, 7, 46, 2, 2, 118, 12, 3, 2, 2, 2, 119, 120, 7, 61, 2, 2, 120, 14, 3, 2, 2, 2, 121, 122, 7, 104, 2, 2, 122, 123, 7, 113, 2, 2, 123, 124, 7, 116, 2, 2, 124, 16, 3, 2, 2, 2, 125, 126, 7, 107, 2, 2, 126, 127, 7, 104, 2, 2, 127, 18, 3, 2, 2, 2, 128, 129, 7, 103, 2, 2, 129, 130, 7, 110, 2, 2, 130, 131, 7, 117, 2, 2, 131, 132, 7, 103, 2, 2, 132, 20, 3, 2, 2, 2, 133, 134, 7, 116, 2, 2, 134, 135, 7, 103, 2, 2, 135, 136, 7, 118, 2, 2, 136, 137, 7, 119, 2, 2, 137, 138, 7, 116, 2, 2, 138, 139, 7, 112, 2, 2, 139, 22, 3, 2, 2, 2, 140, 141, 7, 63, 2, 2, 141, 24, 3, 2, 2, 2, 142, 143, 7, 93, 2, 2, 143, 26, 3, 2, 2, 2, 144, 145, 7, 95, 2, 2, 145, 28, 3, 2, 2, 2, 146, 147, 7, 44, 2, 2, 147, 30, 3, 2, 2, 2, 148, 149, 7, 49, 2, 2, 149, 32, 3, 2, 2, 2, 150, 151, 7, 45, 2, 2, 151, 34, 3, 2, 2, 2, 152, 153, 7, 47, 2, 2, 153, 36, 3, 2, 2, 2, 154, 155, 7, 62, 2, 2, 155, 156, 7, 62, 2, 2, 156, 38, 3, 2, 2, 2, 157, 158, 7, 64, 2, 2, 158, 159, 7, 64, 2, 2, 159, 40, 3, 2, 2, 2, 160, 161, 7, 40, 2, 2, 161, 42, 3, 2, 2, 2, 162, 163, 7, 126, 2, 2, 163, 44, 3, 2, 2, 2, 164, 165, 7, 96, 2, 2, 165, 46, 3, 2, 2, 2, 166, 167, 7, 107, 2, 2, 167, 168, 7, 112, 2, 2, 168, 169, 7, 118, 2, 2, 169, 48, 3, 2, 2, 2, 170, 171, 7, 119, 2, 2, 171, 172, 7, 107, 2, 2, 172, 173, 7, 112, 2, 2, 173, 174, 7, 118, 2, 2, 174, 50, 3, 2, 2, 2, 175, 176, 7, 117, 2, 2, 176, 177, 7, 107, 2, 2, 177, 178, 7, 112, 2, 2, 178, 179, 7, 118, 2, 2, 179, 52, 3, 2, 2, 2, 180, 181, 7, 117, 2, 2, 181, 182, 7, 119, 2, 2, 182, 183, 7, 107, 2, 2, 183, 184, 7, 112, 2, 2, 184, 185, 7, 118, 2, 2, 185, 54, 3, 2, 2, 2, 186, 187, 7, 104, 2, 2, 187, 188, 7, 110, 2, 2, 188, 189, 7, 118, 2, 2, 189, 56, 3, 2, 2, 2, 190, 191, 7, 101, 2, 2, 191, 192, 7, 114, 2, 2, 192, 193, 7, 110, 2, 2, 193, 58, 3, 2, 2, 2, 194, 195, 7, 114, 2, 2, 195, 196, 7, 107, 2, 2, 196, 197, 7, 122, 2, 2, 197, 60, 3, 2, 2, 2, 198, 199, 7, 107, 2, 2, 199, 200, 7, 114, 2, 2, 200, 201, 7, 120, 2, 2, 201, 202, 7, 54, 2, 2, 202, 62, 3, 2, 2, 2, 203, 204, 7, 107, 2, 2, 204, 205, 7, 114, 2, 2, 205, 206, 7, 120, 2, 2, 206, 207, 7, 56, 2, 2, 207, 64, 3, 2, 2, 2, 208, 209, 7, 93, 2, 2, 209, 210, 7, 95, 2, 2, 210, 66, 3, 2, 2, 2, 211, 212, 7, 63, 2, 2, 212, 213, 7, 63, 2, 2, 213, 68, 3, 2, 2, 2, 214, 215, 7, 35, 2, 2, 215, 216, 7, 63, 2, 2, 216, 70, 3, 2, 2, 2, 217, 218, 7, 62, 2, 2, 218, 72, 3, 2, 2, 2, 219, 220, 7, 64, 2, 2, 220, 74, 3, 2, 2, 2, 221, 222, 7, 62, 2, 2, 222, 223, 7, 63, 2, 2, 223, 76, 3, 2, 2, 2, 224, 225, 7, 64, 2, 2, 225, 226, 7, 63, 2, 2, 226, 78, 3, 2, 2, 2, 227, 229, 5, 85, 43, 2, 228, 230, 5, 81, 41, 2, 229, 228, 3, 2, 2, 2, 229, 230, 3, 2, 2, 2, 230, 232, 3, 2, 2, 2, 231, 233, 5, 83, 42, 2, 232, 231, 3, 2, 2, 2, 232, 233, 3, 2, 2, 2, 233, 80, 3, 2, 2, 2, 234, 236, 7, 103, 2, 2, 235, 237, 5, 97, 49, 2, 236, 235, 3, 2, 2, 2, 236, 237, 3, 2, 2, 2, 237, 238, 3, 2, 2, 2, 238, 245, 5, 91, 46, 2, 239, 241, 7, 71, 2, 2, 240, 242, 5, 97, 49, 2, 241, 240, 3, 2, 2, 2, 241, 242, 3, 2, 2, 2, 242, 243, 3, 2, 2, 2, 243, 245, 5, 91, 46, 2, 244, 234, 3, 2, 2, 2, 244, 239, 3, 2, 2, 2, 245, 82, 3, 2, 2, 2, 246, 247, 9, 2, 2, 2, 247, 84, 3, 2, 2, 2, 248, 250, 5, 91, 46, 2, 249, 248, 3, 2, 2, 2, 249, 250, 3, 2, 2, 2, 250, 251, 3, 2, 2, 2, 251, 252, 7, 48, 2, 2, 252, 257, 5, 91, 46, 2, 253, 254, 5, 91, 46, 2, 254, 255, 7, 48, 2, 2, 255, 257, 3, 2, 2, 2, 256, 249, 3, 2, 2, 2, 256, 253, 3, 2, 2, 2, 257, 86, 3, 2, 2, 2, 258, 259, 5, 91, 46, 2, 259, 88, 3, 2, 2, 2, 260, 264, 5, 95, 48, 2, 261, 263, 5, 93, 47, 2, 262, 261, 3, 2, 2, 2, 263, 266, 3, 2, 2, 2, 264, 262, 3, 2, 2, 2, 264, 265, 3, 2, 2, 2, 265, 90, 3, 2, 2, 2, 266, 264, 3, 2, 2, 2, 267, 269, 5, 93, 47, 2, 268, 267, 3, 2, 2, 2, 269, 270, 3, 2, 2, 2, 270, 268, 3, 2, 2, 2, 270, 271, 3, 2, 2, 2, 271, 92, 3, 2, 2, 2, 272, 273, 9, 3, 2, 2, 273, 94, 3, 2, 2, 2, 274, 275, 9, 4, 2, 2, 275, 96, 3, 2, 2, 2, 276, 277, 9, 5, 2, 2, 277, 98, 3, 2, 2, 2, 278, 282, 9, 6, 2, 2, 279, 281, 9, 7, 2, 2, 280, 279, 3, 2, 2, 2, 281, 284, 3, 2, 2, 2, 282, 280, 3, 2, 2, 2, 282, 283, 3, 2, 2, 2, 283, 100, 3, 2, 2, 2, 284, 282, 3, 2, 2, 2, 285, 286, 7, 37, 2, 2, 286, 287, 7, 42, 2, 2, 287, 289, 3, 2, 2, 2, 288, 290, 10, 8, 2, 2, 289, 288, 3, 2, 2, 2, 290, 291, 3, 2, 2, 2, 291, 289, 3, 2, 2, 2, 291, 292, 3, 2, 2, 2, 292, 293, 3, 2, 2, 2, 293, 294, 7, 43, 2, 2, 294, 102, 3, 2, 2, 2, 295, 297, 9, 9, 2, 2, 296, 295, 3, 2, 2, 2, 297, 298, 3, 2, 2, 2, 298, 296, 3, 2, 2, 2, 298, 299, 3, 2, 2, 2, 299, 300, 3, 2, 2, 2, 300, 301, 8, 52, 2, 2, 301, 104, 3, 2, 2, 2, 302, 303, 7, 49, 2, 2, 303, 304, 7, 49, 2, 2, 304, 308, 3, 2, 2, 2, 305, 307, 11, 2, 2, 2, 306, 305, 3, 2, 2, 2, 307, 310, 3, 2, 2, 2, 308, 309, 3, 2, 2, 2, 308, 306, 3, 2, 2, 2, 309, 311, 3, 2, 2, 2, 310, 308, 3, 2, 2, 2, 311, 312, 5, 107, 54, 2, 312, 313, 3, 2, 2, 2, 313, 314, 8, 53, 2, 2, 314, 106, 3, 2, 2, 2, 315, 317, 7, 15, 2, 2, 316, 315, 3, 2, 2, 2, 316, 317, 3, 2, 2, 2, 317, 318, 3, 2, 2, 2, 318, 319, 7, 12, 2, 2, 319, 320, 3, 2, 2, 2, 320, 321, 8, 54, 2, 2, 321, 108, 3, 2, 2, 2, 17, 2, 229, 232, 236, 241, 244, 249, 256, 264, 270, 282, 291, 298, 308, 316, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroLang/HybroLangLexer.py b/HybroLang/HybroLangLexer.py new file mode 100644 index 0000000..e628c3e --- /dev/null +++ b/HybroLang/HybroLangLexer.py @@ -0,0 +1,240 @@ +# Generated from HybroLang.g4 by ANTLR 4.9.2 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\60") + buf.write("\u0142\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7") + buf.write("\t\7\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r") + buf.write("\4\16\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23") + buf.write("\t\23\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4\30\t\30") + buf.write("\4\31\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35\t\35\4\36") + buf.write("\t\36\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4$\t$\4%\t%") + buf.write("\4&\t&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t,\4-\t-\4.") + buf.write("\t.\4/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63\t\63\4\64") + buf.write("\t\64\4\65\t\65\4\66\t\66\3\2\3\2\3\3\3\3\3\4\3\4\3\5") + buf.write("\3\5\3\6\3\6\3\7\3\7\3\b\3\b\3\b\3\b\3\t\3\t\3\t\3\n\3") + buf.write("\n\3\n\3\n\3\n\3\13\3\13\3\13\3\13\3\13\3\13\3\13\3\f") + buf.write("\3\f\3\r\3\r\3\16\3\16\3\17\3\17\3\20\3\20\3\21\3\21\3") + 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buf.write("\u012c\3\2\2\2\u012c\u012d\b\64\2\2\u012dh\3\2\2\2\u012e") + buf.write("\u012f\7\61\2\2\u012f\u0130\7\61\2\2\u0130\u0134\3\2\2") + buf.write("\2\u0131\u0133\13\2\2\2\u0132\u0131\3\2\2\2\u0133\u0136") + buf.write("\3\2\2\2\u0134\u0135\3\2\2\2\u0134\u0132\3\2\2\2\u0135") + buf.write("\u0137\3\2\2\2\u0136\u0134\3\2\2\2\u0137\u0138\5k\66\2") + buf.write("\u0138\u0139\3\2\2\2\u0139\u013a\b\65\2\2\u013aj\3\2\2") + buf.write("\2\u013b\u013d\7\17\2\2\u013c\u013b\3\2\2\2\u013c\u013d") + buf.write("\3\2\2\2\u013d\u013e\3\2\2\2\u013e\u013f\7\f\2\2\u013f") + buf.write("\u0140\3\2\2\2\u0140\u0141\b\66\2\2\u0141l\3\2\2\2\21") + buf.write("\2\u00e5\u00e8\u00ec\u00f1\u00f4\u00f9\u0100\u0108\u010e") + buf.write("\u011a\u0123\u012a\u0134\u013c\3\b\2\2") + return buf.getvalue() + + +class HybroLangLexer(Lexer): + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + T__0 = 1 + T__1 = 2 + T__2 = 3 + T__3 = 4 + T__4 = 5 + T__5 = 6 + T__6 = 7 + T__7 = 8 + T__8 = 9 + T__9 = 10 + T__10 = 11 + T__11 = 12 + T__12 = 13 + T__13 = 14 + T__14 = 15 + T__15 = 16 + T__16 = 17 + T__17 = 18 + T__18 = 19 + T__19 = 20 + T__20 = 21 + T__21 = 22 + T__22 = 23 + T__23 = 24 + T__24 = 25 + T__25 = 26 + T__26 = 27 + T__27 = 28 + T__28 = 29 + T__29 = 30 + T__30 = 31 + T__31 = 32 + T__32 = 33 + T__33 = 34 + T__34 = 35 + T__35 = 36 + T__36 = 37 + T__37 = 38 + DecimalFloatingConstant = 39 + IntegerConstant = 40 + DecimalConstant = 41 + Name = 42 + INLINE = 43 + WhiteSpace = 44 + LineComment = 45 + NewLine = 46 + + channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] + + modeNames = [ "DEFAULT_MODE" ] + + literalNames = [ "", + "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", + "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", + "'<<'", "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", + "'suint'", "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", + "'=='", "'!='", "'<'", "'>'", "'<='", "'>='" ] + + symbolicNames = [ "", + "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", + "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" ] + + ruleNames = [ "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", + "T__7", "T__8", "T__9", "T__10", "T__11", "T__12", "T__13", + "T__14", "T__15", "T__16", "T__17", "T__18", "T__19", + "T__20", "T__21", "T__22", "T__23", "T__24", "T__25", + "T__26", "T__27", "T__28", "T__29", "T__30", "T__31", + "T__32", "T__33", "T__34", "T__35", "T__36", "T__37", + "DecimalFloatingConstant", "ExponentPart", "FloatingSuffix", + "FractionalConstant", "IntegerConstant", "DecimalConstant", + "DigitSequence", "Digit", "NonzeroDigit", "Sign", "Name", + "INLINE", "WhiteSpace", "LineComment", "NewLine" ] + + grammarFileName = "HybroLang.g4" + + def __init__(self, input=None, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) + self._actions = None + self._predicates = None + + diff --git a/HybroLang/HybroLangLexer.tokens b/HybroLang/HybroLangLexer.tokens new file mode 100644 index 0000000..574a34a --- /dev/null +++ b/HybroLang/HybroLangLexer.tokens @@ -0,0 +1,84 @@ +T__0=1 +T__1=2 +T__2=3 +T__3=4 +T__4=5 +T__5=6 +T__6=7 +T__7=8 +T__8=9 +T__9=10 +T__10=11 +T__11=12 +T__12=13 +T__13=14 +T__14=15 +T__15=16 +T__16=17 +T__17=18 +T__18=19 +T__19=20 +T__20=21 +T__21=22 +T__22=23 +T__23=24 +T__24=25 +T__25=26 +T__26=27 +T__27=28 +T__28=29 +T__29=30 +T__30=31 +T__31=32 +T__32=33 +T__33=34 +T__34=35 +T__35=36 +T__36=37 +T__37=38 +DecimalFloatingConstant=39 +IntegerConstant=40 +DecimalConstant=41 +Name=42 +INLINE=43 +WhiteSpace=44 +LineComment=45 +NewLine=46 +'('=1 +')'=2 +'{'=3 +'}'=4 +','=5 +';'=6 +'for'=7 +'if'=8 +'else'=9 +'return'=10 +'='=11 +'['=12 +']'=13 +'*'=14 +'/'=15 +'+'=16 +'-'=17 +'<<'=18 +'>>'=19 +'&'=20 +'|'=21 +'^'=22 +'int'=23 +'uint'=24 +'sint'=25 +'suint'=26 +'flt'=27 +'cpl'=28 +'pix'=29 +'ipv4'=30 +'ipv6'=31 +'[]'=32 +'=='=33 +'!='=34 +'<'=35 +'>'=36 +'<='=37 +'>='=38 diff --git a/HybroLang/HybroLangParser.py b/HybroLang/HybroLangParser.py new file mode 100644 index 0000000..9a40ce4 --- /dev/null +++ b/HybroLang/HybroLangParser.py @@ -0,0 +1,1602 @@ +# Generated from HybroLang.g4 by ANTLR 4.9.2 +# encoding: utf-8 +from antlr4 import * +from io import StringIO +import sys +if sys.version_info[1] > 5: + from typing import TextIO +else: + from typing.io import TextIO + +def serializedATN(): + with StringIO() as buf: + buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\60") + buf.write("\u00ce\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") + buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") + buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23") + buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\3\2\6\2\60\n") + buf.write("\2\r\2\16\2\61\3\3\3\3\3\3\3\4\3\4\3\4\3\4\3\5\3\5\3\5") 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buf.write("\3\2\2\2\u00aa\u00a1\3\2\2\2\u00aa\u00a4\3\2\2\2\u00aa") + buf.write("\u00a7\3\2\2\2\u00ab\u00ae\3\2\2\2\u00ac\u00aa\3\2\2\2") + buf.write("\u00ac\u00ad\3\2\2\2\u00ad\37\3\2\2\2\u00ae\u00ac\3\2") + buf.write("\2\2\u00af\u00b0\7,\2\2\u00b0\u00b1\7\16\2\2\u00b1\u00b2") + buf.write("\5\36\20\2\u00b2\u00b3\7\17\2\2\u00b3\u00b7\3\2\2\2\u00b4") + buf.write("\u00b7\5&\24\2\u00b5\u00b7\7,\2\2\u00b6\u00af\3\2\2\2") + buf.write("\u00b6\u00b4\3\2\2\2\u00b6\u00b5\3\2\2\2\u00b7!\3\2\2") + buf.write("\2\u00b8\u00b9\5*\26\2\u00b9\u00ba\5$\23\2\u00ba\u00bb") + buf.write("\5$\23\2\u00bb#\3\2\2\2\u00bc\u00bf\7*\2\2\u00bd\u00bf") + buf.write("\5(\25\2\u00be\u00bc\3\2\2\2\u00be\u00bd\3\2\2\2\u00bf") + buf.write("%\3\2\2\2\u00c0\u00c4\7*\2\2\u00c1\u00c4\7)\2\2\u00c2") + buf.write("\u00c4\5(\25\2\u00c3\u00c0\3\2\2\2\u00c3\u00c1\3\2\2\2") + buf.write("\u00c3\u00c2\3\2\2\2\u00c4\'\3\2\2\2\u00c5\u00c6\7-\2") + buf.write("\2\u00c6)\3\2\2\2\u00c7\u00c9\t\6\2\2\u00c8\u00ca\7\"") + buf.write("\2\2\u00c9\u00c8\3\2\2\2\u00c9\u00ca\3\2\2\2\u00ca+\3") + buf.write("\2\2\2\u00cb\u00cc\t\7\2\2\u00cc-\3\2\2\2\21\61BGPT^g") + buf.write("\u0089\u0099\u00aa\u00ac\u00b6\u00be\u00c3\u00c9") + return buf.getvalue() + + +class HybroLangParser ( Parser ): + + grammarFileName = "HybroLang.g4" + + atn = ATNDeserializer().deserialize(serializedATN()) + + decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] + + sharedContextCache = PredictionContextCache() + + literalNames = [ "", "'('", "')'", "'{'", "'}'", "','", "';'", + "'for'", "'if'", "'else'", "'return'", "'='", "'['", + "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", "'>>'", + "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", + "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", + "'=='", "'!='", "'<'", "'>'", "'<='", "'>='" ] + + symbolicNames = [ "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "DecimalFloatingConstant", + "IntegerConstant", "DecimalConstant", "Name", "INLINE", + "WhiteSpace", "LineComment", "NewLine" ] + + RULE_compilationunit = 0 + RULE_function = 1 + RULE_fndcl = 2 + RULE_fnprototype = 3 + RULE_fnbody = 4 + RULE_paramdcllist = 5 + RULE_localvardef = 6 + RULE_vardcllist = 7 + RULE_vardcl = 8 + RULE_actionlist = 9 + RULE_condexpr = 10 + RULE_action = 11 + RULE_returnexpr = 12 + RULE_affectexpr = 13 + RULE_unaryexpr = 14 + RULE_varorvalue = 15 + RULE_datatype = 16 + RULE_intconstvalue = 17 + RULE_constvalue = 18 + RULE_constinline = 19 + RULE_typebase = 20 + RULE_condOperator = 21 + + ruleNames = [ "compilationunit", "function", "fndcl", "fnprototype", + "fnbody", "paramdcllist", "localvardef", "vardcllist", + "vardcl", "actionlist", "condexpr", "action", "returnexpr", + "affectexpr", "unaryexpr", "varorvalue", "datatype", + "intconstvalue", "constvalue", "constinline", "typebase", + "condOperator" ] + + EOF = Token.EOF + T__0=1 + T__1=2 + T__2=3 + T__3=4 + T__4=5 + T__5=6 + T__6=7 + T__7=8 + T__8=9 + T__9=10 + T__10=11 + T__11=12 + T__12=13 + T__13=14 + T__14=15 + T__15=16 + T__16=17 + T__17=18 + T__18=19 + T__19=20 + T__20=21 + T__21=22 + T__22=23 + T__23=24 + T__24=25 + T__25=26 + T__26=27 + T__27=28 + T__28=29 + T__29=30 + T__30=31 + T__31=32 + T__32=33 + T__33=34 + T__34=35 + T__35=36 + T__36=37 + T__37=38 + DecimalFloatingConstant=39 + IntegerConstant=40 + DecimalConstant=41 + Name=42 + INLINE=43 + WhiteSpace=44 + LineComment=45 + NewLine=46 + + def __init__(self, input:TokenStream, output:TextIO = sys.stdout): + super().__init__(input, output) + self.checkVersion("4.9.2") + self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) + self._predicates = None + + + + class CompilationunitContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def function(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.FunctionContext) + else: + return self.getTypedRuleContext(HybroLangParser.FunctionContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_compilationunit + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitCompilationunit" ): + return visitor.visitCompilationunit(self) + else: + return visitor.visitChildren(self) + + + + + def compilationunit(self): + + localctx = HybroLangParser.CompilationunitContext(self, self._ctx, self.state) + self.enterRule(localctx, 0, self.RULE_compilationunit) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 45 + self._errHandler.sync(self) + _la = self._input.LA(1) + while True: + self.state = 44 + self.function() + self.state = 47 + self._errHandler.sync(self) + _la = self._input.LA(1) + if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0)): + break + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class FunctionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def fndcl(self): + return self.getTypedRuleContext(HybroLangParser.FndclContext,0) + + + def fnbody(self): + return self.getTypedRuleContext(HybroLangParser.FnbodyContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_function + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitFunction" ): + return visitor.visitFunction(self) + else: + return visitor.visitChildren(self) + + + + + def function(self): + + localctx = HybroLangParser.FunctionContext(self, self._ctx, self.state) + self.enterRule(localctx, 2, self.RULE_function) + try: + self.enterOuterAlt(localctx, 1) + self.state = 49 + self.fndcl() + self.state = 50 + self.fnbody() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class FndclContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def datatype(self): + return self.getTypedRuleContext(HybroLangParser.DatatypeContext,0) + + + def Name(self): + return self.getToken(HybroLangParser.Name, 0) + + def fnprototype(self): + return self.getTypedRuleContext(HybroLangParser.FnprototypeContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_fndcl + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitFndcl" ): + return visitor.visitFndcl(self) + else: + return visitor.visitChildren(self) + + + + + def fndcl(self): + + localctx = HybroLangParser.FndclContext(self, self._ctx, self.state) + self.enterRule(localctx, 4, self.RULE_fndcl) + try: + self.enterOuterAlt(localctx, 1) + self.state = 52 + self.datatype() + self.state = 53 + self.match(HybroLangParser.Name) + self.state = 54 + self.fnprototype() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class FnprototypeContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def paramdcllist(self): + return self.getTypedRuleContext(HybroLangParser.ParamdcllistContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_fnprototype + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitFnprototype" ): + return visitor.visitFnprototype(self) + else: + return visitor.visitChildren(self) + + + + + def fnprototype(self): + + localctx = HybroLangParser.FnprototypeContext(self, self._ctx, self.state) + self.enterRule(localctx, 6, self.RULE_fnprototype) + try: + self.enterOuterAlt(localctx, 1) + self.state = 56 + self.match(HybroLangParser.T__0) + self.state = 57 + self.paramdcllist() + self.state = 58 + self.match(HybroLangParser.T__1) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class FnbodyContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def actionlist(self): + return self.getTypedRuleContext(HybroLangParser.ActionlistContext,0) + + + def localvardef(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.LocalvardefContext) + else: + return self.getTypedRuleContext(HybroLangParser.LocalvardefContext,i) + + + def returnexpr(self): + return self.getTypedRuleContext(HybroLangParser.ReturnexprContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_fnbody + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitFnbody" ): + return visitor.visitFnbody(self) + else: + return visitor.visitChildren(self) + + + + + def fnbody(self): + + localctx = HybroLangParser.FnbodyContext(self, self._ctx, self.state) + self.enterRule(localctx, 8, self.RULE_fnbody) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 60 + self.match(HybroLangParser.T__2) + self.state = 64 + self._errHandler.sync(self) + _la = self._input.LA(1) + while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0): + self.state = 61 + self.localvardef() + self.state = 66 + self._errHandler.sync(self) + _la = self._input.LA(1) + + self.state = 67 + self.actionlist() + self.state = 69 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==HybroLangParser.T__9: + self.state = 68 + self.returnexpr() + + + self.state = 71 + self.match(HybroLangParser.T__3) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ParamdcllistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def vardcl(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.VardclContext) + else: + return self.getTypedRuleContext(HybroLangParser.VardclContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_paramdcllist + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitParamdcllist" ): + return visitor.visitParamdcllist(self) + else: + return visitor.visitChildren(self) + + + + + def paramdcllist(self): + + localctx = HybroLangParser.ParamdcllistContext(self, self._ctx, self.state) + self.enterRule(localctx, 10, self.RULE_paramdcllist) + self._la = 0 # Token type + try: + self.state = 82 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [HybroLangParser.T__22, HybroLangParser.T__23, HybroLangParser.T__24, HybroLangParser.T__25, HybroLangParser.T__26, HybroLangParser.T__27, HybroLangParser.T__28, HybroLangParser.T__29, HybroLangParser.T__30]: + self.enterOuterAlt(localctx, 1) + self.state = 73 + self.vardcl() + self.state = 78 + self._errHandler.sync(self) + _la = self._input.LA(1) + while _la==HybroLangParser.T__4: + self.state = 74 + self.match(HybroLangParser.T__4) + self.state = 75 + self.vardcl() + self.state = 80 + self._errHandler.sync(self) + _la = self._input.LA(1) + + pass + elif token in [HybroLangParser.T__1]: + self.enterOuterAlt(localctx, 2) + + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class LocalvardefContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def vardcllist(self): + return self.getTypedRuleContext(HybroLangParser.VardcllistContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_localvardef + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitLocalvardef" ): + return visitor.visitLocalvardef(self) + else: + return visitor.visitChildren(self) + + + + + def localvardef(self): + + localctx = HybroLangParser.LocalvardefContext(self, self._ctx, self.state) + self.enterRule(localctx, 12, self.RULE_localvardef) + try: + self.enterOuterAlt(localctx, 1) + self.state = 84 + self.vardcllist() + self.state = 85 + self.match(HybroLangParser.T__5) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class VardcllistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def vardcl(self): + return self.getTypedRuleContext(HybroLangParser.VardclContext,0) + + + def Name(self, i:int=None): + if i is None: + return self.getTokens(HybroLangParser.Name) + else: + return self.getToken(HybroLangParser.Name, i) + + def getRuleIndex(self): + return HybroLangParser.RULE_vardcllist + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitVardcllist" ): + return visitor.visitVardcllist(self) + else: + return visitor.visitChildren(self) + + + + + def vardcllist(self): + + localctx = HybroLangParser.VardcllistContext(self, self._ctx, self.state) + self.enterRule(localctx, 14, self.RULE_vardcllist) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 87 + self.vardcl() + self.state = 92 + self._errHandler.sync(self) + _la = self._input.LA(1) + while _la==HybroLangParser.T__4: + self.state = 88 + self.match(HybroLangParser.T__4) + self.state = 89 + self.match(HybroLangParser.Name) + self.state = 94 + self._errHandler.sync(self) + _la = self._input.LA(1) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class VardclContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def datatype(self): + return self.getTypedRuleContext(HybroLangParser.DatatypeContext,0) + + + def Name(self): + return self.getToken(HybroLangParser.Name, 0) + + def getRuleIndex(self): + return HybroLangParser.RULE_vardcl + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitVardcl" ): + return visitor.visitVardcl(self) + else: + return visitor.visitChildren(self) + + + + + def vardcl(self): + + localctx = HybroLangParser.VardclContext(self, self._ctx, self.state) + self.enterRule(localctx, 16, self.RULE_vardcl) + try: + self.enterOuterAlt(localctx, 1) + self.state = 95 + self.datatype() + self.state = 96 + self.match(HybroLangParser.Name) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ActionlistContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def action(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.ActionContext) + else: + return self.getTypedRuleContext(HybroLangParser.ActionContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_actionlist + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitActionlist" ): + return visitor.visitActionlist(self) + else: + return visitor.visitChildren(self) + + + + + def actionlist(self): + + localctx = HybroLangParser.ActionlistContext(self, self._ctx, self.state) + self.enterRule(localctx, 18, self.RULE_actionlist) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 101 + self._errHandler.sync(self) + _la = self._input.LA(1) + while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__6) | (1 << HybroLangParser.T__7) | (1 << HybroLangParser.Name))) != 0): + self.state = 98 + self.action() + self.state = 103 + self._errHandler.sync(self) + _la = self._input.LA(1) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class CondexprContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def varorvalue(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.VarorvalueContext) + else: + return self.getTypedRuleContext(HybroLangParser.VarorvalueContext,i) + + + def condOperator(self): + return self.getTypedRuleContext(HybroLangParser.CondOperatorContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_condexpr + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitCondexpr" ): + return visitor.visitCondexpr(self) + else: + return visitor.visitChildren(self) + + + + + def condexpr(self): + + localctx = HybroLangParser.CondexprContext(self, self._ctx, self.state) + self.enterRule(localctx, 20, self.RULE_condexpr) + try: + self.enterOuterAlt(localctx, 1) + self.state = 104 + self.varorvalue() + self.state = 105 + self.condOperator() + self.state = 106 + self.varorvalue() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ActionContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def affectexpr(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.AffectexprContext) + else: + return self.getTypedRuleContext(HybroLangParser.AffectexprContext,i) + + + def condexpr(self): + return self.getTypedRuleContext(HybroLangParser.CondexprContext,0) + + + def actionlist(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.ActionlistContext) + else: + return self.getTypedRuleContext(HybroLangParser.ActionlistContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_action + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitAction" ): + return visitor.visitAction(self) + else: + return visitor.visitChildren(self) + + + + + def action(self): + + localctx = HybroLangParser.ActionContext(self, self._ctx, self.state) + self.enterRule(localctx, 22, self.RULE_action) + try: + self.state = 135 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [HybroLangParser.Name]: + self.enterOuterAlt(localctx, 1) + self.state = 108 + self.affectexpr() + self.state = 109 + self.match(HybroLangParser.T__5) + pass + elif token in [HybroLangParser.T__6]: + self.enterOuterAlt(localctx, 2) + self.state = 111 + self.match(HybroLangParser.T__6) + self.state = 112 + self.match(HybroLangParser.T__0) + self.state = 113 + self.affectexpr() + self.state = 114 + self.match(HybroLangParser.T__5) + self.state = 115 + self.condexpr() + self.state = 116 + self.match(HybroLangParser.T__5) + self.state = 117 + self.affectexpr() + self.state = 118 + self.match(HybroLangParser.T__1) + self.state = 119 + self.match(HybroLangParser.T__2) + self.state = 120 + self.actionlist() + self.state = 121 + self.match(HybroLangParser.T__3) + pass + elif token in [HybroLangParser.T__7]: + self.enterOuterAlt(localctx, 3) + self.state = 123 + self.match(HybroLangParser.T__7) + self.state = 124 + self.match(HybroLangParser.T__0) + self.state = 125 + self.condexpr() + self.state = 126 + self.match(HybroLangParser.T__1) + self.state = 127 + self.match(HybroLangParser.T__2) + self.state = 128 + self.actionlist() + self.state = 129 + self.match(HybroLangParser.T__3) + self.state = 130 + self.match(HybroLangParser.T__8) + self.state = 131 + self.match(HybroLangParser.T__2) + self.state = 132 + self.actionlist() + self.state = 133 + self.match(HybroLangParser.T__3) + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ReturnexprContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def unaryexpr(self): + return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_returnexpr + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitReturnexpr" ): + return visitor.visitReturnexpr(self) + else: + return visitor.visitChildren(self) + + + + + def returnexpr(self): + + localctx = HybroLangParser.ReturnexprContext(self, self._ctx, self.state) + self.enterRule(localctx, 24, self.RULE_returnexpr) + try: + self.enterOuterAlt(localctx, 1) + self.state = 137 + self.match(HybroLangParser.T__9) + self.state = 138 + self.unaryexpr(0) + self.state = 139 + self.match(HybroLangParser.T__5) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class AffectexprContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def Name(self): + return self.getToken(HybroLangParser.Name, 0) + + def unaryexpr(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.UnaryexprContext) + else: + return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_affectexpr + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitAffectexpr" ): + return visitor.visitAffectexpr(self) + else: + return visitor.visitChildren(self) + + + + + def affectexpr(self): + + localctx = HybroLangParser.AffectexprContext(self, self._ctx, self.state) + self.enterRule(localctx, 26, self.RULE_affectexpr) + try: + self.state = 151 + self._errHandler.sync(self) + la_ = self._interp.adaptivePredict(self._input,8,self._ctx) + if la_ == 1: + self.enterOuterAlt(localctx, 1) + self.state = 141 + self.match(HybroLangParser.Name) + self.state = 142 + self.match(HybroLangParser.T__10) + self.state = 143 + self.unaryexpr(0) + pass + + elif la_ == 2: + self.enterOuterAlt(localctx, 2) + self.state = 144 + self.match(HybroLangParser.Name) + self.state = 145 + self.match(HybroLangParser.T__11) + self.state = 146 + self.unaryexpr(0) + self.state = 147 + self.match(HybroLangParser.T__12) + self.state = 148 + self.match(HybroLangParser.T__10) + self.state = 149 + self.unaryexpr(0) + pass + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class UnaryexprContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + self.op = None # Token + + def varorvalue(self): + return self.getTypedRuleContext(HybroLangParser.VarorvalueContext,0) + + + def unaryexpr(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.UnaryexprContext) + else: + return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_unaryexpr + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitUnaryexpr" ): + return visitor.visitUnaryexpr(self) + else: + return visitor.visitChildren(self) + + + + def unaryexpr(self, _p:int=0): + _parentctx = self._ctx + _parentState = self.state + localctx = HybroLangParser.UnaryexprContext(self, self._ctx, _parentState) + _prevctx = localctx + _startState = 28 + self.enterRecursionRule(localctx, 28, self.RULE_unaryexpr, _p) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 154 + self.varorvalue() + self._ctx.stop = self._input.LT(-1) + self.state = 170 + self._errHandler.sync(self) + _alt = self._interp.adaptivePredict(self._input,10,self._ctx) + while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: + if _alt==1: + if self._parseListeners is not None: + self.triggerExitRuleEvent() + _prevctx = localctx + self.state = 168 + self._errHandler.sync(self) + la_ = self._interp.adaptivePredict(self._input,9,self._ctx) + if la_ == 1: + localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) + self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) + self.state = 156 + if not self.precpred(self._ctx, 5): + from antlr4.error.Errors import FailedPredicateException + raise FailedPredicateException(self, "self.precpred(self._ctx, 5)") + self.state = 157 + localctx.op = self._input.LT(1) + _la = self._input.LA(1) + if not(_la==HybroLangParser.T__13 or _la==HybroLangParser.T__14): + localctx.op = self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + self.state = 158 + self.unaryexpr(6) + pass + + elif la_ == 2: + localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) + self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) + self.state = 159 + if not self.precpred(self._ctx, 4): + from antlr4.error.Errors import FailedPredicateException + raise FailedPredicateException(self, "self.precpred(self._ctx, 4)") + self.state = 160 + localctx.op = self._input.LT(1) + _la = self._input.LA(1) + if not(_la==HybroLangParser.T__15 or _la==HybroLangParser.T__16): + localctx.op = self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + self.state = 161 + self.unaryexpr(5) + pass + + elif la_ == 3: + localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) + self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) + self.state = 162 + if not self.precpred(self._ctx, 3): + from antlr4.error.Errors import FailedPredicateException + raise FailedPredicateException(self, "self.precpred(self._ctx, 3)") + self.state = 163 + localctx.op = self._input.LT(1) + _la = self._input.LA(1) + if not(_la==HybroLangParser.T__17 or _la==HybroLangParser.T__18): + localctx.op = self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + self.state = 164 + self.unaryexpr(4) + pass + + elif la_ == 4: + localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) + self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) + self.state = 165 + if not self.precpred(self._ctx, 2): + from antlr4.error.Errors import FailedPredicateException + raise FailedPredicateException(self, "self.precpred(self._ctx, 2)") + self.state = 166 + localctx.op = self._input.LT(1) + _la = self._input.LA(1) + if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__19) | (1 << HybroLangParser.T__20) | (1 << HybroLangParser.T__21))) != 0)): + localctx.op = self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + self.state = 167 + self.unaryexpr(3) + pass + + + self.state = 172 + self._errHandler.sync(self) + _alt = self._interp.adaptivePredict(self._input,10,self._ctx) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.unrollRecursionContexts(_parentctx) + return localctx + + class VarorvalueContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return HybroLangParser.RULE_varorvalue + + + def copyFrom(self, ctx:ParserRuleContext): + super().copyFrom(ctx) + + + + class VarorvalueVarContext(VarorvalueContext): + + def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext + super().__init__(parser) + self.copyFrom(ctx) + + def Name(self): + return self.getToken(HybroLangParser.Name, 0) + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitVarorvalueVar" ): + return visitor.visitVarorvalueVar(self) + else: + return visitor.visitChildren(self) + + + class VarorvalueArrayContext(VarorvalueContext): + + def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext + super().__init__(parser) + self.copyFrom(ctx) + + def Name(self): + return self.getToken(HybroLangParser.Name, 0) + def unaryexpr(self): + return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,0) + + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitVarorvalueArray" ): + return visitor.visitVarorvalueArray(self) + else: + return visitor.visitChildren(self) + + + class VarorvalueConstContext(VarorvalueContext): + + def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext + super().__init__(parser) + self.copyFrom(ctx) + + def constvalue(self): + return self.getTypedRuleContext(HybroLangParser.ConstvalueContext,0) + + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitVarorvalueConst" ): + return visitor.visitVarorvalueConst(self) + else: + return visitor.visitChildren(self) + + + + def varorvalue(self): + + localctx = HybroLangParser.VarorvalueContext(self, self._ctx, self.state) + self.enterRule(localctx, 30, self.RULE_varorvalue) + try: + self.state = 180 + self._errHandler.sync(self) + la_ = self._interp.adaptivePredict(self._input,11,self._ctx) + if la_ == 1: + localctx = HybroLangParser.VarorvalueArrayContext(self, localctx) + self.enterOuterAlt(localctx, 1) + self.state = 173 + self.match(HybroLangParser.Name) + self.state = 174 + self.match(HybroLangParser.T__11) + self.state = 175 + self.unaryexpr(0) + self.state = 176 + self.match(HybroLangParser.T__12) + pass + + elif la_ == 2: + localctx = HybroLangParser.VarorvalueConstContext(self, localctx) + self.enterOuterAlt(localctx, 2) + self.state = 178 + self.constvalue() + pass + + elif la_ == 3: + localctx = HybroLangParser.VarorvalueVarContext(self, localctx) + self.enterOuterAlt(localctx, 3) + self.state = 179 + self.match(HybroLangParser.Name) + pass + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class DatatypeContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + self.wordlen = None # IntconstvalueContext + self.vectorlen = None # IntconstvalueContext + + def typebase(self): + return self.getTypedRuleContext(HybroLangParser.TypebaseContext,0) + + + def intconstvalue(self, i:int=None): + if i is None: + return self.getTypedRuleContexts(HybroLangParser.IntconstvalueContext) + else: + return self.getTypedRuleContext(HybroLangParser.IntconstvalueContext,i) + + + def getRuleIndex(self): + return HybroLangParser.RULE_datatype + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitDatatype" ): + return visitor.visitDatatype(self) + else: + return visitor.visitChildren(self) + + + + + def datatype(self): + + localctx = HybroLangParser.DatatypeContext(self, self._ctx, self.state) + self.enterRule(localctx, 32, self.RULE_datatype) + try: + self.enterOuterAlt(localctx, 1) + self.state = 182 + self.typebase() + self.state = 183 + localctx.wordlen = self.intconstvalue() + self.state = 184 + localctx.vectorlen = self.intconstvalue() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class IntconstvalueContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def IntegerConstant(self): + return self.getToken(HybroLangParser.IntegerConstant, 0) + + def constinline(self): + return self.getTypedRuleContext(HybroLangParser.ConstinlineContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_intconstvalue + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitIntconstvalue" ): + return visitor.visitIntconstvalue(self) + else: + return visitor.visitChildren(self) + + + + + def intconstvalue(self): + + localctx = HybroLangParser.IntconstvalueContext(self, self._ctx, self.state) + self.enterRule(localctx, 34, self.RULE_intconstvalue) + try: + self.state = 188 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [HybroLangParser.IntegerConstant]: + self.enterOuterAlt(localctx, 1) + self.state = 186 + self.match(HybroLangParser.IntegerConstant) + pass + elif token in [HybroLangParser.INLINE]: + self.enterOuterAlt(localctx, 2) + self.state = 187 + self.constinline() + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ConstvalueContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def IntegerConstant(self): + return self.getToken(HybroLangParser.IntegerConstant, 0) + + def DecimalFloatingConstant(self): + return self.getToken(HybroLangParser.DecimalFloatingConstant, 0) + + def constinline(self): + return self.getTypedRuleContext(HybroLangParser.ConstinlineContext,0) + + + def getRuleIndex(self): + return HybroLangParser.RULE_constvalue + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitConstvalue" ): + return visitor.visitConstvalue(self) + else: + return visitor.visitChildren(self) + + + + + def constvalue(self): + + localctx = HybroLangParser.ConstvalueContext(self, self._ctx, self.state) + self.enterRule(localctx, 36, self.RULE_constvalue) + try: + self.state = 193 + self._errHandler.sync(self) + token = self._input.LA(1) + if token in [HybroLangParser.IntegerConstant]: + self.enterOuterAlt(localctx, 1) + self.state = 190 + self.match(HybroLangParser.IntegerConstant) + pass + elif token in [HybroLangParser.DecimalFloatingConstant]: + self.enterOuterAlt(localctx, 2) + self.state = 191 + self.match(HybroLangParser.DecimalFloatingConstant) + pass + elif token in [HybroLangParser.INLINE]: + self.enterOuterAlt(localctx, 3) + self.state = 192 + self.constinline() + pass + else: + raise NoViableAltException(self) + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class ConstinlineContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + def INLINE(self): + return self.getToken(HybroLangParser.INLINE, 0) + + def getRuleIndex(self): + return HybroLangParser.RULE_constinline + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitConstinline" ): + return visitor.visitConstinline(self) + else: + return visitor.visitChildren(self) + + + + + def constinline(self): + + localctx = HybroLangParser.ConstinlineContext(self, self._ctx, self.state) + self.enterRule(localctx, 38, self.RULE_constinline) + try: + self.enterOuterAlt(localctx, 1) + self.state = 195 + self.match(HybroLangParser.INLINE) + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class TypebaseContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return HybroLangParser.RULE_typebase + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitTypebase" ): + return visitor.visitTypebase(self) + else: + return visitor.visitChildren(self) + + + + + def typebase(self): + + localctx = HybroLangParser.TypebaseContext(self, self._ctx, self.state) + self.enterRule(localctx, 40, self.RULE_typebase) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 197 + _la = self._input.LA(1) + if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0)): + self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + self.state = 199 + self._errHandler.sync(self) + _la = self._input.LA(1) + if _la==HybroLangParser.T__31: + self.state = 198 + self.match(HybroLangParser.T__31) + + + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + class CondOperatorContext(ParserRuleContext): + __slots__ = 'parser' + + def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): + super().__init__(parent, invokingState) + self.parser = parser + + + def getRuleIndex(self): + return HybroLangParser.RULE_condOperator + + def accept(self, visitor:ParseTreeVisitor): + if hasattr( visitor, "visitCondOperator" ): + return visitor.visitCondOperator(self) + else: + return visitor.visitChildren(self) + + + + + def condOperator(self): + + localctx = HybroLangParser.CondOperatorContext(self, self._ctx, self.state) + self.enterRule(localctx, 42, self.RULE_condOperator) + self._la = 0 # Token type + try: + self.enterOuterAlt(localctx, 1) + self.state = 201 + _la = self._input.LA(1) + if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__32) | (1 << HybroLangParser.T__33) | (1 << HybroLangParser.T__34) | (1 << HybroLangParser.T__35) | (1 << HybroLangParser.T__36) | (1 << HybroLangParser.T__37))) != 0)): + self._errHandler.recoverInline(self) + else: + self._errHandler.reportMatch(self) + self.consume() + except RecognitionException as re: + localctx.exception = re + self._errHandler.reportError(self, re) + self._errHandler.recover(self, re) + finally: + self.exitRule() + return localctx + + + + def sempred(self, localctx:RuleContext, ruleIndex:int, predIndex:int): + if self._predicates == None: + self._predicates = dict() + self._predicates[14] = self.unaryexpr_sempred + pred = self._predicates.get(ruleIndex, None) + if pred is None: + raise Exception("No predicate with index:" + str(ruleIndex)) + else: + return pred(localctx, predIndex) + + def unaryexpr_sempred(self, localctx:UnaryexprContext, predIndex:int): + if predIndex == 0: + return self.precpred(self._ctx, 5) + + + if predIndex == 1: + return self.precpred(self._ctx, 4) + + + if predIndex == 2: + return self.precpred(self._ctx, 3) + + + if predIndex == 3: + return self.precpred(self._ctx, 2) + + + + + diff --git a/HybroLang/__pycache__/H2Aarch64Rewrite.cpython-312.pyc b/HybroLang/__pycache__/H2Aarch64Rewrite.cpython-312.pyc new file mode 100644 index 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a/Makefile b/Makefile index e61ec62..9e4d7e7 100755 --- a/Makefile +++ b/Makefile @@ -6,7 +6,14 @@ all: @echo "What action do you target ?" @echo "make buildGrammar # Build grammars (need antlr)" @echo "make DbPopulate # Fill database with instruction sets" - @echo "make clean buildGrammar DbPopulate " + @echo "make clean # Clean grammars generated files and delete database" + @echo "make buildAll # Clean environment Build grammars, fill database and build Demos. HybroGen ready to use" + @echo "make check # To check if your installation is completed" + +buildAll: clean + make buildGrammar + make DbPopulate + make cd ./Demos && make buildAll # Uncomment if you whish to use distant database # DBIDS = --dbIds "DistantHost:DataBaseName:UserDbName:DbPassword" @@ -14,6 +21,8 @@ all: # Uncomment if you whish to use distant database # DBIDS = --dbIds "DistantHost:DataBaseName:UserDbName:DbPassword" + + DbPopulate: ./H2Isa.py -n ${DBIDS} # Create database schema make DbArch ARCH=aarch64 @@ -45,16 +54,42 @@ clean: -(cd Demos/; make clean) doregression: - cd CodeExamples && ./Regression.py ${THEARCH} + @(cd CodeExamples && ./Regression.py ${THEARCH}) aarch64: - make doregression THEARCH=aarch64 + @make doregression THEARCH=aarch64 riscv: - make doregression THEARCH=riscv + @make doregression THEARCH=riscv power: - make doregression THEARCH=power + @make doregression THEARCH=power cxram: - make doregression THEARCH=cxram \ No newline at end of file + @make doregression THEARCH=cxram + + +check: + @echo "[INFO] Start checking data base" +#Later add Sqlite3 database check checking if all aarch are in table if tables are'nt empty + @echo "[INFO] Start check with Regression test" + @make --no-print-directory aarch64 && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") + @make --no-print-directory power && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") + @make --no-print-directory riscv && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") + @echo "[INFO]start check with regressionSingleOp" + @cd CodeExamples && ./RegressionSingleOp.py -d -a aarch64 riscv power + @(cd CodeExamples && ./RegressionSingleOp.py -z -a aarch64) && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") + @(cd CodeExamples && ./RegressionSingleOp.py -z -a power) && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") + @(cd CodeExamples && ./RegressionSingleOp.py -z -a riscv) && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") + @echo "[INFO] Start trying Demo Stencil (can takes a lot of time (15-20 minutes))" + @(cd ./Demos/Stencil && make -s --no-print-directory allAarch64Qemu) && (echo "[OK] Demo stencil on aarch64 works") || (echo "[FAIL] Demo Stencil fail on aarch64") + @(cd ./Demos/Stencil && make -s --no-print-directory allRiscvQemu) && (echo "[OK] Demo stencil on riscv works") || (echo "[FAIL] Demo Stencil fail on riscv") + @(cd ./Demos/Stencil && make -s --no-print-directory allPowerQemu) && (echo "[OK] Demo stencil on power works") || (echo "[FAIL] Demo Stencil fail on power") + @echo "[INFO] Start Trying Demo Vector Matrix" + @(cd ./Demos/VectorMatrix && make -s --no-print-directory aarch64) && (echo "[OK] Demo Vector Matrix on aarch64 works") || (echo "[FAIL] Demo Vector Matrix fail on aarch64") + @(cd ./Demos/VectorMatrix && make -s --no-print-directory riscv) && (echo "[OK] Demo Vector Matrix on riscv works") || (echo "[FAIL] Demo Vector Matrix fail on riscv") + @(cd ./Demos/VectorMatrix && make -s --no-print-directory power) && (echo "[OK] Demo Vector Matrix on power works") || (echo "[FAIL] Demo Vector Matrix fail on power") + @echo "[INFO] Start Trying Demo Newton-SquareRoot-VariablePrecision" + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-aarch64) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on aarch64 works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on aarch64") + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-power) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on power works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on power") + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-riscv) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on riscv works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on riscv") diff --git a/__pycache__/H2Utils.cpython-312.pyc b/__pycache__/H2Utils.cpython-312.pyc new file mode 100644 index 0000000000000000000000000000000000000000..f69dbf9c4fa23244a66e9cc896233d520e53fbbf GIT binary patch literal 394 zcmX@j%ge<81Y74`&ny7ak3k$5V1hC}3jrC^8B!Qh7;_k+7*d#87@`;}88w+-f)w~A zGeXsYC>9`Q2I9|NKw>&W30y9Pv4)|Fje%h`RD_YC1f&iOvOv1fKnfE=WhH|qvtN~f zTVhFKjzVftQGStvm4a&V%l|;2$$X2opeQr1sS7?_wC>3dWr73I69=IMJFg_dOI6zdgK-r`CFS>OsXzX%j6 ztUz2W4I~;E?yzuP;Fg_He34uE3X94e7WQ_JMvso5R-ey6X$DQEBB0M0z?xPv6mf&t soIv6ihfQvNN@-52T@f#k3vx~|Kalvq%*e?2nT>&w`!fp@qaauV0N5o`r2qf` literal 0 HcmV?d00001 diff --git a/__pycache__/SwConfig.cpython-312.pyc b/__pycache__/SwConfig.cpython-312.pyc new file mode 100644 index 0000000000000000000000000000000000000000..417185eb10329bd2afaff98cb6ffd6a30aae5eda GIT binary patch literal 2594 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base" -#Later add Sqlite3 database check checking if all aarch are in table if tables are'nt empty @echo "[INFO] Start check with Regression test" - @make --no-print-directory aarch64 && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") - @make --no-print-directory power && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") - @make --no-print-directory riscv && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") - @echo "[INFO]start check with regressionSingleOp" - @cd CodeExamples && ./RegressionSingleOp.py -d -a aarch64 riscv power - @(cd CodeExamples && ./RegressionSingleOp.py -z -a aarch64) && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") - @(cd CodeExamples && ./RegressionSingleOp.py -z -a power) && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") - @(cd CodeExamples && ./RegressionSingleOp.py -z -a riscv) && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") + @make --no-print-directory aarch64 ${REDIRECT} && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") + @make --no-print-directory power ${REDIRECT} && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") + @make --no-print-directory riscv ${REDIRECT} && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") +# @echo "[INFO]start check with regressionSingleOp" +# @(cd CodeExamples && ./RegressionSingleOp.py -d -a aarch64 riscv power ${REDIRECT}) +# @(cd CodeExamples && ./RegressionSingleOp.py -z -a aarch64 ${REDIRECT} ) && (echo "[OK] Regression test on aarch64")|| (echo "[FAIL] Regression test fail for aarch64") +# @(cd CodeExamples && ./RegressionSingleOp.py -z -a power ${REDIRECT} ) && (echo "[OK] Regression test on power")|| (echo "[FAIL] Regression test fail for power") +# @(cd CodeExamples && ./RegressionSingleOp.py -z -a riscv ${REDIRECT} ) && (echo "[OK] Regression test on riscv")|| (echo "[FAIL] Regression test fail for riscv") @echo "[INFO] Start trying Demo Stencil (can takes a lot of time (15-20 minutes))" - @(cd ./Demos/Stencil && make -s --no-print-directory allAarch64Qemu) && (echo "[OK] Demo stencil on aarch64 works") || (echo "[FAIL] Demo Stencil fail on aarch64") - @(cd ./Demos/Stencil && make -s --no-print-directory allRiscvQemu) && (echo "[OK] Demo stencil on riscv works") || (echo "[FAIL] Demo Stencil fail on riscv") - @(cd ./Demos/Stencil && make -s --no-print-directory allPowerQemu) && (echo "[OK] Demo stencil on power works") || (echo "[FAIL] Demo Stencil fail on power") + @(cd ./Demos/Stencil && make -s --no-print-directory allAarch64Qemu ${REDIRECT} ) && (echo "[OK] Demo stencil on aarch64 works") || (echo "[FAIL] Demo Stencil fail on aarch64") + @(cd ./Demos/Stencil && make -s --no-print-directory allRiscvQemu ${REDIRECT} ) && (echo "[OK] Demo stencil on riscv works") || (echo "[FAIL] Demo Stencil fail on riscv") + @(cd ./Demos/Stencil && make -s --no-print-directory allPowerQemu ${REDIRECT} ) && (echo "[OK] Demo stencil on power works") || (echo "[FAIL] Demo Stencil fail on power") @echo "[INFO] Start Trying Demo Vector Matrix" - @(cd ./Demos/VectorMatrix && make -s --no-print-directory aarch64) && (echo "[OK] Demo Vector Matrix on aarch64 works") || (echo "[FAIL] Demo Vector Matrix fail on aarch64") - @(cd ./Demos/VectorMatrix && make -s --no-print-directory riscv) && (echo "[OK] Demo Vector Matrix on riscv works") || (echo "[FAIL] Demo Vector Matrix fail on riscv") - @(cd ./Demos/VectorMatrix && make -s --no-print-directory power) && (echo "[OK] Demo Vector Matrix on power works") || (echo "[FAIL] Demo Vector Matrix fail on power") + @(cd ./Demos/VectorMatrix && make -s --no-print-directory aarch64 ${REDIRECT} ) && (echo "[OK] Demo Vector Matrix on aarch64 works") || (echo "[FAIL] Demo Vector Matrix fail on aarch64") + @(cd ./Demos/VectorMatrix && make -s --no-print-directory riscv ${REDIRECT} ) && (echo "[OK] Demo Vector Matrix on riscv works") || (echo "[FAIL] Demo Vector Matrix fail on riscv") + @(cd ./Demos/VectorMatrix && make -s --no-print-directory power ${REDIRECT} ) && (echo "[OK] Demo Vector Matrix on power works") || (echo "[FAIL] Demo Vector Matrix fail on power") @echo "[INFO] Start Trying Demo Newton-SquareRoot-VariablePrecision" - @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-aarch64) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on aarch64 works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on aarch64") - @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-power) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on power works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on power") - @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-riscv) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on riscv works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on riscv") + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-aarch64 ${REDIRECT} ) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on aarch64 works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on aarch64") + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-power ${REDIRECT} ) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on power works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on power") + @(cd ./Demos/Newton-SquareRoot-VariablePrecision && make -s --no-print-directory demo-riscv ${REDIRECT} ) && (echo "[OK] Demo Newton-SquareRoot-VariablePrecision on riscv works") || (echo "[FAIL] Demo Newton-SquareRoot-VariablePrecision fail on riscv") From fac330e6185d5364f820815250117f92050ae4b4 Mon Sep 17 00:00:00 2001 From: Quentin MELOTTE Date: Wed, 22 Jul 2026 15:50:27 +0200 Subject: [PATCH 3/6] Delete file generated --- CodeExamples/Add-With-Specialization.aarch64 | Bin 39832 -> 0 bytes .../Add-With-Specialization.aarch64.c | 976 ------- CodeExamples/Add-With-Specialization.power | Bin 78168 -> 0 bytes CodeExamples/Add-With-Specialization.power.c | 774 ------ CodeExamples/Add-With-Specialization.riscv | Bin 29136 -> 0 bytes CodeExamples/Add-With-Specialization.riscv.c | 667 ----- CodeExamples/Add-With-Transprecision.aarch64 | Bin 43928 -> 0 bytes .../Add-With-Transprecision.aarch64.c | 1101 -------- CodeExamples/Add-With-Transprecision.power | Bin 78288 -> 0 bytes CodeExamples/Add-With-Transprecision.power.c | 850 ------ CodeExamples/Add-With-Transprecision.riscv | Bin 29136 -> 0 bytes CodeExamples/Add-With-Transprecision.riscv.c | 722 ------ CodeExamples/Array-Ld-flt.aarch64 | Bin 48048 -> 0 bytes CodeExamples/Array-Ld-flt.aarch64.c | 1233 --------- CodeExamples/Array-Ld-flt.power | Bin 78424 -> 0 bytes CodeExamples/Array-Ld-flt.power.c | 895 ------- CodeExamples/Array-Ld-flt.riscv | Bin 33296 -> 0 bytes CodeExamples/Array-Ld-flt.riscv.c | 815 ------ CodeExamples/Array-Ld.aarch64 | Bin 43952 -> 0 bytes CodeExamples/Array-Ld.aarch64.c | 1178 --------- CodeExamples/Array-Ld.power | Bin 78192 -> 0 bytes CodeExamples/Array-Ld.power.c | 882 ------- CodeExamples/Array-Ld.riscv | Bin 33248 -> 0 bytes CodeExamples/Array-Ld.riscv.c | 795 ------ .../Array-Mult-Specialization.aarch64 | Bin 48416 -> 0 bytes .../Array-Mult-Specialization.aarch64.c | 1327 ---------- CodeExamples/Array-Mult-Specialization.power | Bin 78720 -> 0 bytes .../Array-Mult-Specialization.power.c | 1052 -------- CodeExamples/Array-Mult-Specialization.riscv | Bin 37596 -> 0 bytes .../Array-Mult-Specialization.riscv.c | 918 ------- CodeExamples/Array-St-flt.aarch64 | Bin 48112 -> 0 bytes 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zPs5kZnt=Y3q*wY^>(YxQ{mUvtQYif?2Kc@OFJGal_3L8VZinNz2ol%y@*hGD$*<_u zI=71q3&*#}xGhI|`Tv5vLYxXs-KW3v1woXKuhJ^q4>Ve{RrG3I;OGeHe+F7=YDKTs z*FTcVBlRNnpr8Bydfq|07^j{`>@nh$#B>dlSN?Lxo2z zah@SB+nYp$*43;>dVOeNKMjSWo6Umi!W=90VB9Tj=9viam>W&!>Q~?`DJRJG!+AaZ*|CluRqP -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(int); - -pifi genAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, in1, res; - pifi fPtr; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genAdd (fPtr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d + %d = %d\n", in0, in1, res); - if (res == (in0 + in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Add-With-Specialization.power b/CodeExamples/Add-With-Specialization.power deleted file mode 100755 index 2b39fab45ffaed3d199fd4464e571ef21faf7c55..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78168 zcmeHv4SZD9nfJLflVn0Zm_WezQMnPY3FZrQaZr#XfFytr`B1uVcV{MZJl(&*CpQ^-=V;pcHb<%?_<37|Zmq9+8KDN3?*-HCiu&&gg~DTFu5^3vgQ zPS#&h)ee)pKPU{#9xCGt%(O)9_iKGZ<%)Kr|YTvPeffMvtaeA0p9UDBjFk z0`Z8iB@heV7hvs?XgD5dinDfKTU)q^#o~TsWX;>7!FYiA;^83kc+ioWJh8Yh8uzsO zf+0q6>Qal@>UH(CD?E!T7Tyf8miBN+ig{2s+o*r$I1+Jb_}2)k`uXSg|23M{#@cu) z`jR2W|MiHgF-u7$Ccf&2#CI_pS2YV^>O1NxGV$e5;YqrQuf`}Pl$iKtKUQVpQy)~9 z+r+1Fpss2Y-(3GX6Q9PHx*AM;^LX59;;S)5dAue*ja7BEn)u0MSIL-Z5vv)h-nDz+ zG5Z7Ex}#^kIgP?LSM^f1v)28X&DrH*+R!1RcnEB-v&YuYSZ`%6yHNA2VXTFo{?FQ3 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fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(int); - -pifi genAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x780F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, in1, res; - pifi fPtr; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genAdd (fPtr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d + %d = %d\n", in0, in1, res); - if (res == (in0 + in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Add-With-Specialization.riscv b/CodeExamples/Add-With-Specialization.riscv deleted file mode 100755 index bf3a43a6afa1065502cd2044874f927bb40fd210..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 29136 zcmeHweSB2Kx&NF!n`}Zb1OkFp%bHD2Vw!9qs1+3mVM9oZkOFGGSAWZrEMb35vSD}e z?bZVBh8J6fHde8vEyW0khzJ-cMGUZz5D@|fjFdunkvEYK@gbcbnIJ3R7se??nC&?LdL=n-p7or3rk`q z7RSOlO=-jecuJk{G3o?H|>@kGFPfhR|0knPAW zB&Rt8B1BU@$q>!-nf-Mcvp$?g1u(r=%cHVl{%iiPw|+S*@$UP7>t26mZq3@C{HoXB z-@N|oN8THFTc6)_nHf0k>*;#rwO^Y@4LZMS?!%u^389YK%YZ9#J>bW|_Y0vZCnJRZ zG3Z)-JO87gn?mS2K*xme{{*x#gq{tWO;Y4z*f#;Hb9_j?1iCV$ymZhFA+!Z_ZU{ds zuzN~u1$MXN1v@L5;&HPQyUXQtG5d244<+PHvbmVe<8-hhTVbIyk6Eqg>O8C4V{>_| zMK(tv!+_$gTeU>wt{N+=x@!Do*RzZzvNk ze!RfKRPZEGoWKE>LU95ZTtABQ0f~8l;)wFCiRjV%~+Btbj$c-o?jniM6`O-AX zDMS1(uateBkkLAQ!yija-`sK~&(Q91es9(E8R1)JAAfpCX|~Dt&5V^9ah9RNOVc*4 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-#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(int); - -pifi genAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x73F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genADD_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, in1, res; - pifi fPtr; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genAdd (fPtr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d + %d = %d\n", in0, in1, res); - if (res == (in0 + in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Add-With-Transprecision.aarch64 b/CodeExamples/Add-With-Transprecision.aarch64 deleted file mode 100755 index ba791eed19985442f5601c0deb43e65c871b34f5..0000000000000000000000000000000000000000 GIT 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struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x72 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x272 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRI_F_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_FADD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef float (*pifff)(float, float); -typedef double (*pifdd)(double, double); - -// Simple addition between variables with -// specialization transprecision on data width -// Width depend on the platform. At least 32 & 64 bits. -// Could also be 16 on RISCV or 128 on INTEL - -h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -int main(int argc, char * argv[]) -{ - float in0, in1, resf; - double resd; -#if 0 - long double resD; -#endif - pifff fPtr1; - pifdd fPtr2; - - if (argc < 2) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atof(argv[1]); // Get the users values in1 & in2 - in1 = atof(argv[2]); - fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions -#if 0 - fPtr1 = genAdd (ptr, 16); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); -#endif - - fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); - - fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions - resd = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); - -#if 0 - fPtr2 = genAdd (ptr, 128); // Generate instructions - resD = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); -#endif - - return 0; - -} diff --git a/CodeExamples/Add-With-Transprecision.power b/CodeExamples/Add-With-Transprecision.power deleted file mode 100755 index 75732780162f3482e581ed1471c2617f4e16dfba..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78288 zcmeHv3wRvGm2UOSNHelzdHlebr`y;jlB1UmF=MdNNPbDSF~Se<-XuFSl19>iG$Uq4 zFeVa~9kQ5&+_k?o8?8XoShJ~yYe7Q;ji44Yl z|5J}qt2JZE4=vig-BNc|ojP@@&Rxk$S>4Hprray%T6qE+Y-Y|M#}%K1p32suB}Je(}ZOogh26z0f0 z8E}5YdDtEhR24F=jkr=<^^Zlq{;|gSRT!iO;n*)jRgRiR<@~aoUzSs0k8GF!s(&x#C$yqpRT2{Kb5@zQY%%27KIC~u9_FTA$AwQ=FKWrg2S1qzD)EbpsTTHF10WVe_a;( z>MZnGS?G6zuH&>Ggj=R|F3Uo{Gz)!77J6wGIt!;FN!A{Y$76BU-jPhurJ*H+L_88r zHnHY#vOUxsPDJhrv$pnlEE#S{vbIobYpj7Kl8q?Hn(mHAl3^A~#+q0lfPvHyNF+n? zWS}h+i84ylkXp!AuBokF8dy*^|2nWWx5c88ji$I`$e%flOdJ~i>Jh4O{dAfRxNkqqxKCU(B{t`<`%kI=xIAc+8kJ0CLdN?dWA}Z+QVbUG*cwSPeP7 zUv;t?%DdQwSnx_fKAuY2oNi`a}}^zpWvi0$38iV=(Ac7}^Cs%0{+xwzM&m^v zHa@C@ndNWu)#+dCOkR0kXR`3V&WE)7(sj)^=ekIzq4hzJ2e9f=`;8xeWEj=7 zv;?!WhVjP5FwdG`_Yiys(i zOkc!t#au$&@1kArqOA{`<`r}qs!tEf4j6BK^fcO%%CGE9T^8y5wU*ae!73L$bu&ZX z>x*<&xf4dS2H{p}7p0NEwY{*o3n7ma9>NjO4 zsBRi(qVC%}Q?nmH{S!KaEU@UQ+Zb<4qihSptyE7D+g25n^&fE0>ms^g6fZj9F78UL zp3{|DzqIQy*c#$F?JnM^vtr;_TvC8?WzYw9wq^xF;yrEDFYbS(!S~ol!Zr~;-DtbA zM;0BlY&zU2b!cZ>22!)X+?o3Hx49lElOCN?kC~{u1-McAy|t{fRnqSPcJ1u%dsVvz z(5^h$F7R_+=*0VFJ9HrZnwtDenwwUI{<5yNt9^P+SNrLCU3LCdT@%=WVp^s@L;sgKy`D0*`5^hcNPj)+K2qhww(Ylj77TNu%38fdzf9 zNFLQ*)pu(khx%zW?KQU}Ps&q$jBqE#sm}ef&amXUodx=$H2&5v!#J4T^~lG@YHHJR znNNMYW0ZYM$?cRy^Oj=cA7Wu0PP3ECVGBJy3$P5RzN1dblw{`Ue{k!>mXF<&AQO{k4k&;W}Sx@V&FPek?YC+$FHe@c+cvNK^thP^M zjCi+J)a1#rSc`BT#;$5_?ar&ww=|AO7TF$zJE;t}l`=k)8yK9| zJGkC{=wAD?fz}t)eG+Hi5mrm< zM<3~nww*M~aI?KWvI9kIOYb{>7%WS+4C`(c^{)^8`+&?djG*r|8K-(hUl%`su@Sj3 zw-`6E#U(zJqr9T-tNM_}I(0R$+KY9w+eh;1An#cz<0HuXs!1MUf3|Canj1PW!rA-z z4+ix(o3UqJD{qnW_y}Yk1@6b$-w*V%HwOBdF)+Ypo@83(Nsksdd8t;3Ih9xPIOf@h zz?kB@5kJK$ABbR%Jc#(^nuvFE`WxFFn$er9&Fm}G0)1sDFV=;5T}MzJdw3sX-yWdQ zBSWtYXRvSYARbNd@VJY;u$yQe*2mKYEN>^J4TCN6%J?)^yAytznpe4e-mm`OU>woh zq;cv+yB@;&M`NZJW0>@i{qLWEHk$d`B%epC+<8pu*o*SNMj0KtA7fjq-a?#kI0Cw= z^AO@n?m@&AZu=1b4fv-$S-g?v@-9t;%vT&HyEFm#T-hyXuRBCY^N8{YyCY1@RH1_MqUtP5b_r%!WR4?g8 zoNzqgzPjtz!2T^@{~r23wSGDJOxTBh$lCl{QJ2Cnn=G1VBr6wl%AwJm60(%7Az7tT zmg<9SvS^-?tg9jGD#)VoMeTB!+Vy6?XqT9)e2qKFm>+xHS{~Avq4W$nzBI(uSc@R; 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// Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define PPC_FADDS_RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); -#define PPC_FADDS__RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDFP_RRR_F_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xa & 0x7ff) >> 0)); } while(0); -#define P1_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); -#define P1_FADD__RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FADDS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FADDS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDFP_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FADD__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef float (*pifff)(float, float); -typedef double (*pifdd)(double, double); - -// Simple addition between variables with -// specialization transprecision on data width -// Width depend on the platform. At least 32 & 64 bits. -// Could also be 16 on RISCV or 128 on INTEL - -h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -int main(int argc, char * argv[]) -{ - float in0, in1, resf; - double resd; -#if 0 - long double resD; -#endif - pifff fPtr1; - pifdd fPtr2; - - if (argc < 2) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atof(argv[1]); // Get the users values in1 & in2 - in1 = atof(argv[2]); - fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions -#if 0 - fPtr1 = genAdd (ptr, 16); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); -#endif - - fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); - - fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions - resd = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); - -#if 0 - fPtr2 = genAdd (ptr, 128); // Generate instructions - resD = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); -#endif - - return 0; - -} diff --git a/CodeExamples/Add-With-Transprecision.riscv b/CodeExamples/Add-With-Transprecision.riscv deleted file mode 100755 index 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H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32F_FADD_S_RRR_F_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FADD_D_RRR_F_64_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef float (*pifff)(float, float); -typedef double (*pifdd)(double, double); - -// Simple addition between variables with -// specialization transprecision on data width -// Width depend on the platform. At least 32 & 64 bits. -// Could also be 16 on RISCV or 128 on INTEL - -h2_insn_t * genAdd(h2_insn_t * ptr, int FloatWidth) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, (FloatWidth), 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -int main(int argc, char * argv[]) -{ - float in0, in1, resf; - double resd; -#if 0 - long double resD; -#endif - pifff fPtr1; - pifdd fPtr2; - - if (argc < 2) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atof(argv[1]); // Get the users values in1 & in2 - in1 = atof(argv[2]); - fPtr1 = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr2 = h2_malloc (1024); // Allocate memory for 1024 instructions -#if 0 - fPtr1 = genAdd (ptr, 16); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 16, in0, in1, resf); -#endif - - fPtr1 = (pifff)genAdd (fPtr1, 32); // Generate instructions - resf = fPtr1(in0, in1); // Call generated code - printf("(%d) %10.30f + %10.30f = %10.30f\n", 32, in0, in1, resf); - - fPtr2 = (pifdd)genAdd (fPtr2, 64); // Generate instructions - resd = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30lf + %10.30lf = %10.30lf\n", 64, in0, in1, resd); - -#if 0 - fPtr2 = genAdd (ptr, 128); // Generate instructions - resD = fPtr2(in0, in1); // Call generated code - printf("(%d) %10.30Lf + %10.30Lf = %10.30Lf\n", 128, in0, in1, resD); -#endif - - return 0; - -} diff --git a/CodeExamples/Array-Ld-flt.aarch64 b/CodeExamples/Array-Ld-flt.aarch64 deleted file mode 100755 index 5fe4e94f5bb0ff172c5cb8f0347f11781a5523ff..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 48048 zcmeHw3w%`7wf8=A=9PCyB1Awq;ZYGy0>L6EUQQAaxuRl%ulBZ+Nis>MCX+BTK@=*3 z+SXfXB^P|ODg?E+2JKh+`fRGb2DPs%ZMj8STdNMJw|=en-qc4mS8(os?Z@QIWF`+n z@_oPW=Sj}ld#}CL+H0@9_IsZ*+g7i;#HMLXT{iXvqfnpAl)F>P(Jx&^M?s?dK+=66>69Clf+<(!kMc(M2FY)O%|wX8 zCOORD&q0@P>019rxRLzDZ9E9qnw1p>*}hrz^!%PGfzKya?8^_Cw12KS;lss+;Z^IKHc+MMc0qG z1B~@g`Do2R{_&MvhHdt5XB+xabsuJI=MS0H?=2&;Ujb4g!k zvB+;`;eJDB`;Y17!11}P>))Y2SnY2Z>wBBIyWfr+-|@DNu#T{fu)gpsZ`%>JBWy?5 ze&JW%J{XJLdkA+o^vn9!44904|G8Lf8tGr@w-5SdQLXDB+!DAe8T$)h8%h{ET=K!H z0WWC!b!|UGxe#44KJcEOb7I?(%IxiTmYk^E1wP-O1KO$+s|M;htu0PVX`bBjFWeU1 z$zlUXkY=5&YI%gQPrd><4Hl`Xv)PuvlVuK^-0}>!lh+|{>^Amq(LB~0o6UMrXNsb; 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zZhSz}_gj(S&rb?(Poh`j-99pETt)T5RZmlSr28ef*7Vgn^b3B0pw{mcnJiWnWb{4< z(JTF{_3Aez{US0h%cbYi3lPkr(&V#RQNbN z1XJ>>`N-yoz^D^W{FzMuC&WDv=YOgtbgK{lmw@!+am}~s@%Bd u;P&BG_M_TmDxM@21HxGM -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_F_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x5e2 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_F_32_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x5e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_F_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_F_64_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x3f5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_F_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int); -typedef double (*pifsi)(double *, int); - -/* C compilette prototype */ -h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0002, immValueZero); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4f ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK; - float res32; - double res64; - pifii fPtr32; - pifsi fPtr64; - - - float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; - double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0); // Call generated code - if (f32[in0] != res32) - resultOK ++; - PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); - printf ("res (32) f32[%d] = %f\n", in0, res32); - - /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ - /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ - /* res64 = fPtr64(f64, in0); // Call generated code */ - /* if (f64[in0] != res64) */ - /* resultOK ++; */ - /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ - /* printf ("res (64) f64[%d] = %f\n", in0, res64); */ - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-Ld-flt.power b/CodeExamples/Array-Ld-flt.power deleted file mode 100755 index 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4c1794b..0000000 --- a/CodeExamples/Array-Ld-flt.power.c +++ /dev/null @@ -1,895 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_LFS_RRI_F_32_1(r0,r1,i0) do /* r */ { power_G32(((0x30 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LFS_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int); -typedef double (*pifsi)(double *, int); - -/* C compilette prototype */ -h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x381F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = power_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4f ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK; - float res32; - double res64; - pifii fPtr32; - pifsi fPtr64; - - - float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; - double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0); // Call generated code - if (f32[in0] != res32) - resultOK ++; - PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); - printf ("res (32) f32[%d] = %f\n", in0, res32); - - /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ - /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ - /* res64 = fPtr64(f64, in0); // Call generated code */ - /* if (f64[in0] != res64) */ - /* resultOK ++; */ - /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ - /* printf ("res (64) f64[%d] = %f\n", in0, res64); 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z>3$%dF$0hHYl8#0TG@@~;7!QJc+(04@aX4(fNV~ji02ssGPLCFDxN0qL%A43=d??> zgU`VmT>v?>O4N15vc(f|Me diff --git a/CodeExamples/Array-Ld-flt.riscv.c b/CodeExamples/Array-Ld-flt.riscv.c deleted file mode 100644 index db41554..0000000 --- a/CodeExamples/Array-Ld-flt.riscv.c +++ /dev/null @@ -1,815 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32F_FLW_RRI_F_32_1(r2,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r2 & 0x1f) << 7)|((0x7 & 0x7f) >> 0)); } while(0); -#define RV64D_FLW_RRI_F_64_1(r2,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x3 & 0x7) << 12)|((r2 & 0x1f) << 7)|((0x7 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32F_FLW_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV64D_FLW_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int); -typedef double (*pifsi)(double *, int); - -/* C compilette prototype */ -h2_insn_t * genLoad(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'f', 1, (wordSize), 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'f', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF1F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4f ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK; - float res32; - double res64; - pifii fPtr32; - pifsi fPtr64; - - - float f32[] = {0, 1, 2.2, 3.33, 4.444, 5.5555, 6.66666, 7.777777}; - double f64[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genLoad (ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0); // Call generated code - if (f32[in0] != res32) - resultOK ++; - PRINTARRAY ("32 bits : ", f32, sizeof(f32) / sizeof (float)); - printf ("res (32) f32[%d] = %f\n", in0, res32); - - /* ptr = h2_malloc (1024); // Allocate memory for 1024 instructions */ - /* fPtr64 = (pifsi) genLoad (ptr, 64); // Generate instructions */ - /* res64 = fPtr64(f64, in0); // Call generated code */ - /* if (f64[in0] != res64) */ - /* resultOK ++; */ - /* PRINTARRAY ("64 bits : ", f64, sizeof(f64) / sizeof (double)); */ - /* printf ("res (64) f64[%d] = %f\n", in0, res64); */ - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-Ld.aarch64 b/CodeExamples/Array-Ld.aarch64 deleted file mode 100755 index a2a38992e0f9dbf96b355f1b03984d06fd75b0c9..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 43952 zcmc(I3w%`7o&ULW=aqLz!W-cxKt(hO4~rnUOcD@SP%*)3*S3>MGD)T;GjV33AZ!_w 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-/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifii)(int *, int); -typedef short (*pifsi)(short *, int); -typedef char (*pifci)(char *, int); - -/* C compilette prototype */ -h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 0, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0002, immValueZero); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4d ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; - short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions - res = fPtr32(a32, in0); // Call generated code - if (a32[in0] != res) - resultOK ++; - PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); - printf ("res (32) a32[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions - res = fPtr16(a16, in0); // Call generated code - PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); - if (a16[in0] != res) - resultOK ++; - printf ("res (16) a16[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions - res = fPtr8(a8, in0); // Call generated code - if (a8[in0] != res) - resultOK ++; - PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); - printf ("res (8) a8[%d] = %d\n", in0, res); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-Ld.power b/CodeExamples/Array-Ld.power deleted file mode 100755 index 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zV~3=Kt};l0WP4sulfR$8p+m37j@6u`jt!^Df66H&zoiD2RFj-P6O3dYiGCqha9c+k zmTO3srMH=hmyF-L1wvB!F`gM0m0!^hAfUoZhUmgMg1aUuF)7N5!ARy&{?1DTH%<}L zk&Hh{B|*fchh+X^baTT|gtHN+>OabV)9+D|AOeT6$BIPxKUR*PbH~?}<_D?r-+7J5 MPp_hykEAI3|N55}kN^Mx diff --git a/CodeExamples/Array-Ld.power.c b/CodeExamples/Array-Ld.power.c deleted file mode 100644 index 11e0390..0000000 --- a/CodeExamples/Array-Ld.power.c +++ /dev/null @@ -1,882 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifii)(int *, int); -typedef short (*pifsi)(short *, int); -typedef char (*pifci)(char *, int); - -/* C compilette prototype */ -h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 3, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x781F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = power_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4d ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; - short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions - res = fPtr32(a32, in0); // Call generated code - if (a32[in0] != res) - resultOK ++; - PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); - printf ("res (32) a32[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions - res = fPtr16(a16, in0); // Call generated code - PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); - if (a16[in0] != res) - resultOK ++; - printf ("res (16) a16[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions - res = fPtr8(a8, in0); // Call generated code - if (a8[in0] != res) - resultOK ++; - PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); - printf ("res (8) a8[%d] = %d\n", in0, res); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-Ld.riscv b/CodeExamples/Array-Ld.riscv deleted file mode 100755 index 6785e5c7406b813e93dffc28b3461b6e4e53cd62..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33248 zcmeHw3s@9Kwtx3@!=MmE(U|8tGSCn%j*3|~=AnRt$i}EqlWhKX^Nk1t@+~iCFq`Bi z8+8WJyfjNTYC@th1dZ`Q)TlAWpiV@ML1NGlmnc4>#uy>mfGCgu?^JisjHoDH@AuvN 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Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifii)(int *, int); -typedef short (*pifsi)(short *, int); -typedef char (*pifci)(char *, int); - -/* C compilette prototype */ -h2_insn_t * genAdd(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 2 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, (wordSize), 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, (wordSize), 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, (wordSize), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genR_3(tmp0002, tmp0001, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%4d ", ARRAY[i]); \ - } \ - printf ("\n"); - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - int a32[] = {0, 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000}; - short a16[] = {0, 1, 10, 100, 1000, 10000, 1000, 100, 10, 1}; - char a8[] = {0, 1, 10, 100, 127, 127, 100, 10, 1, 0}; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - resultOK = 0; - printf ("Size of 10 INTs %ld, SHORTs %ld, CHARs %ld \n", sizeof (a32), sizeof (a16), sizeof (a8)); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) genAdd (ptr, 32); // Generate instructions - res = fPtr32(a32, in0); // Call generated code - if (a32[in0] != res) - resultOK ++; - PRINTARRAY ("32 bits : ", a32, sizeof(a32) / sizeof (int)); - printf ("res (32) a32[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) genAdd (ptr, 16); // Generate instructions - res = fPtr16(a16, in0); // Call generated code - PRINTARRAY ("16 bits : ", a16, sizeof(a16) / sizeof (short)); - if (a16[in0] != res) - resultOK ++; - printf ("res (16) a16[%d] = %d\n", in0, res); - - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) genAdd (ptr, 8); // Generate instructions - res = fPtr8(a8, in0); // Call generated code - if (a8[in0] != res) - resultOK ++; - PRINTARRAY ("8 bits : ", a8, sizeof(a8) / sizeof (char)); - printf ("res (8) a8[%d] = %d\n", in0, res); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-Mult-Specialization.aarch64 b/CodeExamples/Array-Mult-Specialization.aarch64 deleted file mode 100755 index 5f29e67b077e9bbe10576173bf02cfc097a84fde..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 48416 zcmc(I3t&{$ng6+SXOhYLDNltP9zM_{5EMbNOcD`UP%z+Y-G3*O$t0N)X5!2QgU~XF zZQ0@~v*2SFm7w)sgWZ-@yPE2*LF~3&Y^4QT{_AUkb<0+}rQjeK?$47vY3NSV^diM zAXeNC9z(A1Dfe^9TDf+Kr^6+>xfTJKYjJRoawiHfQ?8PbT$_v&jzflo`|{UCP`Qlf zMm$N@qcZ;J*Q+_Aa-WuR*hw&ci4+M;be~JQ&n2C5qf#*Cs{B#j=w2!LuCzE1qOgM; zX7FdfOSp6`{~**zetQQG!gX+ua;M4kl&k1&0v*XY+^bL`*2(nJ>1CXhU%4`QR@v%p zsBCR4Z}s}xJIY96Zd1W;O#{C$ z4V-wS;^RmIUk-Q?8^^YWtKkzi#XX)5Z-}*d0s()3wY7(W^l-Ph0?gg&cdufu27dtY z0k1FA#N4h{09msq)aGjT1ig2A*y^@`Kjd+T*lH0M3^jrmYq~4o4SAR=tg|zuhGAn5typR9JXlb;+k4#RmH3;f!(~??~~Y0h-ew`mkgtPX!u(X zSJmH#BM-rZEbLnpi7UE6blJY zr#47k^(MG#FDS0X1UI)$Z6-LiQR?b2!ByE&oO7D~=BahBbe+;!q=B*Rr`GL#x<_~Z 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zI@dz-w8{SEX$hx|I;2n4KT7qmy8%zdALkx9pXEy&oCDvV4_`#$C)cmXBz{|)z~}qo zf&T=Da~27Y=OzB!YJnd`n6B60lAKQ`mHRIxe%SBecuGIC*NF1Fd4hoR^BKT6D&bGd zdOed<;b1%QN4Y1KYB=Pae81R9Ykp@0n@_EhW;6(iF0elP6;NL=WS_Y0+ z&8x%H8qKT1{5`OrO~Y%4#N}PSmg~oQUu&!LE{|)Kv&qK*^Hl&A2n9p!O-)#+Z1mtn zBR_)a46Vj0q~GVE<-bP1v$@sZ;A(X?V&NXk>FphIO*7g#E*j$9W?(IA z3SgDq+1S2%^;(daLWwJDgvyVtmD6Fj@)d0!H(m{R@8+k@D&(pugl(w;UC_5kob$wr zHUM<;6M&Uoyf{Fx)!$qt@Vp_M%8S29nBH)IaC;XRH&V1^93e%%lZiiKk24zCW-uxR-Yd!V za&B(TD?FjadnZM)75f=J>T5#_}zyjc;q0>?yC2g9a@X5|gFvew{)tRUj$-DJ)a@<=ZT%^(y%S`$H_ zj*pw;Sw(Q|>X54eZYUt!7UhFodGL0)g6}!0u3218FW@ThPPC%M6>MP@jca`%7H%jY zV&s9^gn$!qc-`hA0_kgO4Y3NY_ll6G1AhM6q$1$wHKM}PBAZEiw-*ly3emI*3gri5 zyj#Z0yk<)y-%3AR?y#8$y*i(IY?$;v0WH~%qF3)RK9}@SnSW(pDqUpbGCT=O7}?^yXdI4lU#r7zj>Lkq-9$*<;9TP1zH zLX@sbSAl;I56M4M0i>(wljmGgot%bHkKtA@Ny?o)VG-Jz6q%f#7|@bXIHBVnL4Qq_ zaMd#zHwS=Z7~y_>i=g;GDMm6##vPxAzTp8uU{MWU8v5yyK3RW_+XcbP%J7otl^iqE zq;KpH1ax%Gd?`8wyE+a1vBw0)R)r|tWc?Grq$D_I_;E= -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include - -typedef int (*pifi)(int *); -pifi genMulArray(pifi ptr, int b, int len) -{ - /* Code Generation of 12 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0701, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - l = aarch64_genMV_3(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, l); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = aarch64_genMUL_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0003 = aarch64_genADD_3(tmp0003, a, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = aarch64_genMUL_3(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0005 = aarch64_genADD_3(tmp0005, a, tmp0004); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = aarch64_genR_3(tmp0006, tmp0005, immValueZero); - tmp0007 = aarch64_genMUL_3(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - aarch64_genW_3(tmp0003, tmp0007, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -void printArray(int * array, int len) -{ - printf ("Array values (%d) : ", len); - for (int i = 0; i < len; i++) - printf ("%d ", array[i]); - printf ("\n"); -} - -void mulArray(int * array, int len, int value) -{ - for (int i = 0; i < len; i++) - array[i] = array[i] * value; -} - -int main(int argc, char * argv[]) -{ - int arrayLen, mulValue, i, resultOK; - pifi fPtr; - int *array1, *array2; - clock_t startC, stopC, startHg, stopHg; - - if (argc < 3) - { - printf("Give 2 values (array len & mult. coefficient )\n"); - exit(-1); - } - arrayLen = atoi (argv[1]); // Get the - mulValue = atoi (argv[2]); - array1 = calloc (arrayLen, sizeof (int)); - array2 = calloc (arrayLen, sizeof (int)); - for (i = 0; i < arrayLen; i++) - { - array1[i] = random () % 100; - array2[i] = array1[i]; - } - printArray (array1, arrayLen); - printf("// Multiply an array with a constant value\n"); - printf("// Array len = %d constant value %d\n", arrayLen, mulValue); - // Allocate memory for 1024 instructions, generate kernel - fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); - startHg = clock(); - fPtr(array1); // Call generated code - stopHg = clock(); - printArray (array1, arrayLen); - resultOK = 0; - startC = clock(); - mulArray (array2, arrayLen, mulValue); - stopC = clock(); - printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); - for (int i = 0; i < arrayLen; i++) - { - if (array2[i] != array1[i]) - { - printf("Erreur multiplication!\n"); - resultOK = -1; - break; - } - } - return resultOK; -} diff --git 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b/CodeExamples/Array-Mult-Specialization.power.c deleted file mode 100644 index 10fa011..0000000 --- a/CodeExamples/Array-Mult-Specialization.power.c +++ /dev/null @@ -1,1052 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genBGE_1(h2_sValue_t P0); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include - -typedef int (*pifi)(int *); -pifi genMulArray(pifi ptr, int b, int len) -{ - /* Code Generation of 12 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF80F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - l = power_genMV_2(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, l); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = power_genMUL_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0003 = power_genADD_3(tmp0003, a, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = power_genMUL_3(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0005 = power_genADD_3(tmp0005, a, tmp0004); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = power_genR_3(tmp0006, tmp0005, immValueZero); - tmp0007 = power_genMUL_3(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - power_genW_3(tmp0003, tmp0007, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -void printArray(int * array, int len) -{ - printf ("Array values (%d) : ", len); - for (int i = 0; i < len; i++) - printf ("%d ", array[i]); - printf ("\n"); -} - -void mulArray(int * array, int len, int value) -{ - for (int i = 0; i < len; i++) - array[i] = array[i] * value; -} - -int main(int argc, char * argv[]) -{ - int arrayLen, mulValue, i, resultOK; - pifi fPtr; - int *array1, *array2; - clock_t startC, stopC, startHg, stopHg; - - if (argc < 3) - { - printf("Give 2 values (array len & mult. coefficient )\n"); - exit(-1); - } - arrayLen = atoi (argv[1]); // Get the - mulValue = atoi (argv[2]); - array1 = calloc (arrayLen, sizeof (int)); - array2 = calloc (arrayLen, sizeof (int)); - for (i = 0; i < arrayLen; i++) - { - array1[i] = random () % 100; - array2[i] = array1[i]; - } - printArray (array1, arrayLen); - printf("// Multiply an array with a constant value\n"); - printf("// Array len = %d constant value %d\n", arrayLen, mulValue); - // Allocate memory for 1024 instructions, generate kernel - fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); - startHg = clock(); - fPtr(array1); // Call generated code - stopHg = clock(); - printArray (array1, arrayLen); - resultOK = 0; - startC = clock(); - mulArray (array2, arrayLen, mulValue); - stopC = clock(); - printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); - for (int i = 0; i < arrayLen; i++) - { - if (array2[i] != array1[i]) - { - printf("Erreur multiplication!\n"); - resultOK = -1; - break; - } - } - return resultOK; -} diff --git a/CodeExamples/Array-Mult-Specialization.riscv b/CodeExamples/Array-Mult-Specialization.riscv deleted file mode 100755 index 4aa1d4f2ecd1180a921acc40650398f5b9311358..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 37596 zcmeHw3tUuX-v607hl@anqG`8vWZ*dQ;&`hzZBxWSWY^SHt8L%icOn>(ceyz;UbhsT z;i8$EnvzRKgh*s+YU;XXXp^X!k(rrmikH;P1nnqdT>jtRbIutCM4+P2=ly*Cd-R#- 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z@QX`DBdH=gKvQo$_nZ}6S0p;ZQNw^q4N^2((~23Ueb;?ZqZyT!GPJj|LkRIOm1kRy z(<6>{WTZ!XfLz?rA*^1Q%Giae49AzU-gfBGcjefVJ^40UJCH6t1-*gi$CMuJ5d#pQ z{eiqIr1hrk=y)D8qg+1d*~tKDddnWuqxpCQ9F_sH9`=-W2pb@)7fjgo2Yk}=Yf6Up zn)GBuhp?J2#gqFJ96j%*FzrE2(Cd$|XTA`*L^vvI6dXM>r!_}0!jxV&IJ!ssreruO z1KI1aM$wUiS||jm4&kLPFv^NX5gWfLOCrn6>_8dXbt5V|Nv9x^Qm%&jzNRO?3)3FAluyUzo zrN_sr9<9;thn`7Qg0GhEu!kP4jh}^{e3Bq5tLf1*X3C%Pr8Q?V^eBDxQp2YZq3Y4z zl=LE1CFLH8=itbuKMA-k4~IN)SH5N=M9(JFOU;)aKd524cMN*tR3-RS zCc5Yeg{PhYgp5)<2kxu)?ro;`ztcFbK)vaqhvlu?hSCq1f$wCrphtUaitbNJxF*a* zA8M8_-5=IW?@!poj-wmOMM2e3-%zh&bcA#aV7(C$4M*)31lI|UaRokIJ+nEkPHj}k UYSMJt -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include - -typedef int (*pifi)(int *); -pifi genMulArray(pifi ptr, int b, int len) -{ - /* Code Generation of 11 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t l = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x77F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - l = riscv_genMV_2(l, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((len))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGE_3(i, l, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = riscv_genMUL_4(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0003 = riscv_genADD_3(tmp0003, a, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = riscv_genMUL_4(tmp0004, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0005 = riscv_genADD_3(tmp0005, a, tmp0004); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = riscv_genR_3(tmp0006, tmp0005, immValueZero); - tmp0007 = riscv_genMUL_4(tmp0007, tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - riscv_genW_3(tmp0003, tmp0007, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001]; - i = riscv_genBGE_3(i, l, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -void printArray(int * array, int len) -{ - printf ("Array values (%d) : ", len); - for (int i = 0; i < len; i++) - printf ("%d ", array[i]); - printf ("\n"); -} - -void mulArray(int * array, int len, int value) -{ - for (int i = 0; i < len; i++) - array[i] = array[i] * value; -} - -int main(int argc, char * argv[]) -{ - int arrayLen, mulValue, i, resultOK; - pifi fPtr; - int *array1, *array2; - clock_t startC, stopC, startHg, stopHg; - - if (argc < 3) - { - printf("Give 2 values (array len & mult. coefficient )\n"); - exit(-1); - } - arrayLen = atoi (argv[1]); // Get the - mulValue = atoi (argv[2]); - array1 = calloc (arrayLen, sizeof (int)); - array2 = calloc (arrayLen, sizeof (int)); - for (i = 0; i < arrayLen; i++) - { - array1[i] = random () % 100; - array2[i] = array1[i]; - } - printArray (array1, arrayLen); - printf("// Multiply an array with a constant value\n"); - printf("// Array len = %d constant value %d\n", arrayLen, mulValue); - // Allocate memory for 1024 instructions, generate kernel - fPtr = genMulArray ((pifi) h2_malloc (1024), mulValue, arrayLen); - startHg = clock(); - fPtr(array1); // Call generated code - stopHg = clock(); - printArray (array1, arrayLen); - resultOK = 0; - startC = clock(); - mulArray (array2, arrayLen, mulValue); - stopC = clock(); - printf ("C version %ld Hg version %ld\n\n", stopC - startC, stopHg - startHg); - for (int i = 0; i < arrayLen; i++) - { - if (array2[i] != array1[i]) - { - printf("Erreur multiplication!\n"); - resultOK = -1; - break; - } - } - return resultOK; -} diff --git a/CodeExamples/Array-St-flt.aarch64 b/CodeExamples/Array-St-flt.aarch64 deleted file mode 100755 index d2163ddebe7e345e7e3693996edcc83b6672f8a7..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 48112 zcmeHw3w)H-nfH0;ok=G5kVHVB@FqY-GzkPnP%LiySGGIsoX3WG6|En`{u z&SP^~2EcZ_3eS{2<(`nNmFtvjbV;|&CIHK9Cif_JrT{bLDhbJT$T;DcG9=vQfCws= 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zDB@0ctB2N!tzcL*He2K(GB=#oI!|aFEepF`tsQ<}OdG%q`dw{qUo)2J-Hq5cN#K*X zmtm0xSG922txM>gU7=tCb-Xnh4lpl<- zd5YbtRzG;*Q^6Au%uoqf1@>Ax&@4h&Ph(dr=x9p?a1rD?9V)7^F@RbiL$tN2{LqW? zVslJ+B_~UN^hv$6VnlsAhG+a)W;3PBogphqY8)V9#fg_p1QdO}&E!$_5@7I9{DW>V z;W-~6IyR{2x7bXC@VhAqP~#NBp+}9M6(2g6gsUF>ivEzz1cZKv#T_7DEbpNlSiG9fUwLk&OLHHDf;Ogi?JHG=)z<4>i1rBFAP21!ijy8^|u}|Sc8tq zuhwU?Wrht&sq(MnRPHs1r{8L+uv*7mltiB_zhui=;UQ5Ky;|?xBug1qp(0PptQ@CbgkbMndYx-)xVczuuu_Os!*{uS9UD7N4tM%<=l0LRmCkd4P z6g}=uV=Qw+i};vxKX@ z$+$THB*O@|;|@XbN2M6aAQ_j|OOs)QTKi2wU{eiW8v6N?K3RYDdj-Ldl;I`Ot27s- zNx$$uK|nvvvObDV!7fTeA9+Av>{f` -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_F_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_F_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STUR_RRI_F_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_F_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STUR_RRI_F_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_F_128_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1e4 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_F_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_F_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_F_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STUR_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STUR_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 128) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_F_128_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int, float); -typedef double (*pifsi)(double *, int, double); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - aarch64_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != (float) i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%2.2f ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK, loopLimit; - float in132, res32; - double in164, res64; - pifii fPtr32; - pifsi fPtr64; - - float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - - in0 = atoi (argv[1]); // Get index value - in164 = in132 = atof (argv[2]); // fp number to store - resultOK = 0; - loopLimit = sizeof(f32) / sizeof (float); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0, in132); // Call generated code - printf("%2.2f, %2.2f\n", f32[in0], in132); - CHECK (f32, in0, resultOK, loopLimit, in132); - PRINTARRAY("32 bits : ", f32, loopLimit); - printf ("ResultOK %d\n", resultOK); - - loopLimit = sizeof(f64) / sizeof (double); - fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions - res64 = fPtr64(f64, in0, in164); // Call generated code - printf("%2.2f, %2.2f\n", f64[in0], in164); - CHECK (f64, in0, resultOK, loopLimit, in164); - PRINTARRAY("64 bits : ", f64, loopLimit); - printf ("ResultOK %d\n", resultOK); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-St-flt.power b/CodeExamples/Array-St-flt.power deleted file mode 100755 index 652c5e42a177b7c559ea7c32694a4c39e52b9183..0000000000000000000000000000000000000000 GIT binary patch literal 0 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zKS>Ptr$SO!8Kgk6J*U#-@8fSQ(d)t^H7BWKLuvA#qK#M_PpW~%V~OUIG4uE^o@7~iyPJ5)_~lL$l7-6g@!Z2@DLu3=tin=+lclo+cXd)?Qj`^fk<23n z@k<0Z&b19+lJTckU*DC#p&6D!Xtv0oET3E!#gicBYFsjZd9Khp4}_istNy3_KmFb( j31XhXGf$MXQVm?r9c?SEFH+_I907yl#-s`-McMxaKA8Jw diff --git a/CodeExamples/Array-St-flt.power.c b/CodeExamples/Array-St-flt.power.c deleted file mode 100644 index 2b64842..0000000 --- a/CodeExamples/Array-St-flt.power.c +++ /dev/null @@ -1,909 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_STFS_RRI_F_32_1(r1,r0,i0) do /* w */ { power_G32(((0x34 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STFD_RRI_F_64_1(r1,r0,i0) do /* w */ { power_G32(((0x36 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STFS_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STFD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int, float); -typedef double (*pifsi)(double *, int, double); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x381F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = power_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - power_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != (float) i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%2.2f ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK, loopLimit; - float in132, res32; - double in164, res64; - pifii fPtr32; - pifsi fPtr64; - - float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - - in0 = atoi (argv[1]); // Get index value - in164 = in132 = atof (argv[2]); // fp number to store - resultOK = 0; - loopLimit = sizeof(f32) / sizeof (float); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0, in132); // Call generated code - printf("%2.2f, %2.2f\n", f32[in0], in132); - CHECK (f32, in0, resultOK, loopLimit, in132); - PRINTARRAY("32 bits : ", f32, loopLimit); - printf ("ResultOK %d\n", resultOK); - - loopLimit = sizeof(f64) / sizeof (double); - fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions - res64 = fPtr64(f64, in0, in164); // Call generated code - printf("%2.2f, %2.2f\n", f64[in0], in164); - CHECK (f64, in0, resultOK, loopLimit, in164); - PRINTARRAY("64 bits : ", f64, loopLimit); - printf ("ResultOK %d\n", resultOK); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-St-flt.riscv b/CodeExamples/Array-St-flt.riscv deleted file mode 100755 index 29fa139cbb89c72cecd6d6422cdbca563d5e9e38..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33332 zcmeHw3tUvy+V|eGHw+3PhGuss1~$YCqhfWs8sZ>QCLXmqeedZvA`HlPxXBD-+t_@Aqr# znzf#_o@cG+dG>#;z1G^By{9CO9M1DRryV-(7mlbVKc2e}@!CIgoFC%*I0M&{i{gx2 z80XJu$|D}0i-!OO5&0AZ1UqOu>ZK3{ngW#}o67TF9*=~2j8$W;oOqOjQaooK!?8em za3M+^q6PKk@hqf+Z5aaTMddn*P#%JE3N4^1P`Re#Jn+whZWIj2r=XRM{=uFe^%TcN zJ;k%oh%yRV`R`E<@>d7dkLI~CDEHN`4S5tu9?fzCva==($WD*V&dM#E99xiOOM78( zTx?c${@}QDlP%9QNadxvh(Br6)A&`+1JywX`M4KC4+LuWCImVH5r`)Mp(g?zR0sKv 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h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32F_FSW_RRI_F_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x27 & 0x7f) >> 0)); } while(0); -#define RV64D_FSW_RRI_F_64_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x3 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x27 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32F_FSW_RRI_F_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'f') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV64D_FSW_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef float (*pifii)(float *, int, float); -typedef double (*pifsi)(double *, int, double); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t value = {H2REGISTER, 'f', 1, (wordSize), 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF1F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - riscv_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != (float) i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf("%2.2f ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resultOK, loopLimit; - float in132, res32; - double in164, res64; - pifii fPtr32; - pifsi fPtr64; - - float f32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - double f64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - - in0 = atoi (argv[1]); // Get index value - in164 = in132 = atof (argv[2]); // fp number to store - resultOK = 0; - loopLimit = sizeof(f32) / sizeof (float); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 32); // Generate instructions - res32 = fPtr32(f32, in0, in132); // Call generated code - printf("%2.2f, %2.2f\n", f32[in0], in132); - CHECK (f32, in0, resultOK, loopLimit, in132); - PRINTARRAY("32 bits : ", f32, loopLimit); - printf ("ResultOK %d\n", resultOK); - - loopLimit = sizeof(f64) / sizeof (double); - fPtr64 = (pifii) gen_Array_St(ptr, 64); // Generate instructions - res64 = fPtr64(f64, in0, in164); // Call generated code - printf("%2.2f, %2.2f\n", f64[in0], in164); - CHECK (f64, in0, resultOK, loopLimit, in164); - PRINTARRAY("64 bits : ", f64, loopLimit); - printf ("ResultOK %d\n", resultOK); - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Array-St.aarch64 b/CodeExamples/Array-St.aarch64 deleted file mode 100755 index 46f3931aa6143e3c437560d01afc4c63e1c579c4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 48056 zcmeHw3w%`7x$oMu=aqLzBJaXZfP!ceK#QPwm?R)lQ81xOkKRru$t0N)X2Q$_gU~Xl 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use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifli)(long int *, int, long int); -typedef int (*pifii)(int *, int, int); -typedef int (*pifsi)(short *, int, short); -typedef int (*pifci)(char *, int, char); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0107, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = aarch64_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - aarch64_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf(" %2d ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK, loopLimit; - pifli fPtr64; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - - if (argc < 2) - { - printf("Give 1 value\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); - resultOK = 0; - - long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a64) / sizeof (long int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions - res = fPtr64(a64, in0, 42); // Call generated code - CHECK (a64, in0, resultOK, loopLimit, 42); - PRINTARRAY("64 bits : ", a64, loopLimit); - - int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a32) / sizeof (int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions - res = fPtr32(a32, in0, 42); // Call generated code - CHECK (a32, in0, resultOK, loopLimit, 42); - PRINTARRAY("32 bits : ", a32, loopLimit); - - short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a16) / sizeof (short); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions - res = fPtr16(a16, in0, 42); // Call generated code - PRINTARRAY("16 bits : ", a16, loopLimit); - CHECK (a16, in0, resultOK, loopLimit, 42); - - char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a8) / sizeof (char); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions - res = fPtr8(a8, in0, 42); // Call generated code - CHECK (a8, in0, resultOK, loopLimit, 42); - PRINTARRAY("8 bits : ", a8, loopLimit); - - if (resultOK != 0) - return -1; - return 0; -} diff --git a/CodeExamples/Array-St.power b/CodeExamples/Array-St.power deleted file mode 100755 index 6965a9b9ef372956b4fbb5adc0aee89a3dbfcda2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78304 zcmeHw3w&JFdFQz^BWYyG^7w%<3Be<!R0Sk zG%lorA|ML!dyTkSPa}LSsUn8WWo)|dI2(2P|_nW;dF%-2AUoc=IJsG zBt6m!HfgMZQW_zD*;oHNs@(sMCFu=pVTW)X*HG0Eg56`ipsp9x^$hIO9W&6#N7;C9 z)bat!_6+o+jF(^jDq1G%ewJ)xz1PF408rL5@HvGR29lQ7Cs2?5oam*LCBzopUM{_y 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fscOI23_OV)-B+#;vekd}qpCh%eYIa1S@C}Wt?;%2 diff --git a/CodeExamples/Array-St.power.c b/CodeExamples/Array-St.power.c deleted file mode 100644 index a90192b..0000000 --- a/CodeExamples/Array-St.power.c +++ /dev/null @@ -1,909 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifli)(long int *, int, long int); -typedef int (*pifii)(int *, int, int); -typedef int (*pifsi)(short *, int, short); -typedef int (*pifci)(char *, int, char); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 5, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x383F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * (wordSize)) / 8)}); - tmp0001 = power_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - power_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf(" %2d ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK, loopLimit; - pifli fPtr64; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - - if (argc < 2) - { - printf("Give 1 value\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); - resultOK = 0; - - long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a64) / sizeof (long int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions - res = fPtr64(a64, in0, 42); // Call generated code - CHECK (a64, in0, resultOK, loopLimit, 42); - PRINTARRAY("64 bits : ", a64, loopLimit); - - int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a32) / sizeof (int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions - res = fPtr32(a32, in0, 42); // Call generated code - CHECK (a32, in0, resultOK, loopLimit, 42); - PRINTARRAY("32 bits : ", a32, loopLimit); - - short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a16) / sizeof (short); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions - res = fPtr16(a16, in0, 42); // Call generated code - PRINTARRAY("16 bits : ", a16, loopLimit); - CHECK (a16, in0, resultOK, loopLimit, 42); - - char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a8) / sizeof (char); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions - res = fPtr8(a8, in0, 42); // Call generated code - CHECK (a8, in0, resultOK, loopLimit, 42); - PRINTARRAY("8 bits : ", a8, loopLimit); - - if (resultOK != 0) - return -1; - return 0; -} diff --git a/CodeExamples/Array-St.riscv b/CodeExamples/Array-St.riscv deleted file mode 100755 index a53c8cb343de46718a54e0f720fbbacecf9a567c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 33256 zcmeHwdt6l2+W+3OH_Rx6D4Jc5BLf@a;CSnF%1#P6h@4D4YIXX(^%)UH7>md+D$ujQj5xnkj#j@pqUx!BzOsl(8xndYHDVJwgFKtzwfj5-otnoU*FH?{iCgG z)_T@@p0(EVtnXTTt+f|>KNml44A1kNcImiZIifQCcapq;j^nDv z@yyjBjhvSL7o>x{=%V~lJU0pHzV&NE966FlvE1PFv}uFWQwF7{Wz2qRP*$2F`N`qK z2BoEE4j-0ccG%5BRbI-A_!GuIj9;Z4C=a^G#y7$BfTMB);phs0BOU`>PdK_L53(KE zh2*qLj{wn>PBKJuV%$(&%>1=;C<9J(X=#*K@PFt1W807OBkugei;j&a7wuU8`@i)Y z`Onw?@u!dOyXlsH_RQ%#;qIIDr`P^r9{)h|>P7c|Lpk_fR9_CbqN@+w6u2QiG^ND& z(7yv+C3f*Y1iI0Oz7=$^5C88$8-3^npt+|M`C#r;CzUzXCtU(v=9Awr(DgpF1@uH8 zelFGK%uGtPInti7ahbE74ldJ{m1WQ3Y)_>*DI$4BQWlrww5M@1lhV`e$(+@SrcSmx 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ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 1 pointer, an index and return int */ -typedef int (*pifli)(long int *, int, long int); -typedef int (*pifii)(int *, int, int); -typedef int (*pifsi)(short *, int, short); -typedef int (*pifci)(char *, int, char); - -/* C compilette prototype */ -h2_insn_t * gen_Array_St(h2_insn_t * ptr, int wordSize) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t index = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t value = {H2REGISTER, 'i', 1, (wordSize), 12, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1F1F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, index, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * (wordSize)) / 8)}, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, a, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - riscv_genW_3(tmp0001, value, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -#define CHECK(ARRAY, INDICE, RESULT, LIMIT, VALUE) \ - for (int i = 0; i < LIMIT; i++) \ - { \ - if (INDICE == i) \ - { \ - if (ARRAY[INDICE] != VALUE) \ - { \ - RESULT ++; \ - } \ - } \ - else \ - { \ - if (ARRAY[i] != i) \ - { \ - RESULT ++; \ - } \ - } \ - } - -#define PRINTARRAY(MSG, ARRAY, LIMIT)\ - printf (MSG); \ - for (int i = 0; i < LIMIT; i++) \ - { \ - printf(" %2d ", ARRAY[i]); \ - } \ - printf ("\n"); - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK, loopLimit; - pifli fPtr64; - pifii fPtr32; - pifsi fPtr16; - pifci fPtr8; - - - if (argc < 2) - { - printf("Give 1 value\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 - printf ("Size of LONG INT %ld, INTs %ld, SHORTs %ld, CHARs %ld\n", sizeof (long int), sizeof (int), sizeof (short), sizeof (char)); - resultOK = 0; - - long int a64[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a64) / sizeof (long int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr64 = (pifii) gen_Array_St(ptr, 8 * sizeof (long int)); // Generate instructions - res = fPtr64(a64, in0, 42); // Call generated code - CHECK (a64, in0, resultOK, loopLimit, 42); - PRINTARRAY("64 bits : ", a64, loopLimit); - - int a32[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a32) / sizeof (int); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr32 = (pifii) gen_Array_St(ptr, 8 * sizeof (int)); // Generate instructions - res = fPtr32(a32, in0, 42); // Call generated code - CHECK (a32, in0, resultOK, loopLimit, 42); - PRINTARRAY("32 bits : ", a32, loopLimit); - - short a16[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a16) / sizeof (short); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr16 = (pifsi) gen_Array_St(ptr, 8 * sizeof (short)); // Generate instructions - res = fPtr16(a16, in0, 42); // Call generated code - PRINTARRAY("16 bits : ", a16, loopLimit); - CHECK (a16, in0, resultOK, loopLimit, 42); - - char a8[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; - loopLimit = sizeof(a8) / sizeof (char); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr8 = (pifci) gen_Array_St(ptr, 8 * sizeof (char)); // Generate instructions - res = fPtr8(a8, in0, 42); // Call generated code - CHECK (a8, in0, resultOK, loopLimit, 42); - PRINTARRAY("8 bits : ", a8, loopLimit); - - if (resultOK != 0) - return -1; - return 0; -} diff --git a/CodeExamples/Array-Sum-2D.aarch64 b/CodeExamples/Array-Sum-2D.aarch64 deleted file mode 100755 index 2696a911a59ff2cf42f7e908bdd9b1c704fe4397..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52312 zcmeHwe_&MAmH&P7W|B!JzevJwgb9cunuK5SL$FK|5Lpl~LB(~qlSwipS;8dDOf(29 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z66chH$un33c2erSMo7XH=0KZKaWa z$U}Q>Mv(eSjuA#hTUEvFWXe3o3Vdr<`&|`q{a)eLC?71ujV;##evqT6cws*6Y87Ck zv7pA~t6>FIYduITT)$Vu-0t@J@XelxfD>`p!*Wpq>1(L-vjVQ=0>8Tne!dq`;H~FI zUf`~gZ5wTvg+n5RXb(jSq5M=Qbl6{3>W#O)=6hdK=ewM8aGIE ze$plx0hNBa$-$#&+)kIBKf5029wV-+5u)RYDt(j5fe^jF#hvix0O8Q3#^;I-orl8b z4(e627>b3{ ztM|%ioJ80C!U;d4^|uHySo;q1uhxa%lj-T0H(iQ<#iw#tAdcP%Q(?7!jDv&xvI_@C zZzK7aU{(zeWu?-qb>;~&y&6xc{G;VxBhwd4f@(c_g-oE{gQMUO+|lXR0Y*9@{^(Nc z)>|b&=~=`IUX`ER+i@GytNG~xnf{Cs8UC!O@W!b0YCPReMvdzpIMLaWJIJ^Um(rgC;rnY5>DBuC(SH^gqlmcS ziq3y8;*9yLb^0@OJ{{NnQ3;~+{|Rt1a4R;|I>Tua3|BP13M;n_IJD-h(yMjZ^t4PL zPzj~0(kb_?sPt;xqGqc|5HEj4_9Q$+OYyJfJ54fuxk8k#%2$E^2oLc;Ndcs*(nrr# zr8;>ULOp|9!DLeIY?b+Mjf%`NBEe4^6HzD}!~TB+;!w9u_mq=hz4PTt}<7N72{mpw^B>06gyr}dlPx|ha@=Fxq>=zEb5@x)j zac9R#f0QaFE?EpBfM>M+iC$C|9Jl -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int(*pifpii)(int *, int, int); - -// Sum a 2D array with a constant -// Code specialisation on stride and constant value -pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ -{ - /* Code Generation of 22 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0F07, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - sum = aarch64_genMV_3(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = aarch64_genMV_3(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = aarch64_genCMP_2(line, nLine); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = aarch64_genMV_3(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = aarch64_genCMP_2(column, nColumn); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0003 = aarch64_genMUL_3(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}); - tmp0004 = aarch64_genADD_3(tmp0004, tmp0003, column); - if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); - tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = aarch64_genADD_3(tmp0006, a, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = aarch64_genADD_3(tmp0008, sum, tmp0007); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = aarch64_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = aarch64_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = aarch64_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, sum, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) -{ - int sum = 0; - for (int line = 0; line < nLine; line = line + 1) - for (int column = 0; column < nColumn; column = column + 1) - sum = sum + a[line][column] + constant; - return sum; -} - -int main(int argc, char * argv[]) -{ - pifpii ptr; - int in0, resultH, resultS; - int constant, nLine, nColumn; - - if (argc < 3) - { - printf ("./%s \n", argv[0]); - exit(-1); - } - nLine = atoi(argv[1]); - nColumn = atoi(argv[2]); - constant = atoi(argv[3]); - - printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); - int a32[nLine][nColumn]; // Create & fill the array - for (int line = 0; line < nLine; line++) - { - printf ("%d: ", line); - for (int column = 0; column < nColumn; column++) - { - a32[line][column] = line+column; - printf ("%d ", a32[line][column]); - } - printf ("\n"); - } - ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions - resultH = ptr((int *)a32, nLine, nColumn); // Call generated code - - resultS = sumArray(nLine, nColumn, a32, constant); - printf ("%d %d\n", resultH, resultS); - if (resultS == resultH) - return 0; - else - return -1; - -} diff --git a/CodeExamples/Array-Sum-2D.power b/CodeExamples/Array-Sum-2D.power deleted file mode 100755 index c8addeb9d750a8f9c08b247293f482866053ef8e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78352 zcmeHw4}4VBmH&M+lVn0d7$9O)G=qRm*d&BM#X&$OAxHwKS%FG_tG~&R49V1F5+@TK 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-#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBGE_1(h2_sValue_t P0); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int(*pifpii)(int *, int, int); - -// Sum a 2D array with a constant -// Code specialisation on stride and constant value -pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ -{ - /* Code Generation of 22 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1F83F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - sum = power_genMV_2(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = power_genMV_2(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = power_genCMP_2(line, nLine); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = power_genMV_2(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = power_genCMP_2(column, nColumn); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0003 = power_genMUL_3(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}); - tmp0004 = power_genADD_3(tmp0004, tmp0003, column); - if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); - tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = power_genADD_3(tmp0006, a, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = power_genADD_3(tmp0008, sum, tmp0007); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = power_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = power_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = power_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, sum); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) -{ - int sum = 0; - for (int line = 0; line < nLine; line = line + 1) - for (int column = 0; column < nColumn; column = column + 1) - sum = sum + a[line][column] + constant; - return sum; -} - -int main(int argc, char * argv[]) -{ - pifpii ptr; - int in0, resultH, resultS; - int constant, nLine, nColumn; - - if (argc < 3) - { - printf ("./%s \n", argv[0]); - exit(-1); - } - nLine = atoi(argv[1]); - nColumn = atoi(argv[2]); - constant = atoi(argv[3]); - - printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); - int a32[nLine][nColumn]; // Create & fill the array - for (int line = 0; line < nLine; line++) - { - printf ("%d: ", line); - for (int column = 0; column < nColumn; column++) - { - a32[line][column] = line+column; - printf ("%d ", a32[line][column]); - } - printf ("\n"); - } - ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions - resultH = ptr((int *)a32, nLine, nColumn); // Call generated code - - resultS = sumArray(nLine, nColumn, a32, constant); - printf ("%d %d\n", resultH, resultS); - if (resultS == resultH) - return 0; - else - return -1; - -} diff --git a/CodeExamples/Array-Sum-2D.riscv b/CodeExamples/Array-Sum-2D.riscv deleted file mode 100755 index 80c5e7ead5d7ee0b2785ff843fead7681112aec0..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 41540 zcmeHweOy#k{{Nl11A`AChGlKFP7GWpzBnqjeXHFRaTMJ(b=9qHzgr{1h_pO4Gnl!i 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zqqhukswZJhYg7#i@KIxVkX(j9Gk4OXwM@WOdZa^PJp!$8Nsrb7X*{pvSg~9?hlh&fvHQ>4JPH^*abz(W5!) z;BD+6;>ipYmjE(=Lmz-Yg6* -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int(*pifpii)(int *, int, int); - -// Sum a 2D array with a constant -// Code specialisation on stride and constant value -pifpii genAddArray2D(pifpii ptr, int stride, int constant) /* C compilette prototype */ -{ - /* Code Generation of 20 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t nLine = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t nColumn = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1FFF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - sum = riscv_genMV_2(sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = riscv_genMV_2(line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = riscv_genBGE_3(line, nLine, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = riscv_genMV_2(column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = riscv_genBGE_3(column, nColumn, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0003 = riscv_genMUL_4(tmp0003, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((stride))}, immValueZero); - tmp0004 = riscv_genADD_3(tmp0004, tmp0003, column); - if (!tmp0004.dontFree) h2_freeReg(tmp0003.regNro); - tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = riscv_genADD_3(tmp0006, a, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = riscv_genADD_3(tmp0008, sum, tmp0007); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = riscv_genADD_3(sum, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((constant))}); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - column = riscv_genADD_3(column, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - line = riscv_genADD_3(line, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, sum); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005]; - line = riscv_genBGE_3(line, nLine, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000001]; - column = riscv_genBGE_3(column, nColumn, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -int sumArray(int nLine, int nColumn, int a[nLine][nColumn], int constant) -{ - int sum = 0; - for (int line = 0; line < nLine; line = line + 1) - for (int column = 0; column < nColumn; column = column + 1) - sum = sum + a[line][column] + constant; - return sum; -} - -int main(int argc, char * argv[]) -{ - pifpii ptr; - int in0, resultH, resultS; - int constant, nLine, nColumn; - - if (argc < 3) - { - printf ("./%s \n", argv[0]); - exit(-1); - } - nLine = atoi(argv[1]); - nColumn = atoi(argv[2]); - constant = atoi(argv[3]); - - printf ("Array %dx%d. Constant Value %d\n", nLine, nColumn, constant); - int a32[nLine][nColumn]; // Create & fill the array - for (int line = 0; line < nLine; line++) - { - printf ("%d: ", line); - for (int column = 0; column < nColumn; column++) - { - a32[line][column] = line+column; - printf ("%d ", a32[line][column]); - } - printf ("\n"); - } - ptr = (pifpii) genAddArray2D (h2_malloc (1024), nColumn, constant);// Generate instructions - resultH = ptr((int *)a32, nLine, nColumn); // Call generated code - - resultS = sumArray(nLine, nColumn, a32, constant); - printf ("%d %d\n", resultH, resultS); - if (resultS == resultH) - return 0; - else - return -1; - -} diff --git a/CodeExamples/CelciusFarenheit.aarch64 b/CodeExamples/CelciusFarenheit.aarch64 deleted file mode 100755 index 3cc903f9dd5b16ccb2d95517dd25b29752bc1661..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 48128 zcmeHw3w&F}mG@j-$&%ks@&s}nClFF>Cjml2LL=J=X*PibJCx9NE6cWQt2mM)$sv&J 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+0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genC2F(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); - tmp0001 = aarch64_genDIV_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - r = aarch64_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - if (!r.dontFree) h2_freeReg(tmp0001.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -h2_insn_t * genF2C(h2_insn_t * ptr) -{ - /* Code Generation of 4 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = aarch64_genMUL_3(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); - r = aarch64_genDIV_3(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); - if (!r.dontFree) h2_freeReg(tmp0000.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifi fC2F, fF2C; - - resultOK = 0; - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - printf("// Compilette for conversion from celcius to farenheit\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fC2F = (pifi) genC2F (ptr); // - res = fC2F(in0); // Call generated code - printf("%d (celcius) -> (farenheit)%d\n", in0, res); - if (res != (in0 * 9 / 5 + 32)) - resultOK += 1; - printf("// Compilette for conversion from farenheit to celcius\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fF2C = (pifi) genF2C (ptr); // - res = fF2C(in0); // Call generated code - printf("%d (farenheit) -> (celcius)%d\n", in0, res); - if (res != ((in0 - 32) * 5 / 9)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/CelciusFarenheit.power b/CodeExamples/CelciusFarenheit.power deleted file mode 100755 index da8d19922cdd6e1a180e5a93d5767b5a7f8aadbe..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78272 zcmeHw3wRvGm2UOSNE%rWj~^HT4sK(cNRIWeVa*t9G?Hao@(aZeaB|6xM$$+ckYU2+Q$Ex+KZJNf^VPh9C%6Xj3MK}*#=qM00 zHY7dF%`$PF$1Y>($U8U=7Xej04*Ml*1)YM7*#W7Zn-~hn>5=Dfnm{uJm4pP-WSIn< z9%&9cg957{29N>;xStEYN1ZxRK7yqHv~+wH^+?XK9-JwNH_7%=+2yp9 zUqRIm#m#}*rB@a=*Dt-YC>knSLhX_)#FuE+Y}|?~g0$qUZ~FWn&HIMPBQ!o;MG_(*IJi?erXDPbqf64 z6!_bK*KsBuWVd8;R;0jRoB}^R1->u^p84AXF&6emBB2Nix5lD$scZ5f6A1)k4Xn{0 z3;P=V(ZKC~))J0{V*a`qYwbjym#8csW&gk#54PIZ6fjCcN2?m6-4}2G!v< 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z0$!>wxij{%te-%}4oC`JRgeUU`n;W@em8&PhhDcG$~l1@>rYYtq*G9SPfaYzCb51x z5Q#V8wWdQZ0UKtlvU%^iyq0)+m;QW~ayDFhDA -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genC2F(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x780F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); - tmp0001 = power_genDIV_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - r = power_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - if (!r.dontFree) h2_freeReg(tmp0001.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -h2_insn_t * genF2C(h2_insn_t * ptr) -{ - /* Code Generation of 4 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x780F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = power_genMUL_3(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}); - r = power_genDIV_3(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}); - if (!r.dontFree) h2_freeReg(tmp0000.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifi fC2F, fF2C; - - resultOK = 0; - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - printf("// Compilette for conversion from celcius to farenheit\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fC2F = (pifi) genC2F (ptr); // - res = fC2F(in0); // Call generated code - printf("%d (celcius) -> (farenheit)%d\n", in0, res); - if (res != (in0 * 9 / 5 + 32)) - resultOK += 1; - printf("// Compilette for conversion from farenheit to celcius\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fF2C = (pifi) genF2C (ptr); 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VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genC2F(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x73F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}, immValueZero); - tmp0001 = riscv_genDIV_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}, immValueZero); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - r = riscv_genADD_3(r, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - if (!r.dontFree) h2_freeReg(tmp0001.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - -h2_insn_t * genF2C(h2_insn_t * ptr) -{ - /* Code Generation of 4 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x73F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genSUB_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(32)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = riscv_genMUL_4(tmp0000, r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(5)}, immValueZero); - r = riscv_genDIV_4(r, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(9)}, immValueZero); - if (!r.dontFree) h2_freeReg(tmp0000.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, res, resultOK; - pifi fC2F, fF2C; - - resultOK = 0; - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - printf("// Compilette for conversion from celcius to farenheit\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fC2F = (pifi) genC2F (ptr); // - res = fC2F(in0); // Call generated code - printf("%d (celcius) -> (farenheit)%d\n", in0, res); - if (res != (in0 * 9 / 5 + 32)) - resultOK += 1; - printf("// Compilette for conversion from farenheit to celcius\n"); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fF2C = (pifi) genF2C (ptr); // - res = fF2C(in0); // Call generated code - printf("%d (farenheit) -> (celcius)%d\n", in0, res); - if (res != ((in0 - 32) * 5 / 9)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Constants-Operations.aarch64 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uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(); - -pifi genConstAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstSub(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstMul(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genMUL_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstDiv(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0300, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genDIV_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, res; - int isOK = true; - pifi fPtr; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - - printf("// Compilette for simple addition between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstAdd (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d + %d = %d\n", 42, in0, res); - isOK &= (res == (42+in0)); - - printf("// Compilette for simple substraction between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstSub (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d - %d = %d\n", 42, in0, res); - isOK &= (res == (42 - in0)); - - printf("// Compilette for simple multiplication between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstMul (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d * %d = %d\n", 42, in0, res); - isOK &= (res == (42 * in0)); - - printf("// Compilette for simple division between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstDiv (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d / %d = %d\n", 42, in0, res); - isOK &= (res == (42 / in0)); - - return isOK?0:1; -} diff --git a/CodeExamples/Constants-Operations.power b/CodeExamples/Constants-Operations.power deleted file mode 100755 index 24b1682f4dcd421f03e8efae3b955c4c93e19474..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78360 zcmeHw4PaE&mH&M+lVn0d7$9K$eoS5_ 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-bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(); - -pifi genConstAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstSub(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstMul(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genMUL_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstDiv(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genDIV_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, res; - int isOK = true; - pifi fPtr; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - - printf("// Compilette for simple addition between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstAdd (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d + %d = %d\n", 42, in0, res); - isOK &= (res == (42+in0)); - - printf("// Compilette for simple substraction between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstSub (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d - %d = %d\n", 42, in0, res); - isOK &= (res == (42 - in0)); - - printf("// Compilette for simple multiplication between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstMul (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d * %d = %d\n", 42, in0, res); - isOK &= (res == (42 * in0)); - - printf("// Compilette for simple division between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstDiv (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d / %d = %d\n", 42, in0, res); - isOK &= (res == (42 / in0)); - - return isOK?0:1; -} diff --git a/CodeExamples/Constants-Operations.riscv b/CodeExamples/Constants-Operations.riscv deleted file mode 100755 index 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h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} - -/* End Header autogenerated part */ -#include // -*- c -*- -#include - -typedef int (*pifi)(); - -pifi genConstAdd(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x33F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genADD_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstSub(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x33F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genSUB_3(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstMul(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x33F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genMUL_4(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -pifi genConstDiv(pifi ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x33F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genDIV_4(r, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(42)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (pifi) ptr; -} - -int main(int argc, char * argv[]) -{ - int in0, res; - int isOK = true; - pifi fPtr; - - if (argc < 2) - { - printf("Give 1 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in0 - fPtr = (pifi) h2_malloc (1024); // Allocate memory for 1024 instructions - - printf("// Compilette for simple addition between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstAdd (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d + %d = %d\n", 42, in0, res); - isOK &= (res == (42+in0)); - - printf("// Compilette for simple substraction between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstSub (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d - %d = %d\n", 42, in0, res); - isOK &= (res == (42 - in0)); - - printf("// Compilette for simple multiplication between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstMul (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d * %d = %d\n", 42, in0, res); - isOK &= (res == (42 * in0)); - - printf("// Compilette for simple division between constants\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = genConstDiv (fPtr, in0); // Generate instructions - res = fPtr(); // Call generated code - printf("%d / %d = %d\n", 42, in0, res); - isOK &= (res == (42 / in0)); - - return isOK?0:1; -} diff --git a/CodeExamples/If-in-Loop.aarch64 b/CodeExamples/If-in-Loop.aarch64 deleted file mode 100755 index 7d24abd538baab0e56deefcc7b83b7db5c559bfe..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52344 zcmeHw34B}CmG^ymk}dC!ZL&flXMqr~odrTdLL=J=Ax$8`2}_6hD$BOKOdQEbatI`C z6atiCY2qdV+o#Ma@8QKo@KtCKpTRLQ>DG4oKTR={r&6Lhe2EyW!p!uJ>$XBu? z+wt=KzTb~$zjyCF_uO;OIrrS}aZ-k=93`pTXR_R9vYZOTk}(x3`A9Z8*GYQo zEKZ~-?WBM?__a4ATsqdgAFQMJYavQe=!^-c%lcHP%3X_c#OFYde2G{k>r1AW@sfWP z%IaBJb5l)Ob6rVulecwKiQDb3ZJd8eX~0)HN61a|33vH5*YTRDz0-M2TqvD~GaF|H z&K#Wjkt-8KgK$YUl9k$?=#ZW>ac1Ep7U`rigwORL80Fj(eBp=po{J#qLFfeua*0+V z__ayki<7{wPXfOn3H%#?J8;Gy69GuX59u!v{HsaejwEoRk%-Q`B=AbW$FT8i)6R0l zM7!{aXH!#MG;DqV9+ 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H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_NE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr) -{ - /* Code Generation of 22 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0F01, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = aarch64_genDIV_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - reste = aarch64_genMUL_3(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - if (!reste.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, reste); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int selected, res; - int i, tmp; - pifi iPtr; - - if (argc < 2) - { - printf("Give 2 value (LoopValue)\n"); - exit(-1); - } - selected = atoi (argv[1]); // Get threshold value - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifi) genIf (ptr); // Generate instructions - res = iPtr(selected); // Call generated code - printf ("Result %d : %d\n", selected, res); - for (i = 0; i < selected; i = i + 1) - { - if (i % 2) tmp = tmp + i; - } - - return tmp == res; -} diff --git a/CodeExamples/If-in-Loop.power b/CodeExamples/If-in-Loop.power deleted file mode 100755 index 5f619834866535b5ae37302561bb6082b91ecbfe..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78384 zcmeHw4SZC`b?@9=eXNiW%ZIUS6LT@(N(2dk9kSS9BmqX^%ZdS;^toLv(n?xetQ2Ww zi$pSl&=xmN3k^%%LT~LhLRrl5>B+yLPISfVYE;jRuFtD%tE*jLJG{>IKXe`82`4XY>+j>8J-auko{N>sTLRZhb$C76aQfpFlavInqNi1@Y~wzEpNO ztK`>Ex5K=K$mWGN&TFVycwq&-R0=({v&QhyW&@W7ZuS|iT zkph1o@Fvd0gLX?M=kgTzt5e`7rN9@az>9EOBqo}|&CQL?qNz33!b^312sh1qG>&% zLFS?_S@!t99`}08GArMK*Zq)qzwk&_S0K&4qmMiXUJVtQWjgSBj4~tNfp_|`Vh5gm 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zzc_(Tm!Fh?SL!S7LcFTVCy#UC6a5wI7p(ana>9{0I^{t!W5nO|h{n z5;7BRMLrOTIF@g^!p3&;#&IOtpHvAZlGNu_`QjYA@C<-ToVx#L|IOdiB$!ARFt4-g czgiDGi5)B}*9XbU-$cc5@Ksvpk#H;iKO>z1VgLXD diff --git a/CodeExamples/If-in-Loop.power.c b/CodeExamples/If-in-Loop.power.c deleted file mode 100644 index 8eabc2a..0000000 --- a/CodeExamples/If-in-Loop.power.c +++ /dev/null @@ -1,1172 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBNE_1(h2_sValue_t P0); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genBGE_1(h2_sValue_t P0); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BNE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr) -{ - /* Code Generation of 22 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1F80F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = power_genDIV_3(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - reste = power_genMUL_3(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - if (!reste.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, reste); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int selected, res; - int i, tmp; - pifi iPtr; - - if (argc < 2) - { - printf("Give 2 value (LoopValue)\n"); - exit(-1); - } - selected = atoi (argv[1]); // Get threshold value - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifi) genIf (ptr); // Generate instructions - res = iPtr(selected); // Call generated code - printf ("Result %d : %d\n", selected, res); - for (i = 0; i < selected; i = i + 1) - { - if (i % 2) tmp = tmp + i; - } - - return tmp == res; -} diff --git a/CodeExamples/If-in-Loop.riscv b/CodeExamples/If-in-Loop.riscv deleted file mode 100755 index 5080de950997ddccad7c7f5fe307bc927d298bbd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 41564 zcmeHw3s_Xu`uCpM8wM2-#nNuaiGl6J!SUAVbU7vBAaahWN3BlZzn%$UM7|JkW-Rlh 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h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr) -{ - /* Code Generation of 20 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7FF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGE_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0002 = riscv_genDIV_4(tmp0002, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, immValueZero); - reste = riscv_genMUL_4(reste, tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, immValueZero); - if (!reste.dontFree) h2_freeReg(tmp0002.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBNE_3(i, reste, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000005]; - i = riscv_genBGE_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_prologue_00000000]; - i = riscv_genBNE_3(i, reste, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - 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jsTdG^Z{$uMuvgN?k97G5=q5XoM-kmTXX-W1!1_FiK diff --git a/CodeExamples/If.aarch64.c b/CodeExamples/If.aarch64.c deleted file mode 100644 index e3f6f2c..0000000 --- a/CodeExamples/If.aarch64.c +++ /dev/null @@ -1,1117 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_NE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) -{ - /* Code Generation of 12 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 10, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0701, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - threshold = aarch64_genMV_3(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - value = aarch64_genCMP_2(value, threshold); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int selected, toTest, res; - pifi iPtr; - - if (argc < 2) - { - printf("Give 2 value (testValue, testedValue)\n"); - exit(-1); - } - selected = atoi (argv[1]); // Get threshold value - toTest = atoi (argv[2]); // Value to be tested - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifi) genIf (ptr, selected); // Generate instructions - res = iPtr(toTest); // Call generated code - printf ("Result %d = %d : %d\n", selected, toTest, res); - return res; -} diff --git a/CodeExamples/If.power b/CodeExamples/If.power deleted file mode 100755 index c5bbf4e813375810a588d6bcb1084fa5896efdb1..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78264 zcmeHw4SZD9weLPNlVn0Z7$9Q&sGJDcgysvhI8iW@0FuauDWKBV>zz!JNiv$uOlKw< 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z`@kMqzmJ&XQvRXrr{p?>GIRTh{bIQ@s{EHTp&!Xl@wo#iN~`wKlbm&>tRJR2rc2dR z@EMeu+gH!UVcC$9Q?XF>RQ~@UVQxPz+mFlo4T@00+^b=`hEOOA9~GpB+5SY8WFk&|Qq~`!$qiQ#?gre-e^mUYziUY{5ipD$FB0v)ssca9j+T|y2dU~m Q^+8deUTHO7Nm=&)0PCebUjP6A diff --git a/CodeExamples/If.power.c b/CodeExamples/If.power.c deleted file mode 100644 index 41cb10b..0000000 --- a/CodeExamples/If.power.c +++ /dev/null @@ -1,936 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBNE_1(h2_sValue_t P0); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BNE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) -{ - /* Code Generation of 12 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 15, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF80F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - threshold = power_genMV_2(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - value = power_genCMP_2(value, threshold); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000000] + 1; - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int selected, toTest, res; - pifi iPtr; - - if (argc < 2) - { - printf("Give 2 value (testValue, testedValue)\n"); - exit(-1); - } - selected = atoi (argv[1]); // Get threshold value - toTest = atoi (argv[2]); // Value to be tested - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifi) genIf (ptr, selected); // Generate instructions - res = iPtr(toTest); // Call generated code - printf ("Result %d = %d : %d\n", selected, toTest, res); - return res; -} diff --git a/CodeExamples/If.riscv b/CodeExamples/If.riscv deleted file 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VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -/* C compilette prototype */ -h2_insn_t * genIf(h2_insn_t * ptr, int selectedValue) -{ - /* Code Generation of 11 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t value = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t threshold = {H2REGISTER, 'i', 1, 31, 6, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 31, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_endtrue_00000001 */ - #define h2_endtrue_00000001 1 - 0, /* h2_iffalse_00000002 */ - #define h2_iffalse_00000002 2 - 0, /* h2_ifend_00000003 */ - #define h2_ifend_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x77F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - threshold = riscv_genMV_2(threshold, (h2_sValue_t) {H2VALUE, 'i', 1, 31, 0, (int)((selectedValue))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - value = riscv_genBNE_3(value, threshold, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_endtrue_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_iffalse_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_ifend_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000000]; - value = riscv_genBNE_3(value, threshold, intsValue((labelAddresses [h2_iffalse_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_endtrue_00000001]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000003] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int selected, toTest, res; - pifi iPtr; - - if (argc < 2) - { - printf("Give 2 value (testValue, testedValue)\n"); - exit(-1); - } - selected = atoi (argv[1]); // Get threshold value - toTest = atoi (argv[2]); // Value to be tested - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifi) genIf (ptr, selected); // Generate instructions - res = iPtr(toTest); // Call generated code - printf ("Result %d = %d : %d\n", selected, toTest, res); - return res; -} diff --git a/CodeExamples/Loop-in-If.aarch64 b/CodeExamples/Loop-in-If.aarch64 deleted file mode 100755 index 3df33b82cdd3b6517771f56b22b17b0e27196c6f..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52312 zcmeHwdtg-6wf8=AW-^m^NWw!vnD9^@CgGt7f@P9`$OQ#MRC?|0WReWYlrR%#CJMqW zgJ`c66!HbdTU3JDTLZn7R$H5^y#}$Zz1Wr(ZTq!8CZLt?(tf3aVlLu*zqKEeGn1J- zAj$WSCpl;Dz4lsbueJ8t`|QU#XErZheuGKVm^w`CMMkN1tAm5Ym9f=_c~ZjWvQ*|^ zlh{O-0*D!>gXd5vVk-PpvR0u@;^_#9ZmvlH=9(NlqQWr(%v7i(q|hSsMBtDq5x#t{ zNUD%=ZN!yiJ^7HxKlxAzkEn2`l;gAv6&)ps?o&zksiae3SPG^>r61`=XNBZfVR9fv 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H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_GT_I_I_64_1(i0) do /* bgt */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xc & 0x1f) >> 0)); } while(0); -#define A64_B_NE_I_I_64_1(i0) do /* bne */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0x1 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genBGT_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_NE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genBGT_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGT instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGT - -// No specific optimisation for BGT/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GT_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGT instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genPlusOrMul(h2_insn_t * ptr) -{ - /* Code Generation of 32 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_endtrue_00000009 */ - #define h2_endtrue_00000009 9 - 0, /* h2_iffalse_00000010 */ - #define h2_iffalse_00000010 10 - 0, /* h2_ifend_00000011 */ - #define h2_ifend_00000011 11 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0F03, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - plus = aarch64_genCMP_2(plus, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genMUL_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_endtrue_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_iffalse_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_ifend_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000008] + 1; - aarch64_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000009]; - aarch64_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - aarch64_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int plus, loopValue, res; - int i, tmp; - pifii iPtr; - - if (argc < 2) - { - printf("Give 2 values (Plus LoopValue)\n"); - exit(-1); - } - plus = atoi (argv[1]); // Get operator + = 1, other = * - loopValue = atoi (argv[2]); // Get threshold value - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions - res = iPtr(plus, loopValue); // Call generated code - if (plus == 1) - for (tmp = 1, i = 1; i <= loopValue; i = i + 1) - { - tmp *= i; - } - else - for (tmp = 0, i = 1; i <= loopValue; i = i + 1) - { - tmp += i; - } - printf ("Result plus = %d, loopValue %d : %d (%d)\n", plus, loopValue, res, tmp); - return tmp != res; -} diff --git a/CodeExamples/Loop-in-If.power b/CodeExamples/Loop-in-If.power deleted file mode 100755 index 1b3810cab7df8590800027ff37bb0de7ca07b409..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78352 zcmeHw4}4VBmH&M+lVn0d7$9I&Dh~lSp-Bj6>7XDXfF%4g6|i)F_BS&mLo%Ao#K}ZM zn@C{UUF_Q5!WLU}v0z0PchSWz-KDM8=#O^MANyPSTeqcMs_0@jSy?x(+6G16e$Rd9 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h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_BGT_I_I_32_1(i0) do /* bgt */ { power_G32(((0x4181 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_BNE_I_I_32_1(i0) do /* bne */ { power_G32(((0x4082 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBNE_1(h2_sValue_t P0); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBGT_1(h2_sValue_t P0); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBNE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BNE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBGT_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGT instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGT - -// No specific optimisation for BGT/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGT_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGT instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genPlusOrMul(h2_insn_t * ptr) -{ - /* Code Generation of 32 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_endtrue_00000009 */ - #define h2_endtrue_00000009 9 - 0, /* h2_iffalse_00000010 */ - #define h2_iffalse_00000010 10 - 0, /* h2_ifend_00000011 */ - #define h2_ifend_00000011 11 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1F81F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - plus = power_genCMP_2(plus, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genMUL_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_endtrue_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_iffalse_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, LoopValue); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_ifend_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000008] + 1; - power_genBNE_1(intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - power_genBGT_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_endtrue_00000009]; - power_genBA_1(intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - power_genBGT_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int plus, loopValue, res; - int i, tmp; - pifii iPtr; - - if (argc < 2) - { - printf("Give 2 values (Plus LoopValue)\n"); - exit(-1); - } - plus = atoi (argv[1]); // Get operator + = 1, other = * - loopValue = atoi (argv[2]); // Get threshold value - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions - res = iPtr(plus, loopValue); // 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z;Y_}9uSa540mb<8}bbnb?hXm~dXGl?J~l&f&17jLUMsE1D9lV+wYUBAbjc2vYidocPwl-61DE{oQ0a-g@5_-rnN_~;!m35-Vc zYCbv^ryUgW(VlHIB2|d{BS4CkN9&4#2$-H3AMNELK)eB3y@;2tKO@k4Vk(dJcssyH zI~KKGN~iEw1bVMbaoYQx0AFv!ed`6uB_U9sq7dlaG`;a~Ax`CWMW8&|ucRVS8%Unk zt|iEzeyA7qfx>tMm53y>ZNNM0+mNuv?ead z#9jk&^-}rhb(+dYd(p{g$O$zQd1`ba;?z#Un)avyDp2!~#L6JL41ree#7BFXfUEe3 zhr${J+Tju(?TI>Ghi^0T2|MDWwSExz&M0Yku(AU1tVE!G5FbZtvTXT%IFWQwopgPQ zpz_gL>fUUQdzdnmOKsm?&?+CTSx05d`t;?aIKA7Y`l()83y#f}zCl>P2}JenLQhtj(ginGReNf?3`#TVu zZu$~Iy@-!O|Eu^0&qhBeL%CEwdio3pu4oRhgaf-D>Cp%RLJ$I--Y{Fildc`uq`pU) W%B2=fr!2mFQ{Y^NshP-AqyG -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_BNE_RRI_I_32_1(r1,r2,i1) do /* BNE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_BGT_RRI_I_32_1(r2,r1,i1) do /* BGT */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBGT_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBGT_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGT instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGT - -// No specific optimisation for BGT/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGT_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGT instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBNE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BNE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BNE - -// No specific optimisation for BNE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BNE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BNE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genPlusOrMul(h2_insn_t * ptr) -{ - /* Code Generation of 29 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t plus = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t LoopValue = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t reste = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_endtrue_00000009 */ - #define h2_endtrue_00000009 9 - 0, /* h2_iffalse_00000010 */ - #define h2_iffalse_00000010 10 - 0, /* h2_ifend_00000011 */ - #define h2_ifend_00000011 11 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - plus = riscv_genBNE_3(plus, tmp, intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genMUL_4(tmp, tmp, i, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_endtrue_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_iffalse_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, i); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_ifend_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_prologue_00000008]; - plus = riscv_genBNE_3(plus, tmp, intsValue((labelAddresses [h2_iffalse_00000010] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000001]; - i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_endtrue_00000009]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_ifend_00000011] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000005]; - i = riscv_genBGT_3(i, LoopValue, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int plus, loopValue, res; - int i, tmp; - pifii iPtr; - - if (argc < 2) - { - printf("Give 2 values (Plus LoopValue)\n"); - exit(-1); - } - plus = atoi (argv[1]); // Get operator + = 1, other = * - loopValue = atoi (argv[2]); // Get threshold value - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - iPtr = (pifii) genPlusOrMul(ptr); // Generate instructions - res = iPtr(plus, loopValue); // Call generated code - if (plus == 1) - for (tmp = 1, i = 1; i <= loopValue; i = i + 1) - { - tmp *= i; - } - else - for (tmp = 0, i = 1; i <= loopValue; i = i + 1) - { - tmp += i; - } - printf ("Result plus = %d, loopValue %d : %d (%d)\n", plus, loopValue, res, tmp); - return tmp != res; -} diff --git a/CodeExamples/Loop.aarch64 b/CodeExamples/Loop.aarch64 deleted file mode 100755 index ffc1bf970ff29a20201ed1a4db9ec15f29e75c40..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 44024 zcmeHwdwi7Dng4m;cW${~22!G1q6@$h-OV#9oi4ykrAk6d?XpfJZdnp(v{e*U z%6Mg! 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-/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 13 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF1F03, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - res = aarch64_genMV_3(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - res = aarch64_genADD_3(res, res, increment); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, res, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtr; - - if (argc < 3) - { - printf("Give 2 increment values\n"); - exit(-1); - } - in0 = atoi (argv[1]); - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifii) genMul (ptr); // Generate instructions - res = fPtr(in0, in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Loop.power b/CodeExamples/Loop.power deleted file mode 100755 index c89a785b7e4a891262c6f35a8e6d18d2f8fe389e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78264 zcmeHw4SZD9nfJLflVn0d7(T?{7dHYnq4@$WP87@}1W5of%ZJik+sP!EBvX@_I5W{` z6B$_DVyo|lU2L(hR@_>PUG;}8ZfT2c^rgP&+P-vaTWnF$(r%)xFKyK(6}|g^&d1En zWF`qnD!={Ri*uiIpYxpOJRj#g=iKMsTsN;+bG1#=m^y6i97b0jCvy?bLnjGpqYY7LV_8xP6AGk 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(if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genBGE_1(h2_sValue_t P0); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 13 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 17, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3F81F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - res = power_genMV_2(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - res = power_genADD_3(res, res, increment); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, res); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtr; - - if (argc < 3) - { - printf("Give 2 increment values\n"); - exit(-1); - } - in0 = atoi (argv[1]); - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifii) genMul (ptr); // Generate instructions - res = fPtr(in0, in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Loop.riscv b/CodeExamples/Loop.riscv deleted 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BRlul8xATv#1Ru+on1qiOf ssrsL?|M`HWsF)Y1yg-zHPfZ*gnl3A?FEW+Ch!lfkl?Zs8E-6X&Uu4~~IRF3v diff --git a/CodeExamples/Multiple-flt.power.c b/CodeExamples/Multiple-flt.power.c deleted file mode 100644 index 2b58444..0000000 --- a/CodeExamples/Multiple-flt.power.c +++ /dev/null @@ -1,1157 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_FMR_RR_F_32_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define P1_FMR_RR_F_64_1(r0,r1) do /* mv */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x90 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define PPC_FADDS_RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); -#define PPC_FADDS__RRR_F_32_1(r0,r1,r2) do /* add */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDFP_RRR_F_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xa & 0x7ff) >> 0)); } while(0); -#define P1_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2a & 0x7ff) >> 0)); } while(0); -#define P1_FADD__RRR_F_64_1(r0,r1,r2) do /* add */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2b & 0x7ff) >> 0)); } while(0); -#define PPC_FDIVS_RRR_F_32_1(r0,r1,r2) do /* div */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x24 & 0x7ff) >> 0)); } while(0); -#define P1_FDIV_RRR_F_64_1(r0,r1,r2) do /* div */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x24 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define PPC_FSUBS_RRR_F_32_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x28 & 0x7ff) >> 0)); } while(0); -#define PPC_FSUBS__RRR_F_32_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x29 & 0x7ff) >> 0)); } while(0); -#define P1_FSUB_RRR_F_64_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x28 & 0x7ff) >> 0)); } while(0); -#define P1_FSUB__RRR_F_64_1(r0,r1,r2) do /* SUB */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x29 & 0x7ff) >> 0)); } while(0); -#define PPC_FMULS_RRR_F_32_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x32 & 0x3f) >> 0)); } while(0); -#define PPC_FMULS__RRR_F_32_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3b & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x33 & 0x3f) >> 0)); } while(0); -#define P1_FMUL_RRR_F_64_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x32 & 0x3f) >> 0)); } while(0); -#define P1_FMUL__RRR_F_64_1(r0,r1,r2) do /* MUL */ { power_G32(((0x3f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0x1f) << 11)|((r2 & 0x1f) << 6)|((0x33 & 0x3f) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FMULS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FMULS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FMUL_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FMUL__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FSUBS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FSUBS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FSUB_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FSUB__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FADDS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FADDS__RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDFP_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FADD__RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_FMR_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_FDIVS_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_FDIV_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 floats and return float */ -typedef float (*pifff)(float, float); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genMUL_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 2, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3807, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genDIV_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - float fin0, fin1, fres; - pifff fPtrf; - int resultOK; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) - fin1 = atof (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifff) genAddf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple addition of 2 floating point values:\n"); - printf("%f + %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 + fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genSubf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple subraction of 2 floating point values:\n"); - printf("%f - %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 - fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genMulf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple multiplication of 2 floating point values:\n"); - printf("%f * %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 * fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genDivf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple division of 2 floating point values:\n"); - printf("%f / %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 / fin1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-flt.riscv b/CodeExamples/Multiple-flt.riscv deleted file mode 100755 index 486b1b0c0bf1e0d02a177de8d4b3b6ec112d2cd4..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 57932 zcmeHw3wRVowtw~X!SJ7qHhzN*0A}^6e2rxoGgouby5yC@xh)lqS5D1z7?^O3BlgA91$o_Np zyJ@JdI@RY?)j4(QbXA?|$&}RLLj^%#o=d}iVgwZi3G5!k`wub}g!mq&V_jK1i)K+Q zn8TDuI08!n0R=7cDToL*z&4aiAqp@BdWLLzUT7&pLcK<-vFADAC>Ny!HoTPaKbN%`4*^YaQOP3~*Svt~U#Ah~Z| ze&K-RY`xX2?++ZRi^?MWv=NWuuJi-t(?v4A0ig>5)!Pk$uC54#6H0)3Q5hsVl1rGH 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fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32F_FADD_S_RRR_F_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FADD_D_RRR_F_64_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32F_FDIV_S_RRR_F_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0xc & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FDIV_D_RRR_F_64_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0xd & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32F_FMUL_S_RRR_F_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x8 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32F_FSUB_S_RRR_F_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x4 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32F_FMV_S_RR_F_32_1(r3,r1) do /* MV */ { riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -#define RV32D_FMV_D_RR_F_64_1(r3,r1) do /* MV */ { riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FMUL_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FSUB_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FDIV_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32D_FDIV_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 floats and return float */ -typedef float (*pifff)(float, float); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genMUL_4(r, a, b, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genDIV_4(r, a, b, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - float fin0, fin1, fres; - pifff fPtrf; - int resultOK; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) - fin1 = atof (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifff) genAddf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple addition of 2 floating point values:\n"); - printf("%f + %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 + fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genSubf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple subraction of 2 floating point values:\n"); - printf("%f - %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 - fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genMulf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple multiplication of 2 floating point values:\n"); - printf("%f * %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 * fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genDivf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple division of 2 floating point values:\n"); - printf("%f / %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 / fin1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-int.aarch64 b/CodeExamples/Multiple-int.aarch64 deleted file mode 100755 index fadeda4cf1d0df9f07312f9e214fc7c8e94a9cab..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 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h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 ints and return int */ -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genMUL_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0303, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genDIV_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtrf; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) - in1 = atoi (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifii) genAddf (ptr); - res = fPtrf(in0, in1); - printf ("Simple addition of 2 int values:\n"); - printf("%d + %d = %d\n", in0, in1, res); - if (res != (in0 + in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genSubf (ptr); - res = fPtrf(in0, in1); - printf ("Simple subraction of 2 int values:\n"); - printf("%d - %d = %d\n", in0, in1, res); - if (res != (in0 - in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genMulf (ptr); - res = fPtrf(in0, in1); - printf ("Simple multiplication of 2 int values:\n"); - printf("%d * %d = %d\n", in0, in1, res); - if (res != (in0 * in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genDivf (ptr); - res = fPtrf(in0, in1); - printf ("Simple division of 2 int values:\n"); - printf("%d / %d = %d\n", in0, in1, res); - if (res != (in0 / in1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-int.power b/CodeExamples/Multiple-int.power deleted file mode 100755 index 80db09406210c6b8d25f2ba9ce64b0566da20610..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78336 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autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 ints and return int */ -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x781F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x781F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genMUL_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x781F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x781F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genDIV_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtrf; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) - in1 = atoi (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifii) genAddf (ptr); - res = fPtrf(in0, in1); - printf ("Simple addition of 2 int values:\n"); - printf("%d + %d = %d\n", in0, in1, res); - if (res != (in0 + in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genSubf (ptr); - res = fPtrf(in0, in1); - printf ("Simple subraction of 2 int values:\n"); - printf("%d - %d = %d\n", in0, in1, res); - if (res != (in0 - in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genMulf (ptr); - res = fPtrf(in0, in1); - printf ("Simple multiplication of 2 int values:\n"); - printf("%d * %d = %d\n", in0, in1, res); - if (res != (in0 * in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genDivf (ptr); - res = fPtrf(in0, in1); - printf ("Simple division of 2 int values:\n"); - printf("%d / %d = %d\n", in0, in1, res); - if (res != (in0 / in1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-int.riscv b/CodeExamples/Multiple-int.riscv deleted file mode 100755 index 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a/CodeExamples/Multiple-int.riscv.c b/CodeExamples/Multiple-int.riscv.c deleted file mode 100644 index 7bdfe2c..0000000 --- a/CodeExamples/Multiple-int.riscv.c +++ /dev/null @@ -1,1044 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 ints and return int */ -typedef int (*pifii)(int, int); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genMUL_4(r, a, b, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t b = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genDIV_4(r, a, b, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtrf; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - in0 = atoi (argv[1]); // Get the users values in1 & in2 (int) - in1 = atoi (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifii) genAddf (ptr); - res = fPtrf(in0, in1); - printf ("Simple addition of 2 int values:\n"); - printf("%d + %d = %d\n", in0, in1, res); - if (res != (in0 + in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genSubf (ptr); - res = fPtrf(in0, in1); - printf ("Simple subraction of 2 int values:\n"); - printf("%d - %d = %d\n", in0, in1, res); - if (res != (in0 - in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genMulf (ptr); - res = fPtrf(in0, in1); - printf ("Simple multiplication of 2 int values:\n"); - printf("%d * %d = %d\n", in0, in1, res); - if (res != (in0 * in1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifii) genDivf (ptr); - res = fPtrf(in0, in1); - printf ("Simple division of 2 int values:\n"); - printf("%d / %d = %d\n", in0, in1, res); - if (res != (in0 / in1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/Demos/Newton-SquareRoot-VariablePrecision/Newton.c b/Demos/Newton-SquareRoot-VariablePrecision/Newton.c deleted file mode 100644 index d18ae26..0000000 --- a/Demos/Newton-SquareRoot-VariablePrecision/Newton.c +++ /dev/null @@ -1,925 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -void RV32I_RET__I_32_1(){ /* RET */ - riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_RET__I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_ADDI_RRI_I_32_1(int r1,int r0,int i0){ /* ADD */ - riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_ADDI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_ADD_RRR_I_32_1(int r3,int r1,int r2){ /* ADD */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_ADD_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SUB_RRR_I_32_1(int r3,int r1,int r2){ /* SUB */ - riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SUB_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_MV_RR_I_32_1(int r0,int r1){ /* MV */ - riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_MV_RR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_MV_RI_I_32_1(int r3,int i1){ /* MV */ - riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_MV_RI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32F_FMV_S_RR_F_32_1(int r3,int r1){ /* MV */ - riscv_G32(((0x10 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32F_FMV_S_RR_F_32_1\n", h2_asm_pc); -#endif -} -void RV32D_FMV_D_RR_F_64_1(int r3,int r1){ /* MV */ - riscv_G32(((0x11 & 0x7f) << 25)|((r1 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32D_FMV_D_RR_F_64_1\n", h2_asm_pc); -#endif -} -void RV32I_LB_RRI_I_8_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void RV32I_LH_RRI_I_16_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void RV32I_LW_RRI_I_32_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LW_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32F_FADD_S_RRR_F_32_1(int r3,int r1,int r2){ /* ADD */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32F_FADD_S_RRR_F_32_1\n", h2_asm_pc); -#endif -} -void RV32D_FADD_D_RRR_F_64_1(int r3,int r1,int r2){ /* ADD */ - riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32D_FADD_D_RRR_F_64_1\n", h2_asm_pc); -#endif -} -void RV32I_SLLI_RRI_I_32_1(int r3,int r1,int i0){ /* SL */ - riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SLLI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SLL_RRR_I_32_1(int r3,int r1,int r2){ /* SL */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SLL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32F_FDIV_S_RRR_F_32_1(int r3,int r1,int r2){ /* DIV */ - riscv_G32(((0xc & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32F_FDIV_S_RRR_F_32_1\n", h2_asm_pc); -#endif -} -void RV32D_FDIV_D_RRR_F_64_1(int r3,int r1,int r2){ /* DIV */ - riscv_G32(((0xd & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x53 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32D_FDIV_D_RRR_F_64_1\n", h2_asm_pc); -#endif -} -void RV32I_SRLI_RRI_I_32_1(int r3,int r1,int i0){ /* SR */ - riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SRLI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SRL_RRR_I_32_1(int r3,int r1,int r2){ /* SR */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SRL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SB_RRI_I_8_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void RV32I_SH_RRI_I_16_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void RV32I_SW_RRI_I_32_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SW_RRI_I_32_1\n", h2_asm_pc); -#endif -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32F_FMV_S_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32D_FMV_D_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FDIV_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32D_FDIV_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32F_FADD_S_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32D_FADD_D_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -/* -*- c -*- */ - -#include -#include -#include - - -#define True 1 -#define False 0 -#define FLOAT 32 -#define DOUBLE 64 - -typedef float (*piff)(float, float, float); -typedef double (*pidd)(double, double, double); -/* Newton square root demonstration with variable precision */ -h2_insn_t * genIterate(h2_insn_t * ptr, int FloatWidth) -{ - /* Code Generation of 4 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t u = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; - h2_sValue_t val = {H2REGISTER, 'f', 1, (FloatWidth), 11, true}; - h2_sValue_t div = {H2REGISTER, 'f', 1, (FloatWidth), 12, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, (FloatWidth), 10, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, (FloatWidth), 0, true}; - h2_sValue_t tmp1 = {H2REGISTER, 'f', 1, (FloatWidth), 1, true}; - h2_sValue_t tmp2 = {H2REGISTER, 'f', 1, (FloatWidth), 2, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'f', 1, (FloatWidth), -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x31F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp1 = riscv_genDIV_4(tmp1, val, u, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp2 = riscv_genADD_3(tmp2, u, tmp1); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = riscv_genDIV_4(tmp0000, tmp2, div, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - /* r = (u + (#(value) / u)) / 2.0*/ - - return (h2_insn_t *) ptr; -} - -#define ABS(x) ((x < 0) ? -(x) : (x)) - -int main(int argc, char **argv) -{ - int isFloat, iterationNumber; - double af, precf, precd, value, next, diff; - piff fPtr1; - pidd fPtr2; - h2_insn_t * ptr; - char input; - if (argc < 3) - { - printf ("Newton \n"); - exit(-1); - } - iterationNumber = 0; - af = atof (argv[1]); - precd = atof (argv[2]); - precf = 1; // precd * 1.e14; - ptr = h2_malloc (1024); - isFloat = True; - printf ("Compute square root of %f\n", af); - printf ("With precision of %e (float)\n", precf); - printf ("With precision of %e (double)\n", precd); - next = 1.0; - diff = af; - - fPtr1 = (piff) genIterate (ptr, FLOAT); - do - { - if ((diff < precf) && isFloat) - { /* Code re-generation with double for better precision */ - fPtr2 = (pidd) genIterate (ptr, DOUBLE); - isFloat = False; - } - value = next; - next = (isFloat)?fPtr1(value, af, 2.0):fPtr2(value, af, 2.0); - diff = ABS(next - value); - printf("%3d %s : %.20f, %e\n", - iterationNumber++, - isFloat?"float ":"double", - next, isFloat?precf:precd); - - if(iterationNumber > 100){ - return -1; - } - } while ( diff > precd); - if(isFloat){ - return (next != sqrtf(af)) ? -1 : 0; - } - else{ - return (next != sqrt(af)) ? -1 : 0; - } -} diff --git a/Demos/Newton-SquareRoot-VariablePrecision/Newton.riscv b/Demos/Newton-SquareRoot-VariablePrecision/Newton.riscv deleted file mode 100755 index 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zY-%y$NY!$KaMN}r#)k$1YvG&Rxtk*-TkmaaA(3HL$Cwe0g{e_F<hpuHiZenWotCrH;06iI9jP$6Cq~ zk_IEIQ31iI-Wz~r$b~@Yo*|5ZTPb*viucDT-tDel;R;2B8owXA3}G(3A<|*sB$y00 z3MS;LS8ctDslBv}2zA^TBaEyL;);-Nh{)`%vl*8|sCKN#zim@n%?6}xts>p1u3+t6 ztfVO7>$6HqD++0{x(MqBiZ<5xH?pGIZ9ZfcXY?mi&~qxmlt_A%7{(#;GsK_LqvIzLtTR~)?r}cyS^E;a4O;j2x2e< zhBj=|CNvCS*1Ms-9{Ff?7I1OPCr#C(4I5hFH@^3Xc zaff{bWd0}loxq_>_5P{o(E3Jf$Rns_xZ%P%W1c_9!mibhbl+h30~DTrCacC%&+FFPRjiBF_ZC7 z?-dI6OCF4oSLOXuR;FOU(Z(wa3Cw#GqD-UZPgqe!aLnT}|CA9T<0K?B qN2u&a#br`Yl!$qT{zanv8xqu?BjH5k -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_I_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SDIV_RRR_I_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SDIV_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include -#include -#include "ReadPgmImage.h" - -typedef int (*pifc)(int[], int, int, int); - - -void printImage(imgStruct_t *img, char *imageName) -{ - printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width ; column++) - { - printf("%03d ", img->pixelsArray[line*img->width+column]); - } - printf("\n"); - } - printf("\n"); -} - -int imgSum (imgStruct_t *img) -{ - int line, column, sum; - sum = 0; - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width; column++) - { - sum += img->pixelsArray[line*img->width+column]; - } - } - return (0 == sum)?1:sum; -} - -#if 0 -unsigned char clamp(int value) -{ - return (unsigned char)(0 > value)?0:(255 < value)?255:value; -} -#else -#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) -#endif - -pifc genKernel1x1(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF030F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, line, imgWidth); - tmp0001 = aarch64_genADD_3(tmp0001, tmp0000, column); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genMUL_3(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = aarch64_genADD_3(tmp0003, In, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = aarch64_genR_3(tmp0004, tmp0003, immValueZero); - sum = aarch64_genMUL_3(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); - if (!sum.dontFree) h2_freeReg(tmp0004.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0005 = aarch64_genDIV_3(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0005, immValueZero); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel3x3(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 19 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 13, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF3F0F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - njp1 = aarch64_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = aarch64_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = aarch64_genADD_3(tmp0000, stride, njm1); - tmp0001 = aarch64_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = aarch64_genR_3(tmp0003, tmp0002, immValueZero); - sum = aarch64_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = aarch64_genADD_3(tmp0004, stride, column); - tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = aarch64_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = aarch64_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = aarch64_genADD_3(tmp0009, stride, njp1); - tmp0010 = aarch64_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = aarch64_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = aarch64_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = aarch64_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genMV_3(ni, line, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0015 = aarch64_genADD_3(tmp0015, stride, njm1); - tmp0016 = aarch64_genMUL_3(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = aarch64_genADD_3(tmp0017, In, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = aarch64_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = aarch64_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0019); - if (!sum.dontFree) h2_freeReg(tmp0019.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0020 = aarch64_genADD_3(tmp0020, stride, column); - tmp0021 = aarch64_genMUL_3(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = aarch64_genADD_3(tmp0022, In, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = aarch64_genR_3(tmp0023, tmp0022, immValueZero); - tmp0024 = aarch64_genMUL_3(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0024); - if (!sum.dontFree) h2_freeReg(tmp0024.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0025 = aarch64_genADD_3(tmp0025, stride, njp1); - tmp0026 = aarch64_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = aarch64_genADD_3(tmp0027, In, tmp0026); - if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); - tmp0028 = aarch64_genR_3(tmp0028, tmp0027, immValueZero); - tmp0029 = aarch64_genMUL_3(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}); - if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0029); - if (!sum.dontFree) h2_freeReg(tmp0029.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0030 = aarch64_genADD_3(tmp0030, stride, njm1); - tmp0031 = aarch64_genMUL_3(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = aarch64_genADD_3(tmp0032, In, tmp0031); - if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); - tmp0033 = aarch64_genR_3(tmp0033, tmp0032, immValueZero); - tmp0034 = aarch64_genMUL_3(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}); - if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0034); - if (!sum.dontFree) h2_freeReg(tmp0034.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0035 = aarch64_genADD_3(tmp0035, stride, column); - tmp0036 = aarch64_genMUL_3(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = aarch64_genADD_3(tmp0037, In, tmp0036); - if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); - tmp0038 = aarch64_genR_3(tmp0038, tmp0037, immValueZero); - tmp0039 = aarch64_genMUL_3(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}); - if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0039); - if (!sum.dontFree) h2_freeReg(tmp0039.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0040 = aarch64_genADD_3(tmp0040, stride, njp1); - tmp0041 = aarch64_genMUL_3(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = aarch64_genADD_3(tmp0042, In, tmp0041); - if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); - tmp0043 = aarch64_genR_3(tmp0043, tmp0042, immValueZero); - tmp0044 = aarch64_genMUL_3(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}); - if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0044); - if (!sum.dontFree) h2_freeReg(tmp0044.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0045 = aarch64_genDIV_3(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0045, immValueZero); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel5x5(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 41 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 2, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 13, true}; - h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFFFF0F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - njm2 = aarch64_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = aarch64_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp1 = aarch64_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp2 = aarch64_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = aarch64_genADD_3(tmp0000, stride, njm2); - tmp0001 = aarch64_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = aarch64_genR_3(tmp0003, tmp0002, immValueZero); - sum = aarch64_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = aarch64_genADD_3(tmp0004, stride, njm1); - tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = aarch64_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = aarch64_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = aarch64_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = aarch64_genADD_3(tmp0009, stride, column); - tmp0010 = aarch64_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = aarch64_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = aarch64_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = aarch64_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0014 = aarch64_genADD_3(tmp0014, stride, njp1); - tmp0015 = aarch64_genMUL_3(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = aarch64_genADD_3(tmp0016, In, tmp0015); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = aarch64_genR_3(tmp0017, tmp0016, immValueZero); - tmp0018 = aarch64_genMUL_3(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}); - if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0018); - if (!sum.dontFree) h2_freeReg(tmp0018.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0019 = aarch64_genADD_3(tmp0019, stride, njp2); - tmp0020 = aarch64_genMUL_3(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - tmp0021 = aarch64_genADD_3(tmp0021, In, tmp0020); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = aarch64_genR_3(tmp0022, tmp0021, immValueZero); - tmp0023 = aarch64_genMUL_3(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}); - if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0023); - if (!sum.dontFree) h2_freeReg(tmp0023.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0024 = aarch64_genADD_3(tmp0024, stride, njm2); - tmp0025 = aarch64_genMUL_3(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); - tmp0026 = aarch64_genADD_3(tmp0026, In, tmp0025); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = aarch64_genR_3(tmp0027, tmp0026, immValueZero); - tmp0028 = aarch64_genMUL_3(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0028); - if (!sum.dontFree) h2_freeReg(tmp0028.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0029 = aarch64_genADD_3(tmp0029, stride, njm1); - tmp0030 = aarch64_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = aarch64_genADD_3(tmp0031, In, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = aarch64_genR_3(tmp0032, tmp0031, immValueZero); - tmp0033 = aarch64_genMUL_3(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0033); - if (!sum.dontFree) h2_freeReg(tmp0033.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0034 = aarch64_genADD_3(tmp0034, stride, column); - tmp0035 = aarch64_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = aarch64_genADD_3(tmp0036, In, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = aarch64_genR_3(tmp0037, tmp0036, immValueZero); - tmp0038 = aarch64_genMUL_3(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0038); - if (!sum.dontFree) h2_freeReg(tmp0038.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0039 = aarch64_genADD_3(tmp0039, stride, njp1); - tmp0040 = aarch64_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = aarch64_genADD_3(tmp0041, In, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = aarch64_genR_3(tmp0042, tmp0041, immValueZero); - tmp0043 = aarch64_genMUL_3(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0043); - if (!sum.dontFree) h2_freeReg(tmp0043.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0044 = aarch64_genADD_3(tmp0044, stride, njp2); - tmp0045 = aarch64_genMUL_3(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = aarch64_genADD_3(tmp0046, In, tmp0045); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - tmp0047 = aarch64_genR_3(tmp0047, tmp0046, immValueZero); - tmp0048 = aarch64_genMUL_3(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}); - if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0048); - if (!sum.dontFree) h2_freeReg(tmp0048.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genMV_3(ni, line, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0050 = aarch64_genADD_3(tmp0050, stride, njm2); - tmp0051 = aarch64_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = aarch64_genADD_3(tmp0052, In, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = aarch64_genR_3(tmp0053, tmp0052, immValueZero); - tmp0054 = aarch64_genMUL_3(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0054); - if (!sum.dontFree) h2_freeReg(tmp0054.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0055 = aarch64_genADD_3(tmp0055, stride, njm1); - tmp0056 = aarch64_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = aarch64_genADD_3(tmp0057, In, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = aarch64_genR_3(tmp0058, tmp0057, immValueZero); - tmp0059 = aarch64_genMUL_3(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0059); - if (!sum.dontFree) h2_freeReg(tmp0059.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0060 = aarch64_genADD_3(tmp0060, stride, column); - tmp0061 = aarch64_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = aarch64_genADD_3(tmp0062, In, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - tmp0063 = aarch64_genR_3(tmp0063, tmp0062, immValueZero); - tmp0064 = aarch64_genMUL_3(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0064); - if (!sum.dontFree) h2_freeReg(tmp0064.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0065 = aarch64_genADD_3(tmp0065, stride, njp1); - tmp0066 = aarch64_genMUL_3(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = aarch64_genADD_3(tmp0067, In, tmp0066); - if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); - tmp0068 = aarch64_genR_3(tmp0068, tmp0067, immValueZero); - tmp0069 = aarch64_genMUL_3(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}); - if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0069); - if (!sum.dontFree) h2_freeReg(tmp0069.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0070 = aarch64_genADD_3(tmp0070, stride, njp2); - tmp0071 = aarch64_genMUL_3(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); - tmp0072 = aarch64_genADD_3(tmp0072, In, tmp0071); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = aarch64_genR_3(tmp0073, tmp0072, immValueZero); - tmp0074 = aarch64_genMUL_3(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}); - if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0074); - if (!sum.dontFree) h2_freeReg(tmp0074.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0075 = aarch64_genADD_3(tmp0075, stride, njm2); - tmp0076 = aarch64_genMUL_3(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); - tmp0077 = aarch64_genADD_3(tmp0077, In, tmp0076); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = aarch64_genR_3(tmp0078, tmp0077, immValueZero); - tmp0079 = aarch64_genMUL_3(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}); - if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0079); - if (!sum.dontFree) h2_freeReg(tmp0079.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0080 = aarch64_genADD_3(tmp0080, stride, njm1); - tmp0081 = aarch64_genMUL_3(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); - tmp0082 = aarch64_genADD_3(tmp0082, In, tmp0081); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = aarch64_genR_3(tmp0083, tmp0082, immValueZero); - tmp0084 = aarch64_genMUL_3(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}); - if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0084); - if (!sum.dontFree) h2_freeReg(tmp0084.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0085 = aarch64_genADD_3(tmp0085, stride, column); - tmp0086 = aarch64_genMUL_3(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); - tmp0087 = aarch64_genADD_3(tmp0087, In, tmp0086); - if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); - tmp0088 = aarch64_genR_3(tmp0088, tmp0087, immValueZero); - tmp0089 = aarch64_genMUL_3(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}); - if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0089); - if (!sum.dontFree) h2_freeReg(tmp0089.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0090 = aarch64_genADD_3(tmp0090, stride, njp1); - tmp0091 = aarch64_genMUL_3(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); - tmp0092 = aarch64_genADD_3(tmp0092, In, tmp0091); - if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); - tmp0093 = aarch64_genR_3(tmp0093, tmp0092, immValueZero); - tmp0094 = aarch64_genMUL_3(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}); - if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0094); - if (!sum.dontFree) h2_freeReg(tmp0094.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0095 = aarch64_genADD_3(tmp0095, stride, njp2); - tmp0096 = aarch64_genMUL_3(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); - tmp0097 = aarch64_genADD_3(tmp0097, In, tmp0096); - if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); - tmp0098 = aarch64_genR_3(tmp0098, tmp0097, immValueZero); - tmp0099 = aarch64_genMUL_3(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}); - if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0099); - if (!sum.dontFree) h2_freeReg(tmp0099.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = aarch64_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = aarch64_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0100 = aarch64_genADD_3(tmp0100, stride, njm2); - tmp0101 = aarch64_genMUL_3(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); - tmp0102 = aarch64_genADD_3(tmp0102, In, tmp0101); - if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); - tmp0103 = aarch64_genR_3(tmp0103, tmp0102, immValueZero); - tmp0104 = aarch64_genMUL_3(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}); - if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0104); - if (!sum.dontFree) h2_freeReg(tmp0104.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0105 = aarch64_genADD_3(tmp0105, stride, njm1); - tmp0106 = aarch64_genMUL_3(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); - tmp0107 = aarch64_genADD_3(tmp0107, In, tmp0106); - if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); - tmp0108 = aarch64_genR_3(tmp0108, tmp0107, immValueZero); - tmp0109 = aarch64_genMUL_3(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}); - if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0109); - if (!sum.dontFree) h2_freeReg(tmp0109.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0110 = aarch64_genADD_3(tmp0110, stride, column); - tmp0111 = aarch64_genMUL_3(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); - tmp0112 = aarch64_genADD_3(tmp0112, In, tmp0111); - if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); - tmp0113 = aarch64_genR_3(tmp0113, tmp0112, immValueZero); - tmp0114 = aarch64_genMUL_3(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}); - if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0114); - if (!sum.dontFree) h2_freeReg(tmp0114.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0115 = aarch64_genADD_3(tmp0115, stride, njp1); - tmp0116 = aarch64_genMUL_3(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); - tmp0117 = aarch64_genADD_3(tmp0117, In, tmp0116); - if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); - tmp0118 = aarch64_genR_3(tmp0118, tmp0117, immValueZero); - tmp0119 = aarch64_genMUL_3(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}); - if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0119); - if (!sum.dontFree) h2_freeReg(tmp0119.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0120 = aarch64_genADD_3(tmp0120, stride, njp2); - tmp0121 = aarch64_genMUL_3(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); - tmp0122 = aarch64_genADD_3(tmp0122, In, tmp0121); - if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); - tmp0123 = aarch64_genR_3(tmp0123, tmp0122, immValueZero); - tmp0124 = aarch64_genMUL_3(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}); - if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); - sum = aarch64_genADD_3(sum, sum, tmp0124); - if (!sum.dontFree) h2_freeReg(tmp0124.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0125 = aarch64_genDIV_3(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, tmp0125, immValueZero); - if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -#if 0 -#endif -} - -// Compute a stencil for 1 point -int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) -{ - int line, column, sum = 0; - int offset = (Filter->width)/2; - - for (line = 0; line < Filter->height; line++) - { - for (column = 0; column < Filter->width; column++) - { - int ni = (l + line) - offset; - int nj = (c + column) - offset; - sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; - } - } - return sum / coeff; -} - - -void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelStatic(In, line, column, Filter, coeff); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelHL(In->pixelsArray, line, column, In->width); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) -{ - int errors = 0; - for(int line = 0 ; line < staticImg->height ; line++) - { - for(int column = 0 ; column < staticImg->width ; column++) - { - if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) - { - if (0 == errors) - { - printf("Alert : first difference at line %i column %i\n", line, column); - } - errors++; - } - } - } - return errors; -} - -int main(int argc, char *argv[]) -{ - int error, coeff, nXperiment = 20; - imgStruct_t *In, *OutH4, *OutStatic, *Filter; - char *filterImageName, *inputImageName; - if (argc < 5) - { - printf ("./Stencil \n"); - exit(-1); - } - - inputImageName = argv[1]; - filterImageName = argv[4]; - In = readPgmImage(inputImageName); - Filter = readPgmImage(filterImageName); - coeff = imgSum (Filter); -#ifdef VERBOSE - printf ("%s: coeff %d\n", filterImageName, coeff); - printImage (Filter, "Filter"); -#endif - assert (Filter->width == Filter->height); // Only square filters - OutStatic = createImage (In->height, In->width); - OutH4 = createImage (In->height, In->width); -#ifdef VERBOSE - printf ("after init\n"); - printImage(In, "In"); -#endif - ticks_t timeStatic = h2_getticks(); // Static convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionStatic(In, OutStatic, Filter, coeff); - } - timeStatic = h2_getticks() - timeStatic; -#ifdef VERBOSE - printf ("after static\n"); - printImage(OutStatic, "Out"); -#endif - - pifc kernelHL = (pifc)h2_malloc(8192); - ticks_t timeCodeGen = h2_getticks(); - switch (Filter->width) - { - case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; - case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; - case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; - default: printf ("Unknown filter size\n"); exit(-1); - } - timeCodeGen = h2_getticks() - timeCodeGen; - -#ifdef VERBOSE - printf ("after codegen\n"); -#endif - - ticks_t timeH4 = h2_getticks(); // Compilette convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionH4(In, OutH4, Filter, kernelHL); - } - timeH4 = h2_getticks() - timeH4; -#ifdef VERBOSE - printf ("after h2\n"); - printImage(OutH4, "Out H4"); -#endif - error = compareImages(OutH4, OutStatic); - printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", - 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z_xuRwNc?IP#C@vQVZ~UC1YXr$eRa+R$}dw8_o==c6@y;8@rml{tMe#OeyQ(6lA%j} zHehd5T+2azj=yP9{^Q57{L`0yBuke%iSX--QpSIzh2QD9^{ewOP<|;t=<|%)uIg7O zC>y{dQB}V>2Lt8T1wq`WAHR2_g#JcH>8tZHP=2kHn#zAAr|3N>r@#48d3CM^$}dw8 z{u3&%|B}r{kRU9TzB+#c83>DgCJggcVAZSZ!M$0Snyn?Cr!x@j%- zhkn&dk_ta{jtI&{{?MnO+OPCK;nP>=ji6j)tsqL=9rudyIiJ2dmjvY^E7ib}3O;w( zm!!TN?(X@P`75EX_K~Ez+kYxg^OGc%zB=b@ze@eDL6`bo>8tb5E~$S~wqK18g`e{4 zl&^mG+|&_@YWzY>T+*Jhvj<#CtNM}RrrV|dX{n}&(o^(XDDbvl?bn@_BSQJ<*H`(! zN5WhGIa&WXso$prB~|q*_VY+k{q2e&snVb8q!zDDRD^w^}NAAhnZBqs~@%@^EqgWxX$ up`RtI@uSu+3bQ_lxWco|LO&tnFlXZ7_n+Pmrqh2%o6x5}?eJc{Ec<^RwnugV diff --git a/Demos/Stencil/Stencil.power.c b/Demos/Stencil/Stencil.power.c deleted file mode 100644 index 826cc9f..0000000 --- a/Demos/Stencil/Stencil.power.c +++ /dev/null @@ -1,1955 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define PPC_DIVW_RRR_I_32_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d6 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVD__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x3d3 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO_RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d2 & 0x7ff) >> 0)); } while(0); -#define PPC_DIVDO__RRR_I_64_1(r0,r1,r2) do /* div */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x7d3 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (power)\\n"); - #endif - P2 = power_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_DIVDO__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include -#include -#include "ReadPgmImage.h" - -typedef int (*pifc)(int[], int, int, int); - - -void printImage(imgStruct_t *img, char *imageName) -{ - printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width ; column++) - { - printf("%03d ", img->pixelsArray[line*img->width+column]); - } - printf("\n"); - } - printf("\n"); -} - -int imgSum (imgStruct_t *img) -{ - int line, column, sum; - sum = 0; - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width; column++) - { - sum += img->pixelsArray[line*img->width+column]; - } - } - return (0 == sum)?1:sum; -} - -#if 0 -unsigned char clamp(int value) -{ - return (unsigned char)(0 > value)?0:(255 < value)?255:value; -} -#else -#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) -#endif - -pifc genKernel1x1(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x787F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, line, imgWidth); - tmp0001 = power_genADD_3(tmp0001, tmp0000, column); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genMUL_3(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = power_genADD_3(tmp0003, In, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = power_genR_3(tmp0004, tmp0003, immValueZero); - sum = power_genMUL_3(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); - if (!sum.dontFree) h2_freeReg(tmp0004.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0005 = power_genDIV_3(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel3x3(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 19 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 17, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 18, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7F87F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - njp1 = power_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = power_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = power_genADD_3(tmp0000, stride, njm1); - tmp0001 = power_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = power_genR_3(tmp0003, tmp0002, immValueZero); - sum = power_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = power_genADD_3(tmp0004, stride, column); - tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = power_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = power_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = power_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = power_genADD_3(tmp0009, stride, njp1); - tmp0010 = power_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = power_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = power_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = power_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = power_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genMV_2(ni, line); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0015 = power_genADD_3(tmp0015, stride, njm1); - tmp0016 = power_genMUL_3(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = power_genADD_3(tmp0017, In, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = power_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = power_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - sum = power_genADD_3(sum, sum, tmp0019); - if (!sum.dontFree) h2_freeReg(tmp0019.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0020 = power_genADD_3(tmp0020, stride, column); - tmp0021 = power_genMUL_3(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = power_genADD_3(tmp0022, In, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = power_genR_3(tmp0023, tmp0022, immValueZero); - tmp0024 = power_genMUL_3(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - sum = power_genADD_3(sum, sum, tmp0024); - if (!sum.dontFree) h2_freeReg(tmp0024.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0025 = power_genADD_3(tmp0025, stride, njp1); - tmp0026 = power_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = power_genADD_3(tmp0027, In, tmp0026); - if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); - tmp0028 = power_genR_3(tmp0028, tmp0027, immValueZero); - tmp0029 = power_genMUL_3(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}); - if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); - sum = power_genADD_3(sum, sum, tmp0029); - if (!sum.dontFree) h2_freeReg(tmp0029.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0030 = power_genADD_3(tmp0030, stride, njm1); - tmp0031 = power_genMUL_3(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = power_genADD_3(tmp0032, In, tmp0031); - if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); - tmp0033 = power_genR_3(tmp0033, tmp0032, immValueZero); - tmp0034 = power_genMUL_3(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}); - if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); - sum = power_genADD_3(sum, sum, tmp0034); - if (!sum.dontFree) h2_freeReg(tmp0034.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0035 = power_genADD_3(tmp0035, stride, column); - tmp0036 = power_genMUL_3(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = power_genADD_3(tmp0037, In, tmp0036); - if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); - tmp0038 = power_genR_3(tmp0038, tmp0037, immValueZero); - tmp0039 = power_genMUL_3(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}); - if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); - sum = power_genADD_3(sum, sum, tmp0039); - if (!sum.dontFree) h2_freeReg(tmp0039.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0040 = power_genADD_3(tmp0040, stride, njp1); - tmp0041 = power_genMUL_3(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = power_genADD_3(tmp0042, In, tmp0041); - if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); - tmp0043 = power_genR_3(tmp0043, tmp0042, immValueZero); - tmp0044 = power_genMUL_3(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}); - if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); - sum = power_genADD_3(sum, sum, tmp0044); - if (!sum.dontFree) h2_freeReg(tmp0044.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0045 = power_genDIV_3(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0045); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel5x5(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 41 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 17, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 18, true}; - h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 19, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 20, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1FF87F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - njm2 = power_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = power_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp1 = power_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp2 = power_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = power_genADD_3(tmp0000, stride, njm2); - tmp0001 = power_genMUL_3(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = power_genR_3(tmp0003, tmp0002, immValueZero); - sum = power_genMUL_3(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = power_genADD_3(tmp0004, stride, njm1); - tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = power_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = power_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = power_genMUL_3(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = power_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = power_genADD_3(tmp0009, stride, column); - tmp0010 = power_genMUL_3(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = power_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = power_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = power_genMUL_3(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = power_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0014 = power_genADD_3(tmp0014, stride, njp1); - tmp0015 = power_genMUL_3(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = power_genADD_3(tmp0016, In, tmp0015); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = power_genR_3(tmp0017, tmp0016, immValueZero); - tmp0018 = power_genMUL_3(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}); - if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); - sum = power_genADD_3(sum, sum, tmp0018); - if (!sum.dontFree) h2_freeReg(tmp0018.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0019 = power_genADD_3(tmp0019, stride, njp2); - tmp0020 = power_genMUL_3(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - tmp0021 = power_genADD_3(tmp0021, In, tmp0020); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = power_genR_3(tmp0022, tmp0021, immValueZero); - tmp0023 = power_genMUL_3(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}); - if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); - sum = power_genADD_3(sum, sum, tmp0023); - if (!sum.dontFree) h2_freeReg(tmp0023.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0024 = power_genADD_3(tmp0024, stride, njm2); - tmp0025 = power_genMUL_3(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); - tmp0026 = power_genADD_3(tmp0026, In, tmp0025); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = power_genR_3(tmp0027, tmp0026, immValueZero); - tmp0028 = power_genMUL_3(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - sum = power_genADD_3(sum, sum, tmp0028); - if (!sum.dontFree) h2_freeReg(tmp0028.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0029 = power_genADD_3(tmp0029, stride, njm1); - tmp0030 = power_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = power_genADD_3(tmp0031, In, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = power_genR_3(tmp0032, tmp0031, immValueZero); - tmp0033 = power_genMUL_3(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - sum = power_genADD_3(sum, sum, tmp0033); - if (!sum.dontFree) h2_freeReg(tmp0033.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0034 = power_genADD_3(tmp0034, stride, column); - tmp0035 = power_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = power_genADD_3(tmp0036, In, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = power_genR_3(tmp0037, tmp0036, immValueZero); - tmp0038 = power_genMUL_3(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - sum = power_genADD_3(sum, sum, tmp0038); - if (!sum.dontFree) h2_freeReg(tmp0038.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0039 = power_genADD_3(tmp0039, stride, njp1); - tmp0040 = power_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = power_genADD_3(tmp0041, In, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = power_genR_3(tmp0042, tmp0041, immValueZero); - tmp0043 = power_genMUL_3(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - sum = power_genADD_3(sum, sum, tmp0043); - if (!sum.dontFree) h2_freeReg(tmp0043.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0044 = power_genADD_3(tmp0044, stride, njp2); - tmp0045 = power_genMUL_3(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = power_genADD_3(tmp0046, In, tmp0045); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - tmp0047 = power_genR_3(tmp0047, tmp0046, immValueZero); - tmp0048 = power_genMUL_3(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}); - if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); - sum = power_genADD_3(sum, sum, tmp0048); - if (!sum.dontFree) h2_freeReg(tmp0048.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genMV_2(ni, line); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0050 = power_genADD_3(tmp0050, stride, njm2); - tmp0051 = power_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = power_genADD_3(tmp0052, In, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = power_genR_3(tmp0053, tmp0052, immValueZero); - tmp0054 = power_genMUL_3(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - sum = power_genADD_3(sum, sum, tmp0054); - if (!sum.dontFree) h2_freeReg(tmp0054.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0055 = power_genADD_3(tmp0055, stride, njm1); - tmp0056 = power_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = power_genADD_3(tmp0057, In, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = power_genR_3(tmp0058, tmp0057, immValueZero); - tmp0059 = power_genMUL_3(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - sum = power_genADD_3(sum, sum, tmp0059); - if (!sum.dontFree) h2_freeReg(tmp0059.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0060 = power_genADD_3(tmp0060, stride, column); - tmp0061 = power_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = power_genADD_3(tmp0062, In, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - tmp0063 = power_genR_3(tmp0063, tmp0062, immValueZero); - tmp0064 = power_genMUL_3(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - sum = power_genADD_3(sum, sum, tmp0064); - if (!sum.dontFree) h2_freeReg(tmp0064.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0065 = power_genADD_3(tmp0065, stride, njp1); - tmp0066 = power_genMUL_3(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = power_genADD_3(tmp0067, In, tmp0066); - if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); - tmp0068 = power_genR_3(tmp0068, tmp0067, immValueZero); - tmp0069 = power_genMUL_3(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}); - if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); - sum = power_genADD_3(sum, sum, tmp0069); - if (!sum.dontFree) h2_freeReg(tmp0069.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0070 = power_genADD_3(tmp0070, stride, njp2); - tmp0071 = power_genMUL_3(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); - tmp0072 = power_genADD_3(tmp0072, In, tmp0071); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = power_genR_3(tmp0073, tmp0072, immValueZero); - tmp0074 = power_genMUL_3(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}); - if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); - sum = power_genADD_3(sum, sum, tmp0074); - if (!sum.dontFree) h2_freeReg(tmp0074.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0075 = power_genADD_3(tmp0075, stride, njm2); - tmp0076 = power_genMUL_3(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); - tmp0077 = power_genADD_3(tmp0077, In, tmp0076); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = power_genR_3(tmp0078, tmp0077, immValueZero); - tmp0079 = power_genMUL_3(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}); - if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); - sum = power_genADD_3(sum, sum, tmp0079); - if (!sum.dontFree) h2_freeReg(tmp0079.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0080 = power_genADD_3(tmp0080, stride, njm1); - tmp0081 = power_genMUL_3(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); - tmp0082 = power_genADD_3(tmp0082, In, tmp0081); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = power_genR_3(tmp0083, tmp0082, immValueZero); - tmp0084 = power_genMUL_3(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}); - if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); - sum = power_genADD_3(sum, sum, tmp0084); - if (!sum.dontFree) h2_freeReg(tmp0084.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0085 = power_genADD_3(tmp0085, stride, column); - tmp0086 = power_genMUL_3(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); - tmp0087 = power_genADD_3(tmp0087, In, tmp0086); - if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); - tmp0088 = power_genR_3(tmp0088, tmp0087, immValueZero); - tmp0089 = power_genMUL_3(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}); - if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); - sum = power_genADD_3(sum, sum, tmp0089); - if (!sum.dontFree) h2_freeReg(tmp0089.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0090 = power_genADD_3(tmp0090, stride, njp1); - tmp0091 = power_genMUL_3(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); - tmp0092 = power_genADD_3(tmp0092, In, tmp0091); - if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); - tmp0093 = power_genR_3(tmp0093, tmp0092, immValueZero); - tmp0094 = power_genMUL_3(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}); - if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); - sum = power_genADD_3(sum, sum, tmp0094); - if (!sum.dontFree) h2_freeReg(tmp0094.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0095 = power_genADD_3(tmp0095, stride, njp2); - tmp0096 = power_genMUL_3(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); - tmp0097 = power_genADD_3(tmp0097, In, tmp0096); - if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); - tmp0098 = power_genR_3(tmp0098, tmp0097, immValueZero); - tmp0099 = power_genMUL_3(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}); - if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); - sum = power_genADD_3(sum, sum, tmp0099); - if (!sum.dontFree) h2_freeReg(tmp0099.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = power_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = power_genMUL_3(stride, ni, imgWidth); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0100 = power_genADD_3(tmp0100, stride, njm2); - tmp0101 = power_genMUL_3(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); - tmp0102 = power_genADD_3(tmp0102, In, tmp0101); - if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); - tmp0103 = power_genR_3(tmp0103, tmp0102, immValueZero); - tmp0104 = power_genMUL_3(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}); - if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); - sum = power_genADD_3(sum, sum, tmp0104); - if (!sum.dontFree) h2_freeReg(tmp0104.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0105 = power_genADD_3(tmp0105, stride, njm1); - tmp0106 = power_genMUL_3(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); - tmp0107 = power_genADD_3(tmp0107, In, tmp0106); - if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); - tmp0108 = power_genR_3(tmp0108, tmp0107, immValueZero); - tmp0109 = power_genMUL_3(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}); - if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); - sum = power_genADD_3(sum, sum, tmp0109); - if (!sum.dontFree) h2_freeReg(tmp0109.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0110 = power_genADD_3(tmp0110, stride, column); - tmp0111 = power_genMUL_3(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); - tmp0112 = power_genADD_3(tmp0112, In, tmp0111); - if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); - tmp0113 = power_genR_3(tmp0113, tmp0112, immValueZero); - tmp0114 = power_genMUL_3(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}); - if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); - sum = power_genADD_3(sum, sum, tmp0114); - if (!sum.dontFree) h2_freeReg(tmp0114.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0115 = power_genADD_3(tmp0115, stride, njp1); - tmp0116 = power_genMUL_3(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); - tmp0117 = power_genADD_3(tmp0117, In, tmp0116); - if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); - tmp0118 = power_genR_3(tmp0118, tmp0117, immValueZero); - tmp0119 = power_genMUL_3(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}); - if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); - sum = power_genADD_3(sum, sum, tmp0119); - if (!sum.dontFree) h2_freeReg(tmp0119.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0120 = power_genADD_3(tmp0120, stride, njp2); - tmp0121 = power_genMUL_3(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); - tmp0122 = power_genADD_3(tmp0122, In, tmp0121); - if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); - tmp0123 = power_genR_3(tmp0123, tmp0122, immValueZero); - tmp0124 = power_genMUL_3(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}); - if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); - sum = power_genADD_3(sum, sum, tmp0124); - if (!sum.dontFree) h2_freeReg(tmp0124.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0125 = power_genDIV_3(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}); - h2_outputVarName = power_genMV_2(h2_outputVarName, tmp0125); - if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -#if 0 -#endif -} - -// Compute a stencil for 1 point -int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) -{ - int line, column, sum = 0; - int offset = (Filter->width)/2; - - for (line = 0; line < Filter->height; line++) - { - for (column = 0; column < Filter->width; column++) - { - int ni = (l + line) - offset; - int nj = (c + column) - offset; - sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; - } - } - return sum / coeff; -} - - -void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelStatic(In, line, column, Filter, coeff); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelHL(In->pixelsArray, line, column, In->width); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) -{ - int errors = 0; - for(int line = 0 ; line < staticImg->height ; line++) - { - for(int column = 0 ; column < staticImg->width ; column++) - { - if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) - { - if (0 == errors) - { - printf("Alert : first difference at line %i column %i\n", line, column); - } - errors++; - } - } - } - return errors; -} - -int main(int argc, char *argv[]) -{ - int error, coeff, nXperiment = 20; - imgStruct_t *In, *OutH4, *OutStatic, *Filter; - char *filterImageName, *inputImageName; - if (argc < 5) - { - printf ("./Stencil \n"); - exit(-1); - } - - inputImageName = argv[1]; - filterImageName = argv[4]; - In = readPgmImage(inputImageName); - Filter = readPgmImage(filterImageName); - coeff = imgSum (Filter); -#ifdef VERBOSE - printf ("%s: coeff %d\n", filterImageName, coeff); - printImage (Filter, "Filter"); -#endif - assert (Filter->width == Filter->height); // Only square filters - OutStatic = createImage (In->height, In->width); - OutH4 = createImage (In->height, In->width); -#ifdef VERBOSE - printf ("after init\n"); - printImage(In, "In"); -#endif - ticks_t timeStatic = h2_getticks(); // Static convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionStatic(In, OutStatic, Filter, coeff); - } - timeStatic = h2_getticks() - timeStatic; -#ifdef VERBOSE - printf ("after static\n"); - printImage(OutStatic, "Out"); -#endif - - pifc kernelHL = (pifc)h2_malloc(8192); - ticks_t timeCodeGen = h2_getticks(); - switch (Filter->width) - { - case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; - case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; - case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; - default: printf ("Unknown filter size\n"); exit(-1); - } - timeCodeGen = h2_getticks() - timeCodeGen; - -#ifdef VERBOSE - printf ("after codegen\n"); -#endif - - ticks_t timeH4 = h2_getticks(); // Compilette convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionH4(In, OutH4, Filter, kernelHL); - } - timeH4 = h2_getticks() - timeH4; -#ifdef VERBOSE - printf ("after h2\n"); - printImage(OutH4, "Out H4"); -#endif - error = compareImages(OutH4, OutStatic); - printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", - filterImageName, - Filter->width, Filter->height, In->width, In->height, - timeStatic/nXperiment, timeH4/nXperiment, - h2_codeGenTime, h2_insnGenerated, - error); - -#if VERBOSE - writePgmImage(OutStatic, argv[2]); - writePgmImage(OutH4, argv[3]); -#endif - - return (0 == error)?0:-1; -} diff --git a/Demos/Stencil/Stencil.riscv b/Demos/Stencil/Stencil.riscv deleted file mode 100755 index 60c93461d991da91012ba0558f9cc14c29dff531..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 171700 zcmeFa3wTt;{l~q@S=q>+0*V!Dy{x;*VVkD$T5GM0? z)t0}>b7E{M0A#WAyDS=IH0{yQmBmF{7I}=H)W zV)O$mu8Xy;xK2}L5a-Hb9{(-JIsIFIl0MzrZs&O9_!{|57Kw+9?c!mN-hc712Yxo} z(Z~Nf_Gcp>9W`{!<(K{J(P1MlzwCkJQNxojHO`f^zT z;7_)@Q+_}>ha&$Jzxe-I6e$x)PmZxS<#bBqUsoDGq?{f3BlS3=?co32B98T-{(lke zUJ-RUX89-O5IJ7?yQC*eTAJ%ot-9+Ds`7`c`1cXpZKt16(9@O{)3aZi{8|1Rn9~HU7q{b9`kOw>DH&79o6Hyr>Bog?*HrBbDr*+b=|QOOP3y) zyl(c_kM}75BD>Gwvv(go?40(q{CB3FchQE^kN5mX{coEkS&M)A=O144`Y(SlfAX*X?YMZf?6TG03R)wu8~G>45>J`uXlY+94@4ZlkY;tn z@&2^aBH9P!`Hx7+N!cAbF@*o8MBp!@JtE?K+0*2Rmf8~b}4~`r;e5CEcv5$_n4IX^os8J7& z96k7<`yL%84-b9hzLBhiY*svT?FDG%}&KSZ;gCJm53kE|O`CP~%}gS zTbcJ#sc6yo@?IG$$ERndr^zEzslW8x)K3yp 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zB*w^5hUWt~`Q(ane3nu77IF`PPje{8-^>k=dsUYqle+la;-7KS2Fl6bQuxSs^huJj z_3IHi-eXUP9LLBU#=d_=fzij`rdLCb<7y70k6)T#`)rrLIc|eo#LWSICL(vcmRo`{ zb5IA57jUxvJQ6slkH68(K_1VSaiYzVDZdwTJ%&JTY~V|l29upQ-xgOB=)<(j_b{V! z*Fvr`&Pav4X=CIZ-xi;iPFJ!<$J{Y;_x9N$ryg}mK_j<7%bEU8F4$rT7aV<1j_2Yr za+`;3F*TeXQigKtw4AOkN|)H;bCE|hl;Oc=RtA%v`yN~HD?H{fka?sT@$7qHA0FwR pi1M{K83zqG`II-}2GMezEw)DHk -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32M_DIV_RRR_I_32_1(r3,r1,r2) do /* DIV */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x4 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genDIV_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) - { // RISCV has no DIVI - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { // X * NPowerOf2 = X >> N (immediate shift left) - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSR_3(P0, P1, P2); - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_DIV_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include -#include -#include -#include "ReadPgmImage.h" - -typedef int (*pifc)(int[], int, int, int); - - -void printImage(imgStruct_t *img, char *imageName) -{ - printf ("ImageName & size: %s %dx%d\n", imageName, img->height, img->width); - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width ; column++) - { - printf("%03d ", img->pixelsArray[line*img->width+column]); - } - printf("\n"); - } - printf("\n"); -} - -int imgSum (imgStruct_t *img) -{ - int line, column, sum; - sum = 0; - for(int line = 0 ; line < img->height ; line++) - { - for(int column = 0 ; column < img->width; column++) - { - sum += img->pixelsArray[line*img->width+column]; - } - } - return (0 == sum)?1:sum; -} - -#if 0 -unsigned char clamp(int value) -{ - return (unsigned char)(0 > value)?0:(255 < value)?255:value; -} -#else -#define clamp(value) ((unsigned char)(0 > value)?0:(255 < value)?255:value) -#endif - -pifc genKernel1x1(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x3F3F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, line, imgWidth, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, tmp0000, column); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genMUL_4(tmp0002, tmp0001, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = riscv_genADD_3(tmp0003, In, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = riscv_genR_3(tmp0004, tmp0003, immValueZero); - sum = riscv_genMUL_4(sum, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}, immValueZero); - if (!sum.dontFree) h2_freeReg(tmp0004.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0005 = riscv_genDIV_4(tmp0005, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel3x3(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 19 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 28, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 29, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x30003FFF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - njp1 = riscv_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = riscv_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = riscv_genADD_3(tmp0000, stride, njm1); - tmp0001 = riscv_genMUL_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = riscv_genR_3(tmp0003, tmp0002, immValueZero); - sum = riscv_genMUL_4(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0]))}, immValueZero); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = riscv_genADD_3(tmp0004, stride, column); - tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = riscv_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = riscv_genMUL_4(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1]))}, immValueZero); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = riscv_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = riscv_genADD_3(tmp0009, stride, njp1); - tmp0010 = riscv_genMUL_4(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = riscv_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = riscv_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = riscv_genMUL_4(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2]))}, immValueZero); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = riscv_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genMV_2(ni, line); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0015 = riscv_genADD_3(tmp0015, stride, njm1); - tmp0016 = riscv_genMUL_4(tmp0016, tmp0015, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = riscv_genADD_3(tmp0017, In, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = riscv_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = riscv_genMUL_4(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+0]))}, immValueZero); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - sum = riscv_genADD_3(sum, sum, tmp0019); - if (!sum.dontFree) h2_freeReg(tmp0019.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0020 = riscv_genADD_3(tmp0020, stride, column); - tmp0021 = riscv_genMUL_4(tmp0021, tmp0020, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = riscv_genADD_3(tmp0022, In, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = riscv_genR_3(tmp0023, tmp0022, immValueZero); - tmp0024 = riscv_genMUL_4(tmp0024, tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+1]))}, immValueZero); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - sum = riscv_genADD_3(sum, sum, tmp0024); - if (!sum.dontFree) h2_freeReg(tmp0024.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0025 = riscv_genADD_3(tmp0025, stride, njp1); - tmp0026 = riscv_genMUL_4(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = riscv_genADD_3(tmp0027, In, tmp0026); - if (!tmp0027.dontFree) h2_freeReg(tmp0026.regNro); - tmp0028 = riscv_genR_3(tmp0028, tmp0027, immValueZero); - tmp0029 = riscv_genMUL_4(tmp0029, tmp0028, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*3+2]))}, immValueZero); - if (!tmp0029.dontFree) h2_freeReg(tmp0028.regNro); - sum = riscv_genADD_3(sum, sum, tmp0029); - if (!sum.dontFree) h2_freeReg(tmp0029.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0030 = riscv_genADD_3(tmp0030, stride, njm1); - tmp0031 = riscv_genMUL_4(tmp0031, tmp0030, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = riscv_genADD_3(tmp0032, In, tmp0031); - if (!tmp0032.dontFree) h2_freeReg(tmp0031.regNro); - tmp0033 = riscv_genR_3(tmp0033, tmp0032, immValueZero); - tmp0034 = riscv_genMUL_4(tmp0034, tmp0033, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+0]))}, immValueZero); - if (!tmp0034.dontFree) h2_freeReg(tmp0033.regNro); - sum = riscv_genADD_3(sum, sum, tmp0034); - if (!sum.dontFree) h2_freeReg(tmp0034.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0035 = riscv_genADD_3(tmp0035, stride, column); - tmp0036 = riscv_genMUL_4(tmp0036, tmp0035, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = riscv_genADD_3(tmp0037, In, tmp0036); - if (!tmp0037.dontFree) h2_freeReg(tmp0036.regNro); - tmp0038 = riscv_genR_3(tmp0038, tmp0037, immValueZero); - tmp0039 = riscv_genMUL_4(tmp0039, tmp0038, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+1]))}, immValueZero); - if (!tmp0039.dontFree) h2_freeReg(tmp0038.regNro); - sum = riscv_genADD_3(sum, sum, tmp0039); - if (!sum.dontFree) h2_freeReg(tmp0039.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0040 = riscv_genADD_3(tmp0040, stride, njp1); - tmp0041 = riscv_genMUL_4(tmp0041, tmp0040, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = riscv_genADD_3(tmp0042, In, tmp0041); - if (!tmp0042.dontFree) h2_freeReg(tmp0041.regNro); - tmp0043 = riscv_genR_3(tmp0043, tmp0042, immValueZero); - tmp0044 = riscv_genMUL_4(tmp0044, tmp0043, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*3+2]))}, immValueZero); - if (!tmp0044.dontFree) h2_freeReg(tmp0043.regNro); - sum = riscv_genADD_3(sum, sum, tmp0044); - if (!sum.dontFree) h2_freeReg(tmp0044.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0045 = riscv_genDIV_4(tmp0045, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0045); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -pifc genKernel5x5(pifc ptr, int* Filter, int coeff) -{ - /* Code Generation of 41 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t In = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t line = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t column = {H2REGISTER, 'i', 1, 32, 12, true}; - h2_sValue_t imgWidth = {H2REGISTER, 'i', 1, 32, 13, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t sum = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t ni = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t njm2 = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t njm1 = {H2REGISTER, 'i', 1, 32, 28, true}; - h2_sValue_t njp1 = {H2REGISTER, 'i', 1, 32, 29, true}; - h2_sValue_t njp2 = {H2REGISTER, 'i', 1, 32, 30, true}; - h2_sValue_t stride = {H2REGISTER, 'i', 1, 32, 31, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0084 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0085 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0086 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0087 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0088 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0089 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0090 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0091 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0092 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0093 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0094 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0095 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0096 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0097 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0098 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0099 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0100 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0101 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0102 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0103 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0104 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0105 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0106 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0107 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0108 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0109 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0110 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0111 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0112 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0113 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0114 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0115 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0116 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0117 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0118 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0119 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0120 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0121 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0122 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0123 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0124 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0125 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0126 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF0003FFF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - njm2 = riscv_genSUB_3(njm2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njm1 = riscv_genSUB_3(njm1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp1 = riscv_genADD_3(njp1, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - njp2 = riscv_genADD_3(njp2, column, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0000 = riscv_genADD_3(tmp0000, stride, njm2); - tmp0001 = riscv_genMUL_4(tmp0001, tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genADD_3(tmp0002, In, tmp0001); - if (!tmp0002.dontFree) h2_freeReg(tmp0001.regNro); - tmp0003 = riscv_genR_3(tmp0003, tmp0002, immValueZero); - sum = riscv_genMUL_4(sum, tmp0003, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+0]))}, immValueZero); - if (!sum.dontFree) h2_freeReg(tmp0003.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0004 = riscv_genADD_3(tmp0004, stride, njm1); - tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = riscv_genADD_3(tmp0006, In, tmp0005); - if (!tmp0006.dontFree) h2_freeReg(tmp0005.regNro); - tmp0007 = riscv_genR_3(tmp0007, tmp0006, immValueZero); - tmp0008 = riscv_genMUL_4(tmp0008, tmp0007, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+1]))}, immValueZero); - if (!tmp0008.dontFree) h2_freeReg(tmp0007.regNro); - sum = riscv_genADD_3(sum, sum, tmp0008); - if (!sum.dontFree) h2_freeReg(tmp0008.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0009 = riscv_genADD_3(tmp0009, stride, column); - tmp0010 = riscv_genMUL_4(tmp0010, tmp0009, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = riscv_genADD_3(tmp0011, In, tmp0010); - if (!tmp0011.dontFree) h2_freeReg(tmp0010.regNro); - tmp0012 = riscv_genR_3(tmp0012, tmp0011, immValueZero); - tmp0013 = riscv_genMUL_4(tmp0013, tmp0012, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+2]))}, immValueZero); - if (!tmp0013.dontFree) h2_freeReg(tmp0012.regNro); - sum = riscv_genADD_3(sum, sum, tmp0013); - if (!sum.dontFree) h2_freeReg(tmp0013.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0014 = riscv_genADD_3(tmp0014, stride, njp1); - tmp0015 = riscv_genMUL_4(tmp0015, tmp0014, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = riscv_genADD_3(tmp0016, In, tmp0015); - if (!tmp0016.dontFree) h2_freeReg(tmp0015.regNro); - tmp0017 = riscv_genR_3(tmp0017, tmp0016, immValueZero); - tmp0018 = riscv_genMUL_4(tmp0018, tmp0017, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+3]))}, immValueZero); - if (!tmp0018.dontFree) h2_freeReg(tmp0017.regNro); - sum = riscv_genADD_3(sum, sum, tmp0018); - if (!sum.dontFree) h2_freeReg(tmp0018.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0019 = riscv_genADD_3(tmp0019, stride, njp2); - tmp0020 = riscv_genMUL_4(tmp0020, tmp0019, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - tmp0021 = riscv_genADD_3(tmp0021, In, tmp0020); - if (!tmp0021.dontFree) h2_freeReg(tmp0020.regNro); - tmp0022 = riscv_genR_3(tmp0022, tmp0021, immValueZero); - tmp0023 = riscv_genMUL_4(tmp0023, tmp0022, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[0*5+4]))}, immValueZero); - if (!tmp0023.dontFree) h2_freeReg(tmp0022.regNro); - sum = riscv_genADD_3(sum, sum, tmp0023); - if (!sum.dontFree) h2_freeReg(tmp0023.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genSUB_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0024 = riscv_genADD_3(tmp0024, stride, njm2); - tmp0025 = riscv_genMUL_4(tmp0025, tmp0024, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0025.dontFree) h2_freeReg(tmp0024.regNro); - tmp0026 = riscv_genADD_3(tmp0026, In, tmp0025); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = riscv_genR_3(tmp0027, tmp0026, immValueZero); - tmp0028 = riscv_genMUL_4(tmp0028, tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+0]))}, immValueZero); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - sum = riscv_genADD_3(sum, sum, tmp0028); - if (!sum.dontFree) h2_freeReg(tmp0028.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0029 = riscv_genADD_3(tmp0029, stride, njm1); - tmp0030 = riscv_genMUL_4(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = riscv_genADD_3(tmp0031, In, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = riscv_genR_3(tmp0032, tmp0031, immValueZero); - tmp0033 = riscv_genMUL_4(tmp0033, tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+1]))}, immValueZero); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - sum = riscv_genADD_3(sum, sum, tmp0033); - if (!sum.dontFree) h2_freeReg(tmp0033.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0034 = riscv_genADD_3(tmp0034, stride, column); - tmp0035 = riscv_genMUL_4(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = riscv_genADD_3(tmp0036, In, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = riscv_genR_3(tmp0037, tmp0036, immValueZero); - tmp0038 = riscv_genMUL_4(tmp0038, tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+2]))}, immValueZero); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - sum = riscv_genADD_3(sum, sum, tmp0038); - if (!sum.dontFree) h2_freeReg(tmp0038.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0039 = riscv_genADD_3(tmp0039, stride, njp1); - tmp0040 = riscv_genMUL_4(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = riscv_genADD_3(tmp0041, In, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - tmp0042 = riscv_genR_3(tmp0042, tmp0041, immValueZero); - tmp0043 = riscv_genMUL_4(tmp0043, tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+3]))}, immValueZero); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - sum = riscv_genADD_3(sum, sum, tmp0043); - if (!sum.dontFree) h2_freeReg(tmp0043.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0044 = riscv_genADD_3(tmp0044, stride, njp2); - tmp0045 = riscv_genMUL_4(tmp0045, tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = riscv_genADD_3(tmp0046, In, tmp0045); - if (!tmp0046.dontFree) h2_freeReg(tmp0045.regNro); - tmp0047 = riscv_genR_3(tmp0047, tmp0046, immValueZero); - tmp0048 = riscv_genMUL_4(tmp0048, tmp0047, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[1*5+4]))}, immValueZero); - if (!tmp0048.dontFree) h2_freeReg(tmp0047.regNro); - sum = riscv_genADD_3(sum, sum, tmp0048); - if (!sum.dontFree) h2_freeReg(tmp0048.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genMV_2(ni, line); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0050 = riscv_genADD_3(tmp0050, stride, njm2); - tmp0051 = riscv_genMUL_4(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = riscv_genADD_3(tmp0052, In, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = riscv_genR_3(tmp0053, tmp0052, immValueZero); - tmp0054 = riscv_genMUL_4(tmp0054, tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+0]))}, immValueZero); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - sum = riscv_genADD_3(sum, sum, tmp0054); - if (!sum.dontFree) h2_freeReg(tmp0054.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0055 = riscv_genADD_3(tmp0055, stride, njm1); - tmp0056 = riscv_genMUL_4(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = riscv_genADD_3(tmp0057, In, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = riscv_genR_3(tmp0058, tmp0057, immValueZero); - tmp0059 = riscv_genMUL_4(tmp0059, tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+1]))}, immValueZero); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - sum = riscv_genADD_3(sum, sum, tmp0059); - if (!sum.dontFree) h2_freeReg(tmp0059.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0060 = riscv_genADD_3(tmp0060, stride, column); - tmp0061 = riscv_genMUL_4(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = riscv_genADD_3(tmp0062, In, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - tmp0063 = riscv_genR_3(tmp0063, tmp0062, immValueZero); - tmp0064 = riscv_genMUL_4(tmp0064, tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+2]))}, immValueZero); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - sum = riscv_genADD_3(sum, sum, tmp0064); - if (!sum.dontFree) h2_freeReg(tmp0064.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0065 = riscv_genADD_3(tmp0065, stride, njp1); - tmp0066 = riscv_genMUL_4(tmp0066, tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = riscv_genADD_3(tmp0067, In, tmp0066); - if (!tmp0067.dontFree) h2_freeReg(tmp0066.regNro); - tmp0068 = riscv_genR_3(tmp0068, tmp0067, immValueZero); - tmp0069 = riscv_genMUL_4(tmp0069, tmp0068, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+3]))}, immValueZero); - if (!tmp0069.dontFree) h2_freeReg(tmp0068.regNro); - sum = riscv_genADD_3(sum, sum, tmp0069); - if (!sum.dontFree) h2_freeReg(tmp0069.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0070 = riscv_genADD_3(tmp0070, stride, njp2); - tmp0071 = riscv_genMUL_4(tmp0071, tmp0070, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0071.dontFree) h2_freeReg(tmp0070.regNro); - tmp0072 = riscv_genADD_3(tmp0072, In, tmp0071); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = riscv_genR_3(tmp0073, tmp0072, immValueZero); - tmp0074 = riscv_genMUL_4(tmp0074, tmp0073, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[2*5+4]))}, immValueZero); - if (!tmp0074.dontFree) h2_freeReg(tmp0073.regNro); - sum = riscv_genADD_3(sum, sum, tmp0074); - if (!sum.dontFree) h2_freeReg(tmp0074.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0075 = riscv_genADD_3(tmp0075, stride, njm2); - tmp0076 = riscv_genMUL_4(tmp0076, tmp0075, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0076.dontFree) h2_freeReg(tmp0075.regNro); - tmp0077 = riscv_genADD_3(tmp0077, In, tmp0076); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = riscv_genR_3(tmp0078, tmp0077, immValueZero); - tmp0079 = riscv_genMUL_4(tmp0079, tmp0078, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+0]))}, immValueZero); - if (!tmp0079.dontFree) h2_freeReg(tmp0078.regNro); - sum = riscv_genADD_3(sum, sum, tmp0079); - if (!sum.dontFree) h2_freeReg(tmp0079.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0080 = riscv_genADD_3(tmp0080, stride, njm1); - tmp0081 = riscv_genMUL_4(tmp0081, tmp0080, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0081.dontFree) h2_freeReg(tmp0080.regNro); - tmp0082 = riscv_genADD_3(tmp0082, In, tmp0081); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = riscv_genR_3(tmp0083, tmp0082, immValueZero); - tmp0084 = riscv_genMUL_4(tmp0084, tmp0083, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+1]))}, immValueZero); - if (!tmp0084.dontFree) h2_freeReg(tmp0083.regNro); - sum = riscv_genADD_3(sum, sum, tmp0084); - if (!sum.dontFree) h2_freeReg(tmp0084.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0085 = riscv_genADD_3(tmp0085, stride, column); - tmp0086 = riscv_genMUL_4(tmp0086, tmp0085, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0086.dontFree) h2_freeReg(tmp0085.regNro); - tmp0087 = riscv_genADD_3(tmp0087, In, tmp0086); - if (!tmp0087.dontFree) h2_freeReg(tmp0086.regNro); - tmp0088 = riscv_genR_3(tmp0088, tmp0087, immValueZero); - tmp0089 = riscv_genMUL_4(tmp0089, tmp0088, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+2]))}, immValueZero); - if (!tmp0089.dontFree) h2_freeReg(tmp0088.regNro); - sum = riscv_genADD_3(sum, sum, tmp0089); - if (!sum.dontFree) h2_freeReg(tmp0089.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0090 = riscv_genADD_3(tmp0090, stride, njp1); - tmp0091 = riscv_genMUL_4(tmp0091, tmp0090, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0091.dontFree) h2_freeReg(tmp0090.regNro); - tmp0092 = riscv_genADD_3(tmp0092, In, tmp0091); - if (!tmp0092.dontFree) h2_freeReg(tmp0091.regNro); - tmp0093 = riscv_genR_3(tmp0093, tmp0092, immValueZero); - tmp0094 = riscv_genMUL_4(tmp0094, tmp0093, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+3]))}, immValueZero); - if (!tmp0094.dontFree) h2_freeReg(tmp0093.regNro); - sum = riscv_genADD_3(sum, sum, tmp0094); - if (!sum.dontFree) h2_freeReg(tmp0094.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0095 = riscv_genADD_3(tmp0095, stride, njp2); - tmp0096 = riscv_genMUL_4(tmp0096, tmp0095, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0096.dontFree) h2_freeReg(tmp0095.regNro); - tmp0097 = riscv_genADD_3(tmp0097, In, tmp0096); - if (!tmp0097.dontFree) h2_freeReg(tmp0096.regNro); - tmp0098 = riscv_genR_3(tmp0098, tmp0097, immValueZero); - tmp0099 = riscv_genMUL_4(tmp0099, tmp0098, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[3*5+4]))}, immValueZero); - if (!tmp0099.dontFree) h2_freeReg(tmp0098.regNro); - sum = riscv_genADD_3(sum, sum, tmp0099); - if (!sum.dontFree) h2_freeReg(tmp0099.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - ni = riscv_genADD_3(ni, line, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - stride = riscv_genMUL_4(stride, ni, imgWidth, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0100 = riscv_genADD_3(tmp0100, stride, njm2); - tmp0101 = riscv_genMUL_4(tmp0101, tmp0100, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0101.dontFree) h2_freeReg(tmp0100.regNro); - tmp0102 = riscv_genADD_3(tmp0102, In, tmp0101); - if (!tmp0102.dontFree) h2_freeReg(tmp0101.regNro); - tmp0103 = riscv_genR_3(tmp0103, tmp0102, immValueZero); - tmp0104 = riscv_genMUL_4(tmp0104, tmp0103, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+0]))}, immValueZero); - if (!tmp0104.dontFree) h2_freeReg(tmp0103.regNro); - sum = riscv_genADD_3(sum, sum, tmp0104); - if (!sum.dontFree) h2_freeReg(tmp0104.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0105 = riscv_genADD_3(tmp0105, stride, njm1); - tmp0106 = riscv_genMUL_4(tmp0106, tmp0105, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0106.dontFree) h2_freeReg(tmp0105.regNro); - tmp0107 = riscv_genADD_3(tmp0107, In, tmp0106); - if (!tmp0107.dontFree) h2_freeReg(tmp0106.regNro); - tmp0108 = riscv_genR_3(tmp0108, tmp0107, immValueZero); - tmp0109 = riscv_genMUL_4(tmp0109, tmp0108, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+1]))}, immValueZero); - if (!tmp0109.dontFree) h2_freeReg(tmp0108.regNro); - sum = riscv_genADD_3(sum, sum, tmp0109); - if (!sum.dontFree) h2_freeReg(tmp0109.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0110 = riscv_genADD_3(tmp0110, stride, column); - tmp0111 = riscv_genMUL_4(tmp0111, tmp0110, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0111.dontFree) h2_freeReg(tmp0110.regNro); - tmp0112 = riscv_genADD_3(tmp0112, In, tmp0111); - if (!tmp0112.dontFree) h2_freeReg(tmp0111.regNro); - tmp0113 = riscv_genR_3(tmp0113, tmp0112, immValueZero); - tmp0114 = riscv_genMUL_4(tmp0114, tmp0113, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+2]))}, immValueZero); - if (!tmp0114.dontFree) h2_freeReg(tmp0113.regNro); - sum = riscv_genADD_3(sum, sum, tmp0114); - if (!sum.dontFree) h2_freeReg(tmp0114.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0115 = riscv_genADD_3(tmp0115, stride, njp1); - tmp0116 = riscv_genMUL_4(tmp0116, tmp0115, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0116.dontFree) h2_freeReg(tmp0115.regNro); - tmp0117 = riscv_genADD_3(tmp0117, In, tmp0116); - if (!tmp0117.dontFree) h2_freeReg(tmp0116.regNro); - tmp0118 = riscv_genR_3(tmp0118, tmp0117, immValueZero); - tmp0119 = riscv_genMUL_4(tmp0119, tmp0118, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+3]))}, immValueZero); - if (!tmp0119.dontFree) h2_freeReg(tmp0118.regNro); - sum = riscv_genADD_3(sum, sum, tmp0119); - if (!sum.dontFree) h2_freeReg(tmp0119.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0120 = riscv_genADD_3(tmp0120, stride, njp2); - tmp0121 = riscv_genMUL_4(tmp0121, tmp0120, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - if (!tmp0121.dontFree) h2_freeReg(tmp0120.regNro); - tmp0122 = riscv_genADD_3(tmp0122, In, tmp0121); - if (!tmp0122.dontFree) h2_freeReg(tmp0121.regNro); - tmp0123 = riscv_genR_3(tmp0123, tmp0122, immValueZero); - tmp0124 = riscv_genMUL_4(tmp0124, tmp0123, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((Filter[4*5+4]))}, immValueZero); - if (!tmp0124.dontFree) h2_freeReg(tmp0123.regNro); - sum = riscv_genADD_3(sum, sum, tmp0124); - if (!sum.dontFree) h2_freeReg(tmp0124.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0125 = riscv_genDIV_4(tmp0125, sum, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((coeff))}, immValueZero); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, tmp0125); - if (!tmp0126.dontFree) h2_freeReg(tmp0125.regNro); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -#if 0 -#endif -} - -// Compute a stencil for 1 point -int kernelStatic(imgStruct_t *In, int l, int c, imgStruct_t *Filter, int coeff) -{ - int line, column, sum = 0; - int offset = (Filter->width)/2; - - for (line = 0; line < Filter->height; line++) - { - for (column = 0; column < Filter->width; column++) - { - int ni = (l + line) - offset; - int nj = (c + column) - offset; - sum += In->pixelsArray[ni*In->width+nj] * Filter->pixelsArray[line*Filter->width+column]; - } - } - return sum / coeff; -} - - -void convolutionStatic(imgStruct_t *In, imgStruct_t *Out, imgStruct_t *Filter, int coeff) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelStatic(In, line, column, Filter, coeff); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -void convolutionH4(imgStruct_t* In, imgStruct_t *Out, imgStruct_t *Filter, pifc kernelHL) -{ - int offset = Filter->width/2; - int result; - for (int line = offset; line < In->height - offset; line++) - { - for (int column = offset; column < In->width - offset; column++) - { - result = kernelHL(In->pixelsArray, line, column, In->width); - Out->pixelsArray[line*Out->width+column] = clamp(result); - } - } -} - -int compareImages(imgStruct_t *staticImg, imgStruct_t *H4Img) -{ - int errors = 0; - for(int line = 0 ; line < staticImg->height ; line++) - { - for(int column = 0 ; column < staticImg->width ; column++) - { - if((staticImg->pixelsArray[line*staticImg->width+column] - H4Img->pixelsArray[line*H4Img->width+column]) != 0) - { - if (0 == errors) - { - printf("Alert : first difference at line %i column %i\n", line, column); - } - errors++; - } - } - } - return errors; -} - -int main(int argc, char *argv[]) -{ - int error, coeff, nXperiment = 20; - imgStruct_t *In, *OutH4, *OutStatic, *Filter; - char *filterImageName, *inputImageName; - if (argc < 5) - { - printf ("./Stencil \n"); - exit(-1); - } - - inputImageName = argv[1]; - filterImageName = argv[4]; - In = readPgmImage(inputImageName); - Filter = readPgmImage(filterImageName); - coeff = imgSum (Filter); -#ifdef VERBOSE - printf ("%s: coeff %d\n", filterImageName, coeff); - printImage (Filter, "Filter"); -#endif - assert (Filter->width == Filter->height); // Only square filters - OutStatic = createImage (In->height, In->width); - OutH4 = createImage (In->height, In->width); -#ifdef VERBOSE - printf ("after init\n"); - printImage(In, "In"); -#endif - ticks_t timeStatic = h2_getticks(); // Static convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionStatic(In, OutStatic, Filter, coeff); - } - timeStatic = h2_getticks() - timeStatic; -#ifdef VERBOSE - printf ("after static\n"); - printImage(OutStatic, "Out"); -#endif - - pifc kernelHL = (pifc)h2_malloc(8192); - ticks_t timeCodeGen = h2_getticks(); - switch (Filter->width) - { - case 1 : kernelHL = genKernel1x1 (kernelHL, Filter->pixelsArray, coeff); break; - case 3 : kernelHL = genKernel3x3 (kernelHL, Filter->pixelsArray, coeff); break; - case 5 : kernelHL = genKernel5x5 (kernelHL, Filter->pixelsArray, coeff); break; - default: printf ("Unknown filter size\n"); exit(-1); - } - timeCodeGen = h2_getticks() - timeCodeGen; - -#ifdef VERBOSE - printf ("after codegen\n"); -#endif - - ticks_t timeH4 = h2_getticks(); // Compilette convolution - for (int i = 0; i < nXperiment; i++) - { - convolutionH4(In, OutH4, Filter, kernelHL); - } - timeH4 = h2_getticks() - timeH4; -#ifdef VERBOSE - printf ("after h2\n"); - printImage(OutH4, "Out H4"); -#endif - error = compareImages(OutH4, OutStatic); - printf("%s;%ix%i;%ix%i;%lld;%lld;%lld;%d;%d\n", - filterImageName, - Filter->width, Filter->height, In->width, In->height, - timeStatic/nXperiment, timeH4/nXperiment, - h2_codeGenTime, h2_insnGenerated, - error); - -#if VERBOSE - writePgmImage(OutStatic, argv[2]); - writePgmImage(OutH4, argv[3]); -#endif - - return (0 == error)?0:-1; -} diff --git a/Demos/VectorMatrix/VectorMatrix.aarch64 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zgh9_0q2zA-T>ei0Bb$(Z6m;Fs7IG>CwX;oGT{TYE^Z3R2b$w7y_~`(Fc+l@Riv1=c zaen~#J zuW7x01vIo~NBMQ#)b;nt|F_^J-%);DUv)$HuTkL;LjST!qjvm9q=`iNbsg3_e_;ug zPT0cosQ%w__;tP34~2hK8Re>cdi}P;uj{&2u2_bR@>j9nMTBIj{`!6HvhdF+p=)5r1@Wg -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -void A64_RET__I_64_1(){ /* ret */ - aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - -#ifdef H2_DEBUG_INSN -printf("%p : A64_RET__I_64_1\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_8_8(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_8_16(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_16_8(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_16_4(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_16_4\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_32_1(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_SUB_RRI_I_32_1(int r0,int r1,int i0){ /* sub */ - aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_32_2(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_32_4(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_64_2(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_64_2\n", h2_asm_pc); -#endif -} -void A64_SUB_RRI_I_64_1(int r0,int r1,int i0){ /* sub */ - aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_SUB_RRR_I_64_1(int r0,int r1,int r2){ /* sub */ - aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_SUB_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_MOV_RRR_I_8_8(int r0,int r1,int r2){ /* mv */ - aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RRR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_MOV_RRR_I_16_8(int r0,int r1,int r2){ /* mv */ - aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_MV_RR_I_32_4(int r0,int r1){ /* mv */ - aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MV_RR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_MOV_RR_I_32_1(int r0,int r1){ /* mv */ - aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_MOVI_RI_I_32_4(int r0,int i0){ /* mv */ - aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOVI_RI_I_32_4\n", h2_asm_pc); -#endif -} -void A64_MOVI_RI_I_32_2(int r0,int i0){ /* mv */ - aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOVI_RI_I_32_2\n", h2_asm_pc); -#endif -} -void A64_DUP_RR_I_32_4(int r0,int r1){ /* mv */ - aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_DUP_RR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_MOV_RI_I_32_1(int r0,int i0){ /* mv */ - aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_MOV_RR_I_32_2(int r0,int r1){ /* mv */ - aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_DUP_RR_I_32_1(int r0,int r1){ /* mv */ - aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_DUP_RR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_DUP_RR_I_32_2(int r0,int r1){ /* mv */ - aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_DUP_RR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_MOV_RR_I_64_1(int r0,int r1){ /* mv */ - aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_MOV_RI_I_64_1(int r0,int i0){ /* mv */ - aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MOV_RI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_DUP_RR_I_64_1(int r0,int r1){ /* mv */ - aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_DUP_RR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_DUP_RR_I_64_2(int r0,int r1){ /* mv */ - aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_DUP_RR_I_64_2\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_8_8(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_8_16(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_16_4(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_16_4\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_16_8(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_32_4(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_32_1(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_32_2(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_MUL_RRR_I_64_1(int r0,int r1,int r2){ /* mul */ - aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_MUL_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_8_8(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_8_16(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_16_8(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_16_4(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_16_4\n", h2_asm_pc); -#endif -} -void A64_ADD_RRI_I_32_1(int r0,int r1,int i0){ /* add */ - aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_32_1(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_32_2(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_32_4(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_64_2(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_64_2\n", h2_asm_pc); -#endif -} -void A64_ADD_RRR_I_64_1(int r0,int r1,int r2){ /* add */ - aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_ADD_RRI_I_64_1(int r0,int r1,int i0){ /* add */ - aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ADD_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_LSR_RRI_I_32_1(int r0,int r1,int i0){ /* sr */ - aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSR_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_LSR_RRR_I_32_1(int r0,int r1,int r2){ /* sr */ - aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSR_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_LSR_RRI_I_64_1(int r0,int r1,int i0){ /* sr */ - aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSR_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_LSR_RRR_I_64_1(int r0,int r1,int r2){ /* sr */ - aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSR_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_8_8(int r0,int r1){ /* w */ - aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_8_16(int r0,int r1){ /* w */ - aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_8_16\n", h2_asm_pc); -#endif -} -void A64_STRB_RRI_I_8_1(int r0,int r1,int i0){ /* w */ - aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STRB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_16_8(int r0,int r1){ /* w */ - aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_16_4(int r0,int r1){ /* w */ - aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_16_4\n", h2_asm_pc); -#endif -} -void A64_STRH_RRI_I_16_1(int r0,int r1,int i0){ /* w */ - aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STRH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void A64_STR_RRR_I_32_1(int r0,int r1,int r2){ /* w */ - aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STR_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_STR_RRI_I_32_1(int r0,int r1,int i0){ /* w */ - aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STR_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_STR_RRI_I_32_2(int r0,int r1,int i0){ /* w */ - aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STR_RRI_I_32_2\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_32_4(int r0,int r1){ /* w */ - aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_STR_RRR_I_64_1(int r0,int r1,int r2){ /* w */ - aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STR_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_ST1_RR_I_64_2(int r0,int r1){ /* w */ - aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_ST1_RR_I_64_2\n", h2_asm_pc); -#endif -} -void A64_STR_RRI_I_64_1(int r0,int r1,int i0){ /* w */ - aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_STR_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_8_16(int r0,int r1){ /* r */ - aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_8_16\n", h2_asm_pc); -#endif -} -void A64_LDRB_RRI_I_8_1(int r0,int r1,int i0){ /* r */ - aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LDRB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_8_8(int r0,int r1){ /* r */ - aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_8_8\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_16_4(int r0,int r1){ /* r */ - aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_16_4\n", h2_asm_pc); -#endif -} -void A64_LDRH_RRI_I_16_1(int r0,int r1,int i0){ /* r */ - aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LDRH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_16_8(int r0,int r1){ /* r */ - aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_16_8\n", h2_asm_pc); -#endif -} -void A64_LDR_RRI_I_32_1(int r0,int r1,int i0){ /* r */ - aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LDR_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_LDP_RRI_I_32_2(int r0,int r1,int i0){ /* r */ - aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LDP_RRI_I_32_2\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_32_2(int r0,int r1){ /* r */ - aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_32_2\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_32_4(int r0,int r1){ /* r */ - aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_32_4\n", h2_asm_pc); -#endif -} -void A64_LDR_RRR_I_64_1(int r0,int r1,int r2){ /* r */ - aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LDR_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void A64_LD1_RR_I_64_2(int r0,int r1){ /* r */ - aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LD1_RR_I_64_2\n", h2_asm_pc); -#endif -} -void A64_LSL_RRI_I_32_1(int r0,int r1,int i0){ /* sl */ - aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSL_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void A64_LSL_RRR_I_32_1(int r0,int r1,int r2){ /* sl */ - aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void A64_LSL_RRI_I_64_1(int r0,int r1,int i0){ /* sl */ - aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSL_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void A64_LSL_RRR_I_64_1(int r0,int r1,int r2){ /* sl */ - aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : A64_LSL_RRR_I_64_1\n", h2_asm_pc); -#endif -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -/* -*- c -*- */ -// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c -#include -#include -#include -#include -#define T 4 -typedef int d_t; -typedef d_t matrix_t [T][T]; -typedef d_t vector_t [T]; -typedef d_t (*pifvv)(vector_t, vector_t); - -pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) -{ - /* Code Generation of 5 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0103, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = aarch64_genMUL_3(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0001 = aarch64_genADD_3(tmp0001, o, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = aarch64_genMUL_3(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0003 = aarch64_genADD_3(tmp0003, i, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = aarch64_genR_3(tmp0004, tmp0003, immValueZero); - tmp0005 = aarch64_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = aarch64_genMUL_3(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0007 = aarch64_genADD_3(tmp0007, i, tmp0006); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - tmp0008 = aarch64_genR_3(tmp0008, tmp0007, immValueZero); - tmp0009 = aarch64_genMUL_3(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}); - if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); - tmp0010 = aarch64_genADD_3(tmp0010, tmp0005, tmp0009); - if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = aarch64_genMUL_3(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0012 = aarch64_genADD_3(tmp0012, i, tmp0011); - if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); - tmp0013 = aarch64_genR_3(tmp0013, tmp0012, immValueZero); - tmp0014 = aarch64_genMUL_3(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}); - if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); - tmp0015 = aarch64_genADD_3(tmp0015, tmp0010, tmp0014); - if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = aarch64_genMUL_3(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0017 = aarch64_genADD_3(tmp0017, i, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = aarch64_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = aarch64_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - tmp0020 = aarch64_genADD_3(tmp0020, tmp0015, tmp0019); - if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - aarch64_genW_3(tmp0001, tmp0020, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0021 = aarch64_genMUL_3(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0022 = aarch64_genADD_3(tmp0022, o, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = aarch64_genMUL_3(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0024 = aarch64_genADD_3(tmp0024, i, tmp0023); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - tmp0025 = aarch64_genR_3(tmp0025, tmp0024, immValueZero); - tmp0026 = aarch64_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = aarch64_genMUL_3(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0028 = aarch64_genADD_3(tmp0028, i, tmp0027); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - tmp0029 = aarch64_genR_3(tmp0029, tmp0028, immValueZero); - tmp0030 = aarch64_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = aarch64_genADD_3(tmp0031, tmp0026, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = aarch64_genMUL_3(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0033 = aarch64_genADD_3(tmp0033, i, tmp0032); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - tmp0034 = aarch64_genR_3(tmp0034, tmp0033, immValueZero); - tmp0035 = aarch64_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = aarch64_genADD_3(tmp0036, tmp0031, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = aarch64_genMUL_3(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0038 = aarch64_genADD_3(tmp0038, i, tmp0037); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - tmp0039 = aarch64_genR_3(tmp0039, tmp0038, immValueZero); - tmp0040 = aarch64_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = aarch64_genADD_3(tmp0041, tmp0036, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - aarch64_genW_3(tmp0022, tmp0041, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0042 = aarch64_genMUL_3(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0043 = aarch64_genADD_3(tmp0043, o, tmp0042); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - tmp0044 = aarch64_genMUL_3(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0045 = aarch64_genADD_3(tmp0045, i, tmp0044); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = aarch64_genR_3(tmp0046, tmp0045, immValueZero); - tmp0047 = aarch64_genMUL_3(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}); - if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); - tmp0048 = aarch64_genMUL_3(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0049 = aarch64_genADD_3(tmp0049, i, tmp0048); - if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); - tmp0050 = aarch64_genR_3(tmp0050, tmp0049, immValueZero); - tmp0051 = aarch64_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = aarch64_genADD_3(tmp0052, tmp0047, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = aarch64_genMUL_3(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0054 = aarch64_genADD_3(tmp0054, i, tmp0053); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - tmp0055 = aarch64_genR_3(tmp0055, tmp0054, immValueZero); - tmp0056 = aarch64_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = aarch64_genADD_3(tmp0057, tmp0052, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = aarch64_genMUL_3(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0059 = aarch64_genADD_3(tmp0059, i, tmp0058); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - tmp0060 = aarch64_genR_3(tmp0060, tmp0059, immValueZero); - tmp0061 = aarch64_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = aarch64_genADD_3(tmp0062, tmp0057, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - aarch64_genW_3(tmp0043, tmp0062, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0063 = aarch64_genMUL_3(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0064 = aarch64_genADD_3(tmp0064, o, tmp0063); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - tmp0065 = aarch64_genMUL_3(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0066 = aarch64_genADD_3(tmp0066, i, tmp0065); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = aarch64_genR_3(tmp0067, tmp0066, immValueZero); - tmp0068 = aarch64_genMUL_3(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}); - if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); - tmp0069 = aarch64_genMUL_3(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0070 = aarch64_genADD_3(tmp0070, i, tmp0069); - if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); - tmp0071 = aarch64_genR_3(tmp0071, tmp0070, immValueZero); - tmp0072 = aarch64_genMUL_3(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = aarch64_genADD_3(tmp0073, tmp0068, tmp0072); - if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); - if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); - tmp0074 = aarch64_genMUL_3(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0075 = aarch64_genADD_3(tmp0075, i, tmp0074); - if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); - tmp0076 = aarch64_genR_3(tmp0076, tmp0075, immValueZero); - tmp0077 = aarch64_genMUL_3(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = aarch64_genADD_3(tmp0078, tmp0073, tmp0077); - if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); - if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); - tmp0079 = aarch64_genMUL_3(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0080 = aarch64_genADD_3(tmp0080, i, tmp0079); - if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); - tmp0081 = aarch64_genR_3(tmp0081, tmp0080, immValueZero); - tmp0082 = aarch64_genMUL_3(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = aarch64_genADD_3(tmp0083, tmp0078, tmp0082); - if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); - if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); - aarch64_genW_3(tmp0064, tmp0083, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) -{ - o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; - o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; - o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; - o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; - return o[3]; -} - -#if 0 // What the binary code should be with a translation matrix -d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) -{ - - o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; - o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; - o[2] = m[2][2] * i[2] + m[3][2] * i[3]; - o[3] = + i[3]; - return o[3]; -} -#endif -d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) -{ - for (int column = 0; column < T; column++) - { - o[column] = 0; - for (int line = 0; line < T; line++) - { - o[column] += i[line] * m[line][column]; - - } - } - return o[3]; -} - - -int VectorMatrixProductCount(matrix_t mat) -{ - int op = 0; - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - switch (mat[line][column]) - { - case 0 : op += 0; break; - case 1 : op += 1; break; - default: op += 2; break; - } - } - } - return op; -} - - -void printMatrix (matrix_t m, char msg[]) -{ - printf ("%s:\n", msg); - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - printf ("%4d ", m[line][column]); - } - printf ("\n"); - } - printf ("\n"); -} - -void printVector (vector_t v, char msg[]) -{ - for (int i = 0; i < T; i++) - printf ("%4d ", v[i]); - printf ("%s\n", msg); -} - -bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) -{ - int has_differences = false; - for (int line = 0; line < nVector; line++) - for (int i = 0; i < T; i++) - { - if (ref[line][i] != other[line][i]) - has_differences = true; - if (doPrint) - printf("%4d ", other[line][i]); - } - /* printf("%s : ", msg); */ - /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ - return has_differences; -} - -int main (int argc, char *argv[]) -{ - matrix_t m; - char *matrixName; - // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; - vector_t *out, *cout, *in; - uint64_t timeGeneral, timeCompilette; - pifvv vmProduct; - int tmp, doPrint, nXperiment; - unsigned long acc; - bool resultValid; - - if (argc != 19) - { - printf ("Not enough arguments %d\n", argc); - printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); - exit (-1); - } - doPrint = 0; - acc = 0; - nXperiment = atoi (argv[1]); - matrixName = argv[2]; - for (int line = 0; line < 4; line++) - for (int column = 0; column < 4; column++) - { - m[line][column] = atoi (argv[3 + line*4+column]); - } -#ifdef VERBOSE - printMatrix(m, matrixName); -#endif - - in = calloc(nXperiment, sizeof (vector_t)); - out = calloc(nXperiment, sizeof (vector_t)); - cout = calloc(nXperiment, sizeof (vector_t)); - - for (int line = 0; line < nXperiment; line++) - for (int column = 0; column < 4; column++) - in[line][column] = random () % 1000; - - tmp = VectorMatrixProductCount (m); - printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); - -// Repeat one instruction and count ticks -#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} - -#ifdef VERBOSE - printVector (in[0], "Input vector #0"); -#endif - - acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ - DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) - -#ifdef VERBOSE - printVector (out[0], "Output vector #0 (general)"); -#endif - -#if 0 // Possible test with a source level unrolled version - uint64_t timeUnrolled; - vector_t uout0, uout1; - acc += VectorMatrixProductUnrolled (uout0, in0, m); - DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); - vectorCompare(out1, uout1, "Unrolled out0", doPrint); -#endif - - vmProduct = (pifvv) h2_malloc(1024); - vmProduct = genVectorMatrixProduct (vmProduct, m); - acc += vmProduct (cout[0], in[0]); - DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); - -#ifdef VERBOSE - printVector (cout[0], "Output vector #0 (compilette)"); -#endif - - resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); - - printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", - matrixName, nXperiment, - timeGeneral, timeCompilette, - h2_codeGenTime, h2_insnGenerated, - resultValid?"true":"false"); - return resultValid; -} diff --git a/Demos/VectorMatrix/VectorMatrix.power b/Demos/VectorMatrix/VectorMatrix.power deleted file mode 100755 index 3cf332b703c4aebb261c30c4221ad8674f510874..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 80624 zcmeFa4R}=5wLiR1GRaIn86av@#0i2;YzP6VoqPZ@A!_)LrW%oYsmzcBlNv)zf*oW+ zW@6d~OT9_JHYjRn)#AO>m)o1(i?_5lQT`TN>P;)ssECQinh>r{TYEbJ^3!@R1>^*1e?S5+sZ$Ug8JShLv^W;zAjthi)E)ZUEf$%jK2)A7zJo^IS)(eE&FA(m! zKzPjs!qYDhUVNT#ef>{o(V5r#T2amZHU)ZMRg?hLPr9keVPR!Mz07&WbKT?Kc-CoW z%!j(aJ8wVhIo-{aGlyB)nLg$|vzDdhMKf34DC;?MfDN4PXZ|xoY|ohh8#uG+oTf*N zy>-%a^;U0}+2i&6Ccn}1`qvvxtUoV~H4I7G%S2pNU6PZ=mTWdL@6LX;$zfu7IX2`w zoyDbFSx%mfdhQiE^wZ!zv=a{Hpd~G zZ^>S^=d`NcllSZsyGt!!xO>Yh=G|Kok>4Hf@4ok}+K~5Of8Sl2^82qhQafO*z~y;+ z6X*TSPqebB>N@bdZgYEobi;$^D!uiK;~R>LGa81XGp;F4&1f*OFFkgY^SdR_(Up>0)mC&5y96bLy-`o3AeSW~XHw?ucq~Y+%=W&#CM4J^y-WtH)MqpDOZku|0Or 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XKfZptzwnlb`R^@Q%BvoO*9`szd0{3w diff --git a/Demos/VectorMatrix/VectorMatrix.power.c b/Demos/VectorMatrix/VectorMatrix.power.c deleted file mode 100644 index ef2ed96..0000000 --- a/Demos/VectorMatrix/VectorMatrix.power.c +++ /dev/null @@ -1,1457 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -void P1_BLR__I_32_1(){ /* ret */ - power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - -#ifdef H2_DEBUG_INSN -printf("%p : P1_BLR__I_32_1\n", h2_asm_pc); -#endif -} -void P1_SUBI_RRI_I_32_1(int r0,int r1,int i0){ /* sub */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_SUBI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void PPC_SUB_RRR_I_32_1(int r0,int r2,int r1){ /* sub */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : PPC_SUB_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_LI_RI_I_32_1(int r0,int i0){ /* mv */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LI_RI_I_32_1\n", h2_asm_pc); -#endif -} -void P1_MV_RR_I_32_1(int r0,int r1){ /* mv */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_MV_RR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_LI_RI_I_64_1(int r0,int i0){ /* mv */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LI_RI_I_64_1\n", h2_asm_pc); -#endif -} -void V2_03_VSRB_RRR_I_8_16(int r0,int r1,int r2){ /* sr */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSRB_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void V2_03_VSRH_RRR_I_16_8(int r0,int r1,int r2){ /* sr */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSRH_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void V2_03_VSRW_RRR_I_32_4(int r0,int r1,int r2){ /* sr */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSRW_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void V2_07_VSRD_RRR_I_64_2(int r0,int r1,int r2){ /* sr */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_07_VSRD_RRR_I_64_2\n", h2_asm_pc); -#endif -} -void V2_03_VSR_RRR_I_128_1(int r0,int r1,int r2){ /* sr */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSR_RRR_I_128_1\n", h2_asm_pc); -#endif -} -void P1_MULLW_RRR_I_32_1(int r0,int r1,int r2){ /* mul */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_MULLW_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_MULLI_RRI_I_64_1(int r0,int r1,int i0){ /* mul */ - power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_MULLI_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void V2_03_VADDSBS_RRR_I_8_16(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDSBS_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void V2_03_VADDUBS_RRR_I_8_16(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDUBS_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void V2_03_VADDSHS_RRR_I_16_8(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDSHS_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void V2_03_VADDUHS_RRR_I_16_8(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDUHS_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void V2_03_VADDUWS_RRR_I_32_4(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDUWS_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void P1_ADDI_RRI_I_32_1(int r0,int r1,int i0){ /* add */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_ADDI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void V2_03_VADDSWS_RRR_I_32_4(int r0,int r1,int r2){ /* add */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VADDSWS_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void P1_ADD_RRR_I_32_1(int r0,int r1,int r2){ /* add */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_ADD_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_ADD_RRR_I_64_1(int r0,int r1,int r2){ /* add */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_ADD_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void P1_ADDI_RRI_I_64_1(int r0,int r1,int i0){ /* add */ - power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_ADDI_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void P1_STB_RRI_I_8_1(int r1,int r0,int i0){ /* w */ - power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_STB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void P1_STBX_RRR_I_8_1(int r1,int r0,int r2){ /* w */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_STBX_RRR_I_8_1\n", h2_asm_pc); -#endif -} -void P1_STH_RRI_I_16_1(int r1,int r0,int i0){ /* w */ - power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_STH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void P1_STW_RRI_I_32_1(int r1,int r0,int i0){ /* w */ - power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_STW_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void P1_STWX_RRR_I_32_1(int r0,int r1,int r2){ /* w */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_STWX_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void PPC_STD_RRI_I_64_1(int r1,int r0,int i0){ /* w */ - power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : PPC_STD_RRI_I_64_1\n", h2_asm_pc); -#endif -} -void P1_LBZ_RRI_I_8_1(int r0,int r1,int i0){ /* r */ - power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LBZ_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void P1_LBZX_RRR_I_8_1(int r0,int r1,int r2){ /* r */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LBZX_RRR_I_8_1\n", h2_asm_pc); -#endif -} -void P1_LHZ_RRI_I_16_1(int r0,int r1,int i0){ /* r */ - power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LHZ_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void P1_LWZ_RRI_I_32_1(int r0,int r1,int i0){ /* r */ - power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LWZ_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void P1_LWZU_RRI_I_32_1(int r0,int r1,int i0){ /* r */ - power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LWZU_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void P1_LWZUX_RRR_I_32_1(int r0,int r1,int r2){ /* r */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LWZUX_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_LWZX_RRR_I_32_1(int r0,int r1,int r2){ /* r */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_LWZX_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void V2_03_VSLB_RRR_I_8_16(int r0,int r1,int r2){ /* sl */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSLB_RRR_I_8_16\n", h2_asm_pc); -#endif -} -void V2_03_VSLH_RRR_I_16_8(int r0,int r1,int r2){ /* sl */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSLH_RRR_I_16_8\n", h2_asm_pc); -#endif -} -void P1_SLW_RRR_I_32_1(int r1,int r0,int r2){ /* sl */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_SLW_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void P1_SLW__RRR_I_32_1(int r1,int r0,int r2){ /* sl */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : P1_SLW__RRR_I_32_1\n", h2_asm_pc); -#endif -} -void V2_03_VSLW_RRR_I_32_4(int r0,int r1,int r2){ /* sl */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSLW_RRR_I_32_4\n", h2_asm_pc); -#endif -} -void PPC_SLD_RRR_I_64_1(int r1,int r0,int r2){ /* sl */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : PPC_SLD_RRR_I_64_1\n", h2_asm_pc); -#endif -} -void PPC_SLD__RRR_I_64_1(int r1,int r0,int r2){ /* sl */ - power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : PPC_SLD__RRR_I_64_1\n", h2_asm_pc); -#endif -} -void V2_07_VSLD_RRR_I_64_2(int r0,int r1,int r2){ /* sl */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_07_VSLD_RRR_I_64_2\n", h2_asm_pc); -#endif -} -void V2_03_VSL_RRR_I_128_1(int r0,int r1,int r2){ /* sl */ - power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : V2_03_VSL_RRR_I_128_1\n", h2_asm_pc); -#endif -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} - -/* End Header autogenerated part */ -/* -*- c -*- */ -// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c -#include -#include -#include -#include -#define T 4 -typedef int d_t; -typedef d_t matrix_t [T][T]; -typedef d_t vector_t [T]; -typedef d_t (*pifvv)(vector_t, vector_t); - -pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) -{ - /* Code Generation of 5 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 4, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 64, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x381F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp0000 = power_genMUL_3(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0001 = power_genADD_3(tmp0001, o, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = power_genMUL_3(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0003 = power_genADD_3(tmp0003, i, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = power_genR_3(tmp0004, tmp0003, immValueZero); - tmp0005 = power_genMUL_3(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = power_genMUL_3(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0007 = power_genADD_3(tmp0007, i, tmp0006); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - tmp0008 = power_genR_3(tmp0008, tmp0007, immValueZero); - tmp0009 = power_genMUL_3(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}); - if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); - tmp0010 = power_genADD_3(tmp0010, tmp0005, tmp0009); - if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = power_genMUL_3(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0012 = power_genADD_3(tmp0012, i, tmp0011); - if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); - tmp0013 = power_genR_3(tmp0013, tmp0012, immValueZero); - tmp0014 = power_genMUL_3(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}); - if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); - tmp0015 = power_genADD_3(tmp0015, tmp0010, tmp0014); - if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = power_genMUL_3(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0017 = power_genADD_3(tmp0017, i, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = power_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = power_genMUL_3(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - tmp0020 = power_genADD_3(tmp0020, tmp0015, tmp0019); - if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - power_genW_3(tmp0001, tmp0020, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0021 = power_genMUL_3(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0022 = power_genADD_3(tmp0022, o, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = power_genMUL_3(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0024 = power_genADD_3(tmp0024, i, tmp0023); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - tmp0025 = power_genR_3(tmp0025, tmp0024, immValueZero); - tmp0026 = power_genMUL_3(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = power_genMUL_3(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0028 = power_genADD_3(tmp0028, i, tmp0027); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - tmp0029 = power_genR_3(tmp0029, tmp0028, immValueZero); - tmp0030 = power_genMUL_3(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = power_genADD_3(tmp0031, tmp0026, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = power_genMUL_3(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0033 = power_genADD_3(tmp0033, i, tmp0032); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - tmp0034 = power_genR_3(tmp0034, tmp0033, immValueZero); - tmp0035 = power_genMUL_3(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = power_genADD_3(tmp0036, tmp0031, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = power_genMUL_3(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0038 = power_genADD_3(tmp0038, i, tmp0037); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - tmp0039 = power_genR_3(tmp0039, tmp0038, immValueZero); - tmp0040 = power_genMUL_3(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = power_genADD_3(tmp0041, tmp0036, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - power_genW_3(tmp0022, tmp0041, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0042 = power_genMUL_3(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0043 = power_genADD_3(tmp0043, o, tmp0042); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - tmp0044 = power_genMUL_3(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0045 = power_genADD_3(tmp0045, i, tmp0044); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = power_genR_3(tmp0046, tmp0045, immValueZero); - tmp0047 = power_genMUL_3(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}); - if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); - tmp0048 = power_genMUL_3(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0049 = power_genADD_3(tmp0049, i, tmp0048); - if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); - tmp0050 = power_genR_3(tmp0050, tmp0049, immValueZero); - tmp0051 = power_genMUL_3(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = power_genADD_3(tmp0052, tmp0047, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = power_genMUL_3(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0054 = power_genADD_3(tmp0054, i, tmp0053); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - tmp0055 = power_genR_3(tmp0055, tmp0054, immValueZero); - tmp0056 = power_genMUL_3(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = power_genADD_3(tmp0057, tmp0052, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = power_genMUL_3(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0059 = power_genADD_3(tmp0059, i, tmp0058); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - tmp0060 = power_genR_3(tmp0060, tmp0059, immValueZero); - tmp0061 = power_genMUL_3(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = power_genADD_3(tmp0062, tmp0057, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - power_genW_3(tmp0043, tmp0062, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0063 = power_genMUL_3(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0064 = power_genADD_3(tmp0064, o, tmp0063); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - tmp0065 = power_genMUL_3(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0066 = power_genADD_3(tmp0066, i, tmp0065); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = power_genR_3(tmp0067, tmp0066, immValueZero); - tmp0068 = power_genMUL_3(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}); - if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); - tmp0069 = power_genMUL_3(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0070 = power_genADD_3(tmp0070, i, tmp0069); - if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); - tmp0071 = power_genR_3(tmp0071, tmp0070, immValueZero); - tmp0072 = power_genMUL_3(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = power_genADD_3(tmp0073, tmp0068, tmp0072); - if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); - if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); - tmp0074 = power_genMUL_3(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0075 = power_genADD_3(tmp0075, i, tmp0074); - if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); - tmp0076 = power_genR_3(tmp0076, tmp0075, immValueZero); - tmp0077 = power_genMUL_3(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = power_genADD_3(tmp0078, tmp0073, tmp0077); - if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); - if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); - tmp0079 = power_genMUL_3(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 64, 0, (int)((1 * 32) / 8)}); - tmp0080 = power_genADD_3(tmp0080, i, tmp0079); - if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); - tmp0081 = power_genR_3(tmp0081, tmp0080, immValueZero); - tmp0082 = power_genMUL_3(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = power_genADD_3(tmp0083, tmp0078, tmp0082); - if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); - if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); - power_genW_3(tmp0064, tmp0083, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) -{ - o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; - o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; - o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; - o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; - return o[3]; -} - -#if 0 // What the binary code should be with a translation matrix -d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) -{ - - o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; - o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; - o[2] = m[2][2] * i[2] + m[3][2] * i[3]; - o[3] = + i[3]; - return o[3]; -} -#endif -d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) -{ - for (int column = 0; column < T; column++) - { - o[column] = 0; - for (int line = 0; line < T; line++) - { - o[column] += i[line] * m[line][column]; - - } - } - return o[3]; -} - - -int VectorMatrixProductCount(matrix_t mat) -{ - int op = 0; - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - switch (mat[line][column]) - { - case 0 : op += 0; break; - case 1 : op += 1; break; - default: op += 2; break; - } - } - } - return op; -} - - -void printMatrix (matrix_t m, char msg[]) -{ - printf ("%s:\n", msg); - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - printf ("%4d ", m[line][column]); - } - printf ("\n"); - } - printf ("\n"); -} - -void printVector (vector_t v, char msg[]) -{ - for (int i = 0; i < T; i++) - printf ("%4d ", v[i]); - printf ("%s\n", msg); -} - -bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) -{ - int has_differences = false; - for (int line = 0; line < nVector; line++) - for (int i = 0; i < T; i++) - { - if (ref[line][i] != other[line][i]) - has_differences = true; - if (doPrint) - printf("%4d ", other[line][i]); - } - /* printf("%s : ", msg); */ - /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ - return has_differences; -} - -int main (int argc, char *argv[]) -{ - matrix_t m; - char *matrixName; - // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; - vector_t *out, *cout, *in; - uint64_t timeGeneral, timeCompilette; - pifvv vmProduct; - int tmp, doPrint, nXperiment; - unsigned long acc; - bool resultValid; - - if (argc != 19) - { - printf ("Not enough arguments %d\n", argc); - printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); - exit (-1); - } - doPrint = 0; - acc = 0; - nXperiment = atoi (argv[1]); - matrixName = argv[2]; - for (int line = 0; line < 4; line++) - for (int column = 0; column < 4; column++) - { - m[line][column] = atoi (argv[3 + line*4+column]); - } -#ifdef VERBOSE - printMatrix(m, matrixName); -#endif - - in = calloc(nXperiment, sizeof (vector_t)); - out = calloc(nXperiment, sizeof (vector_t)); - cout = calloc(nXperiment, sizeof (vector_t)); - - for (int line = 0; line < nXperiment; line++) - for (int column = 0; column < 4; column++) - in[line][column] = random () % 1000; - - tmp = VectorMatrixProductCount (m); - printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); - -// Repeat one instruction and count ticks -#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} - -#ifdef VERBOSE - printVector (in[0], "Input vector #0"); -#endif - - acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ - DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) - -#ifdef VERBOSE - printVector (out[0], "Output vector #0 (general)"); -#endif - -#if 0 // Possible test with a source level unrolled version - uint64_t timeUnrolled; - vector_t uout0, uout1; - acc += VectorMatrixProductUnrolled (uout0, in0, m); - DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); - vectorCompare(out1, uout1, "Unrolled out0", doPrint); -#endif - - vmProduct = (pifvv) h2_malloc(1024); - vmProduct = genVectorMatrixProduct (vmProduct, m); - acc += vmProduct (cout[0], in[0]); - DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); - -#ifdef VERBOSE - printVector (cout[0], "Output vector #0 (compilette)"); -#endif - - resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); - - printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", - matrixName, nXperiment, - timeGeneral, timeCompilette, - h2_codeGenTime, h2_insnGenerated, - resultValid?"true":"false"); - return resultValid; -} diff --git a/Demos/VectorMatrix/VectorMatrix.riscv b/Demos/VectorMatrix/VectorMatrix.riscv deleted file mode 100755 index 8eea702214e5f50c8ce2d86440163b9568f12d15..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 62544 zcmdSC3tSXOwm;rO%`l4i*o=v6es03jFpkI$cQL_T?_FbXWE5Y!u8MCrqM{}~gD55_ z(lazZ5aKBKNR%J~K>|8NNlbj<$RH{rF=$xh3nRuvQ4^Dxjr#wd?im>n6gOt?{p)9{ zyQ`|Z>zq3EJ*Up8Y8Lk$7^+YxIOjh%?puzoR<}}cFHmM3$Ek35f%E1(I34H1{ho7| zt|^b|D7fCZfqqKl(~sd7h3hChmwrCDrXQ6do62X8ufU1p-`^caXF1i8|IwL(^E|*w zKWYcpL4Jnv7@l`lA^rNHS|WbbE-H7U1Ijy~oPO7FO+PAkws9@$uSMJF=Z$>&Im`a~ zWz?jpyEty@E`{`yX{j&&8_H4rfq(RTyq+71a@Y3#j6C`|=?i>q+Qh)uCjH^HX*1_7 z_`}?3uSZ085BkHj*JgJQnxubymi~{9y7VkGlQRw;j#TakdItR?9=FG@HGcG75B%t# zCw^3?6z`apDf_V7t55e@l=|lXy#MF6UW+`$yWf~PUOi*!tRMWB?{7YH z>6UiZMX$n?|NfL7>-vx0`wta8nd6?qZxVj#F4t7D&E@(zTzk7*kHhs}U9NwN>)9^X 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zbC2b*WIW0rg(UjYJgZhWG&TBbRa_rbp$c9l7&irKZ!i+e7A_ENE2=6R)pozy*4C&t zs*BVLi`3NAXcBQ@P%&<-vS@pgT4jnfuTXU*I=`y=+uO~4IF7-!{563H>Az~p+EXPG zNo=eU7{A6Q{IjW`~Fjcj^uBM|#^#>XnTiE037}RWCQxjU!hUSfJNgFKJol6nXdz-e}Y*5n@vj=b+QehQ#w_^vcv7=LVGe;F&0cyOwT*Ct4#n#_G}Tvv&dXrQ&K& zFc!vzNAI5v!nlK}J|@P`M64>>#ySTkN;q3&uPKQ-;=T5k8RpZEku&GG`5TjE7nw@v zNq;_G@B#F#sv2Fb|Byz-FHb@}nq9wY&G|$euB0XBX1f}{J<d zuP2!55x(%67=#U&P8ubvwPXsvNE?HwD8uPA=u1R#oK9=~NU=!qI>@K>n9C<`Rz@-5 zOC+`IQYw7*e0DX~tHw({OZ^jOyd_%oqcJ17Wl$i zXJ0p#>R=2bZ=w3#r&ZM1nZ(35G2Xsed32DKB^mC(&EsDgW`d8q5o{L(&*f<#b8NE4 zPDS8faKXK@$;b2D5DL6DK5lCmK97ixcwHaQ@sEP9)uaLF`#AFQ8|;tp-9GE(`QD98 z7Me7p}>1>`~CRv<6KMTmS`px29g z0XGzI?`PFZI^#-2zC~c3_Xnlmn~%J`UZA2Ikv8}d`JQ1Vkh_qlKAzrL#xrmfkv33X zaQ_1aw!;c+1LM_*79aOaEz zz9PikR-uiL=T941y!R^J$=C>1)@Sm~H|?oHNAZ=470AbU&N#kB=qTQ8Si#~Wq%T`x v^J_wQ(MT@{7a+2q3lVv -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -void RV32I_RET__I_32_1(){ /* RET */ - riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_RET__I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SUB_RRR_I_32_1(int r3,int r1,int r2){ /* SUB */ - riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SUB_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_MV_RR_I_32_1(int r0,int r1){ /* MV */ - riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_MV_RR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_MV_RI_I_32_1(int r3,int i1){ /* MV */ - riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_MV_RI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SLLI_RRI_I_32_1(int r3,int r1,int i0){ /* SL */ - riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SLLI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SLL_RRR_I_32_1(int r3,int r1,int r2){ /* SL */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SLL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32M_MUL_RRR_I_32_1(int r3,int r1,int r2){ /* MUL */ - riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32M_MUL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_ADDI_RRI_I_32_1(int r1,int r0,int i0){ /* ADD */ - riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_ADDI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_ADD_RRR_I_32_1(int r3,int r1,int r2){ /* ADD */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_ADD_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_LB_RRI_I_8_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void RV32I_LH_RRI_I_16_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void RV32I_LW_RRI_I_32_1(int r3,int r1,int i1){ /* R */ - riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_LW_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SRLI_RRI_I_32_1(int r3,int r1,int i0){ /* SR */ - riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SRLI_RRI_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SRL_RRR_I_32_1(int r3,int r1,int r2){ /* SR */ - riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SRL_RRR_I_32_1\n", h2_asm_pc); -#endif -} -void RV32I_SB_RRI_I_8_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SB_RRI_I_8_1\n", h2_asm_pc); -#endif -} -void RV32I_SH_RRI_I_16_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SH_RRI_I_16_1\n", h2_asm_pc); -#endif -} -void RV32I_SW_RRI_I_32_1(int r1,int r2,int i1){ /* W */ - riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); -#ifdef H2_DEBUG_INSN -printf("%p : RV32I_SW_RRI_I_32_1\n", h2_asm_pc); -#endif -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -/* -*- c -*- */ -// https://gitlab.freedesktop.org/mesa/mesa/-/blob/main/src/mesa/math/m_matrix.c -#include -#include -#include -#include -#define T 4 -typedef int d_t; -typedef d_t matrix_t [T][T]; -typedef d_t vector_t [T]; -typedef d_t (*pifvv)(vector_t, vector_t); - -pifvv genVectorMatrixProduct(pifvv ptr, matrix_t m) -{ - /* Code Generation of 5 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t o = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0007 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0008 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0009 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0010 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0011 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0012 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0013 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0014 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0015 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0016 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0017 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0018 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0019 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0020 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0021 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0022 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0023 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0024 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0025 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0026 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0027 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0028 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0029 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0030 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0031 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0032 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0033 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0034 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0035 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0036 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0037 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0038 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0039 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0040 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0041 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0042 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0043 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0044 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0045 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0046 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0047 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0048 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0049 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0050 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0051 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0052 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0053 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0054 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0055 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0056 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0057 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0058 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0059 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0060 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0061 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0062 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0063 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0064 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0065 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0066 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0067 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0068 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0069 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0070 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0071 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0072 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0073 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0074 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0075 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0076 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0077 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0078 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0079 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0080 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0081 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0082 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0083 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xF1F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp0000 = riscv_genMUL_4(tmp0000, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0001 = riscv_genADD_3(tmp0001, o, tmp0000); - if (!tmp0001.dontFree) h2_freeReg(tmp0000.regNro); - tmp0002 = riscv_genMUL_4(tmp0002, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0003 = riscv_genADD_3(tmp0003, i, tmp0002); - if (!tmp0003.dontFree) h2_freeReg(tmp0002.regNro); - tmp0004 = riscv_genR_3(tmp0004, tmp0003, immValueZero); - tmp0005 = riscv_genMUL_4(tmp0005, tmp0004, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][0]))}, immValueZero); - if (!tmp0005.dontFree) h2_freeReg(tmp0004.regNro); - tmp0006 = riscv_genMUL_4(tmp0006, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0007 = riscv_genADD_3(tmp0007, i, tmp0006); - if (!tmp0007.dontFree) h2_freeReg(tmp0006.regNro); - tmp0008 = riscv_genR_3(tmp0008, tmp0007, immValueZero); - tmp0009 = riscv_genMUL_4(tmp0009, tmp0008, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][0]))}, immValueZero); - if (!tmp0009.dontFree) h2_freeReg(tmp0008.regNro); - tmp0010 = riscv_genADD_3(tmp0010, tmp0005, tmp0009); - if (!tmp0010.dontFree) h2_freeReg(tmp0005.regNro); - if (!tmp0010.dontFree) h2_freeReg(tmp0009.regNro); - tmp0011 = riscv_genMUL_4(tmp0011, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0012 = riscv_genADD_3(tmp0012, i, tmp0011); - if (!tmp0012.dontFree) h2_freeReg(tmp0011.regNro); - tmp0013 = riscv_genR_3(tmp0013, tmp0012, immValueZero); - tmp0014 = riscv_genMUL_4(tmp0014, tmp0013, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][0]))}, immValueZero); - if (!tmp0014.dontFree) h2_freeReg(tmp0013.regNro); - tmp0015 = riscv_genADD_3(tmp0015, tmp0010, tmp0014); - if (!tmp0015.dontFree) h2_freeReg(tmp0010.regNro); - if (!tmp0015.dontFree) h2_freeReg(tmp0014.regNro); - tmp0016 = riscv_genMUL_4(tmp0016, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0017 = riscv_genADD_3(tmp0017, i, tmp0016); - if (!tmp0017.dontFree) h2_freeReg(tmp0016.regNro); - tmp0018 = riscv_genR_3(tmp0018, tmp0017, immValueZero); - tmp0019 = riscv_genMUL_4(tmp0019, tmp0018, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][0]))}, immValueZero); - if (!tmp0019.dontFree) h2_freeReg(tmp0018.regNro); - tmp0020 = riscv_genADD_3(tmp0020, tmp0015, tmp0019); - if (!tmp0020.dontFree) h2_freeReg(tmp0015.regNro); - if (!tmp0020.dontFree) h2_freeReg(tmp0019.regNro); - riscv_genW_3(tmp0001, tmp0020, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0021 = riscv_genMUL_4(tmp0021, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0022 = riscv_genADD_3(tmp0022, o, tmp0021); - if (!tmp0022.dontFree) h2_freeReg(tmp0021.regNro); - tmp0023 = riscv_genMUL_4(tmp0023, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0024 = riscv_genADD_3(tmp0024, i, tmp0023); - if (!tmp0024.dontFree) h2_freeReg(tmp0023.regNro); - tmp0025 = riscv_genR_3(tmp0025, tmp0024, immValueZero); - tmp0026 = riscv_genMUL_4(tmp0026, tmp0025, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][1]))}, immValueZero); - if (!tmp0026.dontFree) h2_freeReg(tmp0025.regNro); - tmp0027 = riscv_genMUL_4(tmp0027, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0028 = riscv_genADD_3(tmp0028, i, tmp0027); - if (!tmp0028.dontFree) h2_freeReg(tmp0027.regNro); - tmp0029 = riscv_genR_3(tmp0029, tmp0028, immValueZero); - tmp0030 = riscv_genMUL_4(tmp0030, tmp0029, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][1]))}, immValueZero); - if (!tmp0030.dontFree) h2_freeReg(tmp0029.regNro); - tmp0031 = riscv_genADD_3(tmp0031, tmp0026, tmp0030); - if (!tmp0031.dontFree) h2_freeReg(tmp0026.regNro); - if (!tmp0031.dontFree) h2_freeReg(tmp0030.regNro); - tmp0032 = riscv_genMUL_4(tmp0032, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0033 = riscv_genADD_3(tmp0033, i, tmp0032); - if (!tmp0033.dontFree) h2_freeReg(tmp0032.regNro); - tmp0034 = riscv_genR_3(tmp0034, tmp0033, immValueZero); - tmp0035 = riscv_genMUL_4(tmp0035, tmp0034, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][1]))}, immValueZero); - if (!tmp0035.dontFree) h2_freeReg(tmp0034.regNro); - tmp0036 = riscv_genADD_3(tmp0036, tmp0031, tmp0035); - if (!tmp0036.dontFree) h2_freeReg(tmp0031.regNro); - if (!tmp0036.dontFree) h2_freeReg(tmp0035.regNro); - tmp0037 = riscv_genMUL_4(tmp0037, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0038 = riscv_genADD_3(tmp0038, i, tmp0037); - if (!tmp0038.dontFree) h2_freeReg(tmp0037.regNro); - tmp0039 = riscv_genR_3(tmp0039, tmp0038, immValueZero); - tmp0040 = riscv_genMUL_4(tmp0040, tmp0039, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][1]))}, immValueZero); - if (!tmp0040.dontFree) h2_freeReg(tmp0039.regNro); - tmp0041 = riscv_genADD_3(tmp0041, tmp0036, tmp0040); - if (!tmp0041.dontFree) h2_freeReg(tmp0036.regNro); - if (!tmp0041.dontFree) h2_freeReg(tmp0040.regNro); - riscv_genW_3(tmp0022, tmp0041, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0042 = riscv_genMUL_4(tmp0042, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0043 = riscv_genADD_3(tmp0043, o, tmp0042); - if (!tmp0043.dontFree) h2_freeReg(tmp0042.regNro); - tmp0044 = riscv_genMUL_4(tmp0044, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0045 = riscv_genADD_3(tmp0045, i, tmp0044); - if (!tmp0045.dontFree) h2_freeReg(tmp0044.regNro); - tmp0046 = riscv_genR_3(tmp0046, tmp0045, immValueZero); - tmp0047 = riscv_genMUL_4(tmp0047, tmp0046, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][2]))}, immValueZero); - if (!tmp0047.dontFree) h2_freeReg(tmp0046.regNro); - tmp0048 = riscv_genMUL_4(tmp0048, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0049 = riscv_genADD_3(tmp0049, i, tmp0048); - if (!tmp0049.dontFree) h2_freeReg(tmp0048.regNro); - tmp0050 = riscv_genR_3(tmp0050, tmp0049, immValueZero); - tmp0051 = riscv_genMUL_4(tmp0051, tmp0050, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][2]))}, immValueZero); - if (!tmp0051.dontFree) h2_freeReg(tmp0050.regNro); - tmp0052 = riscv_genADD_3(tmp0052, tmp0047, tmp0051); - if (!tmp0052.dontFree) h2_freeReg(tmp0047.regNro); - if (!tmp0052.dontFree) h2_freeReg(tmp0051.regNro); - tmp0053 = riscv_genMUL_4(tmp0053, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0054 = riscv_genADD_3(tmp0054, i, tmp0053); - if (!tmp0054.dontFree) h2_freeReg(tmp0053.regNro); - tmp0055 = riscv_genR_3(tmp0055, tmp0054, immValueZero); - tmp0056 = riscv_genMUL_4(tmp0056, tmp0055, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][2]))}, immValueZero); - if (!tmp0056.dontFree) h2_freeReg(tmp0055.regNro); - tmp0057 = riscv_genADD_3(tmp0057, tmp0052, tmp0056); - if (!tmp0057.dontFree) h2_freeReg(tmp0052.regNro); - if (!tmp0057.dontFree) h2_freeReg(tmp0056.regNro); - tmp0058 = riscv_genMUL_4(tmp0058, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0059 = riscv_genADD_3(tmp0059, i, tmp0058); - if (!tmp0059.dontFree) h2_freeReg(tmp0058.regNro); - tmp0060 = riscv_genR_3(tmp0060, tmp0059, immValueZero); - tmp0061 = riscv_genMUL_4(tmp0061, tmp0060, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][2]))}, immValueZero); - if (!tmp0061.dontFree) h2_freeReg(tmp0060.regNro); - tmp0062 = riscv_genADD_3(tmp0062, tmp0057, tmp0061); - if (!tmp0062.dontFree) h2_freeReg(tmp0057.regNro); - if (!tmp0062.dontFree) h2_freeReg(tmp0061.regNro); - riscv_genW_3(tmp0043, tmp0062, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp0063 = riscv_genMUL_4(tmp0063, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0064 = riscv_genADD_3(tmp0064, o, tmp0063); - if (!tmp0064.dontFree) h2_freeReg(tmp0063.regNro); - tmp0065 = riscv_genMUL_4(tmp0065, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0066 = riscv_genADD_3(tmp0066, i, tmp0065); - if (!tmp0066.dontFree) h2_freeReg(tmp0065.regNro); - tmp0067 = riscv_genR_3(tmp0067, tmp0066, immValueZero); - tmp0068 = riscv_genMUL_4(tmp0068, tmp0067, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[0][3]))}, immValueZero); - if (!tmp0068.dontFree) h2_freeReg(tmp0067.regNro); - tmp0069 = riscv_genMUL_4(tmp0069, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0070 = riscv_genADD_3(tmp0070, i, tmp0069); - if (!tmp0070.dontFree) h2_freeReg(tmp0069.regNro); - tmp0071 = riscv_genR_3(tmp0071, tmp0070, immValueZero); - tmp0072 = riscv_genMUL_4(tmp0072, tmp0071, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[1][3]))}, immValueZero); - if (!tmp0072.dontFree) h2_freeReg(tmp0071.regNro); - tmp0073 = riscv_genADD_3(tmp0073, tmp0068, tmp0072); - if (!tmp0073.dontFree) h2_freeReg(tmp0068.regNro); - if (!tmp0073.dontFree) h2_freeReg(tmp0072.regNro); - tmp0074 = riscv_genMUL_4(tmp0074, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(2)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0075 = riscv_genADD_3(tmp0075, i, tmp0074); - if (!tmp0075.dontFree) h2_freeReg(tmp0074.regNro); - tmp0076 = riscv_genR_3(tmp0076, tmp0075, immValueZero); - tmp0077 = riscv_genMUL_4(tmp0077, tmp0076, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[2][3]))}, immValueZero); - if (!tmp0077.dontFree) h2_freeReg(tmp0076.regNro); - tmp0078 = riscv_genADD_3(tmp0078, tmp0073, tmp0077); - if (!tmp0078.dontFree) h2_freeReg(tmp0073.regNro); - if (!tmp0078.dontFree) h2_freeReg(tmp0077.regNro); - tmp0079 = riscv_genMUL_4(tmp0079, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(3)}, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((1 * 32) / 8)}, immValueZero); - tmp0080 = riscv_genADD_3(tmp0080, i, tmp0079); - if (!tmp0080.dontFree) h2_freeReg(tmp0079.regNro); - tmp0081 = riscv_genR_3(tmp0081, tmp0080, immValueZero); - tmp0082 = riscv_genMUL_4(tmp0082, tmp0081, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((m[3][3]))}, immValueZero); - if (!tmp0082.dontFree) h2_freeReg(tmp0081.regNro); - tmp0083 = riscv_genADD_3(tmp0083, tmp0078, tmp0082); - if (!tmp0083.dontFree) h2_freeReg(tmp0078.regNro); - if (!tmp0083.dontFree) h2_freeReg(tmp0082.regNro); - riscv_genW_3(tmp0064, tmp0083, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return ptr; -} - -d_t VectorMatrixProductUnrolled (vector_t o, vector_t i, matrix_t m) -{ - o[0] = i[0]*m[0][0] + i[1]*m[1][0] + i[2]*m[2][0] + i[3]*m[3][0]; - o[1] = i[0]*m[0][1] + i[1]*m[1][1] + i[2]*m[2][1] + i[3]*m[3][1]; - o[2] = i[0]*m[0][2] + i[1]*m[1][2] + i[2]*m[2][2] + i[3]*m[3][2]; - o[3] = i[0]*m[0][3] + i[1]*m[1][3] + i[2]*m[2][3] + i[3]*m[3][3]; - return o[3]; -} - -#if 0 // What the binary code should be with a translation matrix -d_t VectorMatrixProductUnrolledSR(vector_t o, vector_t i, matrix_t m) -{ - - o[0] = m[0][0] * i[0] + + m[3][0] * i[3]; - o[1] = m[1][1] * i[1] + + m[3][1] * i[3]; - o[2] = m[2][2] * i[2] + m[3][2] * i[3]; - o[3] = + i[3]; - return o[3]; -} -#endif -d_t VectorMatrixProduct (vector_t o, vector_t i, matrix_t m) -{ - for (int column = 0; column < T; column++) - { - o[column] = 0; - for (int line = 0; line < T; line++) - { - o[column] += i[line] * m[line][column]; - - } - } - return o[3]; -} - - -int VectorMatrixProductCount(matrix_t mat) -{ - int op = 0; - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - switch (mat[line][column]) - { - case 0 : op += 0; break; - case 1 : op += 1; break; - default: op += 2; break; - } - } - } - return op; -} - - -void printMatrix (matrix_t m, char msg[]) -{ - printf ("%s:\n", msg); - for (int column = 0; column < T; column++) - { - for (int line = 0; line < T; line++) - { - printf ("%4d ", m[line][column]); - } - printf ("\n"); - } - printf ("\n"); -} - -void printVector (vector_t v, char msg[]) -{ - for (int i = 0; i < T; i++) - printf ("%4d ", v[i]); - printf ("%s\n", msg); -} - -bool vectorCompare(vector_t ref[], vector_t other[], char * msg, int doPrint, int nVector) -{ - int has_differences = false; - for (int line = 0; line < nVector; line++) - for (int i = 0; i < T; i++) - { - if (ref[line][i] != other[line][i]) - has_differences = true; - if (doPrint) - printf("%4d ", other[line][i]); - } - /* printf("%s : ", msg); */ - /* printf(" %s\n", (has_differences)?"NOT OK":"OK"); */ - return has_differences; -} - -int main (int argc, char *argv[]) -{ - matrix_t m; - char *matrixName; - // vector_t in0 = {1, 2, 3, 4}, in1 = {5, 6, 7, 8}; - vector_t *out, *cout, *in; - uint64_t timeGeneral, timeCompilette; - pifvv vmProduct; - int tmp, doPrint, nXperiment; - unsigned long acc; - bool resultValid; - - if (argc != 19) - { - printf ("Not enough arguments %d\n", argc); - printf ("VectorMatrix ExperimentNumber MatrixName M11 M12 ... M44\n"); - exit (-1); - } - doPrint = 0; - acc = 0; - nXperiment = atoi (argv[1]); - matrixName = argv[2]; - for (int line = 0; line < 4; line++) - for (int column = 0; column < 4; column++) - { - m[line][column] = atoi (argv[3 + line*4+column]); - } -#ifdef VERBOSE - printMatrix(m, matrixName); -#endif - - in = calloc(nXperiment, sizeof (vector_t)); - out = calloc(nXperiment, sizeof (vector_t)); - cout = calloc(nXperiment, sizeof (vector_t)); - - for (int line = 0; line < nXperiment; line++) - for (int column = 0; column < 4; column++) - in[line][column] = random () % 1000; - - tmp = VectorMatrixProductCount (m); - printf("Operation count Matrix %s : %d theoretical speedup %.1f\n", matrixName, tmp, (0==tmp)?32:32.0/tmp); - -// Repeat one instruction and count ticks -#define DO(INSN, REPEAT, TIME) {uint64_t tickCount = h2_getticks();for (int i = 0; i < REPEAT; i++) INSN; TIME = h2_getticks() - tickCount;} - -#ifdef VERBOSE - printVector (in[0], "Input vector #0"); -#endif - - acc += VectorMatrixProduct (out[0], in[0], m); /* Cold start */ - DO(acc += VectorMatrixProduct (out[i], in[i], m), nXperiment, timeGeneral) - -#ifdef VERBOSE - printVector (out[0], "Output vector #0 (general)"); -#endif - -#if 0 // Possible test with a source level unrolled version - uint64_t timeUnrolled; - vector_t uout0, uout1; - acc += VectorMatrixProductUnrolled (uout0, in0, m); - DO(acc += VectorMatrixProductUnrolled (uout1, in1, m), nXperiment, timeUnrolled); - vectorCompare(out1, uout1, "Unrolled out0", doPrint); -#endif - - vmProduct = (pifvv) h2_malloc(1024); - vmProduct = genVectorMatrixProduct (vmProduct, m); - acc += vmProduct (cout[0], in[0]); - DO(acc += vmProduct (cout[i], in[i]), nXperiment, timeCompilette); - -#ifdef VERBOSE - printVector (cout[0], "Output vector #0 (compilette)"); -#endif - - resultValid = vectorCompare(out, cout, "Compilette", doPrint, nXperiment); - - printf ("%s;%d;%lu;%lu;%lld;%d;%s\n", - matrixName, nXperiment, - timeGeneral, timeCompilette, - h2_codeGenTime, h2_insnGenerated, - resultValid?"true":"false"); - return resultValid; -} diff --git a/HybroGen/IsaDescription.interp b/HybroGen/IsaDescription.interp deleted file mode 100644 index c1157f7..0000000 --- a/HybroGen/IsaDescription.interp +++ /dev/null @@ -1,58 +0,0 @@ -token literal names: -null -'ARCH' -'|' -'[' -']' -'i' -'u' -'f' -null -null -null -null -null -':' -null - -token symbolic names: -null -null -null -null -null -null -null -null -WS -COMMENT -INT -NAME -NEWLINE -SEMICOL -CINLINE - -rule names: -isadescription -headerlines -archline -isalines -commentline -isaline -emptyline -bindescr -binelem -binvalue -regbin -expbin -asmdescr -extname -arith -opname -regName -semname -reglist - - -atn: -[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 16, 133, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 4, 17, 9, 17, 4, 18, 9, 18, 4, 19, 9, 19, 4, 20, 9, 20, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 3, 3, 6, 3, 47, 10, 3, 13, 3, 14, 3, 48, 3, 4, 3, 4, 3, 4, 6, 4, 54, 10, 4, 13, 4, 14, 4, 55, 3, 4, 3, 4, 3, 5, 3, 5, 3, 5, 7, 5, 63, 10, 5, 12, 5, 14, 5, 66, 11, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 6, 9, 78, 10, 9, 13, 9, 14, 9, 79, 3, 10, 3, 10, 3, 10, 5, 10, 85, 10, 10, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 3, 12, 3, 12, 5, 12, 94, 10, 12, 3, 12, 3, 12, 3, 13, 3, 13, 3, 13, 3, 13, 3, 13, 5, 13, 103, 10, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 3, 14, 5, 14, 114, 10, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 3, 20, 3, 20, 7, 20, 128, 10, 20, 12, 20, 14, 20, 131, 11, 20, 3, 20, 2, 2, 21, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 2, 3, 3, 2, 7, 9, 2, 127, 2, 40, 3, 2, 2, 2, 4, 46, 3, 2, 2, 2, 6, 50, 3, 2, 2, 2, 8, 64, 3, 2, 2, 2, 10, 67, 3, 2, 2, 2, 12, 69, 3, 2, 2, 2, 14, 74, 3, 2, 2, 2, 16, 77, 3, 2, 2, 2, 18, 84, 3, 2, 2, 2, 20, 86, 3, 2, 2, 2, 22, 88, 3, 2, 2, 2, 24, 97, 3, 2, 2, 2, 26, 106, 3, 2, 2, 2, 28, 115, 3, 2, 2, 2, 30, 117, 3, 2, 2, 2, 32, 119, 3, 2, 2, 2, 34, 121, 3, 2, 2, 2, 36, 123, 3, 2, 2, 2, 38, 125, 3, 2, 2, 2, 40, 41, 5, 4, 3, 2, 41, 42, 5, 8, 5, 2, 42, 3, 3, 2, 2, 2, 43, 47, 5, 10, 6, 2, 44, 47, 5, 6, 4, 2, 45, 47, 5, 14, 8, 2, 46, 43, 3, 2, 2, 2, 46, 44, 3, 2, 2, 2, 46, 45, 3, 2, 2, 2, 47, 48, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 48, 49, 3, 2, 2, 2, 49, 5, 3, 2, 2, 2, 50, 51, 7, 3, 2, 2, 51, 53, 7, 13, 2, 2, 52, 54, 7, 12, 2, 2, 53, 52, 3, 2, 2, 2, 54, 55, 3, 2, 2, 2, 55, 53, 3, 2, 2, 2, 55, 56, 3, 2, 2, 2, 56, 57, 3, 2, 2, 2, 57, 58, 7, 14, 2, 2, 58, 7, 3, 2, 2, 2, 59, 63, 5, 10, 6, 2, 60, 63, 5, 14, 8, 2, 61, 63, 5, 12, 7, 2, 62, 59, 3, 2, 2, 2, 62, 60, 3, 2, 2, 2, 62, 61, 3, 2, 2, 2, 63, 66, 3, 2, 2, 2, 64, 62, 3, 2, 2, 2, 64, 65, 3, 2, 2, 2, 65, 9, 3, 2, 2, 2, 66, 64, 3, 2, 2, 2, 67, 68, 7, 11, 2, 2, 68, 11, 3, 2, 2, 2, 69, 70, 5, 16, 9, 2, 70, 71, 7, 4, 2, 2, 71, 72, 5, 26, 14, 2, 72, 73, 7, 14, 2, 2, 73, 13, 3, 2, 2, 2, 74, 75, 7, 14, 2, 2, 75, 15, 3, 2, 2, 2, 76, 78, 5, 18, 10, 2, 77, 76, 3, 2, 2, 2, 78, 79, 3, 2, 2, 2, 79, 77, 3, 2, 2, 2, 79, 80, 3, 2, 2, 2, 80, 17, 3, 2, 2, 2, 81, 85, 5, 20, 11, 2, 82, 85, 5, 22, 12, 2, 83, 85, 5, 24, 13, 2, 84, 81, 3, 2, 2, 2, 84, 82, 3, 2, 2, 2, 84, 83, 3, 2, 2, 2, 85, 19, 3, 2, 2, 2, 86, 87, 7, 12, 2, 2, 87, 21, 3, 2, 2, 2, 88, 89, 7, 13, 2, 2, 89, 90, 7, 5, 2, 2, 90, 93, 7, 12, 2, 2, 91, 92, 7, 15, 2, 2, 92, 94, 7, 12, 2, 2, 93, 91, 3, 2, 2, 2, 93, 94, 3, 2, 2, 2, 94, 95, 3, 2, 2, 2, 95, 96, 7, 6, 2, 2, 96, 23, 3, 2, 2, 2, 97, 98, 7, 16, 2, 2, 98, 99, 7, 5, 2, 2, 99, 102, 7, 12, 2, 2, 100, 101, 7, 15, 2, 2, 101, 103, 7, 12, 2, 2, 102, 100, 3, 2, 2, 2, 102, 103, 3, 2, 2, 2, 103, 104, 3, 2, 2, 2, 104, 105, 7, 6, 2, 2, 105, 25, 3, 2, 2, 2, 106, 107, 5, 28, 15, 2, 107, 108, 5, 30, 16, 2, 108, 109, 7, 12, 2, 2, 109, 110, 7, 12, 2, 2, 110, 111, 5, 36, 19, 2, 111, 113, 5, 32, 17, 2, 112, 114, 5, 38, 20, 2, 113, 112, 3, 2, 2, 2, 113, 114, 3, 2, 2, 2, 114, 27, 3, 2, 2, 2, 115, 116, 7, 13, 2, 2, 116, 29, 3, 2, 2, 2, 117, 118, 9, 2, 2, 2, 118, 31, 3, 2, 2, 2, 119, 120, 7, 13, 2, 2, 120, 33, 3, 2, 2, 2, 121, 122, 7, 13, 2, 2, 122, 35, 3, 2, 2, 2, 123, 124, 7, 13, 2, 2, 124, 37, 3, 2, 2, 2, 125, 129, 5, 34, 18, 2, 126, 128, 5, 34, 18, 2, 127, 126, 3, 2, 2, 2, 128, 131, 3, 2, 2, 2, 129, 127, 3, 2, 2, 2, 129, 130, 3, 2, 2, 2, 130, 39, 3, 2, 2, 2, 131, 129, 3, 2, 2, 2, 13, 46, 48, 55, 62, 64, 79, 84, 93, 102, 113, 129] \ No newline at end of file diff --git a/HybroGen/IsaDescription.tokens b/HybroGen/IsaDescription.tokens deleted file mode 100644 index 2dcd920..0000000 --- a/HybroGen/IsaDescription.tokens +++ /dev/null @@ -1,22 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -T__4=5 -T__5=6 -T__6=7 -WS=8 -COMMENT=9 -INT=10 -NAME=11 -NEWLINE=12 -SEMICOL=13 -CINLINE=14 -'ARCH'=1 -'|'=2 -'['=3 -']'=4 -'i'=5 -'u'=6 -'f'=7 -':'=13 diff --git a/HybroGen/IsaDescriptionLexer.interp b/HybroGen/IsaDescriptionLexer.interp deleted file mode 100644 index 23a6756..0000000 --- a/HybroGen/IsaDescriptionLexer.interp +++ /dev/null @@ -1,59 +0,0 @@ -token literal names: -null -'ARCH' -'|' -'[' -']' -'i' -'u' -'f' -null -null -null -null -null -':' -null - -token symbolic names: -null -null -null -null -null -null -null -null -WS -COMMENT -INT -NAME -NEWLINE -SEMICOL -CINLINE - -rule names: -T__0 -T__1 -T__2 -T__3 -T__4 -T__5 -T__6 -WS -COMMENT -INT -NAME -NEWLINE -SEMICOL -CINLINE - -channel names: -DEFAULT_TOKEN_CHANNEL -HIDDEN - -mode names: -DEFAULT_MODE - -atn: -[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 16, 91, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 3, 2, 3, 2, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 7, 3, 7, 3, 8, 3, 8, 3, 9, 6, 9, 50, 10, 9, 13, 9, 14, 9, 51, 3, 9, 3, 9, 3, 10, 3, 10, 7, 10, 58, 10, 10, 12, 10, 14, 10, 61, 11, 10, 3, 10, 3, 10, 3, 11, 6, 11, 66, 10, 11, 13, 11, 14, 11, 67, 3, 12, 3, 12, 7, 12, 72, 10, 12, 12, 12, 14, 12, 75, 11, 12, 3, 13, 5, 13, 78, 10, 13, 3, 13, 3, 13, 3, 14, 3, 14, 3, 15, 3, 15, 6, 15, 86, 10, 15, 13, 15, 14, 15, 87, 3, 15, 3, 15, 3, 59, 2, 16, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 27, 15, 29, 16, 3, 2, 7, 4, 2, 11, 11, 34, 34, 3, 2, 50, 59, 4, 2, 67, 92, 99, 124, 7, 2, 48, 48, 50, 59, 67, 92, 97, 97, 99, 124, 3, 2, 127, 127, 2, 96, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 2, 27, 3, 2, 2, 2, 2, 29, 3, 2, 2, 2, 3, 31, 3, 2, 2, 2, 5, 36, 3, 2, 2, 2, 7, 38, 3, 2, 2, 2, 9, 40, 3, 2, 2, 2, 11, 42, 3, 2, 2, 2, 13, 44, 3, 2, 2, 2, 15, 46, 3, 2, 2, 2, 17, 49, 3, 2, 2, 2, 19, 55, 3, 2, 2, 2, 21, 65, 3, 2, 2, 2, 23, 69, 3, 2, 2, 2, 25, 77, 3, 2, 2, 2, 27, 81, 3, 2, 2, 2, 29, 83, 3, 2, 2, 2, 31, 32, 7, 67, 2, 2, 32, 33, 7, 84, 2, 2, 33, 34, 7, 69, 2, 2, 34, 35, 7, 74, 2, 2, 35, 4, 3, 2, 2, 2, 36, 37, 7, 126, 2, 2, 37, 6, 3, 2, 2, 2, 38, 39, 7, 93, 2, 2, 39, 8, 3, 2, 2, 2, 40, 41, 7, 95, 2, 2, 41, 10, 3, 2, 2, 2, 42, 43, 7, 107, 2, 2, 43, 12, 3, 2, 2, 2, 44, 45, 7, 119, 2, 2, 45, 14, 3, 2, 2, 2, 46, 47, 7, 104, 2, 2, 47, 16, 3, 2, 2, 2, 48, 50, 9, 2, 2, 2, 49, 48, 3, 2, 2, 2, 50, 51, 3, 2, 2, 2, 51, 49, 3, 2, 2, 2, 51, 52, 3, 2, 2, 2, 52, 53, 3, 2, 2, 2, 53, 54, 8, 9, 2, 2, 54, 18, 3, 2, 2, 2, 55, 59, 7, 37, 2, 2, 56, 58, 11, 2, 2, 2, 57, 56, 3, 2, 2, 2, 58, 61, 3, 2, 2, 2, 59, 60, 3, 2, 2, 2, 59, 57, 3, 2, 2, 2, 60, 62, 3, 2, 2, 2, 61, 59, 3, 2, 2, 2, 62, 63, 5, 25, 13, 2, 63, 20, 3, 2, 2, 2, 64, 66, 9, 3, 2, 2, 65, 64, 3, 2, 2, 2, 66, 67, 3, 2, 2, 2, 67, 65, 3, 2, 2, 2, 67, 68, 3, 2, 2, 2, 68, 22, 3, 2, 2, 2, 69, 73, 9, 4, 2, 2, 70, 72, 9, 5, 2, 2, 71, 70, 3, 2, 2, 2, 72, 75, 3, 2, 2, 2, 73, 71, 3, 2, 2, 2, 73, 74, 3, 2, 2, 2, 74, 24, 3, 2, 2, 2, 75, 73, 3, 2, 2, 2, 76, 78, 7, 15, 2, 2, 77, 76, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 79, 3, 2, 2, 2, 79, 80, 7, 12, 2, 2, 80, 26, 3, 2, 2, 2, 81, 82, 7, 60, 2, 2, 82, 28, 3, 2, 2, 2, 83, 85, 7, 125, 2, 2, 84, 86, 10, 6, 2, 2, 85, 84, 3, 2, 2, 2, 86, 87, 3, 2, 2, 2, 87, 85, 3, 2, 2, 2, 87, 88, 3, 2, 2, 2, 88, 89, 3, 2, 2, 2, 89, 90, 7, 127, 2, 2, 90, 30, 3, 2, 2, 2, 9, 2, 51, 59, 67, 73, 77, 87, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroGen/IsaDescriptionLexer.py b/HybroGen/IsaDescriptionLexer.py deleted file mode 100644 index 1ace933..0000000 --- a/HybroGen/IsaDescriptionLexer.py +++ /dev/null @@ -1,92 +0,0 @@ -# Generated from IsaDescription.g4 by ANTLR 4.9.2 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\20") - buf.write("[\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") - buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") - buf.write("\t\16\4\17\t\17\3\2\3\2\3\2\3\2\3\2\3\3\3\3\3\4\3\4\3") - buf.write("\5\3\5\3\6\3\6\3\7\3\7\3\b\3\b\3\t\6\t\62\n\t\r\t\16\t") - buf.write("\63\3\t\3\t\3\n\3\n\7\n:\n\n\f\n\16\n=\13\n\3\n\3\n\3") - buf.write("\13\6\13B\n\13\r\13\16\13C\3\f\3\f\7\fH\n\f\f\f\16\fK") - buf.write("\13\f\3\r\5\rN\n\r\3\r\3\r\3\16\3\16\3\17\3\17\6\17V\n") - buf.write("\17\r\17\16\17W\3\17\3\17\3;\2\20\3\3\5\4\7\5\t\6\13\7") - buf.write("\r\b\17\t\21\n\23\13\25\f\27\r\31\16\33\17\35\20\3\2\7") - buf.write("\4\2\13\13\"\"\3\2\62;\4\2C\\c|\7\2\60\60\62;C\\aac|\3") - buf.write("\2\177\177\2`\2\3\3\2\2\2\2\5\3\2\2\2\2\7\3\2\2\2\2\t") - buf.write("\3\2\2\2\2\13\3\2\2\2\2\r\3\2\2\2\2\17\3\2\2\2\2\21\3") - buf.write("\2\2\2\2\23\3\2\2\2\2\25\3\2\2\2\2\27\3\2\2\2\2\31\3\2") - buf.write("\2\2\2\33\3\2\2\2\2\35\3\2\2\2\3\37\3\2\2\2\5$\3\2\2\2") - buf.write("\7&\3\2\2\2\t(\3\2\2\2\13*\3\2\2\2\r,\3\2\2\2\17.\3\2") - buf.write("\2\2\21\61\3\2\2\2\23\67\3\2\2\2\25A\3\2\2\2\27E\3\2\2") - buf.write("\2\31M\3\2\2\2\33Q\3\2\2\2\35S\3\2\2\2\37 \7C\2\2 !\7") - buf.write("T\2\2!\"\7E\2\2\"#\7J\2\2#\4\3\2\2\2$%\7~\2\2%\6\3\2\2") - buf.write("\2&\'\7]\2\2\'\b\3\2\2\2()\7_\2\2)\n\3\2\2\2*+\7k\2\2") - buf.write("+\f\3\2\2\2,-\7w\2\2-\16\3\2\2\2./\7h\2\2/\20\3\2\2\2") - buf.write("\60\62\t\2\2\2\61\60\3\2\2\2\62\63\3\2\2\2\63\61\3\2\2") - buf.write("\2\63\64\3\2\2\2\64\65\3\2\2\2\65\66\b\t\2\2\66\22\3\2") - buf.write("\2\2\67;\7%\2\28:\13\2\2\298\3\2\2\2:=\3\2\2\2;<\3\2\2") - buf.write("\2;9\3\2\2\2<>\3\2\2\2=;\3\2\2\2>?\5\31\r\2?\24\3\2\2") - buf.write("\2@B\t\3\2\2A@\3\2\2\2BC\3\2\2\2CA\3\2\2\2CD\3\2\2\2D") - buf.write("\26\3\2\2\2EI\t\4\2\2FH\t\5\2\2GF\3\2\2\2HK\3\2\2\2IG") - buf.write("\3\2\2\2IJ\3\2\2\2J\30\3\2\2\2KI\3\2\2\2LN\7\17\2\2ML") - buf.write("\3\2\2\2MN\3\2\2\2NO\3\2\2\2OP\7\f\2\2P\32\3\2\2\2QR\7") - buf.write("<\2\2R\34\3\2\2\2SU\7}\2\2TV\n\6\2\2UT\3\2\2\2VW\3\2\2") - buf.write("\2WU\3\2\2\2WX\3\2\2\2XY\3\2\2\2YZ\7\177\2\2Z\36\3\2\2") - buf.write("\2\t\2\63;CIMW\3\b\2\2") - return buf.getvalue() - - -class IsaDescriptionLexer(Lexer): - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - T__0 = 1 - T__1 = 2 - T__2 = 3 - T__3 = 4 - T__4 = 5 - T__5 = 6 - T__6 = 7 - WS = 8 - COMMENT = 9 - INT = 10 - NAME = 11 - NEWLINE = 12 - SEMICOL = 13 - CINLINE = 14 - - channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] - - modeNames = [ "DEFAULT_MODE" ] - - literalNames = [ "", - "'ARCH'", "'|'", "'['", "']'", "'i'", "'u'", "'f'", "':'" ] - - symbolicNames = [ "", - "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", "CINLINE" ] - - ruleNames = [ "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", - "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", - "CINLINE" ] - - grammarFileName = "IsaDescription.g4" - - def __init__(self, input=None, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) - self._actions = None - self._predicates = None - - diff --git a/HybroGen/IsaDescriptionLexer.tokens b/HybroGen/IsaDescriptionLexer.tokens deleted file mode 100644 index 2dcd920..0000000 --- a/HybroGen/IsaDescriptionLexer.tokens +++ /dev/null @@ -1,22 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -T__4=5 -T__5=6 -T__6=7 -WS=8 -COMMENT=9 -INT=10 -NAME=11 -NEWLINE=12 -SEMICOL=13 -CINLINE=14 -'ARCH'=1 -'|'=2 -'['=3 -']'=4 -'i'=5 -'u'=6 -'f'=7 -':'=13 diff --git a/HybroGen/IsaDescriptionListener.py b/HybroGen/IsaDescriptionListener.py deleted file mode 100644 index f1a6b6f..0000000 --- a/HybroGen/IsaDescriptionListener.py +++ /dev/null @@ -1,183 +0,0 @@ -# Generated from IsaDescription.g4 by ANTLR 4.9.2 -from antlr4 import * -if __name__ is not None and "." in __name__: - from .IsaDescriptionParser import IsaDescriptionParser -else: - from IsaDescriptionParser import IsaDescriptionParser - -# This class defines a complete listener for a parse tree produced by IsaDescriptionParser. -class IsaDescriptionListener(ParseTreeListener): - - # Enter a parse tree produced by IsaDescriptionParser#isadescription. - def enterIsadescription(self, ctx:IsaDescriptionParser.IsadescriptionContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#isadescription. - def exitIsadescription(self, ctx:IsaDescriptionParser.IsadescriptionContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#headerlines. - def enterHeaderlines(self, ctx:IsaDescriptionParser.HeaderlinesContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#headerlines. - def exitHeaderlines(self, ctx:IsaDescriptionParser.HeaderlinesContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#archline. - def enterArchline(self, ctx:IsaDescriptionParser.ArchlineContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#archline. - def exitArchline(self, ctx:IsaDescriptionParser.ArchlineContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#isalines. - def enterIsalines(self, ctx:IsaDescriptionParser.IsalinesContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#isalines. - def exitIsalines(self, ctx:IsaDescriptionParser.IsalinesContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#commentline. - def enterCommentline(self, ctx:IsaDescriptionParser.CommentlineContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#commentline. - def exitCommentline(self, ctx:IsaDescriptionParser.CommentlineContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#isaline. - def enterIsaline(self, ctx:IsaDescriptionParser.IsalineContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#isaline. - def exitIsaline(self, ctx:IsaDescriptionParser.IsalineContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#emptyline. - def enterEmptyline(self, ctx:IsaDescriptionParser.EmptylineContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#emptyline. - def exitEmptyline(self, ctx:IsaDescriptionParser.EmptylineContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#bindescr. - def enterBindescr(self, ctx:IsaDescriptionParser.BindescrContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#bindescr. - def exitBindescr(self, ctx:IsaDescriptionParser.BindescrContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#binelem. - def enterBinelem(self, ctx:IsaDescriptionParser.BinelemContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#binelem. - def exitBinelem(self, ctx:IsaDescriptionParser.BinelemContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#binvalue. - def enterBinvalue(self, ctx:IsaDescriptionParser.BinvalueContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#binvalue. - def exitBinvalue(self, ctx:IsaDescriptionParser.BinvalueContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#regbin. - def enterRegbin(self, ctx:IsaDescriptionParser.RegbinContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#regbin. - def exitRegbin(self, ctx:IsaDescriptionParser.RegbinContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#expbin. - def enterExpbin(self, ctx:IsaDescriptionParser.ExpbinContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#expbin. - def exitExpbin(self, ctx:IsaDescriptionParser.ExpbinContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#asmdescr. - def enterAsmdescr(self, ctx:IsaDescriptionParser.AsmdescrContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#asmdescr. - def exitAsmdescr(self, ctx:IsaDescriptionParser.AsmdescrContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#extname. - def enterExtname(self, ctx:IsaDescriptionParser.ExtnameContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#extname. - def exitExtname(self, ctx:IsaDescriptionParser.ExtnameContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#arith. - def enterArith(self, ctx:IsaDescriptionParser.ArithContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#arith. - def exitArith(self, ctx:IsaDescriptionParser.ArithContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#opname. - def enterOpname(self, ctx:IsaDescriptionParser.OpnameContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#opname. - def exitOpname(self, ctx:IsaDescriptionParser.OpnameContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#regName. - def enterRegName(self, ctx:IsaDescriptionParser.RegNameContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#regName. - def exitRegName(self, ctx:IsaDescriptionParser.RegNameContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#semname. - def enterSemname(self, ctx:IsaDescriptionParser.SemnameContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#semname. - def exitSemname(self, ctx:IsaDescriptionParser.SemnameContext): - pass - - - # Enter a parse tree produced by IsaDescriptionParser#reglist. - def enterReglist(self, ctx:IsaDescriptionParser.ReglistContext): - pass - - # Exit a parse tree produced by IsaDescriptionParser#reglist. - def exitReglist(self, ctx:IsaDescriptionParser.ReglistContext): - pass - - - -del IsaDescriptionParser \ No newline at end of file diff --git a/HybroGen/IsaDescriptionParser.py b/HybroGen/IsaDescriptionParser.py deleted file mode 100644 index cd79c81..0000000 --- a/HybroGen/IsaDescriptionParser.py +++ /dev/null @@ -1,1179 +0,0 @@ -# Generated from IsaDescription.g4 by ANTLR 4.9.2 -# encoding: utf-8 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\20") - buf.write("\u0085\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") - buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") - buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23") - buf.write("\4\24\t\24\3\2\3\2\3\2\3\3\3\3\3\3\6\3/\n\3\r\3\16\3\60") - buf.write("\3\4\3\4\3\4\6\4\66\n\4\r\4\16\4\67\3\4\3\4\3\5\3\5\3") - buf.write("\5\7\5?\n\5\f\5\16\5B\13\5\3\6\3\6\3\7\3\7\3\7\3\7\3\7") - buf.write("\3\b\3\b\3\t\6\tN\n\t\r\t\16\tO\3\n\3\n\3\n\5\nU\n\n\3") - buf.write("\13\3\13\3\f\3\f\3\f\3\f\3\f\5\f^\n\f\3\f\3\f\3\r\3\r") - buf.write("\3\r\3\r\3\r\5\rg\n\r\3\r\3\r\3\16\3\16\3\16\3\16\3\16") - buf.write("\3\16\3\16\5\16r\n\16\3\17\3\17\3\20\3\20\3\21\3\21\3") - buf.write("\22\3\22\3\23\3\23\3\24\3\24\7\24\u0080\n\24\f\24\16\24") - buf.write("\u0083\13\24\3\24\2\2\25\2\4\6\b\n\f\16\20\22\24\26\30") - buf.write("\32\34\36 \"$&\2\3\3\2\7\t\2\177\2(\3\2\2\2\4.\3\2\2\2") - buf.write("\6\62\3\2\2\2\b@\3\2\2\2\nC\3\2\2\2\fE\3\2\2\2\16J\3\2") - buf.write("\2\2\20M\3\2\2\2\22T\3\2\2\2\24V\3\2\2\2\26X\3\2\2\2\30") - buf.write("a\3\2\2\2\32j\3\2\2\2\34s\3\2\2\2\36u\3\2\2\2 w\3\2\2") - buf.write("\2\"y\3\2\2\2${\3\2\2\2&}\3\2\2\2()\5\4\3\2)*\5\b\5\2") - buf.write("*\3\3\2\2\2+/\5\n\6\2,/\5\6\4\2-/\5\16\b\2.+\3\2\2\2.") - buf.write(",\3\2\2\2.-\3\2\2\2/\60\3\2\2\2\60.\3\2\2\2\60\61\3\2") - buf.write("\2\2\61\5\3\2\2\2\62\63\7\3\2\2\63\65\7\r\2\2\64\66\7") - buf.write("\f\2\2\65\64\3\2\2\2\66\67\3\2\2\2\67\65\3\2\2\2\678\3") - buf.write("\2\2\289\3\2\2\29:\7\16\2\2:\7\3\2\2\2;?\5\n\6\2;\3\2\2\2><\3\2\2\2>=\3\2\2\2?B\3\2\2\2") - buf.write("@>\3\2\2\2@A\3\2\2\2A\t\3\2\2\2B@\3\2\2\2CD\7\13\2\2D") - buf.write("\13\3\2\2\2EF\5\20\t\2FG\7\4\2\2GH\5\32\16\2HI\7\16\2") - buf.write("\2I\r\3\2\2\2JK\7\16\2\2K\17\3\2\2\2LN\5\22\n\2ML\3\2") - buf.write("\2\2NO\3\2\2\2OM\3\2\2\2OP\3\2\2\2P\21\3\2\2\2QU\5\24") - buf.write("\13\2RU\5\26\f\2SU\5\30\r\2TQ\3\2\2\2TR\3\2\2\2TS\3\2") - buf.write("\2\2U\23\3\2\2\2VW\7\f\2\2W\25\3\2\2\2XY\7\r\2\2YZ\7\5") - buf.write("\2\2Z]\7\f\2\2[\\\7\17\2\2\\^\7\f\2\2][\3\2\2\2]^\3\2") - buf.write("\2\2^_\3\2\2\2_`\7\6\2\2`\27\3\2\2\2ab\7\20\2\2bc\7\5") - buf.write("\2\2cf\7\f\2\2de\7\17\2\2eg\7\f\2\2fd\3\2\2\2fg\3\2\2") - buf.write("\2gh\3\2\2\2hi\7\6\2\2i\31\3\2\2\2jk\5\34\17\2kl\5\36") - buf.write("\20\2lm\7\f\2\2mn\7\f\2\2no\5$\23\2oq\5 \21\2pr\5&\24") - buf.write("\2qp\3\2\2\2qr\3\2\2\2r\33\3\2\2\2st\7\r\2\2t\35\3\2\2") - buf.write("\2uv\t\2\2\2v\37\3\2\2\2wx\7\r\2\2x!\3\2\2\2yz\7\r\2\2") - buf.write("z#\3\2\2\2{|\7\r\2\2|%\3\2\2\2}\u0081\5\"\22\2~\u0080") - buf.write("\5\"\22\2\177~\3\2\2\2\u0080\u0083\3\2\2\2\u0081\177\3") - buf.write("\2\2\2\u0081\u0082\3\2\2\2\u0082\'\3\2\2\2\u0083\u0081") - buf.write("\3\2\2\2\r.\60\67>@OT]fq\u0081") - return buf.getvalue() - - -class IsaDescriptionParser ( Parser ): - - grammarFileName = "IsaDescription.g4" - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - sharedContextCache = PredictionContextCache() - - literalNames = [ "", "'ARCH'", "'|'", "'['", "']'", "'i'", - "'u'", "'f'", "", "", "", - "", "", "':'" ] - - symbolicNames = [ "", "", "", "", - "", "", "", "", - "WS", "COMMENT", "INT", "NAME", "NEWLINE", "SEMICOL", - "CINLINE" ] - - RULE_isadescription = 0 - RULE_headerlines = 1 - RULE_archline = 2 - RULE_isalines = 3 - RULE_commentline = 4 - RULE_isaline = 5 - RULE_emptyline = 6 - RULE_bindescr = 7 - RULE_binelem = 8 - RULE_binvalue = 9 - RULE_regbin = 10 - RULE_expbin = 11 - RULE_asmdescr = 12 - RULE_extname = 13 - RULE_arith = 14 - RULE_opname = 15 - RULE_regName = 16 - RULE_semname = 17 - RULE_reglist = 18 - - ruleNames = [ "isadescription", "headerlines", "archline", "isalines", - "commentline", "isaline", "emptyline", "bindescr", "binelem", - "binvalue", "regbin", "expbin", "asmdescr", "extname", - "arith", "opname", "regName", "semname", "reglist" ] - - EOF = Token.EOF - T__0=1 - T__1=2 - T__2=3 - T__3=4 - T__4=5 - T__5=6 - T__6=7 - WS=8 - COMMENT=9 - INT=10 - NAME=11 - NEWLINE=12 - SEMICOL=13 - CINLINE=14 - - def __init__(self, input:TokenStream, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) - self._predicates = None - - - - class IsadescriptionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def headerlines(self): - return self.getTypedRuleContext(IsaDescriptionParser.HeaderlinesContext,0) - - - def isalines(self): - return self.getTypedRuleContext(IsaDescriptionParser.IsalinesContext,0) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_isadescription - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterIsadescription" ): - listener.enterIsadescription(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitIsadescription" ): - listener.exitIsadescription(self) - - - - - def isadescription(self): - - localctx = IsaDescriptionParser.IsadescriptionContext(self, self._ctx, self.state) - self.enterRule(localctx, 0, self.RULE_isadescription) - try: - self.enterOuterAlt(localctx, 1) - self.state = 38 - self.headerlines() - self.state = 39 - self.isalines() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class HeaderlinesContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def commentline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.CommentlineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.CommentlineContext,i) - - - def archline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.ArchlineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.ArchlineContext,i) - - - def emptyline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.EmptylineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.EmptylineContext,i) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_headerlines - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterHeaderlines" ): - listener.enterHeaderlines(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitHeaderlines" ): - listener.exitHeaderlines(self) - - - - - def headerlines(self): - - localctx = IsaDescriptionParser.HeaderlinesContext(self, self._ctx, self.state) - self.enterRule(localctx, 2, self.RULE_headerlines) - try: - self.enterOuterAlt(localctx, 1) - self.state = 44 - self._errHandler.sync(self) - _alt = 1 - while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: - if _alt == 1: - self.state = 44 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [IsaDescriptionParser.COMMENT]: - self.state = 41 - self.commentline() - pass - elif token in [IsaDescriptionParser.T__0]: - self.state = 42 - self.archline() - pass - elif token in [IsaDescriptionParser.NEWLINE]: - self.state = 43 - self.emptyline() - pass - else: - raise NoViableAltException(self) - - - else: - raise NoViableAltException(self) - self.state = 46 - self._errHandler.sync(self) - _alt = self._interp.adaptivePredict(self._input,1,self._ctx) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ArchlineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def NEWLINE(self): - return self.getToken(IsaDescriptionParser.NEWLINE, 0) - - def INT(self, i:int=None): - if i is None: - return self.getTokens(IsaDescriptionParser.INT) - else: - return self.getToken(IsaDescriptionParser.INT, i) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_archline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterArchline" ): - listener.enterArchline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitArchline" ): - listener.exitArchline(self) - - - - - def archline(self): - - localctx = IsaDescriptionParser.ArchlineContext(self, self._ctx, self.state) - self.enterRule(localctx, 4, self.RULE_archline) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 48 - self.match(IsaDescriptionParser.T__0) - self.state = 49 - self.match(IsaDescriptionParser.NAME) - self.state = 51 - self._errHandler.sync(self) - _la = self._input.LA(1) - while True: - self.state = 50 - self.match(IsaDescriptionParser.INT) - self.state = 53 - self._errHandler.sync(self) - _la = self._input.LA(1) - if not (_la==IsaDescriptionParser.INT): - break - - self.state = 55 - self.match(IsaDescriptionParser.NEWLINE) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class IsalinesContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def commentline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.CommentlineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.CommentlineContext,i) - - - def emptyline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.EmptylineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.EmptylineContext,i) - - - def isaline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.IsalineContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.IsalineContext,i) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_isalines - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterIsalines" ): - listener.enterIsalines(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitIsalines" ): - listener.exitIsalines(self) - - - - - def isalines(self): - - localctx = IsaDescriptionParser.IsalinesContext(self, self._ctx, self.state) - self.enterRule(localctx, 6, self.RULE_isalines) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 62 - self._errHandler.sync(self) - _la = self._input.LA(1) - while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.COMMENT) | (1 << IsaDescriptionParser.INT) | (1 << IsaDescriptionParser.NAME) | (1 << IsaDescriptionParser.NEWLINE) | (1 << IsaDescriptionParser.CINLINE))) != 0): - self.state = 60 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [IsaDescriptionParser.COMMENT]: - self.state = 57 - self.commentline() - pass - elif token in [IsaDescriptionParser.NEWLINE]: - self.state = 58 - self.emptyline() - pass - elif token in [IsaDescriptionParser.INT, IsaDescriptionParser.NAME, IsaDescriptionParser.CINLINE]: - self.state = 59 - self.isaline() - pass - else: - raise NoViableAltException(self) - - self.state = 64 - self._errHandler.sync(self) - _la = self._input.LA(1) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class CommentlineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def COMMENT(self): - return self.getToken(IsaDescriptionParser.COMMENT, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_commentline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterCommentline" ): - listener.enterCommentline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitCommentline" ): - listener.exitCommentline(self) - - - - - def commentline(self): - - localctx = IsaDescriptionParser.CommentlineContext(self, self._ctx, self.state) - self.enterRule(localctx, 8, self.RULE_commentline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 65 - self.match(IsaDescriptionParser.COMMENT) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class IsalineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def bindescr(self): - return self.getTypedRuleContext(IsaDescriptionParser.BindescrContext,0) - - - def asmdescr(self): - return self.getTypedRuleContext(IsaDescriptionParser.AsmdescrContext,0) - - - def NEWLINE(self): - return self.getToken(IsaDescriptionParser.NEWLINE, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_isaline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterIsaline" ): - listener.enterIsaline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitIsaline" ): - listener.exitIsaline(self) - - - - - def isaline(self): - - localctx = IsaDescriptionParser.IsalineContext(self, self._ctx, self.state) - self.enterRule(localctx, 10, self.RULE_isaline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 67 - self.bindescr() - self.state = 68 - self.match(IsaDescriptionParser.T__1) - self.state = 69 - self.asmdescr() - self.state = 70 - self.match(IsaDescriptionParser.NEWLINE) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class EmptylineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NEWLINE(self): - return self.getToken(IsaDescriptionParser.NEWLINE, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_emptyline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterEmptyline" ): - listener.enterEmptyline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitEmptyline" ): - listener.exitEmptyline(self) - - - - - def emptyline(self): - - localctx = IsaDescriptionParser.EmptylineContext(self, self._ctx, self.state) - self.enterRule(localctx, 12, self.RULE_emptyline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 72 - self.match(IsaDescriptionParser.NEWLINE) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class BindescrContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def binelem(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.BinelemContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.BinelemContext,i) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_bindescr - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterBindescr" ): - listener.enterBindescr(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitBindescr" ): - listener.exitBindescr(self) - - - - - def bindescr(self): - - localctx = IsaDescriptionParser.BindescrContext(self, self._ctx, self.state) - self.enterRule(localctx, 14, self.RULE_bindescr) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 75 - self._errHandler.sync(self) - _la = self._input.LA(1) - while True: - self.state = 74 - self.binelem() - self.state = 77 - self._errHandler.sync(self) - _la = self._input.LA(1) - if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.INT) | (1 << IsaDescriptionParser.NAME) | (1 << IsaDescriptionParser.CINLINE))) != 0)): - break - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class BinelemContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def binvalue(self): - return self.getTypedRuleContext(IsaDescriptionParser.BinvalueContext,0) - - - def regbin(self): - return self.getTypedRuleContext(IsaDescriptionParser.RegbinContext,0) - - - def expbin(self): - return self.getTypedRuleContext(IsaDescriptionParser.ExpbinContext,0) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_binelem - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterBinelem" ): - listener.enterBinelem(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitBinelem" ): - listener.exitBinelem(self) - - - - - def binelem(self): - - localctx = IsaDescriptionParser.BinelemContext(self, self._ctx, self.state) - self.enterRule(localctx, 16, self.RULE_binelem) - try: - self.state = 82 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [IsaDescriptionParser.INT]: - self.enterOuterAlt(localctx, 1) - self.state = 79 - self.binvalue() - pass - elif token in [IsaDescriptionParser.NAME]: - self.enterOuterAlt(localctx, 2) - self.state = 80 - self.regbin() - pass - elif token in [IsaDescriptionParser.CINLINE]: - self.enterOuterAlt(localctx, 3) - self.state = 81 - self.expbin() - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class BinvalueContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def INT(self): - return self.getToken(IsaDescriptionParser.INT, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_binvalue - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterBinvalue" ): - listener.enterBinvalue(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitBinvalue" ): - listener.exitBinvalue(self) - - - - - def binvalue(self): - - localctx = IsaDescriptionParser.BinvalueContext(self, self._ctx, self.state) - self.enterRule(localctx, 18, self.RULE_binvalue) - try: - self.enterOuterAlt(localctx, 1) - self.state = 84 - self.match(IsaDescriptionParser.INT) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegbinContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def INT(self, i:int=None): - if i is None: - return self.getTokens(IsaDescriptionParser.INT) - else: - return self.getToken(IsaDescriptionParser.INT, i) - - def SEMICOL(self): - return self.getToken(IsaDescriptionParser.SEMICOL, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_regbin - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegbin" ): - listener.enterRegbin(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegbin" ): - listener.exitRegbin(self) - - - - - def regbin(self): - - localctx = IsaDescriptionParser.RegbinContext(self, self._ctx, self.state) - self.enterRule(localctx, 20, self.RULE_regbin) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 86 - self.match(IsaDescriptionParser.NAME) - self.state = 87 - self.match(IsaDescriptionParser.T__2) - self.state = 88 - self.match(IsaDescriptionParser.INT) - self.state = 91 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==IsaDescriptionParser.SEMICOL: - self.state = 89 - self.match(IsaDescriptionParser.SEMICOL) - self.state = 90 - self.match(IsaDescriptionParser.INT) - - - self.state = 93 - self.match(IsaDescriptionParser.T__3) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ExpbinContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def CINLINE(self): - return self.getToken(IsaDescriptionParser.CINLINE, 0) - - def INT(self, i:int=None): - if i is None: - return self.getTokens(IsaDescriptionParser.INT) - else: - return self.getToken(IsaDescriptionParser.INT, i) - - def SEMICOL(self): - return self.getToken(IsaDescriptionParser.SEMICOL, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_expbin - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterExpbin" ): - listener.enterExpbin(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitExpbin" ): - listener.exitExpbin(self) - - - - - def expbin(self): - - localctx = IsaDescriptionParser.ExpbinContext(self, self._ctx, self.state) - self.enterRule(localctx, 22, self.RULE_expbin) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 95 - self.match(IsaDescriptionParser.CINLINE) - self.state = 96 - self.match(IsaDescriptionParser.T__2) - self.state = 97 - self.match(IsaDescriptionParser.INT) - self.state = 100 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==IsaDescriptionParser.SEMICOL: - self.state = 98 - self.match(IsaDescriptionParser.SEMICOL) - self.state = 99 - self.match(IsaDescriptionParser.INT) - - - self.state = 102 - self.match(IsaDescriptionParser.T__3) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class AsmdescrContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def extname(self): - return self.getTypedRuleContext(IsaDescriptionParser.ExtnameContext,0) - - - def arith(self): - return self.getTypedRuleContext(IsaDescriptionParser.ArithContext,0) - - - def INT(self, i:int=None): - if i is None: - return self.getTokens(IsaDescriptionParser.INT) - else: - return self.getToken(IsaDescriptionParser.INT, i) - - def semname(self): - return self.getTypedRuleContext(IsaDescriptionParser.SemnameContext,0) - - - def opname(self): - return self.getTypedRuleContext(IsaDescriptionParser.OpnameContext,0) - - - def reglist(self): - return self.getTypedRuleContext(IsaDescriptionParser.ReglistContext,0) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_asmdescr - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterAsmdescr" ): - listener.enterAsmdescr(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitAsmdescr" ): - listener.exitAsmdescr(self) - - - - - def asmdescr(self): - - localctx = IsaDescriptionParser.AsmdescrContext(self, self._ctx, self.state) - self.enterRule(localctx, 24, self.RULE_asmdescr) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 104 - self.extname() - self.state = 105 - self.arith() - self.state = 106 - self.match(IsaDescriptionParser.INT) - self.state = 107 - self.match(IsaDescriptionParser.INT) - self.state = 108 - self.semname() - self.state = 109 - self.opname() - self.state = 111 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==IsaDescriptionParser.NAME: - self.state = 110 - self.reglist() - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ExtnameContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_extname - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterExtname" ): - listener.enterExtname(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitExtname" ): - listener.exitExtname(self) - - - - - def extname(self): - - localctx = IsaDescriptionParser.ExtnameContext(self, self._ctx, self.state) - self.enterRule(localctx, 26, self.RULE_extname) - try: - self.enterOuterAlt(localctx, 1) - self.state = 113 - self.match(IsaDescriptionParser.NAME) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ArithContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_arith - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterArith" ): - listener.enterArith(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitArith" ): - listener.exitArith(self) - - - - - def arith(self): - - localctx = IsaDescriptionParser.ArithContext(self, self._ctx, self.state) - self.enterRule(localctx, 28, self.RULE_arith) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 115 - _la = self._input.LA(1) - if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << IsaDescriptionParser.T__4) | (1 << IsaDescriptionParser.T__5) | (1 << IsaDescriptionParser.T__6))) != 0)): - self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class OpnameContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_opname - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterOpname" ): - listener.enterOpname(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitOpname" ): - listener.exitOpname(self) - - - - - def opname(self): - - localctx = IsaDescriptionParser.OpnameContext(self, self._ctx, self.state) - self.enterRule(localctx, 30, self.RULE_opname) - try: - self.enterOuterAlt(localctx, 1) - self.state = 117 - self.match(IsaDescriptionParser.NAME) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegNameContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_regName - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegName" ): - listener.enterRegName(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegName" ): - listener.exitRegName(self) - - - - - def regName(self): - - localctx = IsaDescriptionParser.RegNameContext(self, self._ctx, self.state) - self.enterRule(localctx, 32, self.RULE_regName) - try: - self.enterOuterAlt(localctx, 1) - self.state = 119 - self.match(IsaDescriptionParser.NAME) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class SemnameContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(IsaDescriptionParser.NAME, 0) - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_semname - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterSemname" ): - listener.enterSemname(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitSemname" ): - listener.exitSemname(self) - - - - - def semname(self): - - localctx = IsaDescriptionParser.SemnameContext(self, self._ctx, self.state) - self.enterRule(localctx, 34, self.RULE_semname) - try: - self.enterOuterAlt(localctx, 1) - self.state = 121 - self.match(IsaDescriptionParser.NAME) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ReglistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def regName(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(IsaDescriptionParser.RegNameContext) - else: - return self.getTypedRuleContext(IsaDescriptionParser.RegNameContext,i) - - - def getRuleIndex(self): - return IsaDescriptionParser.RULE_reglist - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterReglist" ): - listener.enterReglist(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitReglist" ): - listener.exitReglist(self) - - - - - def reglist(self): - - localctx = IsaDescriptionParser.ReglistContext(self, self._ctx, self.state) - self.enterRule(localctx, 36, self.RULE_reglist) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 123 - self.regName() - self.state = 127 - self._errHandler.sync(self) - _la = self._input.LA(1) - while _la==IsaDescriptionParser.NAME: - self.state = 124 - self.regName() - self.state = 129 - self._errHandler.sync(self) - _la = self._input.LA(1) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - - - - diff --git a/HybroGen/RegisterDescription.interp b/HybroGen/RegisterDescription.interp deleted file mode 100644 index 63bbb83..0000000 --- a/HybroGen/RegisterDescription.interp +++ /dev/null @@ -1,50 +0,0 @@ -token literal names: -null -'-' -'v' -'i' -'f' -null -null -null -null -null -null -null -null - -token symbolic names: -null -null -null -null -null -WS -COMMENT -INT -FUNCNAME -REGWN -NEWLINE -PREFIX -NAME - -rule names: -registerdescription -headerlines -commentline -emptyline -registerlines -registerline -registerlist -registerprefix -registerfunctionlist -registerfunction -registerfunctionwn -regbankvec -regbank -registerwidth -extension - - -atn: -[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 3, 14, 89, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 4, 14, 9, 14, 4, 15, 9, 15, 4, 16, 9, 16, 3, 2, 3, 2, 3, 2, 3, 3, 3, 3, 6, 3, 38, 10, 3, 13, 3, 14, 3, 39, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 3, 6, 3, 6, 6, 6, 49, 10, 6, 13, 6, 14, 6, 50, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 7, 5, 7, 60, 10, 7, 3, 8, 3, 8, 3, 9, 3, 9, 3, 9, 5, 9, 67, 10, 9, 3, 10, 3, 10, 5, 10, 71, 10, 10, 3, 11, 3, 11, 3, 12, 3, 12, 3, 12, 5, 12, 78, 10, 12, 3, 13, 5, 13, 81, 10, 13, 3, 14, 3, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 16, 2, 2, 17, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 2, 3, 3, 2, 5, 6, 2, 83, 2, 32, 3, 2, 2, 2, 4, 37, 3, 2, 2, 2, 6, 41, 3, 2, 2, 2, 8, 43, 3, 2, 2, 2, 10, 48, 3, 2, 2, 2, 12, 52, 3, 2, 2, 2, 14, 61, 3, 2, 2, 2, 16, 63, 3, 2, 2, 2, 18, 70, 3, 2, 2, 2, 20, 72, 3, 2, 2, 2, 22, 74, 3, 2, 2, 2, 24, 80, 3, 2, 2, 2, 26, 82, 3, 2, 2, 2, 28, 84, 3, 2, 2, 2, 30, 86, 3, 2, 2, 2, 32, 33, 5, 4, 3, 2, 33, 34, 5, 10, 6, 2, 34, 3, 3, 2, 2, 2, 35, 38, 5, 6, 4, 2, 36, 38, 5, 8, 5, 2, 37, 35, 3, 2, 2, 2, 37, 36, 3, 2, 2, 2, 38, 39, 3, 2, 2, 2, 39, 37, 3, 2, 2, 2, 39, 40, 3, 2, 2, 2, 40, 5, 3, 2, 2, 2, 41, 42, 7, 8, 2, 2, 42, 7, 3, 2, 2, 2, 43, 44, 7, 12, 2, 2, 44, 9, 3, 2, 2, 2, 45, 49, 5, 6, 4, 2, 46, 49, 5, 12, 7, 2, 47, 49, 5, 8, 5, 2, 48, 45, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 48, 47, 3, 2, 2, 2, 49, 50, 3, 2, 2, 2, 50, 48, 3, 2, 2, 2, 50, 51, 3, 2, 2, 2, 51, 11, 3, 2, 2, 2, 52, 53, 5, 30, 16, 2, 53, 54, 5, 24, 13, 2, 54, 55, 5, 26, 14, 2, 55, 56, 5, 14, 8, 2, 56, 57, 5, 28, 15, 2, 57, 59, 5, 18, 10, 2, 58, 60, 7, 12, 2, 2, 59, 58, 3, 2, 2, 2, 59, 60, 3, 2, 2, 2, 60, 13, 3, 2, 2, 2, 61, 62, 5, 16, 9, 2, 62, 15, 3, 2, 2, 2, 63, 66, 7, 13, 2, 2, 64, 65, 7, 3, 2, 2, 65, 67, 7, 9, 2, 2, 66, 64, 3, 2, 2, 2, 66, 67, 3, 2, 2, 2, 67, 17, 3, 2, 2, 2, 68, 71, 5, 20, 11, 2, 69, 71, 5, 22, 12, 2, 70, 68, 3, 2, 2, 2, 70, 69, 3, 2, 2, 2, 71, 19, 3, 2, 2, 2, 72, 73, 7, 10, 2, 2, 73, 21, 3, 2, 2, 2, 74, 77, 7, 11, 2, 2, 75, 76, 7, 3, 2, 2, 76, 78, 7, 9, 2, 2, 77, 75, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 23, 3, 2, 2, 2, 79, 81, 7, 4, 2, 2, 80, 79, 3, 2, 2, 2, 80, 81, 3, 2, 2, 2, 81, 25, 3, 2, 2, 2, 82, 83, 9, 2, 2, 2, 83, 27, 3, 2, 2, 2, 84, 85, 7, 9, 2, 2, 85, 29, 3, 2, 2, 2, 86, 87, 7, 14, 2, 2, 87, 31, 3, 2, 2, 2, 11, 37, 39, 48, 50, 59, 66, 70, 77, 80] \ No newline at end of file diff --git a/HybroGen/RegisterDescription.tokens b/HybroGen/RegisterDescription.tokens deleted file mode 100644 index 7db056c..0000000 --- a/HybroGen/RegisterDescription.tokens +++ /dev/null @@ -1,16 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -WS=5 -COMMENT=6 -INT=7 -FUNCNAME=8 -REGWN=9 -NEWLINE=10 -PREFIX=11 -NAME=12 -'-'=1 -'v'=2 -'i'=3 -'f'=4 diff --git a/HybroGen/RegisterDescriptionLexer.interp b/HybroGen/RegisterDescriptionLexer.interp deleted file mode 100644 index 29a9957..0000000 --- a/HybroGen/RegisterDescriptionLexer.interp +++ /dev/null @@ -1,53 +0,0 @@ -token literal names: -null -'-' -'v' -'i' -'f' -null -null -null -null -null -null -null -null - -token symbolic names: -null -null -null -null -null -WS -COMMENT -INT -FUNCNAME -REGWN -NEWLINE -PREFIX -NAME - -rule names: -T__0 -T__1 -T__2 -T__3 -WS -COMMENT -INT -FUNCNAME -REGWN -NEWLINE -PREFIX -NAME - -channel names: -DEFAULT_TOKEN_CHANNEL -HIDDEN - -mode names: -DEFAULT_MODE - -atn: -[3, 24715, 42794, 33075, 47597, 16764, 15335, 30598, 22884, 2, 14, 96, 8, 1, 4, 2, 9, 2, 4, 3, 9, 3, 4, 4, 9, 4, 4, 5, 9, 5, 4, 6, 9, 6, 4, 7, 9, 7, 4, 8, 9, 8, 4, 9, 9, 9, 4, 10, 9, 10, 4, 11, 9, 11, 4, 12, 9, 12, 4, 13, 9, 13, 3, 2, 3, 2, 3, 3, 3, 3, 3, 4, 3, 4, 3, 5, 3, 5, 3, 6, 6, 6, 37, 10, 6, 13, 6, 14, 6, 38, 3, 6, 3, 6, 3, 7, 3, 7, 7, 7, 45, 10, 7, 12, 7, 14, 7, 48, 11, 7, 3, 7, 3, 7, 3, 7, 3, 7, 3, 8, 6, 8, 55, 10, 8, 13, 8, 14, 8, 56, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 3, 9, 5, 9, 71, 10, 9, 3, 10, 3, 10, 3, 10, 3, 11, 5, 11, 77, 10, 11, 3, 11, 3, 11, 3, 12, 3, 12, 7, 12, 83, 10, 12, 12, 12, 14, 12, 86, 11, 12, 3, 12, 3, 12, 3, 13, 3, 13, 7, 13, 92, 10, 13, 12, 13, 14, 13, 95, 11, 13, 3, 46, 2, 14, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 3, 2, 7, 4, 2, 11, 11, 34, 34, 3, 2, 50, 59, 5, 2, 75, 75, 81, 81, 86, 86, 4, 2, 67, 92, 99, 124, 7, 2, 48, 48, 50, 59, 67, 92, 97, 97, 99, 124, 2, 107, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 3, 27, 3, 2, 2, 2, 5, 29, 3, 2, 2, 2, 7, 31, 3, 2, 2, 2, 9, 33, 3, 2, 2, 2, 11, 36, 3, 2, 2, 2, 13, 42, 3, 2, 2, 2, 15, 54, 3, 2, 2, 2, 17, 70, 3, 2, 2, 2, 19, 72, 3, 2, 2, 2, 21, 76, 3, 2, 2, 2, 23, 80, 3, 2, 2, 2, 25, 89, 3, 2, 2, 2, 27, 28, 7, 47, 2, 2, 28, 4, 3, 2, 2, 2, 29, 30, 7, 120, 2, 2, 30, 6, 3, 2, 2, 2, 31, 32, 7, 107, 2, 2, 32, 8, 3, 2, 2, 2, 33, 34, 7, 104, 2, 2, 34, 10, 3, 2, 2, 2, 35, 37, 9, 2, 2, 2, 36, 35, 3, 2, 2, 2, 37, 38, 3, 2, 2, 2, 38, 36, 3, 2, 2, 2, 38, 39, 3, 2, 2, 2, 39, 40, 3, 2, 2, 2, 40, 41, 8, 6, 2, 2, 41, 12, 3, 2, 2, 2, 42, 46, 7, 37, 2, 2, 43, 45, 11, 2, 2, 2, 44, 43, 3, 2, 2, 2, 45, 48, 3, 2, 2, 2, 46, 47, 3, 2, 2, 2, 46, 44, 3, 2, 2, 2, 47, 49, 3, 2, 2, 2, 48, 46, 3, 2, 2, 2, 49, 50, 5, 21, 11, 2, 50, 51, 3, 2, 2, 2, 51, 52, 8, 7, 2, 2, 52, 14, 3, 2, 2, 2, 53, 55, 9, 3, 2, 2, 54, 53, 3, 2, 2, 2, 55, 56, 3, 2, 2, 2, 56, 54, 3, 2, 2, 2, 56, 57, 3, 2, 2, 2, 57, 16, 3, 2, 2, 2, 58, 71, 7, 92, 2, 2, 59, 60, 7, 84, 2, 2, 60, 71, 7, 67, 2, 2, 61, 62, 7, 72, 2, 2, 62, 71, 7, 82, 2, 2, 63, 64, 7, 85, 2, 2, 64, 71, 7, 82, 2, 2, 65, 66, 7, 73, 2, 2, 66, 71, 7, 82, 2, 2, 67, 68, 7, 86, 2, 2, 68, 71, 7, 82, 2, 2, 69, 71, 7, 90, 2, 2, 70, 58, 3, 2, 2, 2, 70, 59, 3, 2, 2, 2, 70, 61, 3, 2, 2, 2, 70, 63, 3, 2, 2, 2, 70, 65, 3, 2, 2, 2, 70, 67, 3, 2, 2, 2, 70, 69, 3, 2, 2, 2, 71, 18, 3, 2, 2, 2, 72, 73, 9, 4, 2, 2, 73, 74, 5, 15, 8, 2, 74, 20, 3, 2, 2, 2, 75, 77, 7, 15, 2, 2, 76, 75, 3, 2, 2, 2, 76, 77, 3, 2, 2, 2, 77, 78, 3, 2, 2, 2, 78, 79, 7, 12, 2, 2, 79, 22, 3, 2, 2, 2, 80, 84, 7, 38, 2, 2, 81, 83, 9, 5, 2, 2, 82, 81, 3, 2, 2, 2, 83, 86, 3, 2, 2, 2, 84, 82, 3, 2, 2, 2, 84, 85, 3, 2, 2, 2, 85, 87, 3, 2, 2, 2, 86, 84, 3, 2, 2, 2, 87, 88, 5, 15, 8, 2, 88, 24, 3, 2, 2, 2, 89, 93, 9, 5, 2, 2, 90, 92, 9, 6, 2, 2, 91, 90, 3, 2, 2, 2, 92, 95, 3, 2, 2, 2, 93, 91, 3, 2, 2, 2, 93, 94, 3, 2, 2, 2, 94, 26, 3, 2, 2, 2, 95, 93, 3, 2, 2, 2, 10, 2, 38, 46, 56, 70, 76, 84, 93, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroGen/RegisterDescriptionLexer.py b/HybroGen/RegisterDescriptionLexer.py deleted file mode 100644 index 7915d78..0000000 --- a/HybroGen/RegisterDescriptionLexer.py +++ /dev/null @@ -1,92 +0,0 @@ -# Generated from RegisterDescription.g4 by ANTLR 4.9.2 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\16") - buf.write("`\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") - buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\3\2") - buf.write("\3\2\3\3\3\3\3\4\3\4\3\5\3\5\3\6\6\6%\n\6\r\6\16\6&\3") - buf.write("\6\3\6\3\7\3\7\7\7-\n\7\f\7\16\7\60\13\7\3\7\3\7\3\7\3") - buf.write("\7\3\b\6\b\67\n\b\r\b\16\b8\3\t\3\t\3\t\3\t\3\t\3\t\3") - buf.write("\t\3\t\3\t\3\t\3\t\3\t\5\tG\n\t\3\n\3\n\3\n\3\13\5\13") - buf.write("M\n\13\3\13\3\13\3\f\3\f\7\fS\n\f\f\f\16\fV\13\f\3\f\3") - buf.write("\f\3\r\3\r\7\r\\\n\r\f\r\16\r_\13\r\3.\2\16\3\3\5\4\7") - buf.write("\5\t\6\13\7\r\b\17\t\21\n\23\13\25\f\27\r\31\16\3\2\7") - buf.write("\4\2\13\13\"\"\3\2\62;\5\2KKQQVV\4\2C\\c|\7\2\60\60\62") - buf.write(";C\\aac|\2k\2\3\3\2\2\2\2\5\3\2\2\2\2\7\3\2\2\2\2\t\3") - buf.write("\2\2\2\2\13\3\2\2\2\2\r\3\2\2\2\2\17\3\2\2\2\2\21\3\2") - buf.write("\2\2\2\23\3\2\2\2\2\25\3\2\2\2\2\27\3\2\2\2\2\31\3\2\2") - buf.write("\2\3\33\3\2\2\2\5\35\3\2\2\2\7\37\3\2\2\2\t!\3\2\2\2\13") - buf.write("$\3\2\2\2\r*\3\2\2\2\17\66\3\2\2\2\21F\3\2\2\2\23H\3\2") - buf.write("\2\2\25L\3\2\2\2\27P\3\2\2\2\31Y\3\2\2\2\33\34\7/\2\2") - buf.write("\34\4\3\2\2\2\35\36\7x\2\2\36\6\3\2\2\2\37 \7k\2\2 \b") - buf.write("\3\2\2\2!\"\7h\2\2\"\n\3\2\2\2#%\t\2\2\2$#\3\2\2\2%&\3") - buf.write("\2\2\2&$\3\2\2\2&\'\3\2\2\2\'(\3\2\2\2()\b\6\2\2)\f\3") - buf.write("\2\2\2*.\7%\2\2+-\13\2\2\2,+\3\2\2\2-\60\3\2\2\2./\3\2") - buf.write("\2\2.,\3\2\2\2/\61\3\2\2\2\60.\3\2\2\2\61\62\5\25\13\2") - buf.write("\62\63\3\2\2\2\63\64\b\7\2\2\64\16\3\2\2\2\65\67\t\3\2") - buf.write("\2\66\65\3\2\2\2\678\3\2\2\28\66\3\2\2\289\3\2\2\29\20") - buf.write("\3\2\2\2:G\7\\\2\2;<\7T\2\2\7H\2\2>G\7R\2\2") - buf.write("?@\7U\2\2@G\7R\2\2AB\7I\2\2BG\7R\2\2CD\7V\2\2DG\7R\2\2") - buf.write("EG\7Z\2\2F:\3\2\2\2F;\3\2\2\2F=\3\2\2\2F?\3\2\2\2FA\3") - buf.write("\2\2\2FC\3\2\2\2FE\3\2\2\2G\22\3\2\2\2HI\t\4\2\2IJ\5\17") - buf.write("\b\2J\24\3\2\2\2KM\7\17\2\2LK\3\2\2\2LM\3\2\2\2MN\3\2") - buf.write("\2\2NO\7\f\2\2O\26\3\2\2\2PT\7&\2\2QS\t\5\2\2RQ\3\2\2") - buf.write("\2SV\3\2\2\2TR\3\2\2\2TU\3\2\2\2UW\3\2\2\2VT\3\2\2\2W") - buf.write("X\5\17\b\2X\30\3\2\2\2Y]\t\5\2\2Z\\\t\6\2\2[Z\3\2\2\2") - buf.write("\\_\3\2\2\2][\3\2\2\2]^\3\2\2\2^\32\3\2\2\2_]\3\2\2\2") - buf.write("\n\2&.8FLT]\3\b\2\2") - return buf.getvalue() - - -class RegisterDescriptionLexer(Lexer): - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - T__0 = 1 - T__1 = 2 - T__2 = 3 - T__3 = 4 - WS = 5 - COMMENT = 6 - INT = 7 - FUNCNAME = 8 - REGWN = 9 - NEWLINE = 10 - PREFIX = 11 - NAME = 12 - - channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] - - modeNames = [ "DEFAULT_MODE" ] - - literalNames = [ "", - "'-'", "'v'", "'i'", "'f'" ] - - symbolicNames = [ "", - "WS", "COMMENT", "INT", "FUNCNAME", "REGWN", "NEWLINE", "PREFIX", - "NAME" ] - - ruleNames = [ "T__0", "T__1", "T__2", "T__3", "WS", "COMMENT", "INT", - "FUNCNAME", "REGWN", "NEWLINE", "PREFIX", "NAME" ] - - grammarFileName = "RegisterDescription.g4" - - def __init__(self, input=None, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) - self._actions = None - self._predicates = None - - diff --git a/HybroGen/RegisterDescriptionLexer.tokens b/HybroGen/RegisterDescriptionLexer.tokens deleted file mode 100644 index 7db056c..0000000 --- a/HybroGen/RegisterDescriptionLexer.tokens +++ /dev/null @@ -1,16 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -WS=5 -COMMENT=6 -INT=7 -FUNCNAME=8 -REGWN=9 -NEWLINE=10 -PREFIX=11 -NAME=12 -'-'=1 -'v'=2 -'i'=3 -'f'=4 diff --git a/HybroGen/RegisterDescriptionListener.py b/HybroGen/RegisterDescriptionListener.py deleted file mode 100644 index dcd9a40..0000000 --- a/HybroGen/RegisterDescriptionListener.py +++ /dev/null @@ -1,147 +0,0 @@ -# Generated from RegisterDescription.g4 by ANTLR 4.9.2 -from antlr4 import * -if __name__ is not None and "." in __name__: - from .RegisterDescriptionParser import RegisterDescriptionParser -else: - from RegisterDescriptionParser import RegisterDescriptionParser - -# This class defines a complete listener for a parse tree produced by RegisterDescriptionParser. -class RegisterDescriptionListener(ParseTreeListener): - - # Enter a parse tree produced by RegisterDescriptionParser#registerdescription. - def enterRegisterdescription(self, ctx:RegisterDescriptionParser.RegisterdescriptionContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerdescription. - def exitRegisterdescription(self, ctx:RegisterDescriptionParser.RegisterdescriptionContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#headerlines. - def enterHeaderlines(self, ctx:RegisterDescriptionParser.HeaderlinesContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#headerlines. - def exitHeaderlines(self, ctx:RegisterDescriptionParser.HeaderlinesContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#commentline. - def enterCommentline(self, ctx:RegisterDescriptionParser.CommentlineContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#commentline. - def exitCommentline(self, ctx:RegisterDescriptionParser.CommentlineContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#emptyline. - def enterEmptyline(self, ctx:RegisterDescriptionParser.EmptylineContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#emptyline. - def exitEmptyline(self, ctx:RegisterDescriptionParser.EmptylineContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerlines. - def enterRegisterlines(self, ctx:RegisterDescriptionParser.RegisterlinesContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerlines. - def exitRegisterlines(self, ctx:RegisterDescriptionParser.RegisterlinesContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerline. - def enterRegisterline(self, ctx:RegisterDescriptionParser.RegisterlineContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerline. - def exitRegisterline(self, ctx:RegisterDescriptionParser.RegisterlineContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerlist. - def enterRegisterlist(self, ctx:RegisterDescriptionParser.RegisterlistContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerlist. - def exitRegisterlist(self, ctx:RegisterDescriptionParser.RegisterlistContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerprefix. - def enterRegisterprefix(self, ctx:RegisterDescriptionParser.RegisterprefixContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerprefix. - def exitRegisterprefix(self, ctx:RegisterDescriptionParser.RegisterprefixContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerfunctionlist. - def enterRegisterfunctionlist(self, ctx:RegisterDescriptionParser.RegisterfunctionlistContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerfunctionlist. - def exitRegisterfunctionlist(self, ctx:RegisterDescriptionParser.RegisterfunctionlistContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerfunction. - def enterRegisterfunction(self, ctx:RegisterDescriptionParser.RegisterfunctionContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerfunction. - def exitRegisterfunction(self, ctx:RegisterDescriptionParser.RegisterfunctionContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerfunctionwn. - def enterRegisterfunctionwn(self, ctx:RegisterDescriptionParser.RegisterfunctionwnContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerfunctionwn. - def exitRegisterfunctionwn(self, ctx:RegisterDescriptionParser.RegisterfunctionwnContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#regbankvec. - def enterRegbankvec(self, ctx:RegisterDescriptionParser.RegbankvecContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#regbankvec. - def exitRegbankvec(self, ctx:RegisterDescriptionParser.RegbankvecContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#regbank. - def enterRegbank(self, ctx:RegisterDescriptionParser.RegbankContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#regbank. - def exitRegbank(self, ctx:RegisterDescriptionParser.RegbankContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#registerwidth. - def enterRegisterwidth(self, ctx:RegisterDescriptionParser.RegisterwidthContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#registerwidth. - def exitRegisterwidth(self, ctx:RegisterDescriptionParser.RegisterwidthContext): - pass - - - # Enter a parse tree produced by RegisterDescriptionParser#extension. - def enterExtension(self, ctx:RegisterDescriptionParser.ExtensionContext): - pass - - # Exit a parse tree produced by RegisterDescriptionParser#extension. - def exitExtension(self, ctx:RegisterDescriptionParser.ExtensionContext): - pass - - - -del RegisterDescriptionParser \ No newline at end of file diff --git a/HybroGen/RegisterDescriptionParser.py b/HybroGen/RegisterDescriptionParser.py deleted file mode 100644 index cde839d..0000000 --- a/HybroGen/RegisterDescriptionParser.py +++ /dev/null @@ -1,891 +0,0 @@ -# Generated from RegisterDescription.g4 by ANTLR 4.9.2 -# encoding: utf-8 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\16") - buf.write("Y\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7\4\b") - buf.write("\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16\t") - buf.write("\16\4\17\t\17\4\20\t\20\3\2\3\2\3\2\3\3\3\3\6\3&\n\3\r") - buf.write("\3\16\3\'\3\4\3\4\3\5\3\5\3\6\3\6\3\6\6\6\61\n\6\r\6\16") - buf.write("\6\62\3\7\3\7\3\7\3\7\3\7\3\7\3\7\5\7<\n\7\3\b\3\b\3\t") - buf.write("\3\t\3\t\5\tC\n\t\3\n\3\n\5\nG\n\n\3\13\3\13\3\f\3\f\3") - buf.write("\f\5\fN\n\f\3\r\5\rQ\n\r\3\16\3\16\3\17\3\17\3\20\3\20") - buf.write("\3\20\2\2\21\2\4\6\b\n\f\16\20\22\24\26\30\32\34\36\2") - buf.write("\3\3\2\5\6\2S\2 \3\2\2\2\4%\3\2\2\2\6)\3\2\2\2\b+\3\2") - buf.write("\2\2\n\60\3\2\2\2\f\64\3\2\2\2\16=\3\2\2\2\20?\3\2\2\2") - buf.write("\22F\3\2\2\2\24H\3\2\2\2\26J\3\2\2\2\30P\3\2\2\2\32R\3") - buf.write("\2\2\2\34T\3\2\2\2\36V\3\2\2\2 !\5\4\3\2!\"\5\n\6\2\"") - buf.write("\3\3\2\2\2#&\5\6\4\2$&\5\b\5\2%#\3\2\2\2%$\3\2\2\2&\'") - buf.write("\3\2\2\2\'%\3\2\2\2\'(\3\2\2\2(\5\3\2\2\2)*\7\b\2\2*\7") - buf.write("\3\2\2\2+,\7\f\2\2,\t\3\2\2\2-\61\5\6\4\2.\61\5\f\7\2") - buf.write("/\61\5\b\5\2\60-\3\2\2\2\60.\3\2\2\2\60/\3\2\2\2\61\62") - buf.write("\3\2\2\2\62\60\3\2\2\2\62\63\3\2\2\2\63\13\3\2\2\2\64") - buf.write("\65\5\36\20\2\65\66\5\30\r\2\66\67\5\32\16\2\678\5\16") - buf.write("\b\289\5\34\17\29;\5\22\n\2:<\7\f\2\2;:\3\2\2\2;<\3\2") - buf.write("\2\2<\r\3\2\2\2=>\5\20\t\2>\17\3\2\2\2?B\7\r\2\2@A\7\3") - buf.write("\2\2AC\7\t\2\2B@\3\2\2\2BC\3\2\2\2C\21\3\2\2\2DG\5\24") - buf.write("\13\2EG\5\26\f\2FD\3\2\2\2FE\3\2\2\2G\23\3\2\2\2HI\7\n") - buf.write("\2\2I\25\3\2\2\2JM\7\13\2\2KL\7\3\2\2LN\7\t\2\2MK\3\2") - buf.write("\2\2MN\3\2\2\2N\27\3\2\2\2OQ\7\4\2\2PO\3\2\2\2PQ\3\2\2") - buf.write("\2Q\31\3\2\2\2RS\t\2\2\2S\33\3\2\2\2TU\7\t\2\2U\35\3\2") - buf.write("\2\2VW\7\16\2\2W\37\3\2\2\2\13%\'\60\62;BFMP") - return buf.getvalue() - - -class RegisterDescriptionParser ( Parser ): - - grammarFileName = "RegisterDescription.g4" - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - sharedContextCache = PredictionContextCache() - - literalNames = [ "", "'-'", "'v'", "'i'", "'f'" ] - - symbolicNames = [ "", "", "", "", - "", "WS", "COMMENT", "INT", "FUNCNAME", "REGWN", - "NEWLINE", "PREFIX", "NAME" ] - - RULE_registerdescription = 0 - RULE_headerlines = 1 - RULE_commentline = 2 - RULE_emptyline = 3 - RULE_registerlines = 4 - RULE_registerline = 5 - RULE_registerlist = 6 - RULE_registerprefix = 7 - RULE_registerfunctionlist = 8 - RULE_registerfunction = 9 - RULE_registerfunctionwn = 10 - RULE_regbankvec = 11 - RULE_regbank = 12 - RULE_registerwidth = 13 - RULE_extension = 14 - - ruleNames = [ "registerdescription", "headerlines", "commentline", - "emptyline", "registerlines", "registerline", "registerlist", - "registerprefix", "registerfunctionlist", "registerfunction", - "registerfunctionwn", "regbankvec", "regbank", "registerwidth", - "extension" ] - - EOF = Token.EOF - T__0=1 - T__1=2 - T__2=3 - T__3=4 - WS=5 - COMMENT=6 - INT=7 - FUNCNAME=8 - REGWN=9 - NEWLINE=10 - PREFIX=11 - NAME=12 - - def __init__(self, input:TokenStream, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) - self._predicates = None - - - - class RegisterdescriptionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def headerlines(self): - return self.getTypedRuleContext(RegisterDescriptionParser.HeaderlinesContext,0) - - - def registerlines(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlinesContext,0) - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerdescription - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterdescription" ): - listener.enterRegisterdescription(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterdescription" ): - listener.exitRegisterdescription(self) - - - - - def registerdescription(self): - - localctx = RegisterDescriptionParser.RegisterdescriptionContext(self, self._ctx, self.state) - self.enterRule(localctx, 0, self.RULE_registerdescription) - try: - self.enterOuterAlt(localctx, 1) - self.state = 30 - self.headerlines() - self.state = 31 - self.registerlines() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class HeaderlinesContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def commentline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(RegisterDescriptionParser.CommentlineContext) - else: - return self.getTypedRuleContext(RegisterDescriptionParser.CommentlineContext,i) - - - def emptyline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(RegisterDescriptionParser.EmptylineContext) - else: - return self.getTypedRuleContext(RegisterDescriptionParser.EmptylineContext,i) - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_headerlines - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterHeaderlines" ): - listener.enterHeaderlines(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitHeaderlines" ): - listener.exitHeaderlines(self) - - - - - def headerlines(self): - - localctx = RegisterDescriptionParser.HeaderlinesContext(self, self._ctx, self.state) - self.enterRule(localctx, 2, self.RULE_headerlines) - try: - self.enterOuterAlt(localctx, 1) - self.state = 35 - self._errHandler.sync(self) - _alt = 1 - while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: - if _alt == 1: - self.state = 35 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [RegisterDescriptionParser.COMMENT]: - self.state = 33 - self.commentline() - pass - elif token in [RegisterDescriptionParser.NEWLINE]: - self.state = 34 - self.emptyline() - pass - else: - raise NoViableAltException(self) - - - else: - raise NoViableAltException(self) - self.state = 37 - self._errHandler.sync(self) - _alt = self._interp.adaptivePredict(self._input,1,self._ctx) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class CommentlineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def COMMENT(self): - return self.getToken(RegisterDescriptionParser.COMMENT, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_commentline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterCommentline" ): - listener.enterCommentline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitCommentline" ): - listener.exitCommentline(self) - - - - - def commentline(self): - - localctx = RegisterDescriptionParser.CommentlineContext(self, self._ctx, self.state) - self.enterRule(localctx, 4, self.RULE_commentline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 39 - self.match(RegisterDescriptionParser.COMMENT) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class EmptylineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NEWLINE(self): - return self.getToken(RegisterDescriptionParser.NEWLINE, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_emptyline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterEmptyline" ): - listener.enterEmptyline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitEmptyline" ): - listener.exitEmptyline(self) - - - - - def emptyline(self): - - localctx = RegisterDescriptionParser.EmptylineContext(self, self._ctx, self.state) - self.enterRule(localctx, 6, self.RULE_emptyline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 41 - self.match(RegisterDescriptionParser.NEWLINE) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterlinesContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def commentline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(RegisterDescriptionParser.CommentlineContext) - else: - return self.getTypedRuleContext(RegisterDescriptionParser.CommentlineContext,i) - - - def registerline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(RegisterDescriptionParser.RegisterlineContext) - else: - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlineContext,i) - - - def emptyline(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(RegisterDescriptionParser.EmptylineContext) - else: - return self.getTypedRuleContext(RegisterDescriptionParser.EmptylineContext,i) - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerlines - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterlines" ): - listener.enterRegisterlines(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterlines" ): - listener.exitRegisterlines(self) - - - - - def registerlines(self): - - localctx = RegisterDescriptionParser.RegisterlinesContext(self, self._ctx, self.state) - self.enterRule(localctx, 8, self.RULE_registerlines) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 46 - self._errHandler.sync(self) - _la = self._input.LA(1) - while True: - self.state = 46 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [RegisterDescriptionParser.COMMENT]: - self.state = 43 - self.commentline() - pass - elif token in [RegisterDescriptionParser.NAME]: - self.state = 44 - self.registerline() - pass - elif token in [RegisterDescriptionParser.NEWLINE]: - self.state = 45 - self.emptyline() - pass - else: - raise NoViableAltException(self) - - self.state = 48 - self._errHandler.sync(self) - _la = self._input.LA(1) - if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << RegisterDescriptionParser.COMMENT) | (1 << RegisterDescriptionParser.NEWLINE) | (1 << RegisterDescriptionParser.NAME))) != 0)): - break - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterlineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def extension(self): - return self.getTypedRuleContext(RegisterDescriptionParser.ExtensionContext,0) - - - def regbankvec(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegbankvecContext,0) - - - def regbank(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegbankContext,0) - - - def registerlist(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterlistContext,0) - - - def registerwidth(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterwidthContext,0) - - - def registerfunctionlist(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionlistContext,0) - - - def NEWLINE(self): - return self.getToken(RegisterDescriptionParser.NEWLINE, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerline - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterline" ): - listener.enterRegisterline(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterline" ): - listener.exitRegisterline(self) - - - - - def registerline(self): - - localctx = RegisterDescriptionParser.RegisterlineContext(self, self._ctx, self.state) - self.enterRule(localctx, 10, self.RULE_registerline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 50 - self.extension() - self.state = 51 - self.regbankvec() - self.state = 52 - self.regbank() - self.state = 53 - self.registerlist() - self.state = 54 - self.registerwidth() - self.state = 55 - self.registerfunctionlist() - self.state = 57 - self._errHandler.sync(self) - la_ = self._interp.adaptivePredict(self._input,4,self._ctx) - if la_ == 1: - self.state = 56 - self.match(RegisterDescriptionParser.NEWLINE) - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterlistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def registerprefix(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterprefixContext,0) - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerlist - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterlist" ): - listener.enterRegisterlist(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterlist" ): - listener.exitRegisterlist(self) - - - - - def registerlist(self): - - localctx = RegisterDescriptionParser.RegisterlistContext(self, self._ctx, self.state) - self.enterRule(localctx, 12, self.RULE_registerlist) - try: - self.enterOuterAlt(localctx, 1) - self.state = 59 - self.registerprefix() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterprefixContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def PREFIX(self): - return self.getToken(RegisterDescriptionParser.PREFIX, 0) - - def INT(self): - return self.getToken(RegisterDescriptionParser.INT, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerprefix - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterprefix" ): - listener.enterRegisterprefix(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterprefix" ): - listener.exitRegisterprefix(self) - - - - - def registerprefix(self): - - localctx = RegisterDescriptionParser.RegisterprefixContext(self, self._ctx, self.state) - self.enterRule(localctx, 14, self.RULE_registerprefix) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 61 - self.match(RegisterDescriptionParser.PREFIX) - self.state = 64 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==RegisterDescriptionParser.T__0: - self.state = 62 - self.match(RegisterDescriptionParser.T__0) - self.state = 63 - self.match(RegisterDescriptionParser.INT) - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterfunctionlistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def registerfunction(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionContext,0) - - - def registerfunctionwn(self): - return self.getTypedRuleContext(RegisterDescriptionParser.RegisterfunctionwnContext,0) - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerfunctionlist - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterfunctionlist" ): - listener.enterRegisterfunctionlist(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterfunctionlist" ): - listener.exitRegisterfunctionlist(self) - - - - - def registerfunctionlist(self): - - localctx = RegisterDescriptionParser.RegisterfunctionlistContext(self, self._ctx, self.state) - self.enterRule(localctx, 16, self.RULE_registerfunctionlist) - try: - self.state = 68 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [RegisterDescriptionParser.FUNCNAME]: - self.enterOuterAlt(localctx, 1) - self.state = 66 - self.registerfunction() - pass - elif token in [RegisterDescriptionParser.REGWN]: - self.enterOuterAlt(localctx, 2) - self.state = 67 - self.registerfunctionwn() - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterfunctionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def FUNCNAME(self): - return self.getToken(RegisterDescriptionParser.FUNCNAME, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerfunction - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterfunction" ): - listener.enterRegisterfunction(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterfunction" ): - listener.exitRegisterfunction(self) - - - - - def registerfunction(self): - - localctx = RegisterDescriptionParser.RegisterfunctionContext(self, self._ctx, self.state) - self.enterRule(localctx, 18, self.RULE_registerfunction) - try: - self.enterOuterAlt(localctx, 1) - self.state = 70 - self.match(RegisterDescriptionParser.FUNCNAME) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterfunctionwnContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def REGWN(self): - return self.getToken(RegisterDescriptionParser.REGWN, 0) - - def INT(self): - return self.getToken(RegisterDescriptionParser.INT, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerfunctionwn - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterfunctionwn" ): - listener.enterRegisterfunctionwn(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterfunctionwn" ): - listener.exitRegisterfunctionwn(self) - - - - - def registerfunctionwn(self): - - localctx = RegisterDescriptionParser.RegisterfunctionwnContext(self, self._ctx, self.state) - self.enterRule(localctx, 20, self.RULE_registerfunctionwn) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 72 - self.match(RegisterDescriptionParser.REGWN) - self.state = 75 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==RegisterDescriptionParser.T__0: - self.state = 73 - self.match(RegisterDescriptionParser.T__0) - self.state = 74 - self.match(RegisterDescriptionParser.INT) - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegbankvecContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_regbankvec - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegbankvec" ): - listener.enterRegbankvec(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegbankvec" ): - listener.exitRegbankvec(self) - - - - - def regbankvec(self): - - localctx = RegisterDescriptionParser.RegbankvecContext(self, self._ctx, self.state) - self.enterRule(localctx, 22, self.RULE_regbankvec) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 78 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==RegisterDescriptionParser.T__1: - self.state = 77 - self.match(RegisterDescriptionParser.T__1) - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegbankContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_regbank - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegbank" ): - listener.enterRegbank(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegbank" ): - listener.exitRegbank(self) - - - - - def regbank(self): - - localctx = RegisterDescriptionParser.RegbankContext(self, self._ctx, self.state) - self.enterRule(localctx, 24, self.RULE_regbank) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 80 - _la = self._input.LA(1) - if not(_la==RegisterDescriptionParser.T__2 or _la==RegisterDescriptionParser.T__3): - self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class RegisterwidthContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def INT(self): - return self.getToken(RegisterDescriptionParser.INT, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_registerwidth - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterRegisterwidth" ): - listener.enterRegisterwidth(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitRegisterwidth" ): - listener.exitRegisterwidth(self) - - - - - def registerwidth(self): - - localctx = RegisterDescriptionParser.RegisterwidthContext(self, self._ctx, self.state) - self.enterRule(localctx, 26, self.RULE_registerwidth) - try: - self.enterOuterAlt(localctx, 1) - self.state = 82 - self.match(RegisterDescriptionParser.INT) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ExtensionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def NAME(self): - return self.getToken(RegisterDescriptionParser.NAME, 0) - - def getRuleIndex(self): - return RegisterDescriptionParser.RULE_extension - - def enterRule(self, listener:ParseTreeListener): - if hasattr( listener, "enterExtension" ): - listener.enterExtension(self) - - def exitRule(self, listener:ParseTreeListener): - if hasattr( listener, "exitExtension" ): - listener.exitExtension(self) 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9, 3, 9, 3, 9, 3, 10, 3, 10, 3, 10, 3, 10, 3, 10, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 11, 3, 12, 3, 12, 3, 13, 3, 13, 3, 14, 3, 14, 3, 15, 3, 15, 3, 16, 3, 16, 3, 17, 3, 17, 3, 18, 3, 18, 3, 19, 3, 19, 3, 19, 3, 20, 3, 20, 3, 20, 3, 21, 3, 21, 3, 22, 3, 22, 3, 23, 3, 23, 3, 24, 3, 24, 3, 24, 3, 24, 3, 25, 3, 25, 3, 25, 3, 25, 3, 25, 3, 26, 3, 26, 3, 26, 3, 26, 3, 26, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 27, 3, 28, 3, 28, 3, 28, 3, 28, 3, 29, 3, 29, 3, 29, 3, 29, 3, 30, 3, 30, 3, 30, 3, 30, 3, 31, 3, 31, 3, 31, 3, 31, 3, 31, 3, 32, 3, 32, 3, 32, 3, 32, 3, 32, 3, 33, 3, 33, 3, 33, 3, 34, 3, 34, 3, 34, 3, 35, 3, 35, 3, 35, 3, 36, 3, 36, 3, 37, 3, 37, 3, 38, 3, 38, 3, 38, 3, 39, 3, 39, 3, 39, 3, 40, 3, 40, 5, 40, 230, 10, 40, 3, 40, 5, 40, 233, 10, 40, 3, 41, 3, 41, 5, 41, 237, 10, 41, 3, 41, 3, 41, 3, 41, 5, 41, 242, 10, 41, 3, 41, 5, 41, 245, 10, 41, 3, 42, 3, 42, 3, 43, 5, 43, 250, 10, 43, 3, 43, 3, 43, 3, 43, 3, 43, 3, 43, 5, 43, 257, 10, 43, 3, 44, 3, 44, 3, 45, 3, 45, 7, 45, 263, 10, 45, 12, 45, 14, 45, 266, 11, 45, 3, 46, 6, 46, 269, 10, 46, 13, 46, 14, 46, 270, 3, 47, 3, 47, 3, 48, 3, 48, 3, 49, 3, 49, 3, 50, 3, 50, 7, 50, 281, 10, 50, 12, 50, 14, 50, 284, 11, 50, 3, 51, 3, 51, 3, 51, 3, 51, 6, 51, 290, 10, 51, 13, 51, 14, 51, 291, 3, 51, 3, 51, 3, 52, 6, 52, 297, 10, 52, 13, 52, 14, 52, 298, 3, 52, 3, 52, 3, 53, 3, 53, 3, 53, 3, 53, 7, 53, 307, 10, 53, 12, 53, 14, 53, 310, 11, 53, 3, 53, 3, 53, 3, 53, 3, 53, 3, 54, 5, 54, 317, 10, 54, 3, 54, 3, 54, 3, 54, 3, 54, 3, 308, 2, 55, 3, 3, 5, 4, 7, 5, 9, 6, 11, 7, 13, 8, 15, 9, 17, 10, 19, 11, 21, 12, 23, 13, 25, 14, 27, 15, 29, 16, 31, 17, 33, 18, 35, 19, 37, 20, 39, 21, 41, 22, 43, 23, 45, 24, 47, 25, 49, 26, 51, 27, 53, 28, 55, 29, 57, 30, 59, 31, 61, 32, 63, 33, 65, 34, 67, 35, 69, 36, 71, 37, 73, 38, 75, 39, 77, 40, 79, 41, 81, 2, 83, 2, 85, 2, 87, 42, 89, 43, 91, 2, 93, 2, 95, 2, 97, 2, 99, 44, 101, 45, 103, 46, 105, 47, 107, 48, 3, 2, 10, 6, 2, 72, 72, 78, 78, 104, 104, 110, 110, 3, 2, 50, 59, 3, 2, 51, 59, 4, 2, 45, 45, 47, 47, 4, 2, 67, 92, 99, 124, 6, 2, 50, 59, 67, 92, 97, 97, 99, 124, 3, 2, 43, 43, 4, 2, 11, 11, 34, 34, 2, 328, 2, 3, 3, 2, 2, 2, 2, 5, 3, 2, 2, 2, 2, 7, 3, 2, 2, 2, 2, 9, 3, 2, 2, 2, 2, 11, 3, 2, 2, 2, 2, 13, 3, 2, 2, 2, 2, 15, 3, 2, 2, 2, 2, 17, 3, 2, 2, 2, 2, 19, 3, 2, 2, 2, 2, 21, 3, 2, 2, 2, 2, 23, 3, 2, 2, 2, 2, 25, 3, 2, 2, 2, 2, 27, 3, 2, 2, 2, 2, 29, 3, 2, 2, 2, 2, 31, 3, 2, 2, 2, 2, 33, 3, 2, 2, 2, 2, 35, 3, 2, 2, 2, 2, 37, 3, 2, 2, 2, 2, 39, 3, 2, 2, 2, 2, 41, 3, 2, 2, 2, 2, 43, 3, 2, 2, 2, 2, 45, 3, 2, 2, 2, 2, 47, 3, 2, 2, 2, 2, 49, 3, 2, 2, 2, 2, 51, 3, 2, 2, 2, 2, 53, 3, 2, 2, 2, 2, 55, 3, 2, 2, 2, 2, 57, 3, 2, 2, 2, 2, 59, 3, 2, 2, 2, 2, 61, 3, 2, 2, 2, 2, 63, 3, 2, 2, 2, 2, 65, 3, 2, 2, 2, 2, 67, 3, 2, 2, 2, 2, 69, 3, 2, 2, 2, 2, 71, 3, 2, 2, 2, 2, 73, 3, 2, 2, 2, 2, 75, 3, 2, 2, 2, 2, 77, 3, 2, 2, 2, 2, 79, 3, 2, 2, 2, 2, 87, 3, 2, 2, 2, 2, 89, 3, 2, 2, 2, 2, 99, 3, 2, 2, 2, 2, 101, 3, 2, 2, 2, 2, 103, 3, 2, 2, 2, 2, 105, 3, 2, 2, 2, 2, 107, 3, 2, 2, 2, 3, 109, 3, 2, 2, 2, 5, 111, 3, 2, 2, 2, 7, 113, 3, 2, 2, 2, 9, 115, 3, 2, 2, 2, 11, 117, 3, 2, 2, 2, 13, 119, 3, 2, 2, 2, 15, 121, 3, 2, 2, 2, 17, 125, 3, 2, 2, 2, 19, 128, 3, 2, 2, 2, 21, 133, 3, 2, 2, 2, 23, 140, 3, 2, 2, 2, 25, 142, 3, 2, 2, 2, 27, 144, 3, 2, 2, 2, 29, 146, 3, 2, 2, 2, 31, 148, 3, 2, 2, 2, 33, 150, 3, 2, 2, 2, 35, 152, 3, 2, 2, 2, 37, 154, 3, 2, 2, 2, 39, 157, 3, 2, 2, 2, 41, 160, 3, 2, 2, 2, 43, 162, 3, 2, 2, 2, 45, 164, 3, 2, 2, 2, 47, 166, 3, 2, 2, 2, 49, 170, 3, 2, 2, 2, 51, 175, 3, 2, 2, 2, 53, 180, 3, 2, 2, 2, 55, 186, 3, 2, 2, 2, 57, 190, 3, 2, 2, 2, 59, 194, 3, 2, 2, 2, 61, 198, 3, 2, 2, 2, 63, 203, 3, 2, 2, 2, 65, 208, 3, 2, 2, 2, 67, 211, 3, 2, 2, 2, 69, 214, 3, 2, 2, 2, 71, 217, 3, 2, 2, 2, 73, 219, 3, 2, 2, 2, 75, 221, 3, 2, 2, 2, 77, 224, 3, 2, 2, 2, 79, 227, 3, 2, 2, 2, 81, 244, 3, 2, 2, 2, 83, 246, 3, 2, 2, 2, 85, 256, 3, 2, 2, 2, 87, 258, 3, 2, 2, 2, 89, 260, 3, 2, 2, 2, 91, 268, 3, 2, 2, 2, 93, 272, 3, 2, 2, 2, 95, 274, 3, 2, 2, 2, 97, 276, 3, 2, 2, 2, 99, 278, 3, 2, 2, 2, 101, 285, 3, 2, 2, 2, 103, 296, 3, 2, 2, 2, 105, 302, 3, 2, 2, 2, 107, 316, 3, 2, 2, 2, 109, 110, 7, 42, 2, 2, 110, 4, 3, 2, 2, 2, 111, 112, 7, 43, 2, 2, 112, 6, 3, 2, 2, 2, 113, 114, 7, 125, 2, 2, 114, 8, 3, 2, 2, 2, 115, 116, 7, 127, 2, 2, 116, 10, 3, 2, 2, 2, 117, 118, 7, 46, 2, 2, 118, 12, 3, 2, 2, 2, 119, 120, 7, 61, 2, 2, 120, 14, 3, 2, 2, 2, 121, 122, 7, 104, 2, 2, 122, 123, 7, 113, 2, 2, 123, 124, 7, 116, 2, 2, 124, 16, 3, 2, 2, 2, 125, 126, 7, 107, 2, 2, 126, 127, 7, 104, 2, 2, 127, 18, 3, 2, 2, 2, 128, 129, 7, 103, 2, 2, 129, 130, 7, 110, 2, 2, 130, 131, 7, 117, 2, 2, 131, 132, 7, 103, 2, 2, 132, 20, 3, 2, 2, 2, 133, 134, 7, 116, 2, 2, 134, 135, 7, 103, 2, 2, 135, 136, 7, 118, 2, 2, 136, 137, 7, 119, 2, 2, 137, 138, 7, 116, 2, 2, 138, 139, 7, 112, 2, 2, 139, 22, 3, 2, 2, 2, 140, 141, 7, 63, 2, 2, 141, 24, 3, 2, 2, 2, 142, 143, 7, 93, 2, 2, 143, 26, 3, 2, 2, 2, 144, 145, 7, 95, 2, 2, 145, 28, 3, 2, 2, 2, 146, 147, 7, 44, 2, 2, 147, 30, 3, 2, 2, 2, 148, 149, 7, 49, 2, 2, 149, 32, 3, 2, 2, 2, 150, 151, 7, 45, 2, 2, 151, 34, 3, 2, 2, 2, 152, 153, 7, 47, 2, 2, 153, 36, 3, 2, 2, 2, 154, 155, 7, 62, 2, 2, 155, 156, 7, 62, 2, 2, 156, 38, 3, 2, 2, 2, 157, 158, 7, 64, 2, 2, 158, 159, 7, 64, 2, 2, 159, 40, 3, 2, 2, 2, 160, 161, 7, 40, 2, 2, 161, 42, 3, 2, 2, 2, 162, 163, 7, 126, 2, 2, 163, 44, 3, 2, 2, 2, 164, 165, 7, 96, 2, 2, 165, 46, 3, 2, 2, 2, 166, 167, 7, 107, 2, 2, 167, 168, 7, 112, 2, 2, 168, 169, 7, 118, 2, 2, 169, 48, 3, 2, 2, 2, 170, 171, 7, 119, 2, 2, 171, 172, 7, 107, 2, 2, 172, 173, 7, 112, 2, 2, 173, 174, 7, 118, 2, 2, 174, 50, 3, 2, 2, 2, 175, 176, 7, 117, 2, 2, 176, 177, 7, 107, 2, 2, 177, 178, 7, 112, 2, 2, 178, 179, 7, 118, 2, 2, 179, 52, 3, 2, 2, 2, 180, 181, 7, 117, 2, 2, 181, 182, 7, 119, 2, 2, 182, 183, 7, 107, 2, 2, 183, 184, 7, 112, 2, 2, 184, 185, 7, 118, 2, 2, 185, 54, 3, 2, 2, 2, 186, 187, 7, 104, 2, 2, 187, 188, 7, 110, 2, 2, 188, 189, 7, 118, 2, 2, 189, 56, 3, 2, 2, 2, 190, 191, 7, 101, 2, 2, 191, 192, 7, 114, 2, 2, 192, 193, 7, 110, 2, 2, 193, 58, 3, 2, 2, 2, 194, 195, 7, 114, 2, 2, 195, 196, 7, 107, 2, 2, 196, 197, 7, 122, 2, 2, 197, 60, 3, 2, 2, 2, 198, 199, 7, 107, 2, 2, 199, 200, 7, 114, 2, 2, 200, 201, 7, 120, 2, 2, 201, 202, 7, 54, 2, 2, 202, 62, 3, 2, 2, 2, 203, 204, 7, 107, 2, 2, 204, 205, 7, 114, 2, 2, 205, 206, 7, 120, 2, 2, 206, 207, 7, 56, 2, 2, 207, 64, 3, 2, 2, 2, 208, 209, 7, 93, 2, 2, 209, 210, 7, 95, 2, 2, 210, 66, 3, 2, 2, 2, 211, 212, 7, 63, 2, 2, 212, 213, 7, 63, 2, 2, 213, 68, 3, 2, 2, 2, 214, 215, 7, 35, 2, 2, 215, 216, 7, 63, 2, 2, 216, 70, 3, 2, 2, 2, 217, 218, 7, 62, 2, 2, 218, 72, 3, 2, 2, 2, 219, 220, 7, 64, 2, 2, 220, 74, 3, 2, 2, 2, 221, 222, 7, 62, 2, 2, 222, 223, 7, 63, 2, 2, 223, 76, 3, 2, 2, 2, 224, 225, 7, 64, 2, 2, 225, 226, 7, 63, 2, 2, 226, 78, 3, 2, 2, 2, 227, 229, 5, 85, 43, 2, 228, 230, 5, 81, 41, 2, 229, 228, 3, 2, 2, 2, 229, 230, 3, 2, 2, 2, 230, 232, 3, 2, 2, 2, 231, 233, 5, 83, 42, 2, 232, 231, 3, 2, 2, 2, 232, 233, 3, 2, 2, 2, 233, 80, 3, 2, 2, 2, 234, 236, 7, 103, 2, 2, 235, 237, 5, 97, 49, 2, 236, 235, 3, 2, 2, 2, 236, 237, 3, 2, 2, 2, 237, 238, 3, 2, 2, 2, 238, 245, 5, 91, 46, 2, 239, 241, 7, 71, 2, 2, 240, 242, 5, 97, 49, 2, 241, 240, 3, 2, 2, 2, 241, 242, 3, 2, 2, 2, 242, 243, 3, 2, 2, 2, 243, 245, 5, 91, 46, 2, 244, 234, 3, 2, 2, 2, 244, 239, 3, 2, 2, 2, 245, 82, 3, 2, 2, 2, 246, 247, 9, 2, 2, 2, 247, 84, 3, 2, 2, 2, 248, 250, 5, 91, 46, 2, 249, 248, 3, 2, 2, 2, 249, 250, 3, 2, 2, 2, 250, 251, 3, 2, 2, 2, 251, 252, 7, 48, 2, 2, 252, 257, 5, 91, 46, 2, 253, 254, 5, 91, 46, 2, 254, 255, 7, 48, 2, 2, 255, 257, 3, 2, 2, 2, 256, 249, 3, 2, 2, 2, 256, 253, 3, 2, 2, 2, 257, 86, 3, 2, 2, 2, 258, 259, 5, 91, 46, 2, 259, 88, 3, 2, 2, 2, 260, 264, 5, 95, 48, 2, 261, 263, 5, 93, 47, 2, 262, 261, 3, 2, 2, 2, 263, 266, 3, 2, 2, 2, 264, 262, 3, 2, 2, 2, 264, 265, 3, 2, 2, 2, 265, 90, 3, 2, 2, 2, 266, 264, 3, 2, 2, 2, 267, 269, 5, 93, 47, 2, 268, 267, 3, 2, 2, 2, 269, 270, 3, 2, 2, 2, 270, 268, 3, 2, 2, 2, 270, 271, 3, 2, 2, 2, 271, 92, 3, 2, 2, 2, 272, 273, 9, 3, 2, 2, 273, 94, 3, 2, 2, 2, 274, 275, 9, 4, 2, 2, 275, 96, 3, 2, 2, 2, 276, 277, 9, 5, 2, 2, 277, 98, 3, 2, 2, 2, 278, 282, 9, 6, 2, 2, 279, 281, 9, 7, 2, 2, 280, 279, 3, 2, 2, 2, 281, 284, 3, 2, 2, 2, 282, 280, 3, 2, 2, 2, 282, 283, 3, 2, 2, 2, 283, 100, 3, 2, 2, 2, 284, 282, 3, 2, 2, 2, 285, 286, 7, 37, 2, 2, 286, 287, 7, 42, 2, 2, 287, 289, 3, 2, 2, 2, 288, 290, 10, 8, 2, 2, 289, 288, 3, 2, 2, 2, 290, 291, 3, 2, 2, 2, 291, 289, 3, 2, 2, 2, 291, 292, 3, 2, 2, 2, 292, 293, 3, 2, 2, 2, 293, 294, 7, 43, 2, 2, 294, 102, 3, 2, 2, 2, 295, 297, 9, 9, 2, 2, 296, 295, 3, 2, 2, 2, 297, 298, 3, 2, 2, 2, 298, 296, 3, 2, 2, 2, 298, 299, 3, 2, 2, 2, 299, 300, 3, 2, 2, 2, 300, 301, 8, 52, 2, 2, 301, 104, 3, 2, 2, 2, 302, 303, 7, 49, 2, 2, 303, 304, 7, 49, 2, 2, 304, 308, 3, 2, 2, 2, 305, 307, 11, 2, 2, 2, 306, 305, 3, 2, 2, 2, 307, 310, 3, 2, 2, 2, 308, 309, 3, 2, 2, 2, 308, 306, 3, 2, 2, 2, 309, 311, 3, 2, 2, 2, 310, 308, 3, 2, 2, 2, 311, 312, 5, 107, 54, 2, 312, 313, 3, 2, 2, 2, 313, 314, 8, 53, 2, 2, 314, 106, 3, 2, 2, 2, 315, 317, 7, 15, 2, 2, 316, 315, 3, 2, 2, 2, 316, 317, 3, 2, 2, 2, 317, 318, 3, 2, 2, 2, 318, 319, 7, 12, 2, 2, 319, 320, 3, 2, 2, 2, 320, 321, 8, 54, 2, 2, 321, 108, 3, 2, 2, 2, 17, 2, 229, 232, 236, 241, 244, 249, 256, 264, 270, 282, 291, 298, 308, 316, 3, 8, 2, 2] \ No newline at end of file diff --git a/HybroLang/HybroLangLexer.py b/HybroLang/HybroLangLexer.py deleted file mode 100644 index e628c3e..0000000 --- a/HybroLang/HybroLangLexer.py +++ /dev/null @@ -1,240 +0,0 @@ -# Generated from HybroLang.g4 by ANTLR 4.9.2 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\2\60") - buf.write("\u0142\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7") - 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buf.write("\3\2\2\2\u0134\u0135\3\2\2\2\u0134\u0132\3\2\2\2\u0135") - buf.write("\u0137\3\2\2\2\u0136\u0134\3\2\2\2\u0137\u0138\5k\66\2") - buf.write("\u0138\u0139\3\2\2\2\u0139\u013a\b\65\2\2\u013aj\3\2\2") - buf.write("\2\u013b\u013d\7\17\2\2\u013c\u013b\3\2\2\2\u013c\u013d") - buf.write("\3\2\2\2\u013d\u013e\3\2\2\2\u013e\u013f\7\f\2\2\u013f") - buf.write("\u0140\3\2\2\2\u0140\u0141\b\66\2\2\u0141l\3\2\2\2\21") - buf.write("\2\u00e5\u00e8\u00ec\u00f1\u00f4\u00f9\u0100\u0108\u010e") - buf.write("\u011a\u0123\u012a\u0134\u013c\3\b\2\2") - return buf.getvalue() - - -class HybroLangLexer(Lexer): - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - T__0 = 1 - T__1 = 2 - T__2 = 3 - T__3 = 4 - T__4 = 5 - T__5 = 6 - T__6 = 7 - T__7 = 8 - T__8 = 9 - T__9 = 10 - T__10 = 11 - T__11 = 12 - T__12 = 13 - T__13 = 14 - T__14 = 15 - T__15 = 16 - T__16 = 17 - T__17 = 18 - T__18 = 19 - T__19 = 20 - T__20 = 21 - T__21 = 22 - T__22 = 23 - T__23 = 24 - T__24 = 25 - T__25 = 26 - T__26 = 27 - T__27 = 28 - T__28 = 29 - T__29 = 30 - T__30 = 31 - T__31 = 32 - T__32 = 33 - T__33 = 34 - T__34 = 35 - T__35 = 36 - T__36 = 37 - T__37 = 38 - DecimalFloatingConstant = 39 - IntegerConstant = 40 - DecimalConstant = 41 - Name = 42 - INLINE = 43 - WhiteSpace = 44 - LineComment = 45 - NewLine = 46 - - channelNames = [ u"DEFAULT_TOKEN_CHANNEL", u"HIDDEN" ] - - modeNames = [ "DEFAULT_MODE" ] - - literalNames = [ "", - "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", - "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", - "'<<'", "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", - "'suint'", "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", - "'=='", "'!='", "'<'", "'>'", "'<='", "'>='" ] - - symbolicNames = [ "", - "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", - "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" ] - - ruleNames = [ "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", - "T__7", "T__8", "T__9", "T__10", "T__11", "T__12", "T__13", - "T__14", "T__15", "T__16", "T__17", "T__18", "T__19", - "T__20", "T__21", "T__22", "T__23", "T__24", "T__25", - "T__26", "T__27", "T__28", "T__29", "T__30", "T__31", - "T__32", "T__33", "T__34", "T__35", "T__36", "T__37", - "DecimalFloatingConstant", "ExponentPart", "FloatingSuffix", - "FractionalConstant", "IntegerConstant", "DecimalConstant", - "DigitSequence", "Digit", "NonzeroDigit", "Sign", "Name", - "INLINE", "WhiteSpace", "LineComment", "NewLine" ] - - grammarFileName = "HybroLang.g4" - - def __init__(self, input=None, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) - self._actions = None - self._predicates = None - - diff --git a/HybroLang/HybroLangLexer.tokens b/HybroLang/HybroLangLexer.tokens deleted file mode 100644 index 574a34a..0000000 --- a/HybroLang/HybroLangLexer.tokens +++ /dev/null @@ -1,84 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -T__4=5 -T__5=6 -T__6=7 -T__7=8 -T__8=9 -T__9=10 -T__10=11 -T__11=12 -T__12=13 -T__13=14 -T__14=15 -T__15=16 -T__16=17 -T__17=18 -T__18=19 -T__19=20 -T__20=21 -T__21=22 -T__22=23 -T__23=24 -T__24=25 -T__25=26 -T__26=27 -T__27=28 -T__28=29 -T__29=30 -T__30=31 -T__31=32 -T__32=33 -T__33=34 -T__34=35 -T__35=36 -T__36=37 -T__37=38 -DecimalFloatingConstant=39 -IntegerConstant=40 -DecimalConstant=41 -Name=42 -INLINE=43 -WhiteSpace=44 -LineComment=45 -NewLine=46 -'('=1 -')'=2 -'{'=3 -'}'=4 -','=5 -';'=6 -'for'=7 -'if'=8 -'else'=9 -'return'=10 -'='=11 -'['=12 -']'=13 -'*'=14 -'/'=15 -'+'=16 -'-'=17 -'<<'=18 -'>>'=19 -'&'=20 -'|'=21 -'^'=22 -'int'=23 -'uint'=24 -'sint'=25 -'suint'=26 -'flt'=27 -'cpl'=28 -'pix'=29 -'ipv4'=30 -'ipv6'=31 -'[]'=32 -'=='=33 -'!='=34 -'<'=35 -'>'=36 -'<='=37 -'>='=38 diff --git a/HybroLang/HybroLangParser.py b/HybroLang/HybroLangParser.py deleted file mode 100644 index 9a40ce4..0000000 --- a/HybroLang/HybroLangParser.py +++ /dev/null @@ -1,1602 +0,0 @@ -# Generated from HybroLang.g4 by ANTLR 4.9.2 -# encoding: utf-8 -from antlr4 import * -from io import StringIO -import sys -if sys.version_info[1] > 5: - from typing import TextIO -else: - from typing.io import TextIO - -def serializedATN(): - with StringIO() as buf: - buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\60") - buf.write("\u00ce\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7") - buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16") - buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23") - buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\3\2\6\2\60\n") - buf.write("\2\r\2\16\2\61\3\3\3\3\3\3\3\4\3\4\3\4\3\4\3\5\3\5\3\5") - buf.write("\3\5\3\6\3\6\7\6A\n\6\f\6\16\6D\13\6\3\6\3\6\5\6H\n\6") - buf.write("\3\6\3\6\3\7\3\7\3\7\7\7O\n\7\f\7\16\7R\13\7\3\7\5\7U") - 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buf.write("\u0089\u0099\u00aa\u00ac\u00b6\u00be\u00c3\u00c9") - return buf.getvalue() - - -class HybroLangParser ( Parser ): - - grammarFileName = "HybroLang.g4" - - atn = ATNDeserializer().deserialize(serializedATN()) - - decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] - - sharedContextCache = PredictionContextCache() - - literalNames = [ "", "'('", "')'", "'{'", "'}'", "','", "';'", - "'for'", "'if'", "'else'", "'return'", "'='", "'['", - "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", "'>>'", - "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", - "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", - "'=='", "'!='", "'<'", "'>'", "'<='", "'>='" ] - - symbolicNames = [ "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "", - "", "", "", "DecimalFloatingConstant", - "IntegerConstant", "DecimalConstant", "Name", "INLINE", - "WhiteSpace", "LineComment", "NewLine" ] - - RULE_compilationunit = 0 - RULE_function = 1 - RULE_fndcl = 2 - RULE_fnprototype = 3 - RULE_fnbody = 4 - RULE_paramdcllist = 5 - RULE_localvardef = 6 - RULE_vardcllist = 7 - RULE_vardcl = 8 - RULE_actionlist = 9 - RULE_condexpr = 10 - RULE_action = 11 - RULE_returnexpr = 12 - RULE_affectexpr = 13 - RULE_unaryexpr = 14 - RULE_varorvalue = 15 - RULE_datatype = 16 - RULE_intconstvalue = 17 - RULE_constvalue = 18 - RULE_constinline = 19 - RULE_typebase = 20 - RULE_condOperator = 21 - - ruleNames = [ "compilationunit", "function", "fndcl", "fnprototype", - "fnbody", "paramdcllist", "localvardef", "vardcllist", - "vardcl", "actionlist", "condexpr", "action", "returnexpr", - "affectexpr", "unaryexpr", "varorvalue", "datatype", - "intconstvalue", "constvalue", "constinline", "typebase", - "condOperator" ] - - EOF = Token.EOF - T__0=1 - T__1=2 - T__2=3 - T__3=4 - T__4=5 - T__5=6 - T__6=7 - T__7=8 - T__8=9 - T__9=10 - T__10=11 - T__11=12 - T__12=13 - T__13=14 - T__14=15 - T__15=16 - T__16=17 - T__17=18 - T__18=19 - T__19=20 - T__20=21 - T__21=22 - T__22=23 - T__23=24 - T__24=25 - T__25=26 - T__26=27 - T__27=28 - T__28=29 - T__29=30 - T__30=31 - T__31=32 - T__32=33 - T__33=34 - T__34=35 - T__35=36 - T__36=37 - T__37=38 - DecimalFloatingConstant=39 - IntegerConstant=40 - DecimalConstant=41 - Name=42 - INLINE=43 - WhiteSpace=44 - LineComment=45 - NewLine=46 - - def __init__(self, input:TokenStream, output:TextIO = sys.stdout): - super().__init__(input, output) - self.checkVersion("4.9.2") - self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) - self._predicates = None - - - - class CompilationunitContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def function(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.FunctionContext) - else: - return self.getTypedRuleContext(HybroLangParser.FunctionContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_compilationunit - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitCompilationunit" ): - return visitor.visitCompilationunit(self) - else: - return visitor.visitChildren(self) - - - - - def compilationunit(self): - - localctx = HybroLangParser.CompilationunitContext(self, self._ctx, self.state) - self.enterRule(localctx, 0, self.RULE_compilationunit) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 45 - self._errHandler.sync(self) - _la = self._input.LA(1) - while True: - self.state = 44 - self.function() - self.state = 47 - self._errHandler.sync(self) - _la = self._input.LA(1) - if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0)): - break - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class FunctionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def fndcl(self): - return self.getTypedRuleContext(HybroLangParser.FndclContext,0) - - - def fnbody(self): - return self.getTypedRuleContext(HybroLangParser.FnbodyContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_function - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitFunction" ): - return visitor.visitFunction(self) - else: - return visitor.visitChildren(self) - - - - - def function(self): - - localctx = HybroLangParser.FunctionContext(self, self._ctx, self.state) - self.enterRule(localctx, 2, self.RULE_function) - try: - self.enterOuterAlt(localctx, 1) - self.state = 49 - self.fndcl() - self.state = 50 - self.fnbody() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class FndclContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def datatype(self): - return self.getTypedRuleContext(HybroLangParser.DatatypeContext,0) - - - def Name(self): - return self.getToken(HybroLangParser.Name, 0) - - def fnprototype(self): - return self.getTypedRuleContext(HybroLangParser.FnprototypeContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_fndcl - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitFndcl" ): - return visitor.visitFndcl(self) - else: - return visitor.visitChildren(self) - - - - - def fndcl(self): - - localctx = HybroLangParser.FndclContext(self, self._ctx, self.state) - self.enterRule(localctx, 4, self.RULE_fndcl) - try: - self.enterOuterAlt(localctx, 1) - self.state = 52 - self.datatype() - self.state = 53 - self.match(HybroLangParser.Name) - self.state = 54 - self.fnprototype() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class FnprototypeContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def paramdcllist(self): - return self.getTypedRuleContext(HybroLangParser.ParamdcllistContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_fnprototype - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitFnprototype" ): - return visitor.visitFnprototype(self) - else: - return visitor.visitChildren(self) - - - - - def fnprototype(self): - - localctx = HybroLangParser.FnprototypeContext(self, self._ctx, self.state) - self.enterRule(localctx, 6, self.RULE_fnprototype) - try: - self.enterOuterAlt(localctx, 1) - self.state = 56 - self.match(HybroLangParser.T__0) - self.state = 57 - self.paramdcllist() - self.state = 58 - self.match(HybroLangParser.T__1) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class FnbodyContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def actionlist(self): - return self.getTypedRuleContext(HybroLangParser.ActionlistContext,0) - - - def localvardef(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.LocalvardefContext) - else: - return self.getTypedRuleContext(HybroLangParser.LocalvardefContext,i) - - - def returnexpr(self): - return self.getTypedRuleContext(HybroLangParser.ReturnexprContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_fnbody - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitFnbody" ): - return visitor.visitFnbody(self) - else: - return visitor.visitChildren(self) - - - - - def fnbody(self): - - localctx = HybroLangParser.FnbodyContext(self, self._ctx, self.state) - self.enterRule(localctx, 8, self.RULE_fnbody) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 60 - self.match(HybroLangParser.T__2) - self.state = 64 - self._errHandler.sync(self) - _la = self._input.LA(1) - while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0): - self.state = 61 - self.localvardef() - self.state = 66 - self._errHandler.sync(self) - _la = self._input.LA(1) - - self.state = 67 - self.actionlist() - self.state = 69 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==HybroLangParser.T__9: - self.state = 68 - self.returnexpr() - - - self.state = 71 - self.match(HybroLangParser.T__3) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ParamdcllistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def vardcl(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.VardclContext) - else: - return self.getTypedRuleContext(HybroLangParser.VardclContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_paramdcllist - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitParamdcllist" ): - return visitor.visitParamdcllist(self) - else: - return visitor.visitChildren(self) - - - - - def paramdcllist(self): - - localctx = HybroLangParser.ParamdcllistContext(self, self._ctx, self.state) - self.enterRule(localctx, 10, self.RULE_paramdcllist) - self._la = 0 # Token type - try: - self.state = 82 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [HybroLangParser.T__22, HybroLangParser.T__23, HybroLangParser.T__24, HybroLangParser.T__25, HybroLangParser.T__26, HybroLangParser.T__27, HybroLangParser.T__28, HybroLangParser.T__29, HybroLangParser.T__30]: - self.enterOuterAlt(localctx, 1) - self.state = 73 - self.vardcl() - self.state = 78 - self._errHandler.sync(self) - _la = self._input.LA(1) - while _la==HybroLangParser.T__4: - self.state = 74 - self.match(HybroLangParser.T__4) - self.state = 75 - self.vardcl() - self.state = 80 - self._errHandler.sync(self) - _la = self._input.LA(1) - - pass - elif token in [HybroLangParser.T__1]: - self.enterOuterAlt(localctx, 2) - - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class LocalvardefContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def vardcllist(self): - return self.getTypedRuleContext(HybroLangParser.VardcllistContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_localvardef - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitLocalvardef" ): - return visitor.visitLocalvardef(self) - else: - return visitor.visitChildren(self) - - - - - def localvardef(self): - - localctx = HybroLangParser.LocalvardefContext(self, self._ctx, self.state) - self.enterRule(localctx, 12, self.RULE_localvardef) - try: - self.enterOuterAlt(localctx, 1) - self.state = 84 - self.vardcllist() - self.state = 85 - self.match(HybroLangParser.T__5) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class VardcllistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def vardcl(self): - return self.getTypedRuleContext(HybroLangParser.VardclContext,0) - - - def Name(self, i:int=None): - if i is None: - return self.getTokens(HybroLangParser.Name) - else: - return self.getToken(HybroLangParser.Name, i) - - def getRuleIndex(self): - return HybroLangParser.RULE_vardcllist - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitVardcllist" ): - return visitor.visitVardcllist(self) - else: - return visitor.visitChildren(self) - - - - - def vardcllist(self): - - localctx = HybroLangParser.VardcllistContext(self, self._ctx, self.state) - self.enterRule(localctx, 14, self.RULE_vardcllist) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 87 - self.vardcl() - self.state = 92 - self._errHandler.sync(self) - _la = self._input.LA(1) - while _la==HybroLangParser.T__4: - self.state = 88 - self.match(HybroLangParser.T__4) - self.state = 89 - self.match(HybroLangParser.Name) - self.state = 94 - self._errHandler.sync(self) - _la = self._input.LA(1) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class VardclContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def datatype(self): - return self.getTypedRuleContext(HybroLangParser.DatatypeContext,0) - - - def Name(self): - return self.getToken(HybroLangParser.Name, 0) - - def getRuleIndex(self): - return HybroLangParser.RULE_vardcl - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitVardcl" ): - return visitor.visitVardcl(self) - else: - return visitor.visitChildren(self) - - - - - def vardcl(self): - - localctx = HybroLangParser.VardclContext(self, self._ctx, self.state) - self.enterRule(localctx, 16, self.RULE_vardcl) - try: - self.enterOuterAlt(localctx, 1) - self.state = 95 - self.datatype() - self.state = 96 - self.match(HybroLangParser.Name) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ActionlistContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def action(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.ActionContext) - else: - return self.getTypedRuleContext(HybroLangParser.ActionContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_actionlist - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitActionlist" ): - return visitor.visitActionlist(self) - else: - return visitor.visitChildren(self) - - - - - def actionlist(self): - - localctx = HybroLangParser.ActionlistContext(self, self._ctx, self.state) - self.enterRule(localctx, 18, self.RULE_actionlist) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 101 - self._errHandler.sync(self) - _la = self._input.LA(1) - while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__6) | (1 << HybroLangParser.T__7) | (1 << HybroLangParser.Name))) != 0): - self.state = 98 - self.action() - self.state = 103 - self._errHandler.sync(self) - _la = self._input.LA(1) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class CondexprContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def varorvalue(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.VarorvalueContext) - else: - return self.getTypedRuleContext(HybroLangParser.VarorvalueContext,i) - - - def condOperator(self): - return self.getTypedRuleContext(HybroLangParser.CondOperatorContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_condexpr - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitCondexpr" ): - return visitor.visitCondexpr(self) - else: - return visitor.visitChildren(self) - - - - - def condexpr(self): - - localctx = HybroLangParser.CondexprContext(self, self._ctx, self.state) - self.enterRule(localctx, 20, self.RULE_condexpr) - try: - self.enterOuterAlt(localctx, 1) - self.state = 104 - self.varorvalue() - self.state = 105 - self.condOperator() - self.state = 106 - self.varorvalue() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ActionContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def affectexpr(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.AffectexprContext) - else: - return self.getTypedRuleContext(HybroLangParser.AffectexprContext,i) - - - def condexpr(self): - return self.getTypedRuleContext(HybroLangParser.CondexprContext,0) - - - def actionlist(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.ActionlistContext) - else: - return self.getTypedRuleContext(HybroLangParser.ActionlistContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_action - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitAction" ): - return visitor.visitAction(self) - else: - return visitor.visitChildren(self) - - - - - def action(self): - - localctx = HybroLangParser.ActionContext(self, self._ctx, self.state) - self.enterRule(localctx, 22, self.RULE_action) - try: - self.state = 135 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [HybroLangParser.Name]: - self.enterOuterAlt(localctx, 1) - self.state = 108 - self.affectexpr() - self.state = 109 - self.match(HybroLangParser.T__5) - pass - elif token in [HybroLangParser.T__6]: - self.enterOuterAlt(localctx, 2) - self.state = 111 - self.match(HybroLangParser.T__6) - self.state = 112 - self.match(HybroLangParser.T__0) - self.state = 113 - self.affectexpr() - self.state = 114 - self.match(HybroLangParser.T__5) - self.state = 115 - self.condexpr() - self.state = 116 - self.match(HybroLangParser.T__5) - self.state = 117 - self.affectexpr() - self.state = 118 - self.match(HybroLangParser.T__1) - self.state = 119 - self.match(HybroLangParser.T__2) - self.state = 120 - self.actionlist() - self.state = 121 - self.match(HybroLangParser.T__3) - pass - elif token in [HybroLangParser.T__7]: - self.enterOuterAlt(localctx, 3) - self.state = 123 - self.match(HybroLangParser.T__7) - self.state = 124 - self.match(HybroLangParser.T__0) - self.state = 125 - self.condexpr() - self.state = 126 - self.match(HybroLangParser.T__1) - self.state = 127 - self.match(HybroLangParser.T__2) - self.state = 128 - self.actionlist() - self.state = 129 - self.match(HybroLangParser.T__3) - self.state = 130 - self.match(HybroLangParser.T__8) - self.state = 131 - self.match(HybroLangParser.T__2) - self.state = 132 - self.actionlist() - self.state = 133 - self.match(HybroLangParser.T__3) - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ReturnexprContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def unaryexpr(self): - return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_returnexpr - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitReturnexpr" ): - return visitor.visitReturnexpr(self) - else: - return visitor.visitChildren(self) - - - - - def returnexpr(self): - - localctx = HybroLangParser.ReturnexprContext(self, self._ctx, self.state) - self.enterRule(localctx, 24, self.RULE_returnexpr) - try: - self.enterOuterAlt(localctx, 1) - self.state = 137 - self.match(HybroLangParser.T__9) - self.state = 138 - self.unaryexpr(0) - self.state = 139 - self.match(HybroLangParser.T__5) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class AffectexprContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def Name(self): - return self.getToken(HybroLangParser.Name, 0) - - def unaryexpr(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.UnaryexprContext) - else: - return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_affectexpr - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitAffectexpr" ): - return visitor.visitAffectexpr(self) - else: - return visitor.visitChildren(self) - - - - - def affectexpr(self): - - localctx = HybroLangParser.AffectexprContext(self, self._ctx, self.state) - self.enterRule(localctx, 26, self.RULE_affectexpr) - try: - self.state = 151 - self._errHandler.sync(self) - la_ = self._interp.adaptivePredict(self._input,8,self._ctx) - if la_ == 1: - self.enterOuterAlt(localctx, 1) - self.state = 141 - self.match(HybroLangParser.Name) - self.state = 142 - self.match(HybroLangParser.T__10) - self.state = 143 - self.unaryexpr(0) - pass - - elif la_ == 2: - self.enterOuterAlt(localctx, 2) - self.state = 144 - self.match(HybroLangParser.Name) - self.state = 145 - self.match(HybroLangParser.T__11) - self.state = 146 - self.unaryexpr(0) - self.state = 147 - self.match(HybroLangParser.T__12) - self.state = 148 - self.match(HybroLangParser.T__10) - self.state = 149 - self.unaryexpr(0) - pass - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class UnaryexprContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - self.op = None # Token - - def varorvalue(self): - return self.getTypedRuleContext(HybroLangParser.VarorvalueContext,0) - - - def unaryexpr(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.UnaryexprContext) - else: - return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_unaryexpr - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitUnaryexpr" ): - return visitor.visitUnaryexpr(self) - else: - return visitor.visitChildren(self) - - - - def unaryexpr(self, _p:int=0): - _parentctx = self._ctx - _parentState = self.state - localctx = HybroLangParser.UnaryexprContext(self, self._ctx, _parentState) - _prevctx = localctx - _startState = 28 - self.enterRecursionRule(localctx, 28, self.RULE_unaryexpr, _p) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 154 - self.varorvalue() - self._ctx.stop = self._input.LT(-1) - self.state = 170 - self._errHandler.sync(self) - _alt = self._interp.adaptivePredict(self._input,10,self._ctx) - while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER: - if _alt==1: - if self._parseListeners is not None: - self.triggerExitRuleEvent() - _prevctx = localctx - self.state = 168 - self._errHandler.sync(self) - la_ = self._interp.adaptivePredict(self._input,9,self._ctx) - if la_ == 1: - localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) - self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) - self.state = 156 - if not self.precpred(self._ctx, 5): - from antlr4.error.Errors import FailedPredicateException - raise FailedPredicateException(self, "self.precpred(self._ctx, 5)") - self.state = 157 - localctx.op = self._input.LT(1) - _la = self._input.LA(1) - if not(_la==HybroLangParser.T__13 or _la==HybroLangParser.T__14): - localctx.op = self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - self.state = 158 - self.unaryexpr(6) - pass - - elif la_ == 2: - localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) - self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) - self.state = 159 - if not self.precpred(self._ctx, 4): - from antlr4.error.Errors import FailedPredicateException - raise FailedPredicateException(self, "self.precpred(self._ctx, 4)") - self.state = 160 - localctx.op = self._input.LT(1) - _la = self._input.LA(1) - if not(_la==HybroLangParser.T__15 or _la==HybroLangParser.T__16): - localctx.op = self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - self.state = 161 - self.unaryexpr(5) - pass - - elif la_ == 3: - localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) - self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) - self.state = 162 - if not self.precpred(self._ctx, 3): - from antlr4.error.Errors import FailedPredicateException - raise FailedPredicateException(self, "self.precpred(self._ctx, 3)") - self.state = 163 - localctx.op = self._input.LT(1) - _la = self._input.LA(1) - if not(_la==HybroLangParser.T__17 or _la==HybroLangParser.T__18): - localctx.op = self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - self.state = 164 - self.unaryexpr(4) - pass - - elif la_ == 4: - localctx = HybroLangParser.UnaryexprContext(self, _parentctx, _parentState) - self.pushNewRecursionContext(localctx, _startState, self.RULE_unaryexpr) - self.state = 165 - if not self.precpred(self._ctx, 2): - from antlr4.error.Errors import FailedPredicateException - raise FailedPredicateException(self, "self.precpred(self._ctx, 2)") - self.state = 166 - localctx.op = self._input.LT(1) - _la = self._input.LA(1) - if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__19) | (1 << HybroLangParser.T__20) | (1 << HybroLangParser.T__21))) != 0)): - localctx.op = self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - self.state = 167 - self.unaryexpr(3) - pass - - - self.state = 172 - self._errHandler.sync(self) - _alt = self._interp.adaptivePredict(self._input,10,self._ctx) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.unrollRecursionContexts(_parentctx) - return localctx - - class VarorvalueContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return HybroLangParser.RULE_varorvalue - - - def copyFrom(self, ctx:ParserRuleContext): - super().copyFrom(ctx) - - - - class VarorvalueVarContext(VarorvalueContext): - - def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext - super().__init__(parser) - self.copyFrom(ctx) - - def Name(self): - return self.getToken(HybroLangParser.Name, 0) - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitVarorvalueVar" ): - return visitor.visitVarorvalueVar(self) - else: - return visitor.visitChildren(self) - - - class VarorvalueArrayContext(VarorvalueContext): - - def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext - super().__init__(parser) - self.copyFrom(ctx) - - def Name(self): - return self.getToken(HybroLangParser.Name, 0) - def unaryexpr(self): - return self.getTypedRuleContext(HybroLangParser.UnaryexprContext,0) - - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitVarorvalueArray" ): - return visitor.visitVarorvalueArray(self) - else: - return visitor.visitChildren(self) - - - class VarorvalueConstContext(VarorvalueContext): - - def __init__(self, parser, ctx:ParserRuleContext): # actually a HybroLangParser.VarorvalueContext - super().__init__(parser) - self.copyFrom(ctx) - - def constvalue(self): - return self.getTypedRuleContext(HybroLangParser.ConstvalueContext,0) - - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitVarorvalueConst" ): - return visitor.visitVarorvalueConst(self) - else: - return visitor.visitChildren(self) - - - - def varorvalue(self): - - localctx = HybroLangParser.VarorvalueContext(self, self._ctx, self.state) - self.enterRule(localctx, 30, self.RULE_varorvalue) - try: - self.state = 180 - self._errHandler.sync(self) - la_ = self._interp.adaptivePredict(self._input,11,self._ctx) - if la_ == 1: - localctx = HybroLangParser.VarorvalueArrayContext(self, localctx) - self.enterOuterAlt(localctx, 1) - self.state = 173 - self.match(HybroLangParser.Name) - self.state = 174 - self.match(HybroLangParser.T__11) - self.state = 175 - self.unaryexpr(0) - self.state = 176 - self.match(HybroLangParser.T__12) - pass - - elif la_ == 2: - localctx = HybroLangParser.VarorvalueConstContext(self, localctx) - self.enterOuterAlt(localctx, 2) - self.state = 178 - self.constvalue() - pass - - elif la_ == 3: - localctx = HybroLangParser.VarorvalueVarContext(self, localctx) - self.enterOuterAlt(localctx, 3) - self.state = 179 - self.match(HybroLangParser.Name) - pass - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class DatatypeContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - self.wordlen = None # IntconstvalueContext - self.vectorlen = None # IntconstvalueContext - - def typebase(self): - return self.getTypedRuleContext(HybroLangParser.TypebaseContext,0) - - - def intconstvalue(self, i:int=None): - if i is None: - return self.getTypedRuleContexts(HybroLangParser.IntconstvalueContext) - else: - return self.getTypedRuleContext(HybroLangParser.IntconstvalueContext,i) - - - def getRuleIndex(self): - return HybroLangParser.RULE_datatype - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitDatatype" ): - return visitor.visitDatatype(self) - else: - return visitor.visitChildren(self) - - - - - def datatype(self): - - localctx = HybroLangParser.DatatypeContext(self, self._ctx, self.state) - self.enterRule(localctx, 32, self.RULE_datatype) - try: - self.enterOuterAlt(localctx, 1) - self.state = 182 - self.typebase() - self.state = 183 - localctx.wordlen = self.intconstvalue() - self.state = 184 - localctx.vectorlen = self.intconstvalue() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class IntconstvalueContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def IntegerConstant(self): - return self.getToken(HybroLangParser.IntegerConstant, 0) - - def constinline(self): - return self.getTypedRuleContext(HybroLangParser.ConstinlineContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_intconstvalue - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitIntconstvalue" ): - return visitor.visitIntconstvalue(self) - else: - return visitor.visitChildren(self) - - - - - def intconstvalue(self): - - localctx = HybroLangParser.IntconstvalueContext(self, self._ctx, self.state) - self.enterRule(localctx, 34, self.RULE_intconstvalue) - try: - self.state = 188 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [HybroLangParser.IntegerConstant]: - self.enterOuterAlt(localctx, 1) - self.state = 186 - self.match(HybroLangParser.IntegerConstant) - pass - elif token in [HybroLangParser.INLINE]: - self.enterOuterAlt(localctx, 2) - self.state = 187 - self.constinline() - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ConstvalueContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def IntegerConstant(self): - return self.getToken(HybroLangParser.IntegerConstant, 0) - - def DecimalFloatingConstant(self): - return self.getToken(HybroLangParser.DecimalFloatingConstant, 0) - - def constinline(self): - return self.getTypedRuleContext(HybroLangParser.ConstinlineContext,0) - - - def getRuleIndex(self): - return HybroLangParser.RULE_constvalue - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitConstvalue" ): - return visitor.visitConstvalue(self) - else: - return visitor.visitChildren(self) - - - - - def constvalue(self): - - localctx = HybroLangParser.ConstvalueContext(self, self._ctx, self.state) - self.enterRule(localctx, 36, self.RULE_constvalue) - try: - self.state = 193 - self._errHandler.sync(self) - token = self._input.LA(1) - if token in [HybroLangParser.IntegerConstant]: - self.enterOuterAlt(localctx, 1) - self.state = 190 - self.match(HybroLangParser.IntegerConstant) - pass - elif token in [HybroLangParser.DecimalFloatingConstant]: - self.enterOuterAlt(localctx, 2) - self.state = 191 - self.match(HybroLangParser.DecimalFloatingConstant) - pass - elif token in [HybroLangParser.INLINE]: - self.enterOuterAlt(localctx, 3) - self.state = 192 - self.constinline() - pass - else: - raise NoViableAltException(self) - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class ConstinlineContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - def INLINE(self): - return self.getToken(HybroLangParser.INLINE, 0) - - def getRuleIndex(self): - return HybroLangParser.RULE_constinline - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitConstinline" ): - return visitor.visitConstinline(self) - else: - return visitor.visitChildren(self) - - - - - def constinline(self): - - localctx = HybroLangParser.ConstinlineContext(self, self._ctx, self.state) - self.enterRule(localctx, 38, self.RULE_constinline) - try: - self.enterOuterAlt(localctx, 1) - self.state = 195 - self.match(HybroLangParser.INLINE) - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class TypebaseContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return HybroLangParser.RULE_typebase - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitTypebase" ): - return visitor.visitTypebase(self) - else: - return visitor.visitChildren(self) - - - - - def typebase(self): - - localctx = HybroLangParser.TypebaseContext(self, self._ctx, self.state) - self.enterRule(localctx, 40, self.RULE_typebase) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 197 - _la = self._input.LA(1) - if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__22) | (1 << HybroLangParser.T__23) | (1 << HybroLangParser.T__24) | (1 << HybroLangParser.T__25) | (1 << HybroLangParser.T__26) | (1 << HybroLangParser.T__27) | (1 << HybroLangParser.T__28) | (1 << HybroLangParser.T__29) | (1 << HybroLangParser.T__30))) != 0)): - self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - self.state = 199 - self._errHandler.sync(self) - _la = self._input.LA(1) - if _la==HybroLangParser.T__31: - self.state = 198 - self.match(HybroLangParser.T__31) - - - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - class CondOperatorContext(ParserRuleContext): - __slots__ = 'parser' - - def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1): - super().__init__(parent, invokingState) - self.parser = parser - - - def getRuleIndex(self): - return HybroLangParser.RULE_condOperator - - def accept(self, visitor:ParseTreeVisitor): - if hasattr( visitor, "visitCondOperator" ): - return visitor.visitCondOperator(self) - else: - return visitor.visitChildren(self) - - - - - def condOperator(self): - - localctx = HybroLangParser.CondOperatorContext(self, self._ctx, self.state) - self.enterRule(localctx, 42, self.RULE_condOperator) - self._la = 0 # Token type - try: - self.enterOuterAlt(localctx, 1) - self.state = 201 - _la = self._input.LA(1) - if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HybroLangParser.T__32) | (1 << HybroLangParser.T__33) | (1 << HybroLangParser.T__34) | (1 << HybroLangParser.T__35) | (1 << HybroLangParser.T__36) | (1 << HybroLangParser.T__37))) != 0)): - self._errHandler.recoverInline(self) - else: - self._errHandler.reportMatch(self) - self.consume() - except RecognitionException as re: - localctx.exception = re - self._errHandler.reportError(self, re) - self._errHandler.recover(self, re) - finally: - self.exitRule() - return localctx - - - - def sempred(self, localctx:RuleContext, ruleIndex:int, predIndex:int): - if self._predicates == None: - self._predicates = dict() - self._predicates[14] = self.unaryexpr_sempred - pred = self._predicates.get(ruleIndex, None) - if pred is None: - raise Exception("No predicate with index:" + str(ruleIndex)) - else: - return pred(localctx, predIndex) - - def unaryexpr_sempred(self, localctx:UnaryexprContext, predIndex:int): - if predIndex == 0: - return self.precpred(self._ctx, 5) - - - if predIndex == 1: - return self.precpred(self._ctx, 4) - - - if predIndex == 2: - return self.precpred(self._ctx, 3) - - - if predIndex == 3: - return self.precpred(self._ctx, 2) - - - - - diff --git a/HybroLang/__pycache__/H2Aarch64Rewrite.cpython-312.pyc b/HybroLang/__pycache__/H2Aarch64Rewrite.cpython-312.pyc deleted file mode 100644 index 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a/HybroLang/__pycache__/__init__.cpython-312.pyc b/HybroLang/__pycache__/__init__.cpython-312.pyc deleted file mode 100644 index ccec25cde21043933408714bdb761a12860a07d2..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 147 zcmX@j%ge<81Y74`&jitrK?FMZ%mNgd&QQsq$>_I|p@<2{`wUX^%Sb;XKQ}ceKRGc+ zzcAOx!obADNZ+F}sVLt)H4nn@Nz6;vkB`sH%PfhH*DI*}#bJ}1pHiBWYFESxG=dR` Qi$RQ!%#4hTMa)1J05Lft8UO$Q From 0ef1afed6c26a74f6badbb3b5e9f9fc72158bb7f Mon Sep 17 00:00:00 2001 From: Quentin MELOTTE Date: Wed, 22 Jul 2026 15:52:50 +0200 Subject: [PATCH 4/6] Delete file Antlr generated --- HybroLang/.antlr/HybroLang.interp | 125 -- HybroLang/.antlr/HybroLang.tokens | 84 - HybroLang/.antlr/HybroLangBaseListener.java | 327 ---- HybroLang/.antlr/HybroLangLexer.interp | 162 -- HybroLang/.antlr/HybroLangLexer.java | 329 ---- HybroLang/.antlr/HybroLangLexer.tokens | 84 - HybroLang/.antlr/HybroLangListener.java | 255 --- HybroLang/.antlr/HybroLangParser.java | 1680 ------------------- 8 files changed, 3046 deletions(-) delete mode 100644 HybroLang/.antlr/HybroLang.interp delete mode 100644 HybroLang/.antlr/HybroLang.tokens delete mode 100644 HybroLang/.antlr/HybroLangBaseListener.java delete mode 100644 HybroLang/.antlr/HybroLangLexer.interp delete mode 100644 HybroLang/.antlr/HybroLangLexer.java delete mode 100644 HybroLang/.antlr/HybroLangLexer.tokens delete mode 100644 HybroLang/.antlr/HybroLangListener.java delete mode 100644 HybroLang/.antlr/HybroLangParser.java diff --git a/HybroLang/.antlr/HybroLang.interp b/HybroLang/.antlr/HybroLang.interp deleted file mode 100644 index 8ea5afa..0000000 --- a/HybroLang/.antlr/HybroLang.interp +++ /dev/null @@ -1,125 +0,0 @@ -token literal names: -null -'(' -')' -'{' -'}' -',' -';' -'for' -'if' -'else' -'return' -'=' -'[' -']' -'*' -'/' -'+' -'-' -'<<' -'>>' -'&' -'|' -'^' -'int' -'uint' -'sint' -'suint' -'flt' -'cpl' -'pix' -'ipv4' -'ipv6' -'[]' -'==' -'!=' -'<' -'>' -'<=' -'>=' -null -null -null -null -null -null -null -null - -token symbolic names: -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -DecimalFloatingConstant -IntegerConstant -DecimalConstant -Name -INLINE -WhiteSpace -LineComment -NewLine - -rule names: -compilationunit -function -fndcl -fnprototype -fnbody -paramdcllist -localvardef -vardcllist -vardcl -actionlist -condexpr -action -returnexpr -affectexpr -unaryexpr -varorvalue -datatype -intconstvalue -constvalue -constinline -typebase -condOperator - - -atn: -[4, 1, 46, 204, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 1, 0, 4, 0, 46, 8, 0, 11, 0, 12, 0, 47, 1, 1, 1, 1, 1, 1, 1, 2, 1, 2, 1, 2, 1, 2, 1, 3, 1, 3, 1, 3, 1, 3, 1, 4, 1, 4, 5, 4, 63, 8, 4, 10, 4, 12, 4, 66, 9, 4, 1, 4, 1, 4, 3, 4, 70, 8, 4, 1, 4, 1, 4, 1, 5, 1, 5, 1, 5, 5, 5, 77, 8, 5, 10, 5, 12, 5, 80, 9, 5, 1, 5, 3, 5, 83, 8, 5, 1, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 5, 7, 91, 8, 7, 10, 7, 12, 7, 94, 9, 7, 1, 8, 1, 8, 1, 8, 1, 9, 5, 9, 100, 8, 9, 10, 9, 12, 9, 103, 9, 9, 1, 10, 1, 10, 1, 10, 1, 10, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 1, 11, 3, 11, 136, 8, 11, 1, 12, 1, 12, 1, 12, 1, 12, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 1, 13, 3, 13, 152, 8, 13, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 1, 14, 5, 14, 169, 8, 14, 10, 14, 12, 14, 172, 9, 14, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 1, 15, 3, 15, 181, 8, 15, 1, 16, 1, 16, 1, 16, 1, 16, 1, 17, 1, 17, 3, 17, 189, 8, 17, 1, 18, 1, 18, 1, 18, 3, 18, 194, 8, 18, 1, 19, 1, 19, 1, 20, 1, 20, 3, 20, 200, 8, 20, 1, 21, 1, 21, 1, 21, 0, 1, 28, 22, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 0, 6, 1, 0, 14, 15, 1, 0, 16, 17, 1, 0, 18, 19, 1, 0, 20, 22, 1, 0, 23, 31, 1, 0, 33, 38, 201, 0, 45, 1, 0, 0, 0, 2, 49, 1, 0, 0, 0, 4, 52, 1, 0, 0, 0, 6, 56, 1, 0, 0, 0, 8, 60, 1, 0, 0, 0, 10, 82, 1, 0, 0, 0, 12, 84, 1, 0, 0, 0, 14, 87, 1, 0, 0, 0, 16, 95, 1, 0, 0, 0, 18, 101, 1, 0, 0, 0, 20, 104, 1, 0, 0, 0, 22, 135, 1, 0, 0, 0, 24, 137, 1, 0, 0, 0, 26, 151, 1, 0, 0, 0, 28, 153, 1, 0, 0, 0, 30, 180, 1, 0, 0, 0, 32, 182, 1, 0, 0, 0, 34, 188, 1, 0, 0, 0, 36, 193, 1, 0, 0, 0, 38, 195, 1, 0, 0, 0, 40, 197, 1, 0, 0, 0, 42, 201, 1, 0, 0, 0, 44, 46, 3, 2, 1, 0, 45, 44, 1, 0, 0, 0, 46, 47, 1, 0, 0, 0, 47, 45, 1, 0, 0, 0, 47, 48, 1, 0, 0, 0, 48, 1, 1, 0, 0, 0, 49, 50, 3, 4, 2, 0, 50, 51, 3, 8, 4, 0, 51, 3, 1, 0, 0, 0, 52, 53, 3, 32, 16, 0, 53, 54, 5, 42, 0, 0, 54, 55, 3, 6, 3, 0, 55, 5, 1, 0, 0, 0, 56, 57, 5, 1, 0, 0, 57, 58, 3, 10, 5, 0, 58, 59, 5, 2, 0, 0, 59, 7, 1, 0, 0, 0, 60, 64, 5, 3, 0, 0, 61, 63, 3, 12, 6, 0, 62, 61, 1, 0, 0, 0, 63, 66, 1, 0, 0, 0, 64, 62, 1, 0, 0, 0, 64, 65, 1, 0, 0, 0, 65, 67, 1, 0, 0, 0, 66, 64, 1, 0, 0, 0, 67, 69, 3, 18, 9, 0, 68, 70, 3, 24, 12, 0, 69, 68, 1, 0, 0, 0, 69, 70, 1, 0, 0, 0, 70, 71, 1, 0, 0, 0, 71, 72, 5, 4, 0, 0, 72, 9, 1, 0, 0, 0, 73, 78, 3, 16, 8, 0, 74, 75, 5, 5, 0, 0, 75, 77, 3, 16, 8, 0, 76, 74, 1, 0, 0, 0, 77, 80, 1, 0, 0, 0, 78, 76, 1, 0, 0, 0, 78, 79, 1, 0, 0, 0, 79, 83, 1, 0, 0, 0, 80, 78, 1, 0, 0, 0, 81, 83, 1, 0, 0, 0, 82, 73, 1, 0, 0, 0, 82, 81, 1, 0, 0, 0, 83, 11, 1, 0, 0, 0, 84, 85, 3, 14, 7, 0, 85, 86, 5, 6, 0, 0, 86, 13, 1, 0, 0, 0, 87, 92, 3, 16, 8, 0, 88, 89, 5, 5, 0, 0, 89, 91, 5, 42, 0, 0, 90, 88, 1, 0, 0, 0, 91, 94, 1, 0, 0, 0, 92, 90, 1, 0, 0, 0, 92, 93, 1, 0, 0, 0, 93, 15, 1, 0, 0, 0, 94, 92, 1, 0, 0, 0, 95, 96, 3, 32, 16, 0, 96, 97, 5, 42, 0, 0, 97, 17, 1, 0, 0, 0, 98, 100, 3, 22, 11, 0, 99, 98, 1, 0, 0, 0, 100, 103, 1, 0, 0, 0, 101, 99, 1, 0, 0, 0, 101, 102, 1, 0, 0, 0, 102, 19, 1, 0, 0, 0, 103, 101, 1, 0, 0, 0, 104, 105, 3, 30, 15, 0, 105, 106, 3, 42, 21, 0, 106, 107, 3, 30, 15, 0, 107, 21, 1, 0, 0, 0, 108, 109, 3, 26, 13, 0, 109, 110, 5, 6, 0, 0, 110, 136, 1, 0, 0, 0, 111, 112, 5, 7, 0, 0, 112, 113, 5, 1, 0, 0, 113, 114, 3, 26, 13, 0, 114, 115, 5, 6, 0, 0, 115, 116, 3, 20, 10, 0, 116, 117, 5, 6, 0, 0, 117, 118, 3, 26, 13, 0, 118, 119, 5, 2, 0, 0, 119, 120, 5, 3, 0, 0, 120, 121, 3, 18, 9, 0, 121, 122, 5, 4, 0, 0, 122, 136, 1, 0, 0, 0, 123, 124, 5, 8, 0, 0, 124, 125, 5, 1, 0, 0, 125, 126, 3, 20, 10, 0, 126, 127, 5, 2, 0, 0, 127, 128, 5, 3, 0, 0, 128, 129, 3, 18, 9, 0, 129, 130, 5, 4, 0, 0, 130, 131, 5, 9, 0, 0, 131, 132, 5, 3, 0, 0, 132, 133, 3, 18, 9, 0, 133, 134, 5, 4, 0, 0, 134, 136, 1, 0, 0, 0, 135, 108, 1, 0, 0, 0, 135, 111, 1, 0, 0, 0, 135, 123, 1, 0, 0, 0, 136, 23, 1, 0, 0, 0, 137, 138, 5, 10, 0, 0, 138, 139, 3, 28, 14, 0, 139, 140, 5, 6, 0, 0, 140, 25, 1, 0, 0, 0, 141, 142, 5, 42, 0, 0, 142, 143, 5, 11, 0, 0, 143, 152, 3, 28, 14, 0, 144, 145, 5, 42, 0, 0, 145, 146, 5, 12, 0, 0, 146, 147, 3, 28, 14, 0, 147, 148, 5, 13, 0, 0, 148, 149, 5, 11, 0, 0, 149, 150, 3, 28, 14, 0, 150, 152, 1, 0, 0, 0, 151, 141, 1, 0, 0, 0, 151, 144, 1, 0, 0, 0, 152, 27, 1, 0, 0, 0, 153, 154, 6, 14, -1, 0, 154, 155, 3, 30, 15, 0, 155, 170, 1, 0, 0, 0, 156, 157, 10, 5, 0, 0, 157, 158, 7, 0, 0, 0, 158, 169, 3, 28, 14, 6, 159, 160, 10, 4, 0, 0, 160, 161, 7, 1, 0, 0, 161, 169, 3, 28, 14, 5, 162, 163, 10, 3, 0, 0, 163, 164, 7, 2, 0, 0, 164, 169, 3, 28, 14, 4, 165, 166, 10, 2, 0, 0, 166, 167, 7, 3, 0, 0, 167, 169, 3, 28, 14, 3, 168, 156, 1, 0, 0, 0, 168, 159, 1, 0, 0, 0, 168, 162, 1, 0, 0, 0, 168, 165, 1, 0, 0, 0, 169, 172, 1, 0, 0, 0, 170, 168, 1, 0, 0, 0, 170, 171, 1, 0, 0, 0, 171, 29, 1, 0, 0, 0, 172, 170, 1, 0, 0, 0, 173, 174, 5, 42, 0, 0, 174, 175, 5, 12, 0, 0, 175, 176, 3, 28, 14, 0, 176, 177, 5, 13, 0, 0, 177, 181, 1, 0, 0, 0, 178, 181, 3, 36, 18, 0, 179, 181, 5, 42, 0, 0, 180, 173, 1, 0, 0, 0, 180, 178, 1, 0, 0, 0, 180, 179, 1, 0, 0, 0, 181, 31, 1, 0, 0, 0, 182, 183, 3, 40, 20, 0, 183, 184, 3, 34, 17, 0, 184, 185, 3, 34, 17, 0, 185, 33, 1, 0, 0, 0, 186, 189, 5, 40, 0, 0, 187, 189, 3, 38, 19, 0, 188, 186, 1, 0, 0, 0, 188, 187, 1, 0, 0, 0, 189, 35, 1, 0, 0, 0, 190, 194, 5, 40, 0, 0, 191, 194, 5, 39, 0, 0, 192, 194, 3, 38, 19, 0, 193, 190, 1, 0, 0, 0, 193, 191, 1, 0, 0, 0, 193, 192, 1, 0, 0, 0, 194, 37, 1, 0, 0, 0, 195, 196, 5, 43, 0, 0, 196, 39, 1, 0, 0, 0, 197, 199, 7, 4, 0, 0, 198, 200, 5, 32, 0, 0, 199, 198, 1, 0, 0, 0, 199, 200, 1, 0, 0, 0, 200, 41, 1, 0, 0, 0, 201, 202, 7, 5, 0, 0, 202, 43, 1, 0, 0, 0, 15, 47, 64, 69, 78, 82, 92, 101, 135, 151, 168, 170, 180, 188, 193, 199] \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLang.tokens b/HybroLang/.antlr/HybroLang.tokens deleted file mode 100644 index 574a34a..0000000 --- a/HybroLang/.antlr/HybroLang.tokens +++ /dev/null @@ -1,84 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -T__4=5 -T__5=6 -T__6=7 -T__7=8 -T__8=9 -T__9=10 -T__10=11 -T__11=12 -T__12=13 -T__13=14 -T__14=15 -T__15=16 -T__16=17 -T__17=18 -T__18=19 -T__19=20 -T__20=21 -T__21=22 -T__22=23 -T__23=24 -T__24=25 -T__25=26 -T__26=27 -T__27=28 -T__28=29 -T__29=30 -T__30=31 -T__31=32 -T__32=33 -T__33=34 -T__34=35 -T__35=36 -T__36=37 -T__37=38 -DecimalFloatingConstant=39 -IntegerConstant=40 -DecimalConstant=41 -Name=42 -INLINE=43 -WhiteSpace=44 -LineComment=45 -NewLine=46 -'('=1 -')'=2 -'{'=3 -'}'=4 -','=5 -';'=6 -'for'=7 -'if'=8 -'else'=9 -'return'=10 -'='=11 -'['=12 -']'=13 -'*'=14 -'/'=15 -'+'=16 -'-'=17 -'<<'=18 -'>>'=19 -'&'=20 -'|'=21 -'^'=22 -'int'=23 -'uint'=24 -'sint'=25 -'suint'=26 -'flt'=27 -'cpl'=28 -'pix'=29 -'ipv4'=30 -'ipv6'=31 -'[]'=32 -'=='=33 -'!='=34 -'<'=35 -'>'=36 -'<='=37 -'>='=38 diff --git a/HybroLang/.antlr/HybroLangBaseListener.java b/HybroLang/.antlr/HybroLangBaseListener.java deleted file mode 100644 index 1196c27..0000000 --- a/HybroLang/.antlr/HybroLangBaseListener.java +++ /dev/null @@ -1,327 +0,0 @@ -// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 - -import org.antlr.v4.runtime.ParserRuleContext; -import org.antlr.v4.runtime.tree.ErrorNode; -import org.antlr.v4.runtime.tree.TerminalNode; - -/** - * This class provides an empty implementation of {@link HybroLangListener}, - * which can be extended to create a listener which only needs to handle a subset - * of the available methods. - */ -@SuppressWarnings("CheckReturnValue") -public class HybroLangBaseListener implements HybroLangListener { - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterCompilationunit(HybroLangParser.CompilationunitContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitCompilationunit(HybroLangParser.CompilationunitContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterFunction(HybroLangParser.FunctionContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitFunction(HybroLangParser.FunctionContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterFndcl(HybroLangParser.FndclContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitFndcl(HybroLangParser.FndclContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterFnprototype(HybroLangParser.FnprototypeContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitFnprototype(HybroLangParser.FnprototypeContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterFnbody(HybroLangParser.FnbodyContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitFnbody(HybroLangParser.FnbodyContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterParamdcllist(HybroLangParser.ParamdcllistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitParamdcllist(HybroLangParser.ParamdcllistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterLocalvardef(HybroLangParser.LocalvardefContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitLocalvardef(HybroLangParser.LocalvardefContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterVardcllist(HybroLangParser.VardcllistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitVardcllist(HybroLangParser.VardcllistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterVardcl(HybroLangParser.VardclContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitVardcl(HybroLangParser.VardclContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterActionlist(HybroLangParser.ActionlistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitActionlist(HybroLangParser.ActionlistContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterCondexpr(HybroLangParser.CondexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitCondexpr(HybroLangParser.CondexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterAction(HybroLangParser.ActionContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitAction(HybroLangParser.ActionContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterReturnexpr(HybroLangParser.ReturnexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitReturnexpr(HybroLangParser.ReturnexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterAffectexpr(HybroLangParser.AffectexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitAffectexpr(HybroLangParser.AffectexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterUnaryexpr(HybroLangParser.UnaryexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitUnaryexpr(HybroLangParser.UnaryexprContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterDatatype(HybroLangParser.DatatypeContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitDatatype(HybroLangParser.DatatypeContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterIntconstvalue(HybroLangParser.IntconstvalueContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitIntconstvalue(HybroLangParser.IntconstvalueContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterConstvalue(HybroLangParser.ConstvalueContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitConstvalue(HybroLangParser.ConstvalueContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterConstinline(HybroLangParser.ConstinlineContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitConstinline(HybroLangParser.ConstinlineContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterTypebase(HybroLangParser.TypebaseContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitTypebase(HybroLangParser.TypebaseContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterCondOperator(HybroLangParser.CondOperatorContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitCondOperator(HybroLangParser.CondOperatorContext ctx) { } - - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void enterEveryRule(ParserRuleContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void exitEveryRule(ParserRuleContext ctx) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void visitTerminal(TerminalNode node) { } - /** - * {@inheritDoc} - * - *

The default implementation does nothing.

- */ - @Override public void visitErrorNode(ErrorNode node) { } -} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.interp b/HybroLang/.antlr/HybroLangLexer.interp deleted file mode 100644 index 9840595..0000000 --- a/HybroLang/.antlr/HybroLangLexer.interp +++ /dev/null @@ -1,162 +0,0 @@ -token literal names: -null -'(' -')' -'{' -'}' -',' -';' -'for' -'if' -'else' -'return' -'=' -'[' -']' -'*' -'/' -'+' -'-' -'<<' -'>>' -'&' -'|' -'^' -'int' -'uint' -'sint' -'suint' -'flt' -'cpl' -'pix' -'ipv4' -'ipv6' -'[]' -'==' -'!=' -'<' -'>' -'<=' -'>=' -null -null -null -null -null -null -null -null - -token symbolic names: -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -null -DecimalFloatingConstant -IntegerConstant -DecimalConstant -Name -INLINE -WhiteSpace -LineComment -NewLine - -rule names: -T__0 -T__1 -T__2 -T__3 -T__4 -T__5 -T__6 -T__7 -T__8 -T__9 -T__10 -T__11 -T__12 -T__13 -T__14 -T__15 -T__16 -T__17 -T__18 -T__19 -T__20 -T__21 -T__22 -T__23 -T__24 -T__25 -T__26 -T__27 -T__28 -T__29 -T__30 -T__31 -T__32 -T__33 -T__34 -T__35 -T__36 -T__37 -DecimalFloatingConstant -ExponentPart -FloatingSuffix -FractionalConstant -IntegerConstant -DecimalConstant -DigitSequence -Digit -NonzeroDigit -Sign -Name -INLINE -WhiteSpace -LineComment -NewLine - -channel names: -DEFAULT_TOKEN_CHANNEL -HIDDEN - -mode names: -DEFAULT_MODE - -atn: -[4, 0, 46, 320, 6, -1, 2, 0, 7, 0, 2, 1, 7, 1, 2, 2, 7, 2, 2, 3, 7, 3, 2, 4, 7, 4, 2, 5, 7, 5, 2, 6, 7, 6, 2, 7, 7, 7, 2, 8, 7, 8, 2, 9, 7, 9, 2, 10, 7, 10, 2, 11, 7, 11, 2, 12, 7, 12, 2, 13, 7, 13, 2, 14, 7, 14, 2, 15, 7, 15, 2, 16, 7, 16, 2, 17, 7, 17, 2, 18, 7, 18, 2, 19, 7, 19, 2, 20, 7, 20, 2, 21, 7, 21, 2, 22, 7, 22, 2, 23, 7, 23, 2, 24, 7, 24, 2, 25, 7, 25, 2, 26, 7, 26, 2, 27, 7, 27, 2, 28, 7, 28, 2, 29, 7, 29, 2, 30, 7, 30, 2, 31, 7, 31, 2, 32, 7, 32, 2, 33, 7, 33, 2, 34, 7, 34, 2, 35, 7, 35, 2, 36, 7, 36, 2, 37, 7, 37, 2, 38, 7, 38, 2, 39, 7, 39, 2, 40, 7, 40, 2, 41, 7, 41, 2, 42, 7, 42, 2, 43, 7, 43, 2, 44, 7, 44, 2, 45, 7, 45, 2, 46, 7, 46, 2, 47, 7, 47, 2, 48, 7, 48, 2, 49, 7, 49, 2, 50, 7, 50, 2, 51, 7, 51, 2, 52, 7, 52, 1, 0, 1, 0, 1, 1, 1, 1, 1, 2, 1, 2, 1, 3, 1, 3, 1, 4, 1, 4, 1, 5, 1, 5, 1, 6, 1, 6, 1, 6, 1, 6, 1, 7, 1, 7, 1, 7, 1, 8, 1, 8, 1, 8, 1, 8, 1, 8, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 9, 1, 10, 1, 10, 1, 11, 1, 11, 1, 12, 1, 12, 1, 13, 1, 13, 1, 14, 1, 14, 1, 15, 1, 15, 1, 16, 1, 16, 1, 17, 1, 17, 1, 17, 1, 18, 1, 18, 1, 18, 1, 19, 1, 19, 1, 20, 1, 20, 1, 21, 1, 21, 1, 22, 1, 22, 1, 22, 1, 22, 1, 23, 1, 23, 1, 23, 1, 23, 1, 23, 1, 24, 1, 24, 1, 24, 1, 24, 1, 24, 1, 25, 1, 25, 1, 25, 1, 25, 1, 25, 1, 25, 1, 26, 1, 26, 1, 26, 1, 26, 1, 27, 1, 27, 1, 27, 1, 27, 1, 28, 1, 28, 1, 28, 1, 28, 1, 29, 1, 29, 1, 29, 1, 29, 1, 29, 1, 30, 1, 30, 1, 30, 1, 30, 1, 30, 1, 31, 1, 31, 1, 31, 1, 32, 1, 32, 1, 32, 1, 33, 1, 33, 1, 33, 1, 34, 1, 34, 1, 35, 1, 35, 1, 36, 1, 36, 1, 36, 1, 37, 1, 37, 1, 37, 1, 38, 1, 38, 3, 38, 228, 8, 38, 1, 38, 3, 38, 231, 8, 38, 1, 39, 1, 39, 3, 39, 235, 8, 39, 1, 39, 1, 39, 1, 39, 3, 39, 240, 8, 39, 1, 39, 3, 39, 243, 8, 39, 1, 40, 1, 40, 1, 41, 3, 41, 248, 8, 41, 1, 41, 1, 41, 1, 41, 1, 41, 1, 41, 3, 41, 255, 8, 41, 1, 42, 1, 42, 1, 43, 1, 43, 5, 43, 261, 8, 43, 10, 43, 12, 43, 264, 9, 43, 1, 44, 4, 44, 267, 8, 44, 11, 44, 12, 44, 268, 1, 45, 1, 45, 1, 46, 1, 46, 1, 47, 1, 47, 1, 48, 1, 48, 5, 48, 279, 8, 48, 10, 48, 12, 48, 282, 9, 48, 1, 49, 1, 49, 1, 49, 1, 49, 4, 49, 288, 8, 49, 11, 49, 12, 49, 289, 1, 49, 1, 49, 1, 50, 4, 50, 295, 8, 50, 11, 50, 12, 50, 296, 1, 50, 1, 50, 1, 51, 1, 51, 1, 51, 1, 51, 5, 51, 305, 8, 51, 10, 51, 12, 51, 308, 9, 51, 1, 51, 1, 51, 1, 51, 1, 51, 1, 52, 3, 52, 315, 8, 52, 1, 52, 1, 52, 1, 52, 1, 52, 1, 306, 0, 53, 1, 1, 3, 2, 5, 3, 7, 4, 9, 5, 11, 6, 13, 7, 15, 8, 17, 9, 19, 10, 21, 11, 23, 12, 25, 13, 27, 14, 29, 15, 31, 16, 33, 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0, 0, 296, 297, 1, 0, 0, 0, 297, 298, 1, 0, 0, 0, 298, 299, 6, 50, 0, 0, 299, 102, 1, 0, 0, 0, 300, 301, 5, 47, 0, 0, 301, 302, 5, 47, 0, 0, 302, 306, 1, 0, 0, 0, 303, 305, 9, 0, 0, 0, 304, 303, 1, 0, 0, 0, 305, 308, 1, 0, 0, 0, 306, 307, 1, 0, 0, 0, 306, 304, 1, 0, 0, 0, 307, 309, 1, 0, 0, 0, 308, 306, 1, 0, 0, 0, 309, 310, 3, 105, 52, 0, 310, 311, 1, 0, 0, 0, 311, 312, 6, 51, 0, 0, 312, 104, 1, 0, 0, 0, 313, 315, 5, 13, 0, 0, 314, 313, 1, 0, 0, 0, 314, 315, 1, 0, 0, 0, 315, 316, 1, 0, 0, 0, 316, 317, 5, 10, 0, 0, 317, 318, 1, 0, 0, 0, 318, 319, 6, 52, 0, 0, 319, 106, 1, 0, 0, 0, 15, 0, 227, 230, 234, 239, 242, 247, 254, 262, 268, 280, 289, 296, 306, 314, 1, 6, 0, 0] \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.java b/HybroLang/.antlr/HybroLangLexer.java deleted file mode 100644 index fe6b304..0000000 --- a/HybroLang/.antlr/HybroLangLexer.java +++ /dev/null @@ -1,329 +0,0 @@ -// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 -import org.antlr.v4.runtime.Lexer; -import org.antlr.v4.runtime.CharStream; -import org.antlr.v4.runtime.Token; -import org.antlr.v4.runtime.TokenStream; -import org.antlr.v4.runtime.*; -import org.antlr.v4.runtime.atn.*; -import org.antlr.v4.runtime.dfa.DFA; -import org.antlr.v4.runtime.misc.*; - -@SuppressWarnings({"all", "warnings", "unchecked", "unused", "cast", "CheckReturnValue", "this-escape"}) -public class HybroLangLexer extends Lexer { - static { RuntimeMetaData.checkVersion("4.13.1", RuntimeMetaData.VERSION); } - - protected static final DFA[] _decisionToDFA; - protected static final PredictionContextCache _sharedContextCache = - new PredictionContextCache(); - public static final int - T__0=1, T__1=2, T__2=3, T__3=4, T__4=5, T__5=6, T__6=7, T__7=8, T__8=9, - T__9=10, T__10=11, T__11=12, T__12=13, T__13=14, T__14=15, T__15=16, T__16=17, - T__17=18, T__18=19, T__19=20, T__20=21, T__21=22, T__22=23, T__23=24, - T__24=25, T__25=26, T__26=27, T__27=28, T__28=29, T__29=30, T__30=31, - T__31=32, T__32=33, T__33=34, T__34=35, T__35=36, T__36=37, T__37=38, - DecimalFloatingConstant=39, IntegerConstant=40, DecimalConstant=41, Name=42, - INLINE=43, WhiteSpace=44, LineComment=45, NewLine=46; - public static String[] channelNames = { - "DEFAULT_TOKEN_CHANNEL", "HIDDEN" - }; - - public static String[] modeNames = { - "DEFAULT_MODE" - }; - - private static String[] makeRuleNames() { - return new String[] { - "T__0", "T__1", "T__2", "T__3", "T__4", "T__5", "T__6", "T__7", "T__8", - "T__9", "T__10", "T__11", "T__12", "T__13", "T__14", "T__15", "T__16", - "T__17", "T__18", "T__19", "T__20", "T__21", "T__22", "T__23", "T__24", - "T__25", "T__26", "T__27", "T__28", "T__29", "T__30", "T__31", "T__32", - "T__33", "T__34", "T__35", "T__36", "T__37", "DecimalFloatingConstant", - "ExponentPart", "FloatingSuffix", "FractionalConstant", "IntegerConstant", - "DecimalConstant", "DigitSequence", "Digit", "NonzeroDigit", "Sign", - "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" - }; - } - public static final String[] ruleNames = makeRuleNames(); - - private static String[] makeLiteralNames() { - return new String[] { - null, "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", - "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", - "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", - "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", "'=='", "'!='", - "'<'", "'>'", "'<='", "'>='" - }; - } - private static final String[] _LITERAL_NAMES = makeLiteralNames(); - private static String[] makeSymbolicNames() { - return new String[] { - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", - "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" - }; - } - private static final String[] _SYMBOLIC_NAMES = makeSymbolicNames(); - public static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES); - - /** - * @deprecated Use {@link #VOCABULARY} instead. - */ - @Deprecated - public static final String[] tokenNames; - static { - tokenNames = new String[_SYMBOLIC_NAMES.length]; - for (int i = 0; i < tokenNames.length; i++) { - tokenNames[i] = VOCABULARY.getLiteralName(i); - if (tokenNames[i] == null) { - tokenNames[i] = VOCABULARY.getSymbolicName(i); - } - - if (tokenNames[i] == null) { - tokenNames[i] = ""; - } - } - } - - @Override - @Deprecated - public String[] getTokenNames() { - return tokenNames; - } - - @Override - - public Vocabulary getVocabulary() { - return VOCABULARY; - } - - - public HybroLangLexer(CharStream input) { - super(input); - _interp = new LexerATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache); - } - - @Override - public String getGrammarFileName() { return "HybroLang.g4"; } - - @Override - public String[] getRuleNames() { return ruleNames; } - - @Override - public String getSerializedATN() { return _serializedATN; } - - @Override - public String[] getChannelNames() { return channelNames; } - - @Override - public String[] getModeNames() { return modeNames; } - - @Override - public ATN getATN() { return _ATN; } - - public static final String _serializedATN = - "\u0004\u0000.\u0140\u0006\uffff\uffff\u0002\u0000\u0007\u0000\u0002\u0001"+ - "\u0007\u0001\u0002\u0002\u0007\u0002\u0002\u0003\u0007\u0003\u0002\u0004"+ - "\u0007\u0004\u0002\u0005\u0007\u0005\u0002\u0006\u0007\u0006\u0002\u0007"+ - "\u0007\u0007\u0002\b\u0007\b\u0002\t\u0007\t\u0002\n\u0007\n\u0002\u000b"+ - "\u0007\u000b\u0002\f\u0007\f\u0002\r\u0007\r\u0002\u000e\u0007\u000e\u0002"+ - "\u000f\u0007\u000f\u0002\u0010\u0007\u0010\u0002\u0011\u0007\u0011\u0002"+ - "\u0012\u0007\u0012\u0002\u0013\u0007\u0013\u0002\u0014\u0007\u0014\u0002"+ - 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"\"\u0001\u0000\u0000\u0000\u0098\u0099\u0005<\u0000\u0000\u0099\u009a"+ - "\u0005<\u0000\u0000\u009a$\u0001\u0000\u0000\u0000\u009b\u009c\u0005>"+ - "\u0000\u0000\u009c\u009d\u0005>\u0000\u0000\u009d&\u0001\u0000\u0000\u0000"+ - "\u009e\u009f\u0005&\u0000\u0000\u009f(\u0001\u0000\u0000\u0000\u00a0\u00a1"+ - "\u0005|\u0000\u0000\u00a1*\u0001\u0000\u0000\u0000\u00a2\u00a3\u0005^"+ - "\u0000\u0000\u00a3,\u0001\u0000\u0000\u0000\u00a4\u00a5\u0005i\u0000\u0000"+ - "\u00a5\u00a6\u0005n\u0000\u0000\u00a6\u00a7\u0005t\u0000\u0000\u00a7."+ - "\u0001\u0000\u0000\u0000\u00a8\u00a9\u0005u\u0000\u0000\u00a9\u00aa\u0005"+ - "i\u0000\u0000\u00aa\u00ab\u0005n\u0000\u0000\u00ab\u00ac\u0005t\u0000"+ - "\u0000\u00ac0\u0001\u0000\u0000\u0000\u00ad\u00ae\u0005s\u0000\u0000\u00ae"+ - "\u00af\u0005i\u0000\u0000\u00af\u00b0\u0005n\u0000\u0000\u00b0\u00b1\u0005"+ - "t\u0000\u0000\u00b12\u0001\u0000\u0000\u0000\u00b2\u00b3\u0005s\u0000"+ - "\u0000\u00b3\u00b4\u0005u\u0000\u0000\u00b4\u00b5\u0005i\u0000\u0000\u00b5"+ - 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"\u0000\u0000\u0000\u00d4\u00d5\u0005!\u0000\u0000\u00d5\u00d6\u0005=\u0000"+ - "\u0000\u00d6D\u0001\u0000\u0000\u0000\u00d7\u00d8\u0005<\u0000\u0000\u00d8"+ - "F\u0001\u0000\u0000\u0000\u00d9\u00da\u0005>\u0000\u0000\u00daH\u0001"+ - "\u0000\u0000\u0000\u00db\u00dc\u0005<\u0000\u0000\u00dc\u00dd\u0005=\u0000"+ - "\u0000\u00ddJ\u0001\u0000\u0000\u0000\u00de\u00df\u0005>\u0000\u0000\u00df"+ - "\u00e0\u0005=\u0000\u0000\u00e0L\u0001\u0000\u0000\u0000\u00e1\u00e3\u0003"+ - "S)\u0000\u00e2\u00e4\u0003O\'\u0000\u00e3\u00e2\u0001\u0000\u0000\u0000"+ - "\u00e3\u00e4\u0001\u0000\u0000\u0000\u00e4\u00e6\u0001\u0000\u0000\u0000"+ - "\u00e5\u00e7\u0003Q(\u0000\u00e6\u00e5\u0001\u0000\u0000\u0000\u00e6\u00e7"+ - "\u0001\u0000\u0000\u0000\u00e7N\u0001\u0000\u0000\u0000\u00e8\u00ea\u0005"+ - "e\u0000\u0000\u00e9\u00eb\u0003_/\u0000\u00ea\u00e9\u0001\u0000\u0000"+ - "\u0000\u00ea\u00eb\u0001\u0000\u0000\u0000\u00eb\u00ec\u0001\u0000\u0000"+ - "\u0000\u00ec\u00f3\u0003Y,\u0000\u00ed\u00ef\u0005E\u0000\u0000\u00ee"+ - "\u00f0\u0003_/\u0000\u00ef\u00ee\u0001\u0000\u0000\u0000\u00ef\u00f0\u0001"+ - "\u0000\u0000\u0000\u00f0\u00f1\u0001\u0000\u0000\u0000\u00f1\u00f3\u0003"+ - "Y,\u0000\u00f2\u00e8\u0001\u0000\u0000\u0000\u00f2\u00ed\u0001\u0000\u0000"+ - "\u0000\u00f3P\u0001\u0000\u0000\u0000\u00f4\u00f5\u0007\u0000\u0000\u0000"+ - "\u00f5R\u0001\u0000\u0000\u0000\u00f6\u00f8\u0003Y,\u0000\u00f7\u00f6"+ - "\u0001\u0000\u0000\u0000\u00f7\u00f8\u0001\u0000\u0000\u0000\u00f8\u00f9"+ - "\u0001\u0000\u0000\u0000\u00f9\u00fa\u0005.\u0000\u0000\u00fa\u00ff\u0003"+ - "Y,\u0000\u00fb\u00fc\u0003Y,\u0000\u00fc\u00fd\u0005.\u0000\u0000\u00fd"+ - "\u00ff\u0001\u0000\u0000\u0000\u00fe\u00f7\u0001\u0000\u0000\u0000\u00fe"+ - "\u00fb\u0001\u0000\u0000\u0000\u00ffT\u0001\u0000\u0000\u0000\u0100\u0101"+ - "\u0003Y,\u0000\u0101V\u0001\u0000\u0000\u0000\u0102\u0106\u0003].\u0000"+ - "\u0103\u0105\u0003[-\u0000\u0104\u0103\u0001\u0000\u0000\u0000\u0105\u0108"+ - "\u0001\u0000\u0000\u0000\u0106\u0104\u0001\u0000\u0000\u0000\u0106\u0107"+ - "\u0001\u0000\u0000\u0000\u0107X\u0001\u0000\u0000\u0000\u0108\u0106\u0001"+ - "\u0000\u0000\u0000\u0109\u010b\u0003[-\u0000\u010a\u0109\u0001\u0000\u0000"+ - "\u0000\u010b\u010c\u0001\u0000\u0000\u0000\u010c\u010a\u0001\u0000\u0000"+ - "\u0000\u010c\u010d\u0001\u0000\u0000\u0000\u010dZ\u0001\u0000\u0000\u0000"+ - "\u010e\u010f\u0007\u0001\u0000\u0000\u010f\\\u0001\u0000\u0000\u0000\u0110"+ - "\u0111\u0007\u0002\u0000\u0000\u0111^\u0001\u0000\u0000\u0000\u0112\u0113"+ - "\u0007\u0003\u0000\u0000\u0113`\u0001\u0000\u0000\u0000\u0114\u0118\u0007"+ - "\u0004\u0000\u0000\u0115\u0117\u0007\u0005\u0000\u0000\u0116\u0115\u0001"+ - "\u0000\u0000\u0000\u0117\u011a\u0001\u0000\u0000\u0000\u0118\u0116\u0001"+ - "\u0000\u0000\u0000\u0118\u0119\u0001\u0000\u0000\u0000\u0119b\u0001\u0000"+ - "\u0000\u0000\u011a\u0118\u0001\u0000\u0000\u0000\u011b\u011c\u0005#\u0000"+ - "\u0000\u011c\u011d\u0005(\u0000\u0000\u011d\u011f\u0001\u0000\u0000\u0000"+ - "\u011e\u0120\b\u0006\u0000\u0000\u011f\u011e\u0001\u0000\u0000\u0000\u0120"+ - "\u0121\u0001\u0000\u0000\u0000\u0121\u011f\u0001\u0000\u0000\u0000\u0121"+ - "\u0122\u0001\u0000\u0000\u0000\u0122\u0123\u0001\u0000\u0000\u0000\u0123"+ - "\u0124\u0005)\u0000\u0000\u0124d\u0001\u0000\u0000\u0000\u0125\u0127\u0007"+ - "\u0007\u0000\u0000\u0126\u0125\u0001\u0000\u0000\u0000\u0127\u0128\u0001"+ - "\u0000\u0000\u0000\u0128\u0126\u0001\u0000\u0000\u0000\u0128\u0129\u0001"+ - "\u0000\u0000\u0000\u0129\u012a\u0001\u0000\u0000\u0000\u012a\u012b\u0006"+ - "2\u0000\u0000\u012bf\u0001\u0000\u0000\u0000\u012c\u012d\u0005/\u0000"+ - "\u0000\u012d\u012e\u0005/\u0000\u0000\u012e\u0132\u0001\u0000\u0000\u0000"+ - "\u012f\u0131\t\u0000\u0000\u0000\u0130\u012f\u0001\u0000\u0000\u0000\u0131"+ - "\u0134\u0001\u0000\u0000\u0000\u0132\u0133\u0001\u0000\u0000\u0000\u0132"+ - "\u0130\u0001\u0000\u0000\u0000\u0133\u0135\u0001\u0000\u0000\u0000\u0134"+ - "\u0132\u0001\u0000\u0000\u0000\u0135\u0136\u0003i4\u0000\u0136\u0137\u0001"+ - "\u0000\u0000\u0000\u0137\u0138\u00063\u0000\u0000\u0138h\u0001\u0000\u0000"+ - "\u0000\u0139\u013b\u0005\r\u0000\u0000\u013a\u0139\u0001\u0000\u0000\u0000"+ - "\u013a\u013b\u0001\u0000\u0000\u0000\u013b\u013c\u0001\u0000\u0000\u0000"+ - "\u013c\u013d\u0005\n\u0000\u0000\u013d\u013e\u0001\u0000\u0000\u0000\u013e"+ - "\u013f\u00064\u0000\u0000\u013fj\u0001\u0000\u0000\u0000\u000f\u0000\u00e3"+ - "\u00e6\u00ea\u00ef\u00f2\u00f7\u00fe\u0106\u010c\u0118\u0121\u0128\u0132"+ - "\u013a\u0001\u0006\u0000\u0000"; - public static final ATN _ATN = - new ATNDeserializer().deserialize(_serializedATN.toCharArray()); - static { - _decisionToDFA = new DFA[_ATN.getNumberOfDecisions()]; - for (int i = 0; i < _ATN.getNumberOfDecisions(); i++) { - _decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i); - } - } -} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangLexer.tokens b/HybroLang/.antlr/HybroLangLexer.tokens deleted file mode 100644 index 574a34a..0000000 --- a/HybroLang/.antlr/HybroLangLexer.tokens +++ /dev/null @@ -1,84 +0,0 @@ -T__0=1 -T__1=2 -T__2=3 -T__3=4 -T__4=5 -T__5=6 -T__6=7 -T__7=8 -T__8=9 -T__9=10 -T__10=11 -T__11=12 -T__12=13 -T__13=14 -T__14=15 -T__15=16 -T__16=17 -T__17=18 -T__18=19 -T__19=20 -T__20=21 -T__21=22 -T__22=23 -T__23=24 -T__24=25 -T__25=26 -T__26=27 -T__27=28 -T__28=29 -T__29=30 -T__30=31 -T__31=32 -T__32=33 -T__33=34 -T__34=35 -T__35=36 -T__36=37 -T__37=38 -DecimalFloatingConstant=39 -IntegerConstant=40 -DecimalConstant=41 -Name=42 -INLINE=43 -WhiteSpace=44 -LineComment=45 -NewLine=46 -'('=1 -')'=2 -'{'=3 -'}'=4 -','=5 -';'=6 -'for'=7 -'if'=8 -'else'=9 -'return'=10 -'='=11 -'['=12 -']'=13 -'*'=14 -'/'=15 -'+'=16 -'-'=17 -'<<'=18 -'>>'=19 -'&'=20 -'|'=21 -'^'=22 -'int'=23 -'uint'=24 -'sint'=25 -'suint'=26 -'flt'=27 -'cpl'=28 -'pix'=29 -'ipv4'=30 -'ipv6'=31 -'[]'=32 -'=='=33 -'!='=34 -'<'=35 -'>'=36 -'<='=37 -'>='=38 diff --git a/HybroLang/.antlr/HybroLangListener.java b/HybroLang/.antlr/HybroLangListener.java deleted file mode 100644 index 17c0a14..0000000 --- a/HybroLang/.antlr/HybroLangListener.java +++ /dev/null @@ -1,255 +0,0 @@ -// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 -import org.antlr.v4.runtime.tree.ParseTreeListener; - -/** - * This interface defines a complete listener for a parse tree produced by - * {@link HybroLangParser}. - */ -public interface HybroLangListener extends ParseTreeListener { - /** - * Enter a parse tree produced by {@link HybroLangParser#compilationunit}. - * @param ctx the parse tree - */ - void enterCompilationunit(HybroLangParser.CompilationunitContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#compilationunit}. - * @param ctx the parse tree - */ - void exitCompilationunit(HybroLangParser.CompilationunitContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#function}. - * @param ctx the parse tree - */ - void enterFunction(HybroLangParser.FunctionContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#function}. - * @param ctx the parse tree - */ - void exitFunction(HybroLangParser.FunctionContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#fndcl}. - * @param ctx the parse tree - */ - void enterFndcl(HybroLangParser.FndclContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#fndcl}. - * @param ctx the parse tree - */ - void exitFndcl(HybroLangParser.FndclContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#fnprototype}. - * @param ctx the parse tree - */ - void enterFnprototype(HybroLangParser.FnprototypeContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#fnprototype}. - * @param ctx the parse tree - */ - void exitFnprototype(HybroLangParser.FnprototypeContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#fnbody}. - * @param ctx the parse tree - */ - void enterFnbody(HybroLangParser.FnbodyContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#fnbody}. - * @param ctx the parse tree - */ - void exitFnbody(HybroLangParser.FnbodyContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#paramdcllist}. - * @param ctx the parse tree - */ - void enterParamdcllist(HybroLangParser.ParamdcllistContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#paramdcllist}. - * @param ctx the parse tree - */ - void exitParamdcllist(HybroLangParser.ParamdcllistContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#localvardef}. - * @param ctx the parse tree - */ - void enterLocalvardef(HybroLangParser.LocalvardefContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#localvardef}. - * @param ctx the parse tree - */ - void exitLocalvardef(HybroLangParser.LocalvardefContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#vardcllist}. - * @param ctx the parse tree - */ - void enterVardcllist(HybroLangParser.VardcllistContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#vardcllist}. - * @param ctx the parse tree - */ - void exitVardcllist(HybroLangParser.VardcllistContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#vardcl}. - * @param ctx the parse tree - */ - void enterVardcl(HybroLangParser.VardclContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#vardcl}. - * @param ctx the parse tree - */ - void exitVardcl(HybroLangParser.VardclContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#actionlist}. - * @param ctx the parse tree - */ - void enterActionlist(HybroLangParser.ActionlistContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#actionlist}. - * @param ctx the parse tree - */ - void exitActionlist(HybroLangParser.ActionlistContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#condexpr}. - * @param ctx the parse tree - */ - void enterCondexpr(HybroLangParser.CondexprContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#condexpr}. - * @param ctx the parse tree - */ - void exitCondexpr(HybroLangParser.CondexprContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#action}. - * @param ctx the parse tree - */ - void enterAction(HybroLangParser.ActionContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#action}. - * @param ctx the parse tree - */ - void exitAction(HybroLangParser.ActionContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#returnexpr}. - * @param ctx the parse tree - */ - void enterReturnexpr(HybroLangParser.ReturnexprContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#returnexpr}. - * @param ctx the parse tree - */ - void exitReturnexpr(HybroLangParser.ReturnexprContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#affectexpr}. - * @param ctx the parse tree - */ - void enterAffectexpr(HybroLangParser.AffectexprContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#affectexpr}. - * @param ctx the parse tree - */ - void exitAffectexpr(HybroLangParser.AffectexprContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#unaryexpr}. - * @param ctx the parse tree - */ - void enterUnaryexpr(HybroLangParser.UnaryexprContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#unaryexpr}. - * @param ctx the parse tree - */ - void exitUnaryexpr(HybroLangParser.UnaryexprContext ctx); - /** - * Enter a parse tree produced by the {@code varorvalueArray} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void enterVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx); - /** - * Exit a parse tree produced by the {@code varorvalueArray} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void exitVarorvalueArray(HybroLangParser.VarorvalueArrayContext ctx); - /** - * Enter a parse tree produced by the {@code varorvalueConst} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void enterVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx); - /** - * Exit a parse tree produced by the {@code varorvalueConst} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void exitVarorvalueConst(HybroLangParser.VarorvalueConstContext ctx); - /** - * Enter a parse tree produced by the {@code varorvalueVar} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void enterVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx); - /** - * Exit a parse tree produced by the {@code varorvalueVar} - * labeled alternative in {@link HybroLangParser#varorvalue}. - * @param ctx the parse tree - */ - void exitVarorvalueVar(HybroLangParser.VarorvalueVarContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#datatype}. - * @param ctx the parse tree - */ - void enterDatatype(HybroLangParser.DatatypeContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#datatype}. - * @param ctx the parse tree - */ - void exitDatatype(HybroLangParser.DatatypeContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#intconstvalue}. - * @param ctx the parse tree - */ - void enterIntconstvalue(HybroLangParser.IntconstvalueContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#intconstvalue}. - * @param ctx the parse tree - */ - void exitIntconstvalue(HybroLangParser.IntconstvalueContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#constvalue}. - * @param ctx the parse tree - */ - void enterConstvalue(HybroLangParser.ConstvalueContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#constvalue}. - * @param ctx the parse tree - */ - void exitConstvalue(HybroLangParser.ConstvalueContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#constinline}. - * @param ctx the parse tree - */ - void enterConstinline(HybroLangParser.ConstinlineContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#constinline}. - * @param ctx the parse tree - */ - void exitConstinline(HybroLangParser.ConstinlineContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#typebase}. - * @param ctx the parse tree - */ - void enterTypebase(HybroLangParser.TypebaseContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#typebase}. - * @param ctx the parse tree - */ - void exitTypebase(HybroLangParser.TypebaseContext ctx); - /** - * Enter a parse tree produced by {@link HybroLangParser#condOperator}. - * @param ctx the parse tree - */ - void enterCondOperator(HybroLangParser.CondOperatorContext ctx); - /** - * Exit a parse tree produced by {@link HybroLangParser#condOperator}. - * @param ctx the parse tree - */ - void exitCondOperator(HybroLangParser.CondOperatorContext ctx); -} \ No newline at end of file diff --git a/HybroLang/.antlr/HybroLangParser.java b/HybroLang/.antlr/HybroLangParser.java deleted file mode 100644 index 784d4f0..0000000 --- a/HybroLang/.antlr/HybroLangParser.java +++ /dev/null @@ -1,1680 +0,0 @@ -// Generated from /homelocal/qm280442/HybroGen/HybroLang/HybroLang.g4 by ANTLR 4.13.1 -import org.antlr.v4.runtime.atn.*; -import org.antlr.v4.runtime.dfa.DFA; -import org.antlr.v4.runtime.*; -import org.antlr.v4.runtime.misc.*; -import org.antlr.v4.runtime.tree.*; -import java.util.List; -import java.util.Iterator; -import java.util.ArrayList; - -@SuppressWarnings({"all", "warnings", "unchecked", "unused", "cast", "CheckReturnValue"}) -public class HybroLangParser extends Parser { - static { RuntimeMetaData.checkVersion("4.13.1", RuntimeMetaData.VERSION); } - - protected static final DFA[] _decisionToDFA; - protected static final PredictionContextCache _sharedContextCache = - new PredictionContextCache(); - public static final int - T__0=1, T__1=2, T__2=3, T__3=4, T__4=5, T__5=6, T__6=7, T__7=8, T__8=9, - T__9=10, T__10=11, T__11=12, T__12=13, T__13=14, T__14=15, T__15=16, T__16=17, - T__17=18, T__18=19, T__19=20, T__20=21, T__21=22, T__22=23, T__23=24, - T__24=25, T__25=26, T__26=27, T__27=28, T__28=29, T__29=30, T__30=31, - T__31=32, T__32=33, T__33=34, T__34=35, T__35=36, T__36=37, T__37=38, - DecimalFloatingConstant=39, IntegerConstant=40, DecimalConstant=41, Name=42, - INLINE=43, WhiteSpace=44, LineComment=45, NewLine=46; - public static final int - RULE_compilationunit = 0, RULE_function = 1, RULE_fndcl = 2, RULE_fnprototype = 3, - RULE_fnbody = 4, RULE_paramdcllist = 5, RULE_localvardef = 6, RULE_vardcllist = 7, - RULE_vardcl = 8, RULE_actionlist = 9, RULE_condexpr = 10, RULE_action = 11, - RULE_returnexpr = 12, RULE_affectexpr = 13, RULE_unaryexpr = 14, RULE_varorvalue = 15, - RULE_datatype = 16, RULE_intconstvalue = 17, RULE_constvalue = 18, RULE_constinline = 19, - RULE_typebase = 20, RULE_condOperator = 21; - private static String[] makeRuleNames() { - return new String[] { - "compilationunit", "function", "fndcl", "fnprototype", "fnbody", "paramdcllist", - "localvardef", "vardcllist", "vardcl", "actionlist", "condexpr", "action", - "returnexpr", "affectexpr", "unaryexpr", "varorvalue", "datatype", "intconstvalue", - "constvalue", "constinline", "typebase", "condOperator" - }; - } - public static final String[] ruleNames = makeRuleNames(); - - private static String[] makeLiteralNames() { - return new String[] { - null, "'('", "')'", "'{'", "'}'", "','", "';'", "'for'", "'if'", "'else'", - "'return'", "'='", "'['", "']'", "'*'", "'/'", "'+'", "'-'", "'<<'", - "'>>'", "'&'", "'|'", "'^'", "'int'", "'uint'", "'sint'", "'suint'", - "'flt'", "'cpl'", "'pix'", "'ipv4'", "'ipv6'", "'[]'", "'=='", "'!='", - "'<'", "'>'", "'<='", "'>='" - }; - } - private static final String[] _LITERAL_NAMES = makeLiteralNames(); - private static String[] makeSymbolicNames() { - return new String[] { - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, null, null, null, null, null, null, null, null, null, - null, null, null, "DecimalFloatingConstant", "IntegerConstant", "DecimalConstant", - "Name", "INLINE", "WhiteSpace", "LineComment", "NewLine" - }; - } - private static final String[] _SYMBOLIC_NAMES = makeSymbolicNames(); - public static final Vocabulary VOCABULARY = new VocabularyImpl(_LITERAL_NAMES, _SYMBOLIC_NAMES); - - /** - * @deprecated Use {@link #VOCABULARY} instead. - */ - @Deprecated - public static final String[] tokenNames; - static { - tokenNames = new String[_SYMBOLIC_NAMES.length]; - for (int i = 0; i < tokenNames.length; i++) { - tokenNames[i] = VOCABULARY.getLiteralName(i); - if (tokenNames[i] == null) { - tokenNames[i] = VOCABULARY.getSymbolicName(i); - } - - if (tokenNames[i] == null) { - tokenNames[i] = ""; - } - } - } - - @Override - @Deprecated - public String[] getTokenNames() { - return tokenNames; - } - - @Override - - public Vocabulary getVocabulary() { - return VOCABULARY; - } - - @Override - public String getGrammarFileName() { return "HybroLang.g4"; } - - @Override - public String[] getRuleNames() { return ruleNames; } - - @Override - public String getSerializedATN() { return _serializedATN; } - - @Override - public ATN getATN() { return _ATN; } - - public HybroLangParser(TokenStream input) { - super(input); - _interp = new ParserATNSimulator(this,_ATN,_decisionToDFA,_sharedContextCache); - } - - @SuppressWarnings("CheckReturnValue") - public static class CompilationunitContext extends ParserRuleContext { - public List function() { - return getRuleContexts(FunctionContext.class); - } - public FunctionContext function(int i) { - return getRuleContext(FunctionContext.class,i); - } - public CompilationunitContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_compilationunit; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCompilationunit(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCompilationunit(this); - } - } - - public final CompilationunitContext compilationunit() throws RecognitionException { - CompilationunitContext _localctx = new CompilationunitContext(_ctx, getState()); - enterRule(_localctx, 0, RULE_compilationunit); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(45); - _errHandler.sync(this); - _la = _input.LA(1); - do { - { - { - setState(44); - function(); - } - } - setState(47); - _errHandler.sync(this); - _la = _input.LA(1); - } while ( (((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0) ); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class FunctionContext extends ParserRuleContext { - public FndclContext fndcl() { - return getRuleContext(FndclContext.class,0); - } - public FnbodyContext fnbody() { - return getRuleContext(FnbodyContext.class,0); - } - public FunctionContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_function; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFunction(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFunction(this); - } - } - - public final FunctionContext function() throws RecognitionException { - FunctionContext _localctx = new FunctionContext(_ctx, getState()); - enterRule(_localctx, 2, RULE_function); - try { - enterOuterAlt(_localctx, 1); - { - setState(49); - fndcl(); - setState(50); - fnbody(); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class FndclContext extends ParserRuleContext { - public DatatypeContext datatype() { - return getRuleContext(DatatypeContext.class,0); - } - public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } - public FnprototypeContext fnprototype() { - return getRuleContext(FnprototypeContext.class,0); - } - public FndclContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_fndcl; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFndcl(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFndcl(this); - } - } - - public final FndclContext fndcl() throws RecognitionException { - FndclContext _localctx = new FndclContext(_ctx, getState()); - enterRule(_localctx, 4, RULE_fndcl); - try { - enterOuterAlt(_localctx, 1); - { - setState(52); - datatype(); - setState(53); - match(Name); - setState(54); - fnprototype(); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class FnprototypeContext extends ParserRuleContext { - public ParamdcllistContext paramdcllist() { - return getRuleContext(ParamdcllistContext.class,0); - } - public FnprototypeContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_fnprototype; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFnprototype(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFnprototype(this); - } - } - - public final FnprototypeContext fnprototype() throws RecognitionException { - FnprototypeContext _localctx = new FnprototypeContext(_ctx, getState()); - enterRule(_localctx, 6, RULE_fnprototype); - try { - enterOuterAlt(_localctx, 1); - { - setState(56); - match(T__0); - setState(57); - paramdcllist(); - setState(58); - match(T__1); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class FnbodyContext extends ParserRuleContext { - public ActionlistContext actionlist() { - return getRuleContext(ActionlistContext.class,0); - } - public List localvardef() { - return getRuleContexts(LocalvardefContext.class); - } - public LocalvardefContext localvardef(int i) { - return getRuleContext(LocalvardefContext.class,i); - } - public ReturnexprContext returnexpr() { - return getRuleContext(ReturnexprContext.class,0); - } - public FnbodyContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_fnbody; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterFnbody(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitFnbody(this); - } - } - - public final FnbodyContext fnbody() throws RecognitionException { - FnbodyContext _localctx = new FnbodyContext(_ctx, getState()); - enterRule(_localctx, 8, RULE_fnbody); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(60); - match(T__2); - setState(64); - _errHandler.sync(this); - _la = _input.LA(1); - while ((((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0)) { - { - { - setState(61); - localvardef(); - } - } - setState(66); - _errHandler.sync(this); - _la = _input.LA(1); - } - setState(67); - actionlist(); - setState(69); - _errHandler.sync(this); - _la = _input.LA(1); - if (_la==T__9) { - { - setState(68); - returnexpr(); - } - } - - setState(71); - match(T__3); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ParamdcllistContext extends ParserRuleContext { - public List vardcl() { - return getRuleContexts(VardclContext.class); - } - public VardclContext vardcl(int i) { - return getRuleContext(VardclContext.class,i); - } - public ParamdcllistContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_paramdcllist; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterParamdcllist(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitParamdcllist(this); - } - } - - public final ParamdcllistContext paramdcllist() throws RecognitionException { - ParamdcllistContext _localctx = new ParamdcllistContext(_ctx, getState()); - enterRule(_localctx, 10, RULE_paramdcllist); - int _la; - try { - setState(82); - _errHandler.sync(this); - switch (_input.LA(1)) { - case T__22: - case T__23: - case T__24: - case T__25: - case T__26: - case T__27: - case T__28: - case T__29: - case T__30: - enterOuterAlt(_localctx, 1); - { - setState(73); - vardcl(); - setState(78); - _errHandler.sync(this); - _la = _input.LA(1); - while (_la==T__4) { - { - { - setState(74); - match(T__4); - setState(75); - vardcl(); - } - } - setState(80); - _errHandler.sync(this); - _la = _input.LA(1); - } - } - break; - case T__1: - enterOuterAlt(_localctx, 2); - { - } - break; - default: - throw new NoViableAltException(this); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class LocalvardefContext extends ParserRuleContext { - public VardcllistContext vardcllist() { - return getRuleContext(VardcllistContext.class,0); - } - public LocalvardefContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_localvardef; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterLocalvardef(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitLocalvardef(this); - } - } - - public final LocalvardefContext localvardef() throws RecognitionException { - LocalvardefContext _localctx = new LocalvardefContext(_ctx, getState()); - enterRule(_localctx, 12, RULE_localvardef); - try { - enterOuterAlt(_localctx, 1); - { - setState(84); - vardcllist(); - setState(85); - match(T__5); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class VardcllistContext extends ParserRuleContext { - public VardclContext vardcl() { - return getRuleContext(VardclContext.class,0); - } - public List Name() { return getTokens(HybroLangParser.Name); } - public TerminalNode Name(int i) { - return getToken(HybroLangParser.Name, i); - } - public VardcllistContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_vardcllist; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVardcllist(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVardcllist(this); - } - } - - public final VardcllistContext vardcllist() throws RecognitionException { - VardcllistContext _localctx = new VardcllistContext(_ctx, getState()); - enterRule(_localctx, 14, RULE_vardcllist); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(87); - vardcl(); - setState(92); - _errHandler.sync(this); - _la = _input.LA(1); - while (_la==T__4) { - { - { - setState(88); - match(T__4); - setState(89); - match(Name); - } - } - setState(94); - _errHandler.sync(this); - _la = _input.LA(1); - } - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class VardclContext extends ParserRuleContext { - public DatatypeContext datatype() { - return getRuleContext(DatatypeContext.class,0); - } - public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } - public VardclContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_vardcl; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVardcl(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVardcl(this); - } - } - - public final VardclContext vardcl() throws RecognitionException { - VardclContext _localctx = new VardclContext(_ctx, getState()); - enterRule(_localctx, 16, RULE_vardcl); - try { - enterOuterAlt(_localctx, 1); - { - setState(95); - datatype(); - setState(96); - match(Name); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ActionlistContext extends ParserRuleContext { - public List action() { - return getRuleContexts(ActionContext.class); - } - public ActionContext action(int i) { - return getRuleContext(ActionContext.class,i); - } - public ActionlistContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_actionlist; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterActionlist(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitActionlist(this); - } - } - - public final ActionlistContext actionlist() throws RecognitionException { - ActionlistContext _localctx = new ActionlistContext(_ctx, getState()); - enterRule(_localctx, 18, RULE_actionlist); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(101); - _errHandler.sync(this); - _la = _input.LA(1); - while ((((_la) & ~0x3f) == 0 && ((1L << _la) & 4398046511488L) != 0)) { - { - { - setState(98); - action(); - } - } - setState(103); - _errHandler.sync(this); - _la = _input.LA(1); - } - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class CondexprContext extends ParserRuleContext { - public List varorvalue() { - return getRuleContexts(VarorvalueContext.class); - } - public VarorvalueContext varorvalue(int i) { - return getRuleContext(VarorvalueContext.class,i); - } - public CondOperatorContext condOperator() { - return getRuleContext(CondOperatorContext.class,0); - } - public CondexprContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_condexpr; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCondexpr(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCondexpr(this); - } - } - - public final CondexprContext condexpr() throws RecognitionException { - CondexprContext _localctx = new CondexprContext(_ctx, getState()); - enterRule(_localctx, 20, RULE_condexpr); - try { - enterOuterAlt(_localctx, 1); - { - setState(104); - varorvalue(); - setState(105); - condOperator(); - setState(106); - varorvalue(); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ActionContext extends ParserRuleContext { - public List affectexpr() { - return getRuleContexts(AffectexprContext.class); - } - public AffectexprContext affectexpr(int i) { - return getRuleContext(AffectexprContext.class,i); - } - public CondexprContext condexpr() { - return getRuleContext(CondexprContext.class,0); - } - public List actionlist() { - return getRuleContexts(ActionlistContext.class); - } - public ActionlistContext actionlist(int i) { - return getRuleContext(ActionlistContext.class,i); - } - public ActionContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_action; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterAction(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitAction(this); - } - } - - public final ActionContext action() throws RecognitionException { - ActionContext _localctx = new ActionContext(_ctx, getState()); - enterRule(_localctx, 22, RULE_action); - try { - setState(135); - _errHandler.sync(this); - switch (_input.LA(1)) { - case Name: - enterOuterAlt(_localctx, 1); - { - setState(108); - affectexpr(); - setState(109); - match(T__5); - } - break; - case T__6: - enterOuterAlt(_localctx, 2); - { - setState(111); - match(T__6); - setState(112); - match(T__0); - setState(113); - affectexpr(); - setState(114); - match(T__5); - setState(115); - condexpr(); - setState(116); - match(T__5); - setState(117); - affectexpr(); - setState(118); - match(T__1); - setState(119); - match(T__2); - setState(120); - actionlist(); - setState(121); - match(T__3); - } - break; - case T__7: - enterOuterAlt(_localctx, 3); - { - setState(123); - match(T__7); - setState(124); - match(T__0); - setState(125); - condexpr(); - setState(126); - match(T__1); - setState(127); - match(T__2); - setState(128); - actionlist(); - setState(129); - match(T__3); - setState(130); - match(T__8); - setState(131); - match(T__2); - setState(132); - actionlist(); - setState(133); - match(T__3); - } - break; - default: - throw new NoViableAltException(this); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ReturnexprContext extends ParserRuleContext { - public UnaryexprContext unaryexpr() { - return getRuleContext(UnaryexprContext.class,0); - } - public ReturnexprContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_returnexpr; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterReturnexpr(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitReturnexpr(this); - } - } - - public final ReturnexprContext returnexpr() throws RecognitionException { - ReturnexprContext _localctx = new ReturnexprContext(_ctx, getState()); - enterRule(_localctx, 24, RULE_returnexpr); - try { - enterOuterAlt(_localctx, 1); - { - setState(137); - match(T__9); - setState(138); - unaryexpr(0); - setState(139); - match(T__5); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class AffectexprContext extends ParserRuleContext { - public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } - public List unaryexpr() { - return getRuleContexts(UnaryexprContext.class); - } - public UnaryexprContext unaryexpr(int i) { - return getRuleContext(UnaryexprContext.class,i); - } - public AffectexprContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_affectexpr; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterAffectexpr(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitAffectexpr(this); - } - } - - public final AffectexprContext affectexpr() throws RecognitionException { - AffectexprContext _localctx = new AffectexprContext(_ctx, getState()); - enterRule(_localctx, 26, RULE_affectexpr); - try { - setState(151); - _errHandler.sync(this); - switch ( getInterpreter().adaptivePredict(_input,8,_ctx) ) { - case 1: - enterOuterAlt(_localctx, 1); - { - setState(141); - match(Name); - setState(142); - match(T__10); - setState(143); - unaryexpr(0); - } - break; - case 2: - enterOuterAlt(_localctx, 2); - { - setState(144); - match(Name); - setState(145); - match(T__11); - setState(146); - unaryexpr(0); - setState(147); - match(T__12); - setState(148); - match(T__10); - setState(149); - unaryexpr(0); - } - break; - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class UnaryexprContext extends ParserRuleContext { - public Token op; - public VarorvalueContext varorvalue() { - return getRuleContext(VarorvalueContext.class,0); - } - public List unaryexpr() { - return getRuleContexts(UnaryexprContext.class); - } - public UnaryexprContext unaryexpr(int i) { - return getRuleContext(UnaryexprContext.class,i); - } - public UnaryexprContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_unaryexpr; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterUnaryexpr(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitUnaryexpr(this); - } - } - - public final UnaryexprContext unaryexpr() throws RecognitionException { - return unaryexpr(0); - } - - private UnaryexprContext unaryexpr(int _p) throws RecognitionException { - ParserRuleContext _parentctx = _ctx; - int _parentState = getState(); - UnaryexprContext _localctx = new UnaryexprContext(_ctx, _parentState); - UnaryexprContext _prevctx = _localctx; - int _startState = 28; - enterRecursionRule(_localctx, 28, RULE_unaryexpr, _p); - int _la; - try { - int _alt; - enterOuterAlt(_localctx, 1); - { - { - setState(154); - varorvalue(); - } - _ctx.stop = _input.LT(-1); - setState(170); - _errHandler.sync(this); - _alt = getInterpreter().adaptivePredict(_input,10,_ctx); - while ( _alt!=2 && _alt!=org.antlr.v4.runtime.atn.ATN.INVALID_ALT_NUMBER ) { - if ( _alt==1 ) { - if ( _parseListeners!=null ) triggerExitRuleEvent(); - _prevctx = _localctx; - { - setState(168); - _errHandler.sync(this); - switch ( getInterpreter().adaptivePredict(_input,9,_ctx) ) { - case 1: - { - _localctx = new UnaryexprContext(_parentctx, _parentState); - pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); - setState(156); - if (!(precpred(_ctx, 5))) throw new FailedPredicateException(this, "precpred(_ctx, 5)"); - setState(157); - ((UnaryexprContext)_localctx).op = _input.LT(1); - _la = _input.LA(1); - if ( !(_la==T__13 || _la==T__14) ) { - ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - setState(158); - unaryexpr(6); - } - break; - case 2: - { - _localctx = new UnaryexprContext(_parentctx, _parentState); - pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); - setState(159); - if (!(precpred(_ctx, 4))) throw new FailedPredicateException(this, "precpred(_ctx, 4)"); - setState(160); - ((UnaryexprContext)_localctx).op = _input.LT(1); - _la = _input.LA(1); - if ( !(_la==T__15 || _la==T__16) ) { - ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - setState(161); - unaryexpr(5); - } - break; - case 3: - { - _localctx = new UnaryexprContext(_parentctx, _parentState); - pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); - setState(162); - if (!(precpred(_ctx, 3))) throw new FailedPredicateException(this, "precpred(_ctx, 3)"); - setState(163); - ((UnaryexprContext)_localctx).op = _input.LT(1); - _la = _input.LA(1); - if ( !(_la==T__17 || _la==T__18) ) { - ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - setState(164); - unaryexpr(4); - } - break; - case 4: - { - _localctx = new UnaryexprContext(_parentctx, _parentState); - pushNewRecursionContext(_localctx, _startState, RULE_unaryexpr); - setState(165); - if (!(precpred(_ctx, 2))) throw new FailedPredicateException(this, "precpred(_ctx, 2)"); - setState(166); - ((UnaryexprContext)_localctx).op = _input.LT(1); - _la = _input.LA(1); - if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 7340032L) != 0)) ) { - ((UnaryexprContext)_localctx).op = (Token)_errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - setState(167); - unaryexpr(3); - } - break; - } - } - } - setState(172); - _errHandler.sync(this); - _alt = getInterpreter().adaptivePredict(_input,10,_ctx); - } - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - unrollRecursionContexts(_parentctx); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class VarorvalueContext extends ParserRuleContext { - public VarorvalueContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_varorvalue; } - - public VarorvalueContext() { } - public void copyFrom(VarorvalueContext ctx) { - super.copyFrom(ctx); - } - } - @SuppressWarnings("CheckReturnValue") - public static class VarorvalueVarContext extends VarorvalueContext { - public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } - public VarorvalueVarContext(VarorvalueContext ctx) { copyFrom(ctx); } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueVar(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueVar(this); - } - } - @SuppressWarnings("CheckReturnValue") - public static class VarorvalueArrayContext extends VarorvalueContext { - public TerminalNode Name() { return getToken(HybroLangParser.Name, 0); } - public UnaryexprContext unaryexpr() { - return getRuleContext(UnaryexprContext.class,0); - } - public VarorvalueArrayContext(VarorvalueContext ctx) { copyFrom(ctx); } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueArray(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueArray(this); - } - } - @SuppressWarnings("CheckReturnValue") - public static class VarorvalueConstContext extends VarorvalueContext { - public ConstvalueContext constvalue() { - return getRuleContext(ConstvalueContext.class,0); - } - public VarorvalueConstContext(VarorvalueContext ctx) { copyFrom(ctx); } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterVarorvalueConst(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitVarorvalueConst(this); - } - } - - public final VarorvalueContext varorvalue() throws RecognitionException { - VarorvalueContext _localctx = new VarorvalueContext(_ctx, getState()); - enterRule(_localctx, 30, RULE_varorvalue); - try { - setState(180); - _errHandler.sync(this); - switch ( getInterpreter().adaptivePredict(_input,11,_ctx) ) { - case 1: - _localctx = new VarorvalueArrayContext(_localctx); - enterOuterAlt(_localctx, 1); - { - setState(173); - match(Name); - setState(174); - match(T__11); - setState(175); - unaryexpr(0); - setState(176); - match(T__12); - } - break; - case 2: - _localctx = new VarorvalueConstContext(_localctx); - enterOuterAlt(_localctx, 2); - { - setState(178); - constvalue(); - } - break; - case 3: - _localctx = new VarorvalueVarContext(_localctx); - enterOuterAlt(_localctx, 3); - { - setState(179); - match(Name); - } - break; - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class DatatypeContext extends ParserRuleContext { - public IntconstvalueContext wordlen; - public IntconstvalueContext vectorlen; - public TypebaseContext typebase() { - return getRuleContext(TypebaseContext.class,0); - } - public List intconstvalue() { - return getRuleContexts(IntconstvalueContext.class); - } - public IntconstvalueContext intconstvalue(int i) { - return getRuleContext(IntconstvalueContext.class,i); - } - public DatatypeContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_datatype; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterDatatype(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitDatatype(this); - } - } - - public final DatatypeContext datatype() throws RecognitionException { - DatatypeContext _localctx = new DatatypeContext(_ctx, getState()); - enterRule(_localctx, 32, RULE_datatype); - try { - enterOuterAlt(_localctx, 1); - { - setState(182); - typebase(); - setState(183); - ((DatatypeContext)_localctx).wordlen = intconstvalue(); - setState(184); - ((DatatypeContext)_localctx).vectorlen = intconstvalue(); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class IntconstvalueContext extends ParserRuleContext { - public TerminalNode IntegerConstant() { return getToken(HybroLangParser.IntegerConstant, 0); } - public ConstinlineContext constinline() { - return getRuleContext(ConstinlineContext.class,0); - } - public IntconstvalueContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_intconstvalue; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterIntconstvalue(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitIntconstvalue(this); - } - } - - public final IntconstvalueContext intconstvalue() throws RecognitionException { - IntconstvalueContext _localctx = new IntconstvalueContext(_ctx, getState()); - enterRule(_localctx, 34, RULE_intconstvalue); - try { - setState(188); - _errHandler.sync(this); - switch (_input.LA(1)) { - case IntegerConstant: - enterOuterAlt(_localctx, 1); - { - setState(186); - match(IntegerConstant); - } - break; - case INLINE: - enterOuterAlt(_localctx, 2); - { - setState(187); - constinline(); - } - break; - default: - throw new NoViableAltException(this); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ConstvalueContext extends ParserRuleContext { - public TerminalNode IntegerConstant() { return getToken(HybroLangParser.IntegerConstant, 0); } - public TerminalNode DecimalFloatingConstant() { return getToken(HybroLangParser.DecimalFloatingConstant, 0); } - public ConstinlineContext constinline() { - return getRuleContext(ConstinlineContext.class,0); - } - public ConstvalueContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_constvalue; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterConstvalue(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitConstvalue(this); - } - } - - public final ConstvalueContext constvalue() throws RecognitionException { - ConstvalueContext _localctx = new ConstvalueContext(_ctx, getState()); - enterRule(_localctx, 36, RULE_constvalue); - try { - setState(193); - _errHandler.sync(this); - switch (_input.LA(1)) { - case IntegerConstant: - enterOuterAlt(_localctx, 1); - { - setState(190); - match(IntegerConstant); - } - break; - case DecimalFloatingConstant: - enterOuterAlt(_localctx, 2); - { - setState(191); - match(DecimalFloatingConstant); - } - break; - case INLINE: - enterOuterAlt(_localctx, 3); - { - setState(192); - constinline(); - } - break; - default: - throw new NoViableAltException(this); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class ConstinlineContext extends ParserRuleContext { - public TerminalNode INLINE() { return getToken(HybroLangParser.INLINE, 0); } - public ConstinlineContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_constinline; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterConstinline(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitConstinline(this); - } - } - - public final ConstinlineContext constinline() throws RecognitionException { - ConstinlineContext _localctx = new ConstinlineContext(_ctx, getState()); - enterRule(_localctx, 38, RULE_constinline); - try { - enterOuterAlt(_localctx, 1); - { - setState(195); - match(INLINE); - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class TypebaseContext extends ParserRuleContext { - public TypebaseContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_typebase; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterTypebase(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitTypebase(this); - } - } - - public final TypebaseContext typebase() throws RecognitionException { - TypebaseContext _localctx = new TypebaseContext(_ctx, getState()); - enterRule(_localctx, 40, RULE_typebase); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(197); - _la = _input.LA(1); - if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 4286578688L) != 0)) ) { - _errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - setState(199); - _errHandler.sync(this); - _la = _input.LA(1); - if (_la==T__31) { - { - setState(198); - match(T__31); - } - } - - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - @SuppressWarnings("CheckReturnValue") - public static class CondOperatorContext extends ParserRuleContext { - public CondOperatorContext(ParserRuleContext parent, int invokingState) { - super(parent, invokingState); - } - @Override public int getRuleIndex() { return RULE_condOperator; } - @Override - public void enterRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).enterCondOperator(this); - } - @Override - public void exitRule(ParseTreeListener listener) { - if ( listener instanceof HybroLangListener ) ((HybroLangListener)listener).exitCondOperator(this); - } - } - - public final CondOperatorContext condOperator() throws RecognitionException { - CondOperatorContext _localctx = new CondOperatorContext(_ctx, getState()); - enterRule(_localctx, 42, RULE_condOperator); - int _la; - try { - enterOuterAlt(_localctx, 1); - { - setState(201); - _la = _input.LA(1); - if ( !((((_la) & ~0x3f) == 0 && ((1L << _la) & 541165879296L) != 0)) ) { - _errHandler.recoverInline(this); - } - else { - if ( _input.LA(1)==Token.EOF ) matchedEOF = true; - _errHandler.reportMatch(this); - consume(); - } - } - } - catch (RecognitionException re) { - _localctx.exception = re; - _errHandler.reportError(this, re); - _errHandler.recover(this, re); - } - finally { - exitRule(); - } - return _localctx; - } - - public boolean sempred(RuleContext _localctx, int ruleIndex, int predIndex) { - switch (ruleIndex) { - case 14: - return unaryexpr_sempred((UnaryexprContext)_localctx, predIndex); - } - return true; - } - private boolean unaryexpr_sempred(UnaryexprContext _localctx, int predIndex) { - switch (predIndex) { - case 0: - return precpred(_ctx, 5); - case 1: - return precpred(_ctx, 4); - case 2: - return precpred(_ctx, 3); - case 3: - return precpred(_ctx, 2); - } - return true; - } - - public static final String _serializedATN = - "\u0004\u0001.\u00cc\u0002\u0000\u0007\u0000\u0002\u0001\u0007\u0001\u0002"+ - "\u0002\u0007\u0002\u0002\u0003\u0007\u0003\u0002\u0004\u0007\u0004\u0002"+ - "\u0005\u0007\u0005\u0002\u0006\u0007\u0006\u0002\u0007\u0007\u0007\u0002"+ - "\b\u0007\b\u0002\t\u0007\t\u0002\n\u0007\n\u0002\u000b\u0007\u000b\u0002"+ - "\f\u0007\f\u0002\r\u0007\r\u0002\u000e\u0007\u000e\u0002\u000f\u0007\u000f"+ - "\u0002\u0010\u0007\u0010\u0002\u0011\u0007\u0011\u0002\u0012\u0007\u0012"+ - "\u0002\u0013\u0007\u0013\u0002\u0014\u0007\u0014\u0002\u0015\u0007\u0015"+ - "\u0001\u0000\u0004\u0000.\b\u0000\u000b\u0000\f\u0000/\u0001\u0001\u0001"+ - "\u0001\u0001\u0001\u0001\u0002\u0001\u0002\u0001\u0002\u0001\u0002\u0001"+ - "\u0003\u0001\u0003\u0001\u0003\u0001\u0003\u0001\u0004\u0001\u0004\u0005"+ - "\u0004?\b\u0004\n\u0004\f\u0004B\t\u0004\u0001\u0004\u0001\u0004\u0003"+ - "\u0004F\b\u0004\u0001\u0004\u0001\u0004\u0001\u0005\u0001\u0005\u0001"+ - "\u0005\u0005\u0005M\b\u0005\n\u0005\f\u0005P\t\u0005\u0001\u0005\u0003"+ - "\u0005S\b\u0005\u0001\u0006\u0001\u0006\u0001\u0006\u0001\u0007\u0001"+ - "\u0007\u0001\u0007\u0005\u0007[\b\u0007\n\u0007\f\u0007^\t\u0007\u0001"+ - "\b\u0001\b\u0001\b\u0001\t\u0005\td\b\t\n\t\f\tg\t\t\u0001\n\u0001\n\u0001"+ - "\n\u0001\n\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ - "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ - "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ - "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b"+ - "\u0001\u000b\u0001\u000b\u0001\u000b\u0001\u000b\u0003\u000b\u0088\b\u000b"+ - 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"\u0000\u0000\u0000\u00a9\u00ac\u0001\u0000\u0000\u0000\u00aa\u00a8\u0001"+ - "\u0000\u0000\u0000\u00aa\u00ab\u0001\u0000\u0000\u0000\u00ab\u001d\u0001"+ - "\u0000\u0000\u0000\u00ac\u00aa\u0001\u0000\u0000\u0000\u00ad\u00ae\u0005"+ - "*\u0000\u0000\u00ae\u00af\u0005\f\u0000\u0000\u00af\u00b0\u0003\u001c"+ - "\u000e\u0000\u00b0\u00b1\u0005\r\u0000\u0000\u00b1\u00b5\u0001\u0000\u0000"+ - "\u0000\u00b2\u00b5\u0003$\u0012\u0000\u00b3\u00b5\u0005*\u0000\u0000\u00b4"+ - "\u00ad\u0001\u0000\u0000\u0000\u00b4\u00b2\u0001\u0000\u0000\u0000\u00b4"+ - "\u00b3\u0001\u0000\u0000\u0000\u00b5\u001f\u0001\u0000\u0000\u0000\u00b6"+ - "\u00b7\u0003(\u0014\u0000\u00b7\u00b8\u0003\"\u0011\u0000\u00b8\u00b9"+ - "\u0003\"\u0011\u0000\u00b9!\u0001\u0000\u0000\u0000\u00ba\u00bd\u0005"+ - "(\u0000\u0000\u00bb\u00bd\u0003&\u0013\u0000\u00bc\u00ba\u0001\u0000\u0000"+ - "\u0000\u00bc\u00bb\u0001\u0000\u0000\u0000\u00bd#\u0001\u0000\u0000\u0000"+ - "\u00be\u00c2\u0005(\u0000\u0000\u00bf\u00c2\u0005\'\u0000\u0000\u00c0"+ - "\u00c2\u0003&\u0013\u0000\u00c1\u00be\u0001\u0000\u0000\u0000\u00c1\u00bf"+ - "\u0001\u0000\u0000\u0000\u00c1\u00c0\u0001\u0000\u0000\u0000\u00c2%\u0001"+ - "\u0000\u0000\u0000\u00c3\u00c4\u0005+\u0000\u0000\u00c4\'\u0001\u0000"+ - "\u0000\u0000\u00c5\u00c7\u0007\u0004\u0000\u0000\u00c6\u00c8\u0005 \u0000"+ - "\u0000\u00c7\u00c6\u0001\u0000\u0000\u0000\u00c7\u00c8\u0001\u0000\u0000"+ - "\u0000\u00c8)\u0001\u0000\u0000\u0000\u00c9\u00ca\u0007\u0005\u0000\u0000"+ - "\u00ca+\u0001\u0000\u0000\u0000\u000f/@ENR\\e\u0087\u0097\u00a8\u00aa"+ - "\u00b4\u00bc\u00c1\u00c7"; - public static final ATN _ATN = - new ATNDeserializer().deserialize(_serializedATN.toCharArray()); - static { - _decisionToDFA = new DFA[_ATN.getNumberOfDecisions()]; - for (int i = 0; i < _ATN.getNumberOfDecisions(); i++) { - _decisionToDFA[i] = new DFA(_ATN.getDecisionState(i), i); - } - } -} \ No newline at end of file From ff03240358a351dd14309d66daa9feadc4a991e4 Mon Sep 17 00:00:00 2001 From: Quentin MELOTTE Date: Wed, 22 Jul 2026 15:53:50 +0200 Subject: [PATCH 5/6] Delete pycache --- __pycache__/H2Utils.cpython-312.pyc | Bin 394 -> 0 bytes __pycache__/SwConfig.cpython-312.pyc | Bin 2594 -> 0 bytes 2 files changed, 0 insertions(+), 0 deletions(-) delete mode 100644 __pycache__/H2Utils.cpython-312.pyc delete mode 100644 __pycache__/SwConfig.cpython-312.pyc diff --git a/__pycache__/H2Utils.cpython-312.pyc b/__pycache__/H2Utils.cpython-312.pyc deleted file mode 100644 index f69dbf9c4fa23244a66e9cc896233d520e53fbbf..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 394 zcmX@j%ge<81Y74`&ny7ak3k$5V1hC}3jrC^8B!Qh7;_k+7*d#87@`;}88w+-f)w~A zGeXsYC>9`Q2I9|NKw>&W30y9Pv4)|Fje%h`RD_YC1f&iOvOv1fKnfE=WhH|qvtN~f zTVhFKjzVftQGStvm4a&V%l|;2$$X2opeQr1sS7?_wC>3dWr73I69=IMJFg_dOI6zdgK-r`CFS>OsXzX%j6 ztUz2W4I~;E?yzuP;Fg_He34uE3X94e7WQ_JMvso5R-ey6X$DQEBB0M0z?xPv6mf&t soIv6ihfQvNN@-52T@f#k3vx~|Kalvq%*e?2nT>&w`!fp@qaauV0N5o`r2qf` diff --git a/__pycache__/SwConfig.cpython-312.pyc b/__pycache__/SwConfig.cpython-312.pyc deleted file mode 100644 index 417185eb10329bd2afaff98cb6ffd6a30aae5eda..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2594 zcmb_eO>7fK6n?Wm_BwHJ0vJM2(WVJ5E+mGCpMZc6@&kfmiJvsoQduqDO>nTi$*fKA z)
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-add;int;16;2;value;aarch64;Fail -add;int;16;4;value;aarch64;Success; -add;int;16;8;value;aarch64;Fail -add;int;16;16;value;aarch64;Fail -add;int;16;32;value;aarch64;Fail -add;int;16;64;value;aarch64;Fail -add;int;16;128;value;aarch64;Fail -add;int;32;1;value;aarch64;Success; -add;int;32;2;value;aarch64;Fail -add;int;32;4;value;aarch64;Success; -add;int;32;8;value;aarch64;Fail -add;int;32;16;value;aarch64;Fail -add;int;32;32;value;aarch64;Fail -add;int;32;64;value;aarch64;Fail -add;int;32;128;value;aarch64;Fail -add;int;64;1;value;aarch64;Success; -add;int;64;2;value;aarch64;Fail -add;int;64;4;value;aarch64;Fail -add;int;64;8;value;aarch64;Fail -add;int;64;16;value;aarch64;Fail -add;int;64;32;value;aarch64;Fail -add;int;64;64;value;aarch64;Fail -add;int;64;128;value;aarch64;Fail -mul;int;8;1;value;aarch64;Success; -mul;int;8;2;value;aarch64;Fail -mul;int;8;4;value;aarch64;Fail -mul;int;8;8;value;aarch64;Fail -mul;int;8;16;value;aarch64;Fail -mul;int;8;32;value;aarch64;Fail -mul;int;8;64;value;aarch64;Fail -mul;int;8;128;value;aarch64;Fail -mul;int;16;1;value;aarch64;Success; -mul;int;16;2;value;aarch64;Fail -mul;int;16;4;value;aarch64;Success; -mul;int;16;8;value;aarch64;Fail -mul;int;16;16;value;aarch64;Fail -mul;int;16;32;value;aarch64;Fail -mul;int;16;64;value;aarch64;Fail -mul;int;16;128;value;aarch64;Fail -mul;int;32;1;value;aarch64;Success; -mul;int;32;2;value;aarch64;Fail -mul;int;32;4;value;aarch64;Success; -mul;int;32;8;value;aarch64;Fail -mul;int;32;16;value;aarch64;Fail -mul;int;32;32;value;aarch64;Fail -mul;int;32;64;value;aarch64;Fail -mul;int;32;128;value;aarch64;Fail -mul;int;64;1;value;aarch64;Success; -mul;int;64;2;value;aarch64;Fail -mul;int;64;4;value;aarch64;Fail -mul;int;64;8;value;aarch64;Fail -mul;int;64;16;value;aarch64;Fail -mul;int;64;32;value;aarch64;Fail -mul;int;64;64;value;aarch64;Fail -mul;int;64;128;value;aarch64;Fail -sub;int;8;1;value;aarch64;Success; -sub;int;8;2;value;aarch64;Fail -sub;int;8;4;value;aarch64;Fail -sub;int;8;8;value;aarch64;Fail -sub;int;8;16;value;aarch64;Fail -sub;int;8;32;value;aarch64;Fail -sub;int;8;64;value;aarch64;Fail -sub;int;8;128;value;aarch64;Fail -sub;int;16;1;value;aarch64;Success; -sub;int;16;2;value;aarch64;Fail -sub;int;16;4;value;aarch64;Success; -sub;int;16;8;value;aarch64;Fail -sub;int;16;16;value;aarch64;Fail -sub;int;16;32;value;aarch64;Fail -sub;int;16;64;value;aarch64;Fail -sub;int;16;128;value;aarch64;Fail -sub;int;32;1;value;aarch64;Success; -sub;int;32;2;value;aarch64;Fail -sub;int;32;4;value;aarch64;Success; -sub;int;32;8;value;aarch64;Fail -sub;int;32;16;value;aarch64;Fail -sub;int;32;32;value;aarch64;Fail -sub;int;32;64;value;aarch64;Fail -sub;int;32;128;value;aarch64;Fail -sub;int;64;1;value;aarch64;Success; -sub;int;64;2;value;aarch64;Success; -sub;int;64;4;value;aarch64;Fail -sub;int;64;8;value;aarch64;Fail -sub;int;64;16;value;aarch64;Fail -sub;int;64;32;value;aarch64;Fail -sub;int;64;64;value;aarch64;Fail -sub;int;64;128;value;aarch64;Fail -div;int;8;1;value;aarch64;Success; -div;int;8;2;value;aarch64;Fail -div;int;8;4;value;aarch64;Fail -div;int;8;8;value;aarch64;Fail -div;int;8;16;value;aarch64;Fail -div;int;8;32;value;aarch64;Fail -div;int;8;64;value;aarch64;Fail -div;int;8;128;value;aarch64;Fail -div;int;16;1;value;aarch64;Success; -div;int;16;2;value;aarch64;Fail -div;int;16;4;value;aarch64;Fail -div;int;16;8;value;aarch64;Fail -div;int;16;16;value;aarch64;Fail -div;int;16;32;value;aarch64;Fail -div;int;16;64;value;aarch64;Fail -div;int;16;128;value;aarch64;Fail -div;int;32;1;value;aarch64;Success; -div;int;32;2;value;aarch64;Fail -div;int;32;4;value;aarch64;Fail -div;int;32;8;value;aarch64;Fail -div;int;32;16;value;aarch64;Fail -div;int;32;32;value;aarch64;Fail -div;int;32;64;value;aarch64;Fail -div;int;32;128;value;aarch64;Fail -div;int;64;1;value;aarch64;Success; -div;int;64;2;value;aarch64;Fail -div;int;64;4;value;aarch64;Fail -div;int;64;8;value;aarch64;Fail -div;int;64;16;value;aarch64;Fail -div;int;64;32;value;aarch64;Fail -div;int;64;64;value;aarch64;Fail -div;int;64;128;value;aarch64;Fail -add;flt;32;1;value;aarch64;Success; -add;flt;32;2;value;aarch64;Fail -add;flt;32;4;value;aarch64;Fail -add;flt;32;8;value;aarch64;Fail -add;flt;32;16;value;aarch64;Fail -add;flt;32;32;value;aarch64;Fail -add;flt;32;64;value;aarch64;Fail -add;flt;32;128;value;aarch64;Fail -add;flt;64;1;value;aarch64;Success; -add;flt;64;2;value;aarch64;Fail -add;flt;64;4;value;aarch64;Fail -add;flt;64;8;value;aarch64;Fail -add;flt;64;16;value;aarch64;Fail -add;flt;64;32;value;aarch64;Fail -add;flt;64;64;value;aarch64;Fail -add;flt;64;128;value;aarch64;Fail -mul;flt;32;1;value;aarch64;Success; -mul;flt;32;2;value;aarch64;Fail -mul;flt;32;4;value;aarch64;Fail -mul;flt;32;8;value;aarch64;Fail -mul;flt;32;16;value;aarch64;Fail -mul;flt;32;32;value;aarch64;Fail -mul;flt;32;64;value;aarch64;Fail -mul;flt;32;128;value;aarch64;Fail -mul;flt;64;1;value;aarch64;Success; -mul;flt;64;2;value;aarch64;Fail -mul;flt;64;4;value;aarch64;Fail -mul;flt;64;8;value;aarch64;Fail -mul;flt;64;16;value;aarch64;Fail -mul;flt;64;32;value;aarch64;Fail -mul;flt;64;64;value;aarch64;Fail -mul;flt;64;128;value;aarch64;Fail -sub;flt;32;1;value;aarch64;Success; -sub;flt;32;2;value;aarch64;Fail -sub;flt;32;4;value;aarch64;Fail -sub;flt;32;8;value;aarch64;Fail -sub;flt;32;16;value;aarch64;Fail -sub;flt;32;32;value;aarch64;Fail -sub;flt;32;64;value;aarch64;Fail -sub;flt;32;128;value;aarch64;Fail -sub;flt;64;1;value;aarch64;Success; -sub;flt;64;2;value;aarch64;Fail -sub;flt;64;4;value;aarch64;Fail -sub;flt;64;8;value;aarch64;Fail -sub;flt;64;16;value;aarch64;Fail -sub;flt;64;32;value;aarch64;Fail -sub;flt;64;64;value;aarch64;Fail -sub;flt;64;128;value;aarch64;Fail -div;flt;32;1;value;aarch64;Success; -div;flt;32;2;value;aarch64;Fail -div;flt;32;4;value;aarch64;Fail -div;flt;32;8;value;aarch64;Fail -div;flt;32;16;value;aarch64;Fail -div;flt;32;32;value;aarch64;Fail -div;flt;32;64;value;aarch64;Fail -div;flt;32;128;value;aarch64;Fail -div;flt;64;1;value;aarch64;Success; -div;flt;64;2;value;aarch64;Fail -div;flt;64;4;value;aarch64;Fail -div;flt;64;8;value;aarch64;Fail -div;flt;64;16;value;aarch64;Fail -div;flt;64;32;value;aarch64;Fail -div;flt;64;64;value;aarch64;Fail -div;flt;64;128;value;aarch64;Fail -mod;int;8;1;value;aarch64;Fail -mod;int;8;2;value;aarch64;Fail -mod;int;8;4;value;aarch64;Fail -mod;int;8;8;value;aarch64;Fail -mod;int;8;16;value;aarch64;Fail -mod;int;8;32;value;aarch64;Fail -mod;int;8;64;value;aarch64;Fail -mod;int;8;128;value;aarch64;Fail -mod;int;16;1;value;aarch64;Fail -mod;int;16;2;value;aarch64;Fail -mod;int;16;4;value;aarch64;Fail -mod;int;16;8;value;aarch64;Fail -mod;int;16;16;value;aarch64;Fail -mod;int;16;32;value;aarch64;Fail -mod;int;16;64;value;aarch64;Fail -mod;int;16;128;value;aarch64;Fail -mod;int;32;1;value;aarch64;Fail -mod;int;32;2;value;aarch64;Fail -mod;int;32;4;value;aarch64;Fail -mod;int;32;8;value;aarch64;Fail -mod;int;32;16;value;aarch64;Fail -mod;int;32;32;value;aarch64;Fail -mod;int;32;64;value;aarch64;Fail -mod;int;32;128;value;aarch64;Fail -mod;int;64;1;value;aarch64;Fail -mod;int;64;2;value;aarch64;Fail -mod;int;64;4;value;aarch64;Fail -mod;int;64;8;value;aarch64;Fail -mod;int;64;16;value;aarch64;Fail -mod;int;64;32;value;aarch64;Fail -mod;int;64;64;value;aarch64;Fail -mod;int;64;128;value;aarch64;Fail -or;int;8;1;value;aarch64;Success; -or;int;8;2;value;aarch64;Fail -or;int;8;4;value;aarch64;Fail -or;int;8;8;value;aarch64;Fail -or;int;8;16;value;aarch64;Fail -or;int;8;32;value;aarch64;Fail -or;int;8;64;value;aarch64;Fail -or;int;8;128;value;aarch64;Fail -or;int;16;1;value;aarch64;Success; -or;int;16;2;value;aarch64;Fail -or;int;16;4;value;aarch64;Success; -or;int;16;8;value;aarch64;Fail -or;int;16;16;value;aarch64;Fail -or;int;16;32;value;aarch64;Fail -or;int;16;64;value;aarch64;Fail -or;int;16;128;value;aarch64;Fail -or;int;32;1;value;aarch64;Success; -or;int;32;2;value;aarch64;Fail -or;int;32;4;value;aarch64;Success; -or;int;32;8;value;aarch64;Fail -or;int;32;16;value;aarch64;Fail -or;int;32;32;value;aarch64;Fail -or;int;32;64;value;aarch64;Fail -or;int;32;128;value;aarch64;Fail -or;int;64;1;value;aarch64;Success; -or;int;64;2;value;aarch64;Fail -or;int;64;4;value;aarch64;Fail -or;int;64;8;value;aarch64;Fail -or;int;64;16;value;aarch64;Fail -or;int;64;32;value;aarch64;Fail -or;int;64;64;value;aarch64;Fail -or;int;64;128;value;aarch64;Fail -and;int;8;1;value;aarch64;Success; -and;int;8;2;value;aarch64;Fail -and;int;8;4;value;aarch64;Fail -and;int;8;8;value;aarch64;Fail -and;int;8;16;value;aarch64;Fail -and;int;8;32;value;aarch64;Fail -and;int;8;64;value;aarch64;Fail -and;int;8;128;value;aarch64;Fail -and;int;16;1;value;aarch64;Success; -and;int;16;2;value;aarch64;Fail -and;int;16;4;value;aarch64;Success; -and;int;16;8;value;aarch64;Fail -and;int;16;16;value;aarch64;Fail -and;int;16;32;value;aarch64;Fail -and;int;16;64;value;aarch64;Fail -and;int;16;128;value;aarch64;Fail -and;int;32;1;value;aarch64;Success; -and;int;32;2;value;aarch64;Fail -and;int;32;4;value;aarch64;Success; -and;int;32;8;value;aarch64;Fail -and;int;32;16;value;aarch64;Fail -and;int;32;32;value;aarch64;Fail -and;int;32;64;value;aarch64;Fail -and;int;32;128;value;aarch64;Fail -and;int;64;1;value;aarch64;Success; -and;int;64;2;value;aarch64;Fail -and;int;64;4;value;aarch64;Fail -and;int;64;8;value;aarch64;Fail -and;int;64;16;value;aarch64;Fail -and;int;64;32;value;aarch64;Fail -and;int;64;64;value;aarch64;Fail -and;int;64;128;value;aarch64;Fail -xor;int;8;1;value;aarch64;Success; -xor;int;8;2;value;aarch64;Fail -xor;int;8;4;value;aarch64;Fail -xor;int;8;8;value;aarch64;Fail -xor;int;8;16;value;aarch64;Fail -xor;int;8;32;value;aarch64;Fail -xor;int;8;64;value;aarch64;Fail -xor;int;8;128;value;aarch64;Fail -xor;int;16;1;value;aarch64;Success; -xor;int;16;2;value;aarch64;Fail -xor;int;16;4;value;aarch64;Success; -xor;int;16;8;value;aarch64;Fail -xor;int;16;16;value;aarch64;Fail -xor;int;16;32;value;aarch64;Fail -xor;int;16;64;value;aarch64;Fail -xor;int;16;128;value;aarch64;Fail -xor;int;32;1;value;aarch64;Success; -xor;int;32;2;value;aarch64;Fail -xor;int;32;4;value;aarch64;Success; -xor;int;32;8;value;aarch64;Fail -xor;int;32;16;value;aarch64;Fail -xor;int;32;32;value;aarch64;Fail -xor;int;32;64;value;aarch64;Fail -xor;int;32;128;value;aarch64;Fail -xor;int;64;1;value;aarch64;Success; -xor;int;64;2;value;aarch64;Fail -xor;int;64;4;value;aarch64;Fail -xor;int;64;8;value;aarch64;Fail -xor;int;64;16;value;aarch64;Fail -xor;int;64;32;value;aarch64;Fail -xor;int;64;64;value;aarch64;Fail -xor;int;64;128;value;aarch64;Fail -sl;int;8;1;value;aarch64;Success; -sl;int;8;2;value;aarch64;Fail -sl;int;8;4;value;aarch64;Fail -sl;int;8;8;value;aarch64;Fail -sl;int;8;16;value;aarch64;Fail -sl;int;8;32;value;aarch64;Fail -sl;int;8;64;value;aarch64;Fail -sl;int;8;128;value;aarch64;Fail -sl;int;16;1;value;aarch64;Success; -sl;int;16;2;value;aarch64;Fail -sl;int;16;4;value;aarch64;Fail -sl;int;16;8;value;aarch64;Fail -sl;int;16;16;value;aarch64;Fail -sl;int;16;32;value;aarch64;Fail -sl;int;16;64;value;aarch64;Fail -sl;int;16;128;value;aarch64;Fail -sl;int;32;1;value;aarch64;Success; -sl;int;32;2;value;aarch64;Fail -sl;int;32;4;value;aarch64;Fail -sl;int;32;8;value;aarch64;Fail -sl;int;32;16;value;aarch64;Fail -sl;int;32;32;value;aarch64;Fail -sl;int;32;64;value;aarch64;Fail -sl;int;32;128;value;aarch64;Fail -sl;int;64;1;value;aarch64;Success; -sl;int;64;2;value;aarch64;Fail -sl;int;64;4;value;aarch64;Fail -sl;int;64;8;value;aarch64;Fail -sl;int;64;16;value;aarch64;Fail -sl;int;64;32;value;aarch64;Fail -sl;int;64;64;value;aarch64;Fail -sl;int;64;128;value;aarch64;Fail -sr;int;8;1;value;aarch64;Success; -sr;int;8;2;value;aarch64;Fail -sr;int;8;4;value;aarch64;Fail -sr;int;8;8;value;aarch64;Fail -sr;int;8;16;value;aarch64;Fail -sr;int;8;32;value;aarch64;Fail -sr;int;8;64;value;aarch64;Fail -sr;int;8;128;value;aarch64;Fail -sr;int;16;1;value;aarch64;Success; -sr;int;16;2;value;aarch64;Fail -sr;int;16;4;value;aarch64;Fail -sr;int;16;8;value;aarch64;Fail -sr;int;16;16;value;aarch64;Fail -sr;int;16;32;value;aarch64;Fail -sr;int;16;64;value;aarch64;Fail -sr;int;16;128;value;aarch64;Fail -sr;int;32;1;value;aarch64;Success; -sr;int;32;2;value;aarch64;Fail -sr;int;32;4;value;aarch64;Fail -sr;int;32;8;value;aarch64;Fail -sr;int;32;16;value;aarch64;Fail -sr;int;32;32;value;aarch64;Fail -sr;int;32;64;value;aarch64;Fail -sr;int;32;128;value;aarch64;Fail -sr;int;64;1;value;aarch64;Success; -sr;int;64;2;value;aarch64;Fail -sr;int;64;4;value;aarch64;Fail -sr;int;64;8;value;aarch64;Fail -sr;int;64;16;value;aarch64;Fail -sr;int;64;32;value;aarch64;Fail -sr;int;64;64;value;aarch64;Fail -sr;int;64;128;value;aarch64;Fail -add;int;8;1;value;riscv;Success; -add;int;8;2;value;riscv;Fail -add;int;8;4;value;riscv;Fail -add;int;8;8;value;riscv;Fail -add;int;8;16;value;riscv;Fail -add;int;8;32;value;riscv;Fail -add;int;8;64;value;riscv;Fail -add;int;8;128;value;riscv;Fail -add;int;16;1;value;riscv;Success; -add;int;16;2;value;riscv;Fail -add;int;16;4;value;riscv;Fail -add;int;16;8;value;riscv;Fail -add;int;16;16;value;riscv;Fail -add;int;16;32;value;riscv;Fail -add;int;16;64;value;riscv;Fail -add;int;16;128;value;riscv;Fail -add;int;32;1;value;riscv;Success; -add;int;32;2;value;riscv;Fail -add;int;32;4;value;riscv;Fail -add;int;32;8;value;riscv;Fail -add;int;32;16;value;riscv;Fail -add;int;32;32;value;riscv;Fail -add;int;32;64;value;riscv;Fail -add;int;32;128;value;riscv;Fail -add;int;64;1;value;riscv;Fail -add;int;64;2;value;riscv;Fail -add;int;64;4;value;riscv;Fail -add;int;64;8;value;riscv;Fail -add;int;64;16;value;riscv;Fail -add;int;64;32;value;riscv;Fail -add;int;64;64;value;riscv;Fail -add;int;64;128;value;riscv;Fail -mul;int;8;1;value;riscv;Success; -mul;int;8;2;value;riscv;Fail -mul;int;8;4;value;riscv;Fail -mul;int;8;8;value;riscv;Fail -mul;int;8;16;value;riscv;Fail -mul;int;8;32;value;riscv;Fail -mul;int;8;64;value;riscv;Fail -mul;int;8;128;value;riscv;Fail -mul;int;16;1;value;riscv;Success; -mul;int;16;2;value;riscv;Fail -mul;int;16;4;value;riscv;Fail -mul;int;16;8;value;riscv;Fail -mul;int;16;16;value;riscv;Fail -mul;int;16;32;value;riscv;Fail -mul;int;16;64;value;riscv;Fail -mul;int;16;128;value;riscv;Fail -mul;int;32;1;value;riscv;Success; -mul;int;32;2;value;riscv;Fail -mul;int;32;4;value;riscv;Fail -mul;int;32;8;value;riscv;Fail -mul;int;32;16;value;riscv;Fail -mul;int;32;32;value;riscv;Fail -mul;int;32;64;value;riscv;Fail -mul;int;32;128;value;riscv;Fail -mul;int;64;1;value;riscv;Fail -mul;int;64;2;value;riscv;Fail -mul;int;64;4;value;riscv;Fail -mul;int;64;8;value;riscv;Fail -mul;int;64;16;value;riscv;Fail -mul;int;64;32;value;riscv;Fail -mul;int;64;64;value;riscv;Fail -mul;int;64;128;value;riscv;Fail -sub;int;8;1;value;riscv;Success; -sub;int;8;2;value;riscv;Fail -sub;int;8;4;value;riscv;Fail -sub;int;8;8;value;riscv;Fail -sub;int;8;16;value;riscv;Fail -sub;int;8;32;value;riscv;Fail -sub;int;8;64;value;riscv;Fail -sub;int;8;128;value;riscv;Fail -sub;int;16;1;value;riscv;Success; -sub;int;16;2;value;riscv;Fail -sub;int;16;4;value;riscv;Fail -sub;int;16;8;value;riscv;Fail -sub;int;16;16;value;riscv;Fail -sub;int;16;32;value;riscv;Fail -sub;int;16;64;value;riscv;Fail -sub;int;16;128;value;riscv;Fail -sub;int;32;1;value;riscv;Success; -sub;int;32;2;value;riscv;Fail -sub;int;32;4;value;riscv;Fail -sub;int;32;8;value;riscv;Fail -sub;int;32;16;value;riscv;Fail -sub;int;32;32;value;riscv;Fail -sub;int;32;64;value;riscv;Fail -sub;int;32;128;value;riscv;Fail -sub;int;64;1;value;riscv;Fail -sub;int;64;2;value;riscv;Fail -sub;int;64;4;value;riscv;Fail -sub;int;64;8;value;riscv;Fail -sub;int;64;16;value;riscv;Fail -sub;int;64;32;value;riscv;Fail -sub;int;64;64;value;riscv;Fail -sub;int;64;128;value;riscv;Fail -div;int;8;1;value;riscv;Success; -div;int;8;2;value;riscv;Fail -div;int;8;4;value;riscv;Fail -div;int;8;8;value;riscv;Fail -div;int;8;16;value;riscv;Fail -div;int;8;32;value;riscv;Fail -div;int;8;64;value;riscv;Fail -div;int;8;128;value;riscv;Fail -div;int;16;1;value;riscv;Success; -div;int;16;2;value;riscv;Fail -div;int;16;4;value;riscv;Fail -div;int;16;8;value;riscv;Fail -div;int;16;16;value;riscv;Fail -div;int;16;32;value;riscv;Fail -div;int;16;64;value;riscv;Fail -div;int;16;128;value;riscv;Fail -div;int;32;1;value;riscv;Success; -div;int;32;2;value;riscv;Fail -div;int;32;4;value;riscv;Fail -div;int;32;8;value;riscv;Fail -div;int;32;16;value;riscv;Fail -div;int;32;32;value;riscv;Fail -div;int;32;64;value;riscv;Fail -div;int;32;128;value;riscv;Fail -div;int;64;1;value;riscv;Fail -div;int;64;2;value;riscv;Fail -div;int;64;4;value;riscv;Fail -div;int;64;8;value;riscv;Fail -div;int;64;16;value;riscv;Fail -div;int;64;32;value;riscv;Fail -div;int;64;64;value;riscv;Fail -div;int;64;128;value;riscv;Fail -add;flt;32;1;value;riscv;Success; -add;flt;32;2;value;riscv;Fail -add;flt;32;4;value;riscv;Fail -add;flt;32;8;value;riscv;Fail -add;flt;32;16;value;riscv;Fail -add;flt;32;32;value;riscv;Fail -add;flt;32;64;value;riscv;Fail -add;flt;32;128;value;riscv;Fail -add;flt;64;1;value;riscv;Success; -add;flt;64;2;value;riscv;Fail -add;flt;64;4;value;riscv;Fail -add;flt;64;8;value;riscv;Fail -add;flt;64;16;value;riscv;Fail -add;flt;64;32;value;riscv;Fail -add;flt;64;64;value;riscv;Fail -add;flt;64;128;value;riscv;Fail -mul;flt;32;1;value;riscv;Success; -mul;flt;32;2;value;riscv;Fail -mul;flt;32;4;value;riscv;Fail -mul;flt;32;8;value;riscv;Fail -mul;flt;32;16;value;riscv;Fail -mul;flt;32;32;value;riscv;Fail -mul;flt;32;64;value;riscv;Fail -mul;flt;32;128;value;riscv;Fail -mul;flt;64;1;value;riscv;Fail -mul;flt;64;2;value;riscv;Fail -mul;flt;64;4;value;riscv;Fail -mul;flt;64;8;value;riscv;Fail -mul;flt;64;16;value;riscv;Fail -mul;flt;64;32;value;riscv;Fail -mul;flt;64;64;value;riscv;Fail -mul;flt;64;128;value;riscv;Fail -sub;flt;32;1;value;riscv;Success; -sub;flt;32;2;value;riscv;Fail -sub;flt;32;4;value;riscv;Fail -sub;flt;32;8;value;riscv;Fail -sub;flt;32;16;value;riscv;Fail -sub;flt;32;32;value;riscv;Fail -sub;flt;32;64;value;riscv;Fail -sub;flt;32;128;value;riscv;Fail -sub;flt;64;1;value;riscv;Fail -sub;flt;64;2;value;riscv;Fail -sub;flt;64;4;value;riscv;Fail -sub;flt;64;8;value;riscv;Fail -sub;flt;64;16;value;riscv;Fail -sub;flt;64;32;value;riscv;Fail -sub;flt;64;64;value;riscv;Fail -sub;flt;64;128;value;riscv;Fail -div;flt;32;1;value;riscv;Success; -div;flt;32;2;value;riscv;Fail -div;flt;32;4;value;riscv;Fail -div;flt;32;8;value;riscv;Fail -div;flt;32;16;value;riscv;Fail -div;flt;32;32;value;riscv;Fail -div;flt;32;64;value;riscv;Fail -div;flt;32;128;value;riscv;Fail -div;flt;64;1;value;riscv;Success; -div;flt;64;2;value;riscv;Fail -div;flt;64;4;value;riscv;Fail -div;flt;64;8;value;riscv;Fail -div;flt;64;16;value;riscv;Fail -div;flt;64;32;value;riscv;Fail -div;flt;64;64;value;riscv;Fail -div;flt;64;128;value;riscv;Fail -mod;int;8;1;value;riscv;Fail -mod;int;8;2;value;riscv;Fail -mod;int;8;4;value;riscv;Fail -mod;int;8;8;value;riscv;Fail -mod;int;8;16;value;riscv;Fail -mod;int;8;32;value;riscv;Fail -mod;int;8;64;value;riscv;Fail -mod;int;8;128;value;riscv;Fail -mod;int;16;1;value;riscv;Fail -mod;int;16;2;value;riscv;Fail -mod;int;16;4;value;riscv;Fail -mod;int;16;8;value;riscv;Fail -mod;int;16;16;value;riscv;Fail -mod;int;16;32;value;riscv;Fail -mod;int;16;64;value;riscv;Fail -mod;int;16;128;value;riscv;Fail -mod;int;32;1;value;riscv;Fail -mod;int;32;2;value;riscv;Fail -mod;int;32;4;value;riscv;Fail -mod;int;32;8;value;riscv;Fail -mod;int;32;16;value;riscv;Fail -mod;int;32;32;value;riscv;Fail -mod;int;32;64;value;riscv;Fail -mod;int;32;128;value;riscv;Fail -mod;int;64;1;value;riscv;Fail -mod;int;64;2;value;riscv;Fail -mod;int;64;4;value;riscv;Fail -mod;int;64;8;value;riscv;Fail -mod;int;64;16;value;riscv;Fail -mod;int;64;32;value;riscv;Fail -mod;int;64;64;value;riscv;Fail -mod;int;64;128;value;riscv;Fail -or;int;8;1;value;riscv;Success; -or;int;8;2;value;riscv;Fail -or;int;8;4;value;riscv;Fail -or;int;8;8;value;riscv;Fail -or;int;8;16;value;riscv;Fail -or;int;8;32;value;riscv;Fail -or;int;8;64;value;riscv;Fail -or;int;8;128;value;riscv;Fail -or;int;16;1;value;riscv;Success; -or;int;16;2;value;riscv;Fail -or;int;16;4;value;riscv;Fail -or;int;16;8;value;riscv;Fail -or;int;16;16;value;riscv;Fail -or;int;16;32;value;riscv;Fail -or;int;16;64;value;riscv;Fail -or;int;16;128;value;riscv;Fail -or;int;32;1;value;riscv;Success; -or;int;32;2;value;riscv;Fail -or;int;32;4;value;riscv;Fail -or;int;32;8;value;riscv;Fail -or;int;32;16;value;riscv;Fail -or;int;32;32;value;riscv;Fail -or;int;32;64;value;riscv;Fail -or;int;32;128;value;riscv;Fail -or;int;64;1;value;riscv;Fail -or;int;64;2;value;riscv;Fail -or;int;64;4;value;riscv;Fail -or;int;64;8;value;riscv;Fail -or;int;64;16;value;riscv;Fail -or;int;64;32;value;riscv;Fail -or;int;64;64;value;riscv;Fail -or;int;64;128;value;riscv;Fail -and;int;8;1;value;riscv;Success; -and;int;8;2;value;riscv;Fail -and;int;8;4;value;riscv;Fail -and;int;8;8;value;riscv;Fail -and;int;8;16;value;riscv;Fail -and;int;8;32;value;riscv;Fail -and;int;8;64;value;riscv;Fail -and;int;8;128;value;riscv;Fail -and;int;16;1;value;riscv;Success; -and;int;16;2;value;riscv;Fail -and;int;16;4;value;riscv;Fail -and;int;16;8;value;riscv;Fail -and;int;16;16;value;riscv;Fail -and;int;16;32;value;riscv;Fail -and;int;16;64;value;riscv;Fail -and;int;16;128;value;riscv;Fail -and;int;32;1;value;riscv;Success; -and;int;32;2;value;riscv;Fail -and;int;32;4;value;riscv;Fail -and;int;32;8;value;riscv;Fail -and;int;32;16;value;riscv;Fail -and;int;32;32;value;riscv;Fail -and;int;32;64;value;riscv;Fail -and;int;32;128;value;riscv;Fail -and;int;64;1;value;riscv;Fail -and;int;64;2;value;riscv;Fail -and;int;64;4;value;riscv;Fail -and;int;64;8;value;riscv;Fail -and;int;64;16;value;riscv;Fail -and;int;64;32;value;riscv;Fail -and;int;64;64;value;riscv;Fail -and;int;64;128;value;riscv;Fail -xor;int;8;1;value;riscv;Success; -xor;int;8;2;value;riscv;Fail -xor;int;8;4;value;riscv;Fail -xor;int;8;8;value;riscv;Fail -xor;int;8;16;value;riscv;Fail -xor;int;8;32;value;riscv;Fail -xor;int;8;64;value;riscv;Fail -xor;int;8;128;value;riscv;Fail -xor;int;16;1;value;riscv;Success; -xor;int;16;2;value;riscv;Fail -xor;int;16;4;value;riscv;Fail -xor;int;16;8;value;riscv;Fail -xor;int;16;16;value;riscv;Fail -xor;int;16;32;value;riscv;Fail -xor;int;16;64;value;riscv;Fail -xor;int;16;128;value;riscv;Fail -xor;int;32;1;value;riscv;Success; -xor;int;32;2;value;riscv;Fail -xor;int;32;4;value;riscv;Fail -xor;int;32;8;value;riscv;Fail -xor;int;32;16;value;riscv;Fail -xor;int;32;32;value;riscv;Fail -xor;int;32;64;value;riscv;Fail -xor;int;32;128;value;riscv;Fail -xor;int;64;1;value;riscv;Fail -xor;int;64;2;value;riscv;Fail -xor;int;64;4;value;riscv;Fail -xor;int;64;8;value;riscv;Fail -xor;int;64;16;value;riscv;Fail -xor;int;64;32;value;riscv;Fail -xor;int;64;64;value;riscv;Fail -xor;int;64;128;value;riscv;Fail -sl;int;8;1;value;riscv;Success; -sl;int;8;2;value;riscv;Fail -sl;int;8;4;value;riscv;Fail -sl;int;8;8;value;riscv;Fail -sl;int;8;16;value;riscv;Fail -sl;int;8;32;value;riscv;Fail -sl;int;8;64;value;riscv;Fail -sl;int;8;128;value;riscv;Fail -sl;int;16;1;value;riscv;Success; -sl;int;16;2;value;riscv;Fail -sl;int;16;4;value;riscv;Fail -sl;int;16;8;value;riscv;Fail -sl;int;16;16;value;riscv;Fail -sl;int;16;32;value;riscv;Fail -sl;int;16;64;value;riscv;Fail -sl;int;16;128;value;riscv;Fail -sl;int;32;1;value;riscv;Success; -sl;int;32;2;value;riscv;Fail -sl;int;32;4;value;riscv;Fail -sl;int;32;8;value;riscv;Fail -sl;int;32;16;value;riscv;Fail -sl;int;32;32;value;riscv;Fail -sl;int;32;64;value;riscv;Fail -sl;int;32;128;value;riscv;Fail -sl;int;64;1;value;riscv;Fail -sl;int;64;2;value;riscv;Fail -sl;int;64;4;value;riscv;Fail -sl;int;64;8;value;riscv;Fail -sl;int;64;16;value;riscv;Fail -sl;int;64;32;value;riscv;Fail -sl;int;64;64;value;riscv;Fail -sl;int;64;128;value;riscv;Fail -sr;int;8;1;value;riscv;Success; -sr;int;8;2;value;riscv;Fail -sr;int;8;4;value;riscv;Fail -sr;int;8;8;value;riscv;Fail -sr;int;8;16;value;riscv;Fail -sr;int;8;32;value;riscv;Fail -sr;int;8;64;value;riscv;Fail -sr;int;8;128;value;riscv;Fail -sr;int;16;1;value;riscv;Success; -sr;int;16;2;value;riscv;Fail -sr;int;16;4;value;riscv;Fail -sr;int;16;8;value;riscv;Fail -sr;int;16;16;value;riscv;Fail -sr;int;16;32;value;riscv;Fail -sr;int;16;64;value;riscv;Fail -sr;int;16;128;value;riscv;Fail -sr;int;32;1;value;riscv;Success; -sr;int;32;2;value;riscv;Fail -sr;int;32;4;value;riscv;Fail -sr;int;32;8;value;riscv;Fail -sr;int;32;16;value;riscv;Fail -sr;int;32;32;value;riscv;Fail -sr;int;32;64;value;riscv;Fail -sr;int;32;128;value;riscv;Fail -sr;int;64;1;value;riscv;Fail -sr;int;64;2;value;riscv;Fail -sr;int;64;4;value;riscv;Fail -sr;int;64;8;value;riscv;Fail -sr;int;64;16;value;riscv;Fail -sr;int;64;32;value;riscv;Fail -sr;int;64;64;value;riscv;Fail -sr;int;64;128;value;riscv;Fail -add;int;8;1;value;power;Success; -add;int;8;2;value;power;Fail -add;int;8;4;value;power;Fail -add;int;8;8;value;power;Fail -add;int;8;16;value;power;Fail -add;int;8;32;value;power;Fail -add;int;8;64;value;power;Fail -add;int;8;128;value;power;Fail -add;int;16;1;value;power;Success; -add;int;16;2;value;power;Fail -add;int;16;4;value;power;Fail -add;int;16;8;value;power;Fail -add;int;16;16;value;power;Fail -add;int;16;32;value;power;Fail -add;int;16;64;value;power;Fail -add;int;16;128;value;power;Fail -add;int;32;1;value;power;Success; -add;int;32;2;value;power;Fail -add;int;32;4;value;power;Fail -add;int;32;8;value;power;Fail -add;int;32;16;value;power;Fail -add;int;32;32;value;power;Fail -add;int;32;64;value;power;Fail -add;int;32;128;value;power;Fail -add;int;64;1;value;power;Fail -add;int;64;2;value;power;Fail -add;int;64;4;value;power;Fail -add;int;64;8;value;power;Fail -add;int;64;16;value;power;Fail -add;int;64;32;value;power;Fail -add;int;64;64;value;power;Fail -add;int;64;128;value;power;Fail -mul;int;8;1;value;power;Success; -mul;int;8;2;value;power;Fail -mul;int;8;4;value;power;Fail -mul;int;8;8;value;power;Fail -mul;int;8;16;value;power;Fail -mul;int;8;32;value;power;Fail -mul;int;8;64;value;power;Fail -mul;int;8;128;value;power;Fail -mul;int;16;1;value;power;Success; -mul;int;16;2;value;power;Fail -mul;int;16;4;value;power;Fail -mul;int;16;8;value;power;Fail -mul;int;16;16;value;power;Fail -mul;int;16;32;value;power;Fail -mul;int;16;64;value;power;Fail -mul;int;16;128;value;power;Fail -mul;int;32;1;value;power;Success; -mul;int;32;2;value;power;Fail -mul;int;32;4;value;power;Fail -mul;int;32;8;value;power;Fail -mul;int;32;16;value;power;Fail -mul;int;32;32;value;power;Fail -mul;int;32;64;value;power;Fail -mul;int;32;128;value;power;Fail -mul;int;64;1;value;power;Fail -mul;int;64;2;value;power;Fail -mul;int;64;4;value;power;Fail -mul;int;64;8;value;power;Fail -mul;int;64;16;value;power;Fail -mul;int;64;32;value;power;Fail -mul;int;64;64;value;power;Fail -mul;int;64;128;value;power;Fail -sub;int;8;1;value;power;Success; -sub;int;8;2;value;power;Fail -sub;int;8;4;value;power;Fail -sub;int;8;8;value;power;Fail -sub;int;8;16;value;power;Fail -sub;int;8;32;value;power;Fail -sub;int;8;64;value;power;Fail -sub;int;8;128;value;power;Fail -sub;int;16;1;value;power;Success; -sub;int;16;2;value;power;Fail -sub;int;16;4;value;power;Fail -sub;int;16;8;value;power;Fail -sub;int;16;16;value;power;Fail -sub;int;16;32;value;power;Fail -sub;int;16;64;value;power;Fail -sub;int;16;128;value;power;Fail -sub;int;32;1;value;power;Success; -sub;int;32;2;value;power;Fail -sub;int;32;4;value;power;Fail -sub;int;32;8;value;power;Fail -sub;int;32;16;value;power;Fail -sub;int;32;32;value;power;Fail -sub;int;32;64;value;power;Fail -sub;int;32;128;value;power;Fail -sub;int;64;1;value;power;Fail -sub;int;64;2;value;power;Fail -sub;int;64;4;value;power;Fail -sub;int;64;8;value;power;Fail -sub;int;64;16;value;power;Fail -sub;int;64;32;value;power;Fail -sub;int;64;64;value;power;Fail -sub;int;64;128;value;power;Fail -div;int;8;1;value;power;Success; -div;int;8;2;value;power;Fail -div;int;8;4;value;power;Fail -div;int;8;8;value;power;Fail -div;int;8;16;value;power;Fail -div;int;8;32;value;power;Fail -div;int;8;64;value;power;Fail -div;int;8;128;value;power;Fail -div;int;16;1;value;power;Success; -div;int;16;2;value;power;Fail -div;int;16;4;value;power;Fail -div;int;16;8;value;power;Fail -div;int;16;16;value;power;Fail -div;int;16;32;value;power;Fail -div;int;16;64;value;power;Fail -div;int;16;128;value;power;Fail -div;int;32;1;value;power;Success; -div;int;32;2;value;power;Fail -div;int;32;4;value;power;Fail -div;int;32;8;value;power;Fail -div;int;32;16;value;power;Fail -div;int;32;32;value;power;Fail -div;int;32;64;value;power;Fail -div;int;32;128;value;power;Fail -div;int;64;1;value;power;Fail -div;int;64;2;value;power;Fail -div;int;64;4;value;power;Fail -div;int;64;8;value;power;Fail -div;int;64;16;value;power;Fail -div;int;64;32;value;power;Fail -div;int;64;64;value;power;Fail -div;int;64;128;value;power;Fail -add;flt;32;1;value;power;Success; -add;flt;32;2;value;power;Fail -add;flt;32;4;value;power;Fail -add;flt;32;8;value;power;Fail -add;flt;32;16;value;power;Fail -add;flt;32;32;value;power;Fail -add;flt;32;64;value;power;Fail -add;flt;32;128;value;power;Fail -add;flt;64;1;value;power;Success; -add;flt;64;2;value;power;Fail -add;flt;64;4;value;power;Fail -add;flt;64;8;value;power;Fail -add;flt;64;16;value;power;Fail -add;flt;64;32;value;power;Fail -add;flt;64;64;value;power;Fail -add;flt;64;128;value;power;Fail -mul;flt;32;1;value;power;Success; -mul;flt;32;2;value;power;Fail -mul;flt;32;4;value;power;Fail -mul;flt;32;8;value;power;Fail -mul;flt;32;16;value;power;Fail -mul;flt;32;32;value;power;Fail -mul;flt;32;64;value;power;Fail -mul;flt;32;128;value;power;Fail -mul;flt;64;1;value;power;Success; -mul;flt;64;2;value;power;Fail -mul;flt;64;4;value;power;Fail -mul;flt;64;8;value;power;Fail -mul;flt;64;16;value;power;Fail -mul;flt;64;32;value;power;Fail -mul;flt;64;64;value;power;Fail -mul;flt;64;128;value;power;Fail -sub;flt;32;1;value;power;Success; -sub;flt;32;2;value;power;Fail -sub;flt;32;4;value;power;Fail -sub;flt;32;8;value;power;Fail -sub;flt;32;16;value;power;Fail -sub;flt;32;32;value;power;Fail -sub;flt;32;64;value;power;Fail -sub;flt;32;128;value;power;Fail -sub;flt;64;1;value;power;Success; -sub;flt;64;2;value;power;Fail -sub;flt;64;4;value;power;Fail -sub;flt;64;8;value;power;Fail -sub;flt;64;16;value;power;Fail -sub;flt;64;32;value;power;Fail -sub;flt;64;64;value;power;Fail -sub;flt;64;128;value;power;Fail -div;flt;32;1;value;power;Success; -div;flt;32;2;value;power;Fail -div;flt;32;4;value;power;Fail -div;flt;32;8;value;power;Fail -div;flt;32;16;value;power;Fail -div;flt;32;32;value;power;Fail -div;flt;32;64;value;power;Fail -div;flt;32;128;value;power;Fail -div;flt;64;1;value;power;Success; -div;flt;64;2;value;power;Fail -div;flt;64;4;value;power;Fail -div;flt;64;8;value;power;Fail -div;flt;64;16;value;power;Fail -div;flt;64;32;value;power;Fail -div;flt;64;64;value;power;Fail -div;flt;64;128;value;power;Fail -mod;int;8;1;value;power;Fail -mod;int;8;2;value;power;Fail -mod;int;8;4;value;power;Fail -mod;int;8;8;value;power;Fail -mod;int;8;16;value;power;Fail -mod;int;8;32;value;power;Fail -mod;int;8;64;value;power;Fail -mod;int;8;128;value;power;Fail -mod;int;16;1;value;power;Fail -mod;int;16;2;value;power;Fail -mod;int;16;4;value;power;Fail -mod;int;16;8;value;power;Fail -mod;int;16;16;value;power;Fail -mod;int;16;32;value;power;Fail -mod;int;16;64;value;power;Fail -mod;int;16;128;value;power;Fail -mod;int;32;1;value;power;Fail -mod;int;32;2;value;power;Fail -mod;int;32;4;value;power;Fail -mod;int;32;8;value;power;Fail -mod;int;32;16;value;power;Fail -mod;int;32;32;value;power;Fail -mod;int;32;64;value;power;Fail -mod;int;32;128;value;power;Fail -mod;int;64;1;value;power;Fail -mod;int;64;2;value;power;Fail -mod;int;64;4;value;power;Fail -mod;int;64;8;value;power;Fail -mod;int;64;16;value;power;Fail -mod;int;64;32;value;power;Fail -mod;int;64;64;value;power;Fail -mod;int;64;128;value;power;Fail -or;int;8;1;value;power;Success; -or;int;8;2;value;power;Fail -or;int;8;4;value;power;Fail -or;int;8;8;value;power;Fail -or;int;8;16;value;power;Fail -or;int;8;32;value;power;Fail -or;int;8;64;value;power;Fail -or;int;8;128;value;power;Fail -or;int;16;1;value;power;Success; -or;int;16;2;value;power;Fail -or;int;16;4;value;power;Fail -or;int;16;8;value;power;Fail -or;int;16;16;value;power;Fail -or;int;16;32;value;power;Fail -or;int;16;64;value;power;Fail -or;int;16;128;value;power;Fail -or;int;32;1;value;power;Success; -or;int;32;2;value;power;Fail -or;int;32;4;value;power;Fail -or;int;32;8;value;power;Fail -or;int;32;16;value;power;Fail -or;int;32;32;value;power;Fail -or;int;32;64;value;power;Fail -or;int;32;128;value;power;Fail -or;int;64;1;value;power;Fail -or;int;64;2;value;power;Fail -or;int;64;4;value;power;Fail -or;int;64;8;value;power;Fail -or;int;64;16;value;power;Fail -or;int;64;32;value;power;Fail -or;int;64;64;value;power;Fail -or;int;64;128;value;power;Fail -and;int;8;1;value;power;Success; -and;int;8;2;value;power;Fail -and;int;8;4;value;power;Fail -and;int;8;8;value;power;Fail -and;int;8;16;value;power;Fail -and;int;8;32;value;power;Fail -and;int;8;64;value;power;Fail -and;int;8;128;value;power;Fail -and;int;16;1;value;power;Success; -and;int;16;2;value;power;Fail -and;int;16;4;value;power;Fail -and;int;16;8;value;power;Fail -and;int;16;16;value;power;Fail -and;int;16;32;value;power;Fail -and;int;16;64;value;power;Fail -and;int;16;128;value;power;Fail -and;int;32;1;value;power;Success; -and;int;32;2;value;power;Fail -and;int;32;4;value;power;Fail -and;int;32;8;value;power;Fail -and;int;32;16;value;power;Fail -and;int;32;32;value;power;Fail -and;int;32;64;value;power;Fail -and;int;32;128;value;power;Fail -and;int;64;1;value;power;Fail -and;int;64;2;value;power;Fail -and;int;64;4;value;power;Fail -and;int;64;8;value;power;Fail -and;int;64;16;value;power;Fail -and;int;64;32;value;power;Fail -and;int;64;64;value;power;Fail -and;int;64;128;value;power;Fail -xor;int;8;1;value;power;Success; -xor;int;8;2;value;power;Fail -xor;int;8;4;value;power;Fail -xor;int;8;8;value;power;Fail -xor;int;8;16;value;power;Fail -xor;int;8;32;value;power;Fail -xor;int;8;64;value;power;Fail -xor;int;8;128;value;power;Fail -xor;int;16;1;value;power;Success; -xor;int;16;2;value;power;Fail -xor;int;16;4;value;power;Fail -xor;int;16;8;value;power;Fail -xor;int;16;16;value;power;Fail -xor;int;16;32;value;power;Fail -xor;int;16;64;value;power;Fail -xor;int;16;128;value;power;Fail -xor;int;32;1;value;power;Success; -xor;int;32;2;value;power;Fail -xor;int;32;4;value;power;Fail -xor;int;32;8;value;power;Fail -xor;int;32;16;value;power;Fail -xor;int;32;32;value;power;Fail -xor;int;32;64;value;power;Fail -xor;int;32;128;value;power;Fail -xor;int;64;1;value;power;Fail -xor;int;64;2;value;power;Fail -xor;int;64;4;value;power;Fail -xor;int;64;8;value;power;Fail -xor;int;64;16;value;power;Fail -xor;int;64;32;value;power;Fail -xor;int;64;64;value;power;Fail -xor;int;64;128;value;power;Fail -sl;int;8;1;value;power;Success; -sl;int;8;2;value;power;Fail -sl;int;8;4;value;power;Fail -sl;int;8;8;value;power;Fail -sl;int;8;16;value;power;Fail -sl;int;8;32;value;power;Fail -sl;int;8;64;value;power;Fail -sl;int;8;128;value;power;Fail -sl;int;16;1;value;power;Success; -sl;int;16;2;value;power;Fail -sl;int;16;4;value;power;Fail -sl;int;16;8;value;power;Fail -sl;int;16;16;value;power;Fail -sl;int;16;32;value;power;Fail -sl;int;16;64;value;power;Fail -sl;int;16;128;value;power;Fail -sl;int;32;1;value;power;Success; -sl;int;32;2;value;power;Fail -sl;int;32;4;value;power;Fail -sl;int;32;8;value;power;Fail -sl;int;32;16;value;power;Fail -sl;int;32;32;value;power;Fail -sl;int;32;64;value;power;Fail -sl;int;32;128;value;power;Fail -sl;int;64;1;value;power;Fail -sl;int;64;2;value;power;Fail -sl;int;64;4;value;power;Fail -sl;int;64;8;value;power;Fail -sl;int;64;16;value;power;Fail -sl;int;64;32;value;power;Fail -sl;int;64;64;value;power;Fail -sl;int;64;128;value;power;Fail -sr;int;8;1;value;power;Fail -sr;int;8;2;value;power;Fail -sr;int;8;4;value;power;Fail -sr;int;8;8;value;power;Fail -sr;int;8;16;value;power;Fail -sr;int;8;32;value;power;Fail -sr;int;8;64;value;power;Fail -sr;int;8;128;value;power;Fail -sr;int;16;1;value;power;Fail -sr;int;16;2;value;power;Fail -sr;int;16;4;value;power;Fail -sr;int;16;8;value;power;Fail -sr;int;16;16;value;power;Fail -sr;int;16;32;value;power;Fail -sr;int;16;64;value;power;Fail -sr;int;16;128;value;power;Fail -sr;int;32;1;value;power;Fail -sr;int;32;2;value;power;Fail -sr;int;32;4;value;power;Fail -sr;int;32;8;value;power;Fail -sr;int;32;16;value;power;Fail -sr;int;32;32;value;power;Fail -sr;int;32;64;value;power;Fail -sr;int;32;128;value;power;Fail -sr;int;64;1;value;power;Fail -sr;int;64;2;value;power;Fail -sr;int;64;4;value;power;Fail -sr;int;64;8;value;power;Fail -sr;int;64;16;value;power;Fail -sr;int;64;32;value;power;Fail -sr;int;64;64;value;power;Fail -sr;int;64;128;value;power;Fail -add;int;8;1;address;aarch64;Fail -add;int;8;2;address;aarch64;Fail -add;int;8;4;address;aarch64;Fail -add;int;8;8;address;aarch64;Success; -add;int;8;16;address;aarch64;Success; -add;int;8;32;address;aarch64;Fail -add;int;8;64;address;aarch64;Fail -add;int;8;128;address;aarch64;Fail -add;int;16;1;address;aarch64;Fail -add;int;16;2;address;aarch64;Fail -add;int;16;4;address;aarch64;Success; -add;int;16;8;address;aarch64;Success; -add;int;16;16;address;aarch64;Fail -add;int;16;32;address;aarch64;Fail -add;int;16;64;address;aarch64;Fail -add;int;16;128;address;aarch64;Fail -add;int;32;1;address;aarch64;Fail -add;int;32;2;address;aarch64;Success; -add;int;32;4;address;aarch64;Success; -add;int;32;8;address;aarch64;Fail -add;int;32;16;address;aarch64;Fail -add;int;32;32;address;aarch64;Fail -add;int;32;64;address;aarch64;Fail -add;int;32;128;address;aarch64;Fail -add;int;64;1;address;aarch64;Fail -add;int;64;2;address;aarch64;Fail -add;int;64;4;address;aarch64;Fail -add;int;64;8;address;aarch64;Fail -add;int;64;16;address;aarch64;Fail -add;int;64;32;address;aarch64;Fail -add;int;64;64;address;aarch64;Fail -add;int;64;128;address;aarch64;Fail -mul;int;8;1;address;aarch64;Fail -mul;int;8;2;address;aarch64;Fail -mul;int;8;4;address;aarch64;Fail -mul;int;8;8;address;aarch64;Fail -mul;int;8;16;address;aarch64;Fail -mul;int;8;32;address;aarch64;Fail -mul;int;8;64;address;aarch64;Fail -mul;int;8;128;address;aarch64;Fail -mul;int;16;1;address;aarch64;Fail -mul;int;16;2;address;aarch64;Fail -mul;int;16;4;address;aarch64;Success; -mul;int;16;8;address;aarch64;Success; -mul;int;16;16;address;aarch64;Fail -mul;int;16;32;address;aarch64;Fail -mul;int;16;64;address;aarch64;Fail -mul;int;16;128;address;aarch64;Fail -mul;int;32;1;address;aarch64;Fail -mul;int;32;2;address;aarch64;Success; -mul;int;32;4;address;aarch64;Success; -mul;int;32;8;address;aarch64;Fail -mul;int;32;16;address;aarch64;Fail -mul;int;32;32;address;aarch64;Fail -mul;int;32;64;address;aarch64;Fail -mul;int;32;128;address;aarch64;Fail -mul;int;64;1;address;aarch64;Fail -mul;int;64;2;address;aarch64;Fail -mul;int;64;4;address;aarch64;Fail -mul;int;64;8;address;aarch64;Fail -mul;int;64;16;address;aarch64;Fail -mul;int;64;32;address;aarch64;Fail -mul;int;64;64;address;aarch64;Fail -mul;int;64;128;address;aarch64;Fail -sub;int;8;1;address;aarch64;Fail -sub;int;8;2;address;aarch64;Fail -sub;int;8;4;address;aarch64;Fail -sub;int;8;8;address;aarch64;Success; -sub;int;8;16;address;aarch64;Success; -sub;int;8;32;address;aarch64;Fail -sub;int;8;64;address;aarch64;Fail -sub;int;8;128;address;aarch64;Fail -sub;int;16;1;address;aarch64;Fail -sub;int;16;2;address;aarch64;Fail -sub;int;16;4;address;aarch64;Success; -sub;int;16;8;address;aarch64;Success; -sub;int;16;16;address;aarch64;Fail -sub;int;16;32;address;aarch64;Fail -sub;int;16;64;address;aarch64;Fail -sub;int;16;128;address;aarch64;Fail -sub;int;32;1;address;aarch64;Fail -sub;int;32;2;address;aarch64;Success; -sub;int;32;4;address;aarch64;Success; -sub;int;32;8;address;aarch64;Fail -sub;int;32;16;address;aarch64;Fail -sub;int;32;32;address;aarch64;Fail -sub;int;32;64;address;aarch64;Fail -sub;int;32;128;address;aarch64;Fail -sub;int;64;1;address;aarch64;Fail -sub;int;64;2;address;aarch64;Fail -sub;int;64;4;address;aarch64;Fail -sub;int;64;8;address;aarch64;Fail -sub;int;64;16;address;aarch64;Fail -sub;int;64;32;address;aarch64;Fail -sub;int;64;64;address;aarch64;Fail -sub;int;64;128;address;aarch64;Fail -div;int;8;1;address;aarch64;Fail -div;int;8;2;address;aarch64;Fail -div;int;8;4;address;aarch64;Fail -div;int;8;8;address;aarch64;Fail -div;int;8;16;address;aarch64;Fail -div;int;8;32;address;aarch64;Fail -div;int;8;64;address;aarch64;Fail -div;int;8;128;address;aarch64;Fail -div;int;16;1;address;aarch64;Fail -div;int;16;2;address;aarch64;Fail -div;int;16;4;address;aarch64;Fail -div;int;16;8;address;aarch64;Fail -div;int;16;16;address;aarch64;Fail -div;int;16;32;address;aarch64;Fail -div;int;16;64;address;aarch64;Fail -div;int;16;128;address;aarch64;Fail -div;int;32;1;address;aarch64;Fail -div;int;32;2;address;aarch64;Fail -div;int;32;4;address;aarch64;Fail -div;int;32;8;address;aarch64;Fail -div;int;32;16;address;aarch64;Fail -div;int;32;32;address;aarch64;Fail -div;int;32;64;address;aarch64;Fail -div;int;32;128;address;aarch64;Fail -div;int;64;1;address;aarch64;Fail -div;int;64;2;address;aarch64;Fail -div;int;64;4;address;aarch64;Fail -div;int;64;8;address;aarch64;Fail -div;int;64;16;address;aarch64;Fail -div;int;64;32;address;aarch64;Fail -div;int;64;64;address;aarch64;Fail -div;int;64;128;address;aarch64;Fail -add;flt;32;1;address;aarch64;Fail -add;flt;32;2;address;aarch64;Fail -add;flt;32;4;address;aarch64;Fail -add;flt;32;8;address;aarch64;Fail -add;flt;32;16;address;aarch64;Fail -add;flt;32;32;address;aarch64;Fail -add;flt;32;64;address;aarch64;Fail -add;flt;32;128;address;aarch64;Fail -add;flt;64;1;address;aarch64;Fail -add;flt;64;2;address;aarch64;Fail -add;flt;64;4;address;aarch64;Fail -add;flt;64;8;address;aarch64;Fail -add;flt;64;16;address;aarch64;Fail -add;flt;64;32;address;aarch64;Fail -add;flt;64;64;address;aarch64;Fail -add;flt;64;128;address;aarch64;Fail -mul;flt;32;1;address;aarch64;Fail -mul;flt;32;2;address;aarch64;Fail -mul;flt;32;4;address;aarch64;Fail -mul;flt;32;8;address;aarch64;Fail -mul;flt;32;16;address;aarch64;Fail -mul;flt;32;32;address;aarch64;Fail -mul;flt;32;64;address;aarch64;Fail -mul;flt;32;128;address;aarch64;Fail -mul;flt;64;1;address;aarch64;Fail -mul;flt;64;2;address;aarch64;Fail -mul;flt;64;4;address;aarch64;Fail -mul;flt;64;8;address;aarch64;Fail -mul;flt;64;16;address;aarch64;Fail -mul;flt;64;32;address;aarch64;Fail -mul;flt;64;64;address;aarch64;Fail -mul;flt;64;128;address;aarch64;Fail -sub;flt;32;1;address;aarch64;Fail -sub;flt;32;2;address;aarch64;Fail -sub;flt;32;4;address;aarch64;Fail -sub;flt;32;8;address;aarch64;Fail -sub;flt;32;16;address;aarch64;Fail -sub;flt;32;32;address;aarch64;Fail -sub;flt;32;64;address;aarch64;Fail -sub;flt;32;128;address;aarch64;Fail -sub;flt;64;1;address;aarch64;Fail -sub;flt;64;2;address;aarch64;Fail -sub;flt;64;4;address;aarch64;Fail -sub;flt;64;8;address;aarch64;Fail -sub;flt;64;16;address;aarch64;Fail -sub;flt;64;32;address;aarch64;Fail -sub;flt;64;64;address;aarch64;Fail -sub;flt;64;128;address;aarch64;Fail -div;flt;32;1;address;aarch64;Fail -div;flt;32;2;address;aarch64;Fail -div;flt;32;4;address;aarch64;Fail -div;flt;32;8;address;aarch64;Fail -div;flt;32;16;address;aarch64;Fail -div;flt;32;32;address;aarch64;Fail -div;flt;32;64;address;aarch64;Fail -div;flt;32;128;address;aarch64;Fail -div;flt;64;1;address;aarch64;Fail -div;flt;64;2;address;aarch64;Fail -div;flt;64;4;address;aarch64;Fail -div;flt;64;8;address;aarch64;Fail -div;flt;64;16;address;aarch64;Fail -div;flt;64;32;address;aarch64;Fail -div;flt;64;64;address;aarch64;Fail -div;flt;64;128;address;aarch64;Fail -mod;int;8;1;address;aarch64;Fail -mod;int;8;2;address;aarch64;Fail -mod;int;8;4;address;aarch64;Fail -mod;int;8;8;address;aarch64;Fail -mod;int;8;16;address;aarch64;Fail -mod;int;8;32;address;aarch64;Fail -mod;int;8;64;address;aarch64;Fail -mod;int;8;128;address;aarch64;Fail -mod;int;16;1;address;aarch64;Fail -mod;int;16;2;address;aarch64;Fail -mod;int;16;4;address;aarch64;Fail -mod;int;16;8;address;aarch64;Fail -mod;int;16;16;address;aarch64;Fail -mod;int;16;32;address;aarch64;Fail -mod;int;16;64;address;aarch64;Fail -mod;int;16;128;address;aarch64;Fail -mod;int;32;1;address;aarch64;Fail -mod;int;32;2;address;aarch64;Fail -mod;int;32;4;address;aarch64;Fail -mod;int;32;8;address;aarch64;Fail -mod;int;32;16;address;aarch64;Fail -mod;int;32;32;address;aarch64;Fail -mod;int;32;64;address;aarch64;Fail -mod;int;32;128;address;aarch64;Fail -mod;int;64;1;address;aarch64;Fail -mod;int;64;2;address;aarch64;Fail -mod;int;64;4;address;aarch64;Fail -mod;int;64;8;address;aarch64;Fail -mod;int;64;16;address;aarch64;Fail -mod;int;64;32;address;aarch64;Fail -mod;int;64;64;address;aarch64;Fail -mod;int;64;128;address;aarch64;Fail -or;int;8;1;address;aarch64;Fail -or;int;8;2;address;aarch64;Fail -or;int;8;4;address;aarch64;Fail -or;int;8;8;address;aarch64;Success; -or;int;8;16;address;aarch64;Success; -or;int;8;32;address;aarch64;Fail -or;int;8;64;address;aarch64;Fail -or;int;8;128;address;aarch64;Fail -or;int;16;1;address;aarch64;Fail -or;int;16;2;address;aarch64;Fail -or;int;16;4;address;aarch64;Success; -or;int;16;8;address;aarch64;Success; -or;int;16;16;address;aarch64;Fail -or;int;16;32;address;aarch64;Fail -or;int;16;64;address;aarch64;Fail -or;int;16;128;address;aarch64;Fail -or;int;32;1;address;aarch64;Fail -or;int;32;2;address;aarch64;Success; -or;int;32;4;address;aarch64;Success; -or;int;32;8;address;aarch64;Fail -or;int;32;16;address;aarch64;Fail -or;int;32;32;address;aarch64;Fail -or;int;32;64;address;aarch64;Fail -or;int;32;128;address;aarch64;Fail -or;int;64;1;address;aarch64;Fail -or;int;64;2;address;aarch64;Fail -or;int;64;4;address;aarch64;Fail -or;int;64;8;address;aarch64;Fail -or;int;64;16;address;aarch64;Fail -or;int;64;32;address;aarch64;Fail -or;int;64;64;address;aarch64;Fail -or;int;64;128;address;aarch64;Fail -and;int;8;1;address;aarch64;Fail -and;int;8;2;address;aarch64;Fail -and;int;8;4;address;aarch64;Fail -and;int;8;8;address;aarch64;Success; -and;int;8;16;address;aarch64;Success; -and;int;8;32;address;aarch64;Fail -and;int;8;64;address;aarch64;Fail -and;int;8;128;address;aarch64;Fail -and;int;16;1;address;aarch64;Fail -and;int;16;2;address;aarch64;Fail -and;int;16;4;address;aarch64;Success; -and;int;16;8;address;aarch64;Success; -and;int;16;16;address;aarch64;Fail -and;int;16;32;address;aarch64;Fail -and;int;16;64;address;aarch64;Fail -and;int;16;128;address;aarch64;Fail -and;int;32;1;address;aarch64;Fail -and;int;32;2;address;aarch64;Success; -and;int;32;4;address;aarch64;Success; -and;int;32;8;address;aarch64;Fail -and;int;32;16;address;aarch64;Fail -and;int;32;32;address;aarch64;Fail -and;int;32;64;address;aarch64;Fail -and;int;32;128;address;aarch64;Fail -and;int;64;1;address;aarch64;Fail -and;int;64;2;address;aarch64;Fail -and;int;64;4;address;aarch64;Fail -and;int;64;8;address;aarch64;Fail -and;int;64;16;address;aarch64;Fail -and;int;64;32;address;aarch64;Fail -and;int;64;64;address;aarch64;Fail -and;int;64;128;address;aarch64;Fail -xor;int;8;1;address;aarch64;Fail -xor;int;8;2;address;aarch64;Fail -xor;int;8;4;address;aarch64;Fail -xor;int;8;8;address;aarch64;Success; -xor;int;8;16;address;aarch64;Success; -xor;int;8;32;address;aarch64;Fail -xor;int;8;64;address;aarch64;Fail -xor;int;8;128;address;aarch64;Fail -xor;int;16;1;address;aarch64;Fail -xor;int;16;2;address;aarch64;Fail -xor;int;16;4;address;aarch64;Success; -xor;int;16;8;address;aarch64;Success; -xor;int;16;16;address;aarch64;Fail -xor;int;16;32;address;aarch64;Fail -xor;int;16;64;address;aarch64;Fail -xor;int;16;128;address;aarch64;Fail -xor;int;32;1;address;aarch64;Fail -xor;int;32;2;address;aarch64;Success; -xor;int;32;4;address;aarch64;Success; -xor;int;32;8;address;aarch64;Fail -xor;int;32;16;address;aarch64;Fail -xor;int;32;32;address;aarch64;Fail -xor;int;32;64;address;aarch64;Fail -xor;int;32;128;address;aarch64;Fail -xor;int;64;1;address;aarch64;Fail -xor;int;64;2;address;aarch64;Fail -xor;int;64;4;address;aarch64;Fail -xor;int;64;8;address;aarch64;Fail -xor;int;64;16;address;aarch64;Fail -xor;int;64;32;address;aarch64;Fail -xor;int;64;64;address;aarch64;Fail -xor;int;64;128;address;aarch64;Fail -sl;int;8;1;address;aarch64;Fail -sl;int;8;2;address;aarch64;Fail -sl;int;8;4;address;aarch64;Fail -sl;int;8;8;address;aarch64;Fail -sl;int;8;16;address;aarch64;Fail -sl;int;8;32;address;aarch64;Fail -sl;int;8;64;address;aarch64;Fail -sl;int;8;128;address;aarch64;Fail -sl;int;16;1;address;aarch64;Fail -sl;int;16;2;address;aarch64;Fail -sl;int;16;4;address;aarch64;Fail -sl;int;16;8;address;aarch64;Fail -sl;int;16;16;address;aarch64;Fail -sl;int;16;32;address;aarch64;Fail -sl;int;16;64;address;aarch64;Fail -sl;int;16;128;address;aarch64;Fail -sl;int;32;1;address;aarch64;Fail -sl;int;32;2;address;aarch64;Fail -sl;int;32;4;address;aarch64;Fail -sl;int;32;8;address;aarch64;Fail -sl;int;32;16;address;aarch64;Fail -sl;int;32;32;address;aarch64;Fail -sl;int;32;64;address;aarch64;Fail -sl;int;32;128;address;aarch64;Fail -sl;int;64;1;address;aarch64;Fail -sl;int;64;2;address;aarch64;Fail -sl;int;64;4;address;aarch64;Fail -sl;int;64;8;address;aarch64;Fail -sl;int;64;16;address;aarch64;Fail -sl;int;64;32;address;aarch64;Fail -sl;int;64;64;address;aarch64;Fail -sl;int;64;128;address;aarch64;Fail -sr;int;8;1;address;aarch64;Fail -sr;int;8;2;address;aarch64;Fail -sr;int;8;4;address;aarch64;Fail -sr;int;8;8;address;aarch64;Fail -sr;int;8;16;address;aarch64;Fail -sr;int;8;32;address;aarch64;Fail -sr;int;8;64;address;aarch64;Fail -sr;int;8;128;address;aarch64;Fail -sr;int;16;1;address;aarch64;Fail -sr;int;16;2;address;aarch64;Fail -sr;int;16;4;address;aarch64;Fail -sr;int;16;8;address;aarch64;Fail -sr;int;16;16;address;aarch64;Fail -sr;int;16;32;address;aarch64;Fail -sr;int;16;64;address;aarch64;Fail -sr;int;16;128;address;aarch64;Fail -sr;int;32;1;address;aarch64;Fail -sr;int;32;2;address;aarch64;Fail -sr;int;32;4;address;aarch64;Fail -sr;int;32;8;address;aarch64;Fail -sr;int;32;16;address;aarch64;Fail -sr;int;32;32;address;aarch64;Fail -sr;int;32;64;address;aarch64;Fail -sr;int;32;128;address;aarch64;Fail -sr;int;64;1;address;aarch64;Fail -sr;int;64;2;address;aarch64;Fail -sr;int;64;4;address;aarch64;Fail -sr;int;64;8;address;aarch64;Fail -sr;int;64;16;address;aarch64;Fail -sr;int;64;32;address;aarch64;Fail -sr;int;64;64;address;aarch64;Fail -sr;int;64;128;address;aarch64;Fail -add;int;8;1;address;riscv;Fail -add;int;8;2;address;riscv;Fail -add;int;8;4;address;riscv;Fail -add;int;8;8;address;riscv;Fail -add;int;8;16;address;riscv;Fail -add;int;8;32;address;riscv;Fail -add;int;8;64;address;riscv;Fail -add;int;8;128;address;riscv;Fail -add;int;16;1;address;riscv;Fail -add;int;16;2;address;riscv;Fail -add;int;16;4;address;riscv;Fail -add;int;16;8;address;riscv;Fail -add;int;16;16;address;riscv;Fail -add;int;16;32;address;riscv;Fail -add;int;16;64;address;riscv;Fail -add;int;16;128;address;riscv;Fail -add;int;32;1;address;riscv;Fail -add;int;32;2;address;riscv;Fail -add;int;32;4;address;riscv;Fail -add;int;32;8;address;riscv;Fail -add;int;32;16;address;riscv;Fail -add;int;32;32;address;riscv;Fail -add;int;32;64;address;riscv;Fail -add;int;32;128;address;riscv;Fail -add;int;64;1;address;riscv;Fail -add;int;64;2;address;riscv;Fail -add;int;64;4;address;riscv;Fail -add;int;64;8;address;riscv;Fail -add;int;64;16;address;riscv;Fail -add;int;64;32;address;riscv;Fail -add;int;64;64;address;riscv;Fail -add;int;64;128;address;riscv;Fail -mul;int;8;1;address;riscv;Fail -mul;int;8;2;address;riscv;Fail -mul;int;8;4;address;riscv;Fail -mul;int;8;8;address;riscv;Fail -mul;int;8;16;address;riscv;Fail -mul;int;8;32;address;riscv;Fail -mul;int;8;64;address;riscv;Fail -mul;int;8;128;address;riscv;Fail -mul;int;16;1;address;riscv;Fail -mul;int;16;2;address;riscv;Fail -mul;int;16;4;address;riscv;Fail -mul;int;16;8;address;riscv;Fail -mul;int;16;16;address;riscv;Fail -mul;int;16;32;address;riscv;Fail -mul;int;16;64;address;riscv;Fail -mul;int;16;128;address;riscv;Fail -mul;int;32;1;address;riscv;Fail -mul;int;32;2;address;riscv;Fail -mul;int;32;4;address;riscv;Fail -mul;int;32;8;address;riscv;Fail -mul;int;32;16;address;riscv;Fail -mul;int;32;32;address;riscv;Fail -mul;int;32;64;address;riscv;Fail -mul;int;32;128;address;riscv;Fail -mul;int;64;1;address;riscv;Fail -mul;int;64;2;address;riscv;Fail -mul;int;64;4;address;riscv;Fail -mul;int;64;8;address;riscv;Fail -mul;int;64;16;address;riscv;Fail -mul;int;64;32;address;riscv;Fail -mul;int;64;64;address;riscv;Fail -mul;int;64;128;address;riscv;Fail -sub;int;8;1;address;riscv;Fail -sub;int;8;2;address;riscv;Fail -sub;int;8;4;address;riscv;Fail -sub;int;8;8;address;riscv;Fail -sub;int;8;16;address;riscv;Fail -sub;int;8;32;address;riscv;Fail -sub;int;8;64;address;riscv;Fail -sub;int;8;128;address;riscv;Fail -sub;int;16;1;address;riscv;Fail -sub;int;16;2;address;riscv;Fail -sub;int;16;4;address;riscv;Fail -sub;int;16;8;address;riscv;Fail -sub;int;16;16;address;riscv;Fail -sub;int;16;32;address;riscv;Fail -sub;int;16;64;address;riscv;Fail -sub;int;16;128;address;riscv;Fail -sub;int;32;1;address;riscv;Fail -sub;int;32;2;address;riscv;Fail -sub;int;32;4;address;riscv;Fail -sub;int;32;8;address;riscv;Fail -sub;int;32;16;address;riscv;Fail -sub;int;32;32;address;riscv;Fail -sub;int;32;64;address;riscv;Fail -sub;int;32;128;address;riscv;Fail -sub;int;64;1;address;riscv;Fail -sub;int;64;2;address;riscv;Fail -sub;int;64;4;address;riscv;Fail -sub;int;64;8;address;riscv;Fail -sub;int;64;16;address;riscv;Fail -sub;int;64;32;address;riscv;Fail -sub;int;64;64;address;riscv;Fail -sub;int;64;128;address;riscv;Fail -div;int;8;1;address;riscv;Fail -div;int;8;2;address;riscv;Fail -div;int;8;4;address;riscv;Fail -div;int;8;8;address;riscv;Fail -div;int;8;16;address;riscv;Fail -div;int;8;32;address;riscv;Fail -div;int;8;64;address;riscv;Fail -div;int;8;128;address;riscv;Fail -div;int;16;1;address;riscv;Fail -div;int;16;2;address;riscv;Fail -div;int;16;4;address;riscv;Fail -div;int;16;8;address;riscv;Fail -div;int;16;16;address;riscv;Fail -div;int;16;32;address;riscv;Fail -div;int;16;64;address;riscv;Fail -div;int;16;128;address;riscv;Fail -div;int;32;1;address;riscv;Fail -div;int;32;2;address;riscv;Fail -div;int;32;4;address;riscv;Fail -div;int;32;8;address;riscv;Fail -div;int;32;16;address;riscv;Fail -div;int;32;32;address;riscv;Fail -div;int;32;64;address;riscv;Fail -div;int;32;128;address;riscv;Fail -div;int;64;1;address;riscv;Fail -div;int;64;2;address;riscv;Fail -div;int;64;4;address;riscv;Fail -div;int;64;8;address;riscv;Fail -div;int;64;16;address;riscv;Fail -div;int;64;32;address;riscv;Fail -div;int;64;64;address;riscv;Fail -div;int;64;128;address;riscv;Fail -add;flt;32;1;address;riscv;Fail -add;flt;32;2;address;riscv;Fail -add;flt;32;4;address;riscv;Fail -add;flt;32;8;address;riscv;Fail -add;flt;32;16;address;riscv;Fail -add;flt;32;32;address;riscv;Fail -add;flt;32;64;address;riscv;Fail -add;flt;32;128;address;riscv;Fail -add;flt;64;1;address;riscv;Fail -add;flt;64;2;address;riscv;Fail -add;flt;64;4;address;riscv;Fail -add;flt;64;8;address;riscv;Fail -add;flt;64;16;address;riscv;Fail -add;flt;64;32;address;riscv;Fail -add;flt;64;64;address;riscv;Fail -add;flt;64;128;address;riscv;Fail -mul;flt;32;1;address;riscv;Fail -mul;flt;32;2;address;riscv;Fail -mul;flt;32;4;address;riscv;Fail -mul;flt;32;8;address;riscv;Fail -mul;flt;32;16;address;riscv;Fail -mul;flt;32;32;address;riscv;Fail -mul;flt;32;64;address;riscv;Fail -mul;flt;32;128;address;riscv;Fail -mul;flt;64;1;address;riscv;Fail -mul;flt;64;2;address;riscv;Fail -mul;flt;64;4;address;riscv;Fail -mul;flt;64;8;address;riscv;Fail -mul;flt;64;16;address;riscv;Fail -mul;flt;64;32;address;riscv;Fail -mul;flt;64;64;address;riscv;Fail -mul;flt;64;128;address;riscv;Fail -sub;flt;32;1;address;riscv;Fail -sub;flt;32;2;address;riscv;Fail -sub;flt;32;4;address;riscv;Fail -sub;flt;32;8;address;riscv;Fail -sub;flt;32;16;address;riscv;Fail -sub;flt;32;32;address;riscv;Fail -sub;flt;32;64;address;riscv;Fail -sub;flt;32;128;address;riscv;Fail -sub;flt;64;1;address;riscv;Fail -sub;flt;64;2;address;riscv;Fail -sub;flt;64;4;address;riscv;Fail -sub;flt;64;8;address;riscv;Fail -sub;flt;64;16;address;riscv;Fail -sub;flt;64;32;address;riscv;Fail -sub;flt;64;64;address;riscv;Fail -sub;flt;64;128;address;riscv;Fail -div;flt;32;1;address;riscv;Fail -div;flt;32;2;address;riscv;Fail -div;flt;32;4;address;riscv;Fail -div;flt;32;8;address;riscv;Fail -div;flt;32;16;address;riscv;Fail -div;flt;32;32;address;riscv;Fail -div;flt;32;64;address;riscv;Fail -div;flt;32;128;address;riscv;Fail -div;flt;64;1;address;riscv;Fail -div;flt;64;2;address;riscv;Fail -div;flt;64;4;address;riscv;Fail -div;flt;64;8;address;riscv;Fail -div;flt;64;16;address;riscv;Fail -div;flt;64;32;address;riscv;Fail -div;flt;64;64;address;riscv;Fail -div;flt;64;128;address;riscv;Fail -mod;int;8;1;address;riscv;Fail -mod;int;8;2;address;riscv;Fail -mod;int;8;4;address;riscv;Fail -mod;int;8;8;address;riscv;Fail -mod;int;8;16;address;riscv;Fail -mod;int;8;32;address;riscv;Fail -mod;int;8;64;address;riscv;Fail -mod;int;8;128;address;riscv;Fail -mod;int;16;1;address;riscv;Fail -mod;int;16;2;address;riscv;Fail -mod;int;16;4;address;riscv;Fail -mod;int;16;8;address;riscv;Fail -mod;int;16;16;address;riscv;Fail -mod;int;16;32;address;riscv;Fail -mod;int;16;64;address;riscv;Fail -mod;int;16;128;address;riscv;Fail -mod;int;32;1;address;riscv;Fail -mod;int;32;2;address;riscv;Fail -mod;int;32;4;address;riscv;Fail -mod;int;32;8;address;riscv;Fail -mod;int;32;16;address;riscv;Fail -mod;int;32;32;address;riscv;Fail -mod;int;32;64;address;riscv;Fail -mod;int;32;128;address;riscv;Fail -mod;int;64;1;address;riscv;Fail -mod;int;64;2;address;riscv;Fail -mod;int;64;4;address;riscv;Fail -mod;int;64;8;address;riscv;Fail -mod;int;64;16;address;riscv;Fail -mod;int;64;32;address;riscv;Fail -mod;int;64;64;address;riscv;Fail -mod;int;64;128;address;riscv;Fail -or;int;8;1;address;riscv;Fail -or;int;8;2;address;riscv;Fail -or;int;8;4;address;riscv;Fail -or;int;8;8;address;riscv;Fail -or;int;8;16;address;riscv;Fail -or;int;8;32;address;riscv;Fail -or;int;8;64;address;riscv;Fail -or;int;8;128;address;riscv;Fail -or;int;16;1;address;riscv;Fail -or;int;16;2;address;riscv;Fail -or;int;16;4;address;riscv;Fail -or;int;16;8;address;riscv;Fail -or;int;16;16;address;riscv;Fail -or;int;16;32;address;riscv;Fail -or;int;16;64;address;riscv;Fail -or;int;16;128;address;riscv;Fail -or;int;32;1;address;riscv;Fail -or;int;32;2;address;riscv;Fail -or;int;32;4;address;riscv;Fail -or;int;32;8;address;riscv;Fail -or;int;32;16;address;riscv;Fail -or;int;32;32;address;riscv;Fail -or;int;32;64;address;riscv;Fail -or;int;32;128;address;riscv;Fail -or;int;64;1;address;riscv;Fail -or;int;64;2;address;riscv;Fail -or;int;64;4;address;riscv;Fail -or;int;64;8;address;riscv;Fail -or;int;64;16;address;riscv;Fail -or;int;64;32;address;riscv;Fail -or;int;64;64;address;riscv;Fail -or;int;64;128;address;riscv;Fail -and;int;8;1;address;riscv;Fail -and;int;8;2;address;riscv;Fail -and;int;8;4;address;riscv;Fail -and;int;8;8;address;riscv;Fail -and;int;8;16;address;riscv;Fail -and;int;8;32;address;riscv;Fail -and;int;8;64;address;riscv;Fail -and;int;8;128;address;riscv;Fail -and;int;16;1;address;riscv;Fail -and;int;16;2;address;riscv;Fail -and;int;16;4;address;riscv;Fail -and;int;16;8;address;riscv;Fail -and;int;16;16;address;riscv;Fail -and;int;16;32;address;riscv;Fail -and;int;16;64;address;riscv;Fail -and;int;16;128;address;riscv;Fail -and;int;32;1;address;riscv;Fail -and;int;32;2;address;riscv;Fail -and;int;32;4;address;riscv;Fail -and;int;32;8;address;riscv;Fail -and;int;32;16;address;riscv;Fail -and;int;32;32;address;riscv;Fail -and;int;32;64;address;riscv;Fail -and;int;32;128;address;riscv;Fail -and;int;64;1;address;riscv;Fail -and;int;64;2;address;riscv;Fail -and;int;64;4;address;riscv;Fail -and;int;64;8;address;riscv;Fail -and;int;64;16;address;riscv;Fail -and;int;64;32;address;riscv;Fail -and;int;64;64;address;riscv;Fail -and;int;64;128;address;riscv;Fail -xor;int;8;1;address;riscv;Fail -xor;int;8;2;address;riscv;Fail -xor;int;8;4;address;riscv;Fail -xor;int;8;8;address;riscv;Fail -xor;int;8;16;address;riscv;Fail -xor;int;8;32;address;riscv;Fail -xor;int;8;64;address;riscv;Fail -xor;int;8;128;address;riscv;Fail -xor;int;16;1;address;riscv;Fail -xor;int;16;2;address;riscv;Fail -xor;int;16;4;address;riscv;Fail -xor;int;16;8;address;riscv;Fail -xor;int;16;16;address;riscv;Fail -xor;int;16;32;address;riscv;Fail -xor;int;16;64;address;riscv;Fail -xor;int;16;128;address;riscv;Fail -xor;int;32;1;address;riscv;Fail -xor;int;32;2;address;riscv;Fail -xor;int;32;4;address;riscv;Fail -xor;int;32;8;address;riscv;Fail -xor;int;32;16;address;riscv;Fail -xor;int;32;32;address;riscv;Fail -xor;int;32;64;address;riscv;Fail -xor;int;32;128;address;riscv;Fail -xor;int;64;1;address;riscv;Fail -xor;int;64;2;address;riscv;Fail -xor;int;64;4;address;riscv;Fail -xor;int;64;8;address;riscv;Fail -xor;int;64;16;address;riscv;Fail -xor;int;64;32;address;riscv;Fail -xor;int;64;64;address;riscv;Fail -xor;int;64;128;address;riscv;Fail -sl;int;8;1;address;riscv;Fail -sl;int;8;2;address;riscv;Fail -sl;int;8;4;address;riscv;Fail -sl;int;8;8;address;riscv;Fail -sl;int;8;16;address;riscv;Fail -sl;int;8;32;address;riscv;Fail -sl;int;8;64;address;riscv;Fail -sl;int;8;128;address;riscv;Fail -sl;int;16;1;address;riscv;Fail -sl;int;16;2;address;riscv;Fail -sl;int;16;4;address;riscv;Fail -sl;int;16;8;address;riscv;Fail -sl;int;16;16;address;riscv;Fail -sl;int;16;32;address;riscv;Fail -sl;int;16;64;address;riscv;Fail -sl;int;16;128;address;riscv;Fail -sl;int;32;1;address;riscv;Fail -sl;int;32;2;address;riscv;Fail -sl;int;32;4;address;riscv;Fail -sl;int;32;8;address;riscv;Fail -sl;int;32;16;address;riscv;Fail -sl;int;32;32;address;riscv;Fail -sl;int;32;64;address;riscv;Fail -sl;int;32;128;address;riscv;Fail -sl;int;64;1;address;riscv;Fail -sl;int;64;2;address;riscv;Fail -sl;int;64;4;address;riscv;Fail -sl;int;64;8;address;riscv;Fail -sl;int;64;16;address;riscv;Fail -sl;int;64;32;address;riscv;Fail -sl;int;64;64;address;riscv;Fail -sl;int;64;128;address;riscv;Fail -sr;int;8;1;address;riscv;Fail -sr;int;8;2;address;riscv;Fail -sr;int;8;4;address;riscv;Fail -sr;int;8;8;address;riscv;Fail -sr;int;8;16;address;riscv;Fail -sr;int;8;32;address;riscv;Fail -sr;int;8;64;address;riscv;Fail -sr;int;8;128;address;riscv;Fail -sr;int;16;1;address;riscv;Fail -sr;int;16;2;address;riscv;Fail -sr;int;16;4;address;riscv;Fail -sr;int;16;8;address;riscv;Fail -sr;int;16;16;address;riscv;Fail -sr;int;16;32;address;riscv;Fail -sr;int;16;64;address;riscv;Fail -sr;int;16;128;address;riscv;Fail -sr;int;32;1;address;riscv;Fail -sr;int;32;2;address;riscv;Fail -sr;int;32;4;address;riscv;Fail -sr;int;32;8;address;riscv;Fail -sr;int;32;16;address;riscv;Fail -sr;int;32;32;address;riscv;Fail -sr;int;32;64;address;riscv;Fail -sr;int;32;128;address;riscv;Fail -sr;int;64;1;address;riscv;Fail -sr;int;64;2;address;riscv;Fail -sr;int;64;4;address;riscv;Fail -sr;int;64;8;address;riscv;Fail -sr;int;64;16;address;riscv;Fail -sr;int;64;32;address;riscv;Fail -sr;int;64;64;address;riscv;Fail -sr;int;64;128;address;riscv;Fail -add;int;8;1;address;power;Fail -add;int;8;2;address;power;Fail -add;int;8;4;address;power;Fail -add;int;8;8;address;power;Fail -add;int;8;16;address;power;Fail -add;int;8;32;address;power;Fail -add;int;8;64;address;power;Fail -add;int;8;128;address;power;Fail -add;int;16;1;address;power;Fail -add;int;16;2;address;power;Fail -add;int;16;4;address;power;Fail -add;int;16;8;address;power;Fail -add;int;16;16;address;power;Fail -add;int;16;32;address;power;Fail -add;int;16;64;address;power;Fail -add;int;16;128;address;power;Fail -add;int;32;1;address;power;Fail -add;int;32;2;address;power;Fail -add;int;32;4;address;power;Fail -add;int;32;8;address;power;Fail -add;int;32;16;address;power;Fail -add;int;32;32;address;power;Fail -add;int;32;64;address;power;Fail -add;int;32;128;address;power;Fail -add;int;64;1;address;power;Fail -add;int;64;2;address;power;Fail -add;int;64;4;address;power;Fail -add;int;64;8;address;power;Fail -add;int;64;16;address;power;Fail -add;int;64;32;address;power;Fail -add;int;64;64;address;power;Fail -add;int;64;128;address;power;Fail -mul;int;8;1;address;power;Fail -mul;int;8;2;address;power;Fail -mul;int;8;4;address;power;Fail -mul;int;8;8;address;power;Fail -mul;int;8;16;address;power;Fail -mul;int;8;32;address;power;Fail -mul;int;8;64;address;power;Fail -mul;int;8;128;address;power;Fail -mul;int;16;1;address;power;Fail -mul;int;16;2;address;power;Fail -mul;int;16;4;address;power;Fail -mul;int;16;8;address;power;Fail -mul;int;16;16;address;power;Fail -mul;int;16;32;address;power;Fail -mul;int;16;64;address;power;Fail -mul;int;16;128;address;power;Fail -mul;int;32;1;address;power;Fail -mul;int;32;2;address;power;Fail -mul;int;32;4;address;power;Fail -mul;int;32;8;address;power;Fail -mul;int;32;16;address;power;Fail -mul;int;32;32;address;power;Fail -mul;int;32;64;address;power;Fail -mul;int;32;128;address;power;Fail -mul;int;64;1;address;power;Fail -mul;int;64;2;address;power;Fail -mul;int;64;4;address;power;Fail -mul;int;64;8;address;power;Fail -mul;int;64;16;address;power;Fail -mul;int;64;32;address;power;Fail -mul;int;64;64;address;power;Fail -mul;int;64;128;address;power;Fail -sub;int;8;1;address;power;Fail -sub;int;8;2;address;power;Fail -sub;int;8;4;address;power;Fail -sub;int;8;8;address;power;Fail -sub;int;8;16;address;power;Fail -sub;int;8;32;address;power;Fail -sub;int;8;64;address;power;Fail -sub;int;8;128;address;power;Fail -sub;int;16;1;address;power;Fail -sub;int;16;2;address;power;Fail -sub;int;16;4;address;power;Fail -sub;int;16;8;address;power;Fail -sub;int;16;16;address;power;Fail -sub;int;16;32;address;power;Fail -sub;int;16;64;address;power;Fail -sub;int;16;128;address;power;Fail -sub;int;32;1;address;power;Fail -sub;int;32;2;address;power;Fail -sub;int;32;4;address;power;Fail -sub;int;32;8;address;power;Fail -sub;int;32;16;address;power;Fail -sub;int;32;32;address;power;Fail -sub;int;32;64;address;power;Fail -sub;int;32;128;address;power;Fail -sub;int;64;1;address;power;Fail -sub;int;64;2;address;power;Fail -sub;int;64;4;address;power;Fail -sub;int;64;8;address;power;Fail -sub;int;64;16;address;power;Fail -sub;int;64;32;address;power;Fail -sub;int;64;64;address;power;Fail -sub;int;64;128;address;power;Fail -div;int;8;1;address;power;Fail -div;int;8;2;address;power;Fail -div;int;8;4;address;power;Fail -div;int;8;8;address;power;Fail -div;int;8;16;address;power;Fail -div;int;8;32;address;power;Fail -div;int;8;64;address;power;Fail -div;int;8;128;address;power;Fail -div;int;16;1;address;power;Fail -div;int;16;2;address;power;Fail -div;int;16;4;address;power;Fail -div;int;16;8;address;power;Fail -div;int;16;16;address;power;Fail -div;int;16;32;address;power;Fail -div;int;16;64;address;power;Fail -div;int;16;128;address;power;Fail -div;int;32;1;address;power;Fail -div;int;32;2;address;power;Fail -div;int;32;4;address;power;Fail -div;int;32;8;address;power;Fail -div;int;32;16;address;power;Fail -div;int;32;32;address;power;Fail -div;int;32;64;address;power;Fail -div;int;32;128;address;power;Fail -div;int;64;1;address;power;Fail -div;int;64;2;address;power;Fail -div;int;64;4;address;power;Fail -div;int;64;8;address;power;Fail -div;int;64;16;address;power;Fail -div;int;64;32;address;power;Fail -div;int;64;64;address;power;Fail -div;int;64;128;address;power;Fail -add;flt;32;1;address;power;Fail -add;flt;32;2;address;power;Fail -add;flt;32;4;address;power;Fail -add;flt;32;8;address;power;Fail -add;flt;32;16;address;power;Fail -add;flt;32;32;address;power;Fail -add;flt;32;64;address;power;Fail -add;flt;32;128;address;power;Fail -add;flt;64;1;address;power;Fail -add;flt;64;2;address;power;Fail -add;flt;64;4;address;power;Fail -add;flt;64;8;address;power;Fail -add;flt;64;16;address;power;Fail -add;flt;64;32;address;power;Fail -add;flt;64;64;address;power;Fail -add;flt;64;128;address;power;Fail -mul;flt;32;1;address;power;Fail -mul;flt;32;2;address;power;Fail -mul;flt;32;4;address;power;Fail -mul;flt;32;8;address;power;Fail -mul;flt;32;16;address;power;Fail -mul;flt;32;32;address;power;Fail -mul;flt;32;64;address;power;Fail -mul;flt;32;128;address;power;Fail -mul;flt;64;1;address;power;Fail -mul;flt;64;2;address;power;Fail -mul;flt;64;4;address;power;Fail -mul;flt;64;8;address;power;Fail -mul;flt;64;16;address;power;Fail -mul;flt;64;32;address;power;Fail -mul;flt;64;64;address;power;Fail -mul;flt;64;128;address;power;Fail -sub;flt;32;1;address;power;Fail -sub;flt;32;2;address;power;Fail -sub;flt;32;4;address;power;Fail -sub;flt;32;8;address;power;Fail -sub;flt;32;16;address;power;Fail -sub;flt;32;32;address;power;Fail -sub;flt;32;64;address;power;Fail -sub;flt;32;128;address;power;Fail -sub;flt;64;1;address;power;Fail -sub;flt;64;2;address;power;Fail -sub;flt;64;4;address;power;Fail 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-mod;int;16;1;address;power;Fail -mod;int;16;2;address;power;Fail -mod;int;16;4;address;power;Fail -mod;int;16;8;address;power;Fail -mod;int;16;16;address;power;Fail -mod;int;16;32;address;power;Fail -mod;int;16;64;address;power;Fail -mod;int;16;128;address;power;Fail -mod;int;32;1;address;power;Fail -mod;int;32;2;address;power;Fail -mod;int;32;4;address;power;Fail -mod;int;32;8;address;power;Fail -mod;int;32;16;address;power;Fail -mod;int;32;32;address;power;Fail -mod;int;32;64;address;power;Fail -mod;int;32;128;address;power;Fail -mod;int;64;1;address;power;Fail -mod;int;64;2;address;power;Fail -mod;int;64;4;address;power;Fail -mod;int;64;8;address;power;Fail -mod;int;64;16;address;power;Fail -mod;int;64;32;address;power;Fail -mod;int;64;64;address;power;Fail -mod;int;64;128;address;power;Fail -or;int;8;1;address;power;Fail -or;int;8;2;address;power;Fail -or;int;8;4;address;power;Fail -or;int;8;8;address;power;Fail -or;int;8;16;address;power;Fail -or;int;8;32;address;power;Fail -or;int;8;64;address;power;Fail -or;int;8;128;address;power;Fail -or;int;16;1;address;power;Fail -or;int;16;2;address;power;Fail -or;int;16;4;address;power;Fail -or;int;16;8;address;power;Fail -or;int;16;16;address;power;Fail -or;int;16;32;address;power;Fail -or;int;16;64;address;power;Fail -or;int;16;128;address;power;Fail -or;int;32;1;address;power;Fail -or;int;32;2;address;power;Fail -or;int;32;4;address;power;Fail -or;int;32;8;address;power;Fail -or;int;32;16;address;power;Fail -or;int;32;32;address;power;Fail -or;int;32;64;address;power;Fail -or;int;32;128;address;power;Fail -or;int;64;1;address;power;Fail -or;int;64;2;address;power;Fail -or;int;64;4;address;power;Fail -or;int;64;8;address;power;Fail -or;int;64;16;address;power;Fail -or;int;64;32;address;power;Fail -or;int;64;64;address;power;Fail -or;int;64;128;address;power;Fail -and;int;8;1;address;power;Fail -and;int;8;2;address;power;Fail -and;int;8;4;address;power;Fail -and;int;8;8;address;power;Fail -and;int;8;16;address;power;Fail -and;int;8;32;address;power;Fail -and;int;8;64;address;power;Fail -and;int;8;128;address;power;Fail -and;int;16;1;address;power;Fail -and;int;16;2;address;power;Fail -and;int;16;4;address;power;Fail -and;int;16;8;address;power;Fail -and;int;16;16;address;power;Fail -and;int;16;32;address;power;Fail -and;int;16;64;address;power;Fail -and;int;16;128;address;power;Fail -and;int;32;1;address;power;Fail -and;int;32;2;address;power;Fail -and;int;32;4;address;power;Fail -and;int;32;8;address;power;Fail -and;int;32;16;address;power;Fail -and;int;32;32;address;power;Fail -and;int;32;64;address;power;Fail -and;int;32;128;address;power;Fail -and;int;64;1;address;power;Fail -and;int;64;2;address;power;Fail -and;int;64;4;address;power;Fail -and;int;64;8;address;power;Fail -and;int;64;16;address;power;Fail -and;int;64;32;address;power;Fail -and;int;64;64;address;power;Fail -and;int;64;128;address;power;Fail -xor;int;8;1;address;power;Fail -xor;int;8;2;address;power;Fail -xor;int;8;4;address;power;Fail -xor;int;8;8;address;power;Fail -xor;int;8;16;address;power;Fail -xor;int;8;32;address;power;Fail -xor;int;8;64;address;power;Fail -xor;int;8;128;address;power;Fail -xor;int;16;1;address;power;Fail -xor;int;16;2;address;power;Fail -xor;int;16;4;address;power;Fail -xor;int;16;8;address;power;Fail -xor;int;16;16;address;power;Fail -xor;int;16;32;address;power;Fail -xor;int;16;64;address;power;Fail -xor;int;16;128;address;power;Fail -xor;int;32;1;address;power;Fail -xor;int;32;2;address;power;Fail -xor;int;32;4;address;power;Fail -xor;int;32;8;address;power;Fail -xor;int;32;16;address;power;Fail -xor;int;32;32;address;power;Fail -xor;int;32;64;address;power;Fail -xor;int;32;128;address;power;Fail -xor;int;64;1;address;power;Fail -xor;int;64;2;address;power;Fail -xor;int;64;4;address;power;Fail -xor;int;64;8;address;power;Fail -xor;int;64;16;address;power;Fail -xor;int;64;32;address;power;Fail -xor;int;64;64;address;power;Fail -xor;int;64;128;address;power;Fail -sl;int;8;1;address;power;Fail -sl;int;8;2;address;power;Fail -sl;int;8;4;address;power;Fail -sl;int;8;8;address;power;Fail -sl;int;8;16;address;power;Fail -sl;int;8;32;address;power;Fail -sl;int;8;64;address;power;Fail -sl;int;8;128;address;power;Fail -sl;int;16;1;address;power;Fail -sl;int;16;2;address;power;Fail -sl;int;16;4;address;power;Fail -sl;int;16;8;address;power;Fail -sl;int;16;16;address;power;Fail -sl;int;16;32;address;power;Fail -sl;int;16;64;address;power;Fail -sl;int;16;128;address;power;Fail -sl;int;32;1;address;power;Fail -sl;int;32;2;address;power;Fail -sl;int;32;4;address;power;Fail -sl;int;32;8;address;power;Fail -sl;int;32;16;address;power;Fail -sl;int;32;32;address;power;Fail -sl;int;32;64;address;power;Fail -sl;int;32;128;address;power;Fail -sl;int;64;1;address;power;Fail -sl;int;64;2;address;power;Fail -sl;int;64;4;address;power;Fail -sl;int;64;8;address;power;Fail -sl;int;64;16;address;power;Fail -sl;int;64;32;address;power;Fail -sl;int;64;64;address;power;Fail -sl;int;64;128;address;power;Fail -sr;int;8;1;address;power;Fail -sr;int;8;2;address;power;Fail -sr;int;8;4;address;power;Fail -sr;int;8;8;address;power;Fail -sr;int;8;16;address;power;Fail -sr;int;8;32;address;power;Fail -sr;int;8;64;address;power;Fail -sr;int;8;128;address;power;Fail -sr;int;16;1;address;power;Fail -sr;int;16;2;address;power;Fail -sr;int;16;4;address;power;Fail -sr;int;16;8;address;power;Fail -sr;int;16;16;address;power;Fail -sr;int;16;32;address;power;Fail -sr;int;16;64;address;power;Fail -sr;int;16;128;address;power;Fail -sr;int;32;1;address;power;Fail -sr;int;32;2;address;power;Fail -sr;int;32;4;address;power;Fail -sr;int;32;8;address;power;Fail -sr;int;32;16;address;power;Fail -sr;int;32;32;address;power;Fail -sr;int;32;64;address;power;Fail -sr;int;32;128;address;power;Fail -sr;int;64;1;address;power;Fail -sr;int;64;2;address;power;Fail -sr;int;64;4;address;power;Fail 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a/CodeExamples/Loop.riscv.c +++ /dev/null @@ -1,790 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifii)(int, int); - -h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 12 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 28, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x10000FFF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - res = riscv_genMV_2(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - res = riscv_genADD_3(res, res, increment); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, res); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000001]; - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res, resultOK; - pifii fPtr; - - if (argc < 3) - { - printf("Give 2 increment values\n"); - exit(-1); - } - in0 = atoi (argv[1]); - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifii) genMul (ptr); // Generate instructions - res = fPtr(in0, in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/LoopNest.aarch64 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z5X=7zWy#dKyx!0MkjsZjI9%GlbiLXSeuX?j(dG5N|4ZAc)IfjH<#l)rIM(v|`M?P- z-%3O*moBHnSCD5dub(3{>`;X?pPGa&r_;v~A(-Z0uUj^9`5KMLVSM?w0jK(>#^LGm z@oN~urAvpWEOD8^w;f#n4von0d@B;-^dKP)MPj(VsSvNoP@%rZ<7NR64j;&CrbQhxq!Rlue@z9i)*a`|}uE%=ry@T7LUxbm8hsY&V=`&9vYh0A*BavC-# zN%^DHFmbUNR08*S{S&>oDkN^rf2blY)VOht!_SAG_8;9ZlX>D)3<&<7(UUR|^!Jmj YS3LhCkeR6bj}NI*^e%< -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); -#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - A64_B_GE_I_I_64_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 64 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 11, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_begin_00000009 */ - #define h2_begin_00000009 9 - 0, /* h2_end_00000010 */ - #define h2_end_00000010 10 - 0, /* h2_BA_00000011 */ - #define h2_BA_00000011 11 - 0, /* h2_prologue_00000012 */ - #define h2_prologue_00000012 12 - 0, /* h2_begin_00000013 */ - #define h2_begin_00000013 13 - 0, /* h2_end_00000014 */ - #define h2_end_00000014 14 - 0, /* h2_BA_00000015 */ - #define h2_BA_00000015 15 - 0, /* h2_prologue_00000016 */ - #define h2_prologue_00000016 16 - 0, /* h2_begin_00000017 */ - #define h2_begin_00000017 17 - 0, /* h2_end_00000018 */ - #define h2_end_00000018 18 - 0, /* h2_BA_00000019 */ - #define h2_BA_00000019 19 - 0, /* h2_prologue_00000020 */ - #define h2_prologue_00000020 20 - 0, /* h2_begin_00000021 */ - #define h2_begin_00000021 21 - 0, /* h2_end_00000022 */ - #define h2_end_00000022 22 - 0, /* h2_BA_00000023 */ - #define h2_BA_00000023 23 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0F01, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000012); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000013); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000015); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000014); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000020); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000021); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_prologue_00000016); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_begin_00000017); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000019); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000018); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_BA_00000023); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genLABEL_1(h2_end_00000022); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000013] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000009] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000011]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000015]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000021] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000017] + 1; - aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000019]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000023]; - aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resC, resD; - pifi fPtr; - - in0 = atoi(argv[1]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifi) genLoopNest(ptr); // Generate instructions - resD = fPtr(in0); // Call generated code - resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, - printf("Result C : %d Result D : %d\n", resC, resD); - printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); - if (resD == resC) - return 0; - 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-#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); -#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); -#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genBGE_1(h2_sValue_t P0); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genBA_1(h2_sValue_t P0); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genBGE_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BGE_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genBA_1(h2_sValue_t P0) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) - { - P1_BL_I_I_32_1(P0.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for CMP instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for CMP - -// No specific optimisation for CMP/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, CMP instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 64 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 15, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 16, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_begin_00000009 */ - #define h2_begin_00000009 9 - 0, /* h2_end_00000010 */ - #define h2_end_00000010 10 - 0, /* h2_BA_00000011 */ - #define h2_BA_00000011 11 - 0, /* h2_prologue_00000012 */ - #define h2_prologue_00000012 12 - 0, /* h2_begin_00000013 */ - #define h2_begin_00000013 13 - 0, /* h2_end_00000014 */ - #define h2_end_00000014 14 - 0, /* h2_BA_00000015 */ - #define h2_BA_00000015 15 - 0, /* h2_prologue_00000016 */ - #define h2_prologue_00000016 16 - 0, /* h2_begin_00000017 */ - #define h2_begin_00000017 17 - 0, /* h2_end_00000018 */ - #define h2_end_00000018 18 - 0, /* h2_BA_00000019 */ - #define h2_BA_00000019 19 - 0, /* h2_prologue_00000020 */ - #define h2_prologue_00000020 20 - 0, /* h2_begin_00000021 */ - #define h2_begin_00000021 21 - 0, /* h2_end_00000022 */ - #define h2_end_00000022 22 - 0, /* h2_BA_00000023 */ - #define h2_BA_00000023 23 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x1F80F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000012); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000013); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000015); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000014); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000020); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000021); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genCMP_2(i, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_prologue_00000016); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_begin_00000017); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genCMP_2(j, len); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000019); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000018); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_BA_00000023); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genLABEL_1(h2_end_00000022); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000013] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000009] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000011]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000015]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000021] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_begin_00000017] + 1; - power_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000019]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); - h2_asm_pc = labelAddresses [h2_BA_00000023]; - power_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resC, resD; - pifi fPtr; - - in0 = atoi(argv[1]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifi) genLoopNest(ptr); // Generate instructions - resD = fPtr(in0); // Call generated code - resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, - printf("Result C : %d Result D : %d\n", resC, resD); - printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); - if (resD == resC) - return 0; - else - return -1; -} diff --git a/CodeExamples/LoopNest.riscv b/CodeExamples/LoopNest.riscv deleted file mode 100755 index a782ca2fd27bb2e325c12f423dd4b1d88d45da55..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 49712 zcmeI5dtemR^~Yy3n{0RpXteld&0|^95MGw5RSaPvpa>N3S#1bOfY^}4Bv7regjyTv&@SV=@i|S4qQ7JOJ!MdqRPF?Bc} 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zGM|mm2k_@&ilve>HT-e&5o@LN5vHza9Fs2OZjb=o9&A&|eVLw!aiW&pi)38B+T1gDwces{*<* zOy8r>c0NBd;%sgJLmP##9h$oH%GcuOe$&Uwx%uo$XB2R~KGD@Vv#_|Rc=q(^T&T0M z`Fc@(UYTAzD?O82n(QL>j9K~VGjj8%W#p!373UYSsh&MoW3N?^n_Zlp#gp(8a->gZ zxb%#|!i>Apxoa%EOPgNEUOhc)_N-ZVAreM$3zk#dj&)pqe!=+cqT*z=gJEVfhrm>n z*Y>5JG{`4kJRx)QXACj^NM~$)M#`q>_>1pF8q;d~9 zVf5(9qo&vrj4{11JDa6x8O8ZIDQV-zrjAVK=6k4CFuPc8{=%Em)8*dWy!B>oIeDSZ z%gnbH>3rQfd0hI?5XI-Gkm>2ElP6pAFDPUaI6WjvZ??K=N>88c8!=@>dg`dOvEyZ- z>Fr2`pA0Z5T>teqrVr7S%1POC?8=PEY!irP*vV{&%!Se#ARit^KEX5?jYH*K0OT;p+fJ+rcB;Xdscvh%XU z>ZlikP_w+z`mT7wbs<>!QdhxhE=f5|dQN6W=FIGN8toV>$OrT6!uXH^K1)UcLltDq z$S%sc`#8C2MMc(n?GK;B^@{DoRJAim>Ie+N+=+UC(F(Zv&OgqJrd&VL@&zrq=&o7C z8Phly7nJ-|6lRC=hn5^(52YYAG*1Ay6En5V z$VYXNSuX-XEm{4@EhO2BQ6=7!Gm47~bEeHMCJiQMWlx(ugDjPihY@U2J(;q*rcEov zuPsWRjo5Wyva8aJwF=e6sgpk!z$aHTwgH;lHx)y~hRK>&I!%kCP2Rf-pX{$!(&46V zA6$0S@g08Uu1WahK1(i@bfnw@`mvs?_`Bf?!V;wE$=i!T)WgSx)MiLOC6yxYq2)X1CDcV9S6|g9_awO#nS;oi?~2WJK&nI5AmvVq z%_sYowJ5r -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BGE instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BGE - -// No specific optimisation for BGE/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, BGE instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for BA instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for BA - -// No specific optimisation for BA/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, BA instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ -{ - /* Code Generation of 58 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 6, true}; - h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 7, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; - h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; -h2_insn_t * labelAddresses []={ - 0, /* h2_prologue_00000000 */ - #define h2_prologue_00000000 0 - 0, /* h2_begin_00000001 */ - #define h2_begin_00000001 1 - 0, /* h2_end_00000002 */ - #define h2_end_00000002 2 - 0, /* h2_BA_00000003 */ - #define h2_BA_00000003 3 - 0, /* h2_prologue_00000004 */ - #define h2_prologue_00000004 4 - 0, /* h2_begin_00000005 */ - #define h2_begin_00000005 5 - 0, /* h2_end_00000006 */ - #define h2_end_00000006 6 - 0, /* h2_BA_00000007 */ - #define h2_BA_00000007 7 - 0, /* h2_prologue_00000008 */ - #define h2_prologue_00000008 8 - 0, /* h2_begin_00000009 */ - #define h2_begin_00000009 9 - 0, /* h2_end_00000010 */ - #define h2_end_00000010 10 - 0, /* h2_BA_00000011 */ - #define h2_BA_00000011 11 - 0, /* h2_prologue_00000012 */ - #define h2_prologue_00000012 12 - 0, /* h2_begin_00000013 */ - #define h2_begin_00000013 13 - 0, /* h2_end_00000014 */ - #define h2_end_00000014 14 - 0, /* h2_BA_00000015 */ - #define h2_BA_00000015 15 - 0, /* h2_prologue_00000016 */ - #define h2_prologue_00000016 16 - 0, /* h2_begin_00000017 */ - #define h2_begin_00000017 17 - 0, /* h2_end_00000018 */ - #define h2_end_00000018 18 - 0, /* h2_BA_00000019 */ - #define h2_BA_00000019 19 - 0, /* h2_prologue_00000020 */ - #define h2_prologue_00000020 20 - 0, /* h2_begin_00000021 */ - #define h2_begin_00000021 21 - 0, /* h2_end_00000022 */ - #define h2_end_00000022 22 - 0, /* h2_BA_00000023 */ - #define h2_BA_00000023 23 - }; - - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x7FF, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000012); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000013); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000000); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000001); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000003); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000002); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000004); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000005); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000007); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000006); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000008); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000009); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000011); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000010); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000015); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000014); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000020); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000021); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_prologue_00000016); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_begin_00000017); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000019); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000018); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_BA_00000023); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc)*4)); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genLABEL_1(h2_end_00000022); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = labelAddresses [h2_begin_00000013]; - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000001]; - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000003]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000005]; - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000007]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000009]; - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000011]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000015]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000021]; - i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_begin_00000017]; - j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000019]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc)*4)); - h2_asm_pc = labelAddresses [h2_BA_00000023]; - intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc)*4)); - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, resC, resD; - pifi fPtr; - - in0 = atoi(argv[1]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - fPtr = (pifi) genLoopNest(ptr); // Generate instructions - resD = fPtr(in0); // Call generated code - resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, - printf("Result C : %d Result D : %d\n", resC, resD); - printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); - if (resD == resC) - return 0; - else - return -1; -} diff --git a/CodeExamples/Mult-With-Specialization.aarch64 b/CodeExamples/Mult-With-Specialization.aarch64 deleted file mode 100755 index 0e59760f19f933831209c0fcb9084bb23b5f794a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 43968 zcmeHwdtg-6x$oMu=au(U-og%#f@l&zR1iE&5)e6}VuFgNz0ORMNisE=2{RJ}p=I#V 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zHT@@2=^I@fGu9{wXx?GIQq%tzMCRjGXlg$HUYnpw#aChFb_0#pb``yPfAYi->3 -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genMult(h2_insn_t * ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genMUL_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res; - pifi fPtr; - - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = (pifi) genMult (ptr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Mult-With-Specialization.power b/CodeExamples/Mult-With-Specialization.power deleted file mode 100755 index 7187df068ab3f7f066a0debe97737838454486b6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78208 zcmeHv3w%^px$oLDlVn033=nAguYbS+lVt2px-X6ssq@dQD*xDaet4X2k^Z(Xk zvNM@U0&Pz5+`VDXx7N45^{w^&*IM6t?47-1<=We9n#R;+W3w5>JWl2!o`-&L^_L16 z8^RvuX1VyC$F5`9h&wnBKZ2@!oDNCViaLcDvx8DTHz^d9%OlR|48dlKsu~i_l4+7~ zd4xGld{}T5W!xI^OLf)X66yL|8kbkpM-{?#P*RnTsz>=eGM`80Q?y@JOi^VY*+%zT zX&)#rPf;Cdbm{z8$WpNB#l4axs-lbs@bZvugbo{4(Co(|Aby5WI!B^Ks|mF2HTR zs5sRGq=$6o;3nG$TWWjKmxr4!l2JEjO!9~F%=C>FrgGBpmxHhRqB+-^4Dw4d@S8I5 zOEU2924BaWdJ%5v>RF$Ge^mzl%nbaB415;o4klPM5Q{}(EZUWb(@#r>ACXuvoM>b1 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z;<$pye&h}C(?32WyzPPTrnTN1STeS5 z3q`p>CM^;(6Nh)uje)zE476{8!$=+tnYxEL4?R}mMQ*7>A<}h-0iCSC9Y`^EY*T(X z5}aGgV>mt<+cyOgjdTQsqu&e*p^xGTT$CVv z133%0kqv7`aN1}Ft+u|N+tVD6%i7V%V6r=!icS`_iSj2+fWcw%T`*(wx)svJNf%(w zEeDQ?l^nGuUb2vlD>r+q8LNzM>rD8YK@%}SJ5&fx1`qmJC4a0{Th~}Y2d$Mj?XK+b z!&z0fZVMx`poy4BxhoKh1B_7-FVb+V>Zc4c1Xso?Ilh&NKsUm??^ebly!TZGI?##9 z)zcYnGR7*oGe?2s(|Nf#y~a^(djuLpPJj%tNM|P=TY(p7?rO*RtUnA#sG|H~he~R0 zj-i{%7#-lNFhEd2^2bs_YEqNqrBgbApd|(0R)DJWFHnA^u9?;PMx=_ziaCg={OX)c z?2pE-`7rH|y55f%ru<}nb)E*wFFFUHi)83h`*fve5qN*XJF}|%etEtI$}e@2lA2$n zGX9Vm?-?Y^KP~fv@{3+kql=bN6jbG_6QC8~(UM7(ug>v6`SnRblE10=tw9RC1FZ6^ z^FC01rPg1`DY_L>^iHvgt8+n6e(8dYslQ~ib_7UNihyC{L&>=WG4dV{HNu)B`Cj^sY7v@ zL6=k!dWpxJU!6aL@~d14N-AMVa_Oxk%CGQK=b)hcqL=E-m$F~+9z?*LU!9kN@=Kl5 zDEZX#znGF=ovVWKt0ATQ)cjwO`IVSDf7R)L376WxiP%W{sW|PksQxOyI;X9kWd3g< zFEy3Qug-HlGJiiQ$EEs*!cW!f2-3{uC(nK538(76TnYV1eM-+=U{P3=kCx=Bt7ZNu z=!bBiWu83C3KZR3Z&ZeYKHv%{EZ!YU3RqQ6m@JUL;jOaAt}zmMs%d+&jurv zN74`G39dM|%AB9xZYIf8{LUAO{K}6h4T3vT=6hs*m9FS~I&j6cQe}_{DN$CMA%AqX zknEHB6iLOOq?GSbGDOeH{D*0B!&QR23AgG$%74?}r;PM{MC5g#M3jG8Iey6(TqQ+k T3hDFjey@ -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_POWER -#define H2_POWER - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -typedef uint32_t h2_insn_t; -static h2_insn_t *h2_asm_pc; -static h2_insn_t *h2_save_asm_pc; - -static ticks_t h2_getticks(void) -{ - unsigned int tbl, tbu0, tbu1; - - do { - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); - __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); - __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); - } while (tbu0 != tbu1); - - return (((unsigned long long)tbu0) << 32) | tbl; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - -#endif /*H2_POWER*/ -/* In memory instruction generator */ -#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ - } while(0); -#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); -#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); -#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); -#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); -#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); -#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); -#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); -#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); -#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); -#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); -#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); -#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); -#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); -#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); -#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); -#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); -#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); -#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); -#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genRET_0(); -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/power - -P1_BLR__I_32_1(); - -} -h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (power)\\n"); - #endif - // MV const in tmp register - P1 = power_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -// No specific optimisation for MUL/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/power - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - P1_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genMult(h2_insn_t * ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x780F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = power_genMUL_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = power_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - power_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res; - pifi fPtr; - - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = (pifi) genMult (ptr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Mult-With-Specialization.riscv b/CodeExamples/Mult-With-Specialization.riscv deleted file mode 100755 index 2a6a6a009ea4c5d988f3105be86fe46647641d81..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 29172 zcmeHwdwdi{wtw~XB$E&bfq?jC$RwRH8zvCc6snk2uENkAfTW}J_QlM4cLu(DZ~J#KxN3L@l(xsD=~N1>cTJzxq{uJO1K_zS@s1tan)Xk}x*b!U~NF;)ezPUO1(_ZZB%yDHtKOnhp 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b6a8bc2..0000000 --- a/CodeExamples/Mult-With-Specialization.riscv.c +++ /dev/null @@ -1,755 +0,0 @@ -/* Begin Header autogenerated part */ -#ifndef H2_COMMON -#define H2_COMMON -/* Common HybroGen inserted code */ -#include -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_RISCV_RV32G -#define H2_RISCV_RV32G - -#define H2SYS /* Has operating system */ - -#include -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -static int h2_riscvVectorLen = 1; -static int h2_riscvVectorWidth = 1; -static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; - -#if 0 -/* -https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang -*/ - -ticks_t h2_getticks(void) -{ - unsigned long dst; - // output into any register, likely a0 - // regular instruction: - asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); - // regular instruction with symbolic csr and register names - // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); - // pseudo-instruction: - // asm volatile ("csrr %0, cycle" : "=r" (dst) ); - // pseudo-instruction: - //asm volatile ("rdcycle %0" : "=r" (dst) ); - return dst; -} -#endif - -#if 1 -// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h -// HW counter measument -ticks_t h2_getticks(void) -{ - uint64_t result; -#if __riscv_xlen == 64 - asm volatile("rdtime %0" : "=r" (result)); -#elif __riscv_xlen == 32 - uint32_t l, h, h2; - do - { - asm volatile( - "rdtimeh %0 \n" - "rdtime %1 \n" - "rdtimeh %2 \n" - : "=r" (h), "=r" (l), "=r" (h2)); - } while (h2 != h); - result =(((uint64_t)h)<<32) | ((uint64_t)l); -#endif - return result; -} -#endif - - -#if 0 -// System level clock measurment -#include -ticks_t h2_getticks(void) -{ - int res; - struct timeval My_time; - uint64_t tick; - res = gettimeofday(&My_time, NULL); - tick = My_time.tv_sec * 1000000 + My_time.tv_usec; - if (0 == res) - { - return tick; - } else - { - return 0; - } -} -#endif - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - long pageSize= getpagesize(); - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - perror("(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /*H2_RISCV_RV32G*/ -/* In memory instruction generator */ -#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ - } while(0); -#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); -#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); -#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genRET_0(); -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (riscv)\\n"); - #endif - // MV const in tmp register - P1 = riscv_genMV_2(PTMP, P1); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul & 1 mv -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (riscv)\n"); -#endif - return riscv_genMV_2(P0, immValueZero); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return riscv_genSL_3(P0, P1, P2); - } - -if (isValue(P2)) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (riscv)\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/riscv - -RV32I_RET__I_32_1(); - -} -h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -/* -*- c -*- */ -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI sub (riscv)\\n"); - #endif - P2 = riscv_genMV_2(PTMP, P2); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/riscv - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -typedef int (*pifi)(int); - -h2_insn_t * genMult(h2_insn_t * ptr, int b) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; - h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0x73F, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - riscv_genADD_3(SP, SP, intsValue(-48)); -riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); -riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); -riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); -riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); -riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); -riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); -riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); -riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); -riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); -riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); - r = riscv_genMUL_4(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); - riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); - riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); - riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); - riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); - riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); - riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); - riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); - riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); - riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); - riscv_genADD_3(SP, SP, intsValue(48)); - riscv_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *) ptr; -} - - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - int in0, in1, res; - pifi fPtr; - - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - in0 = atoi (argv[1]); // Get the users values in1 & in2 - in1 = atoi (argv[2]); - ptr = h2_malloc (1024); // Allocate memory for 1024 instructions - printf("// Compilette for simple addition between 1 variable with\n"); - printf("// code specialization on value = %d\n", in0); - fPtr = (pifi) genMult (ptr, in0); // Generate instructions - res = fPtr(in1); // Call generated code - printf("%d * %d = %d\n", in0, in1, res); - if (res == (in0 * in1)) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-flt.aarch64 b/CodeExamples/Multiple-flt.aarch64 deleted file mode 100755 index 5bfdddaab4100ce20e88d390e8ccda8490a3f8b6..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 52288 zcmeHw33yx8mH&Nuk}a?CmOUiTSxOqPorEocFp=$qkRd>@!_w&tvTVz?iX%Ic90Ey; zve42(OFRk7l+6L!l0c^!hW@Er7#yG-I?c41CbZ0yMG4R{L;G*a?n0{hox4a^vSiC^ zzkc7m{0g;F2j3hQ2D2 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z^<9lE6t41ZZehZzI@itsHc9Hdo0*KX*2AT-YAlzviEu5IrUCHYCjiK)Zfqca5rk9dQYDwCMS$`%X`*mlmRRFkBtGIdYYndsJ(^H?)@4o!#!%jUE1&nSdGW zaJPB<&DaOdL6t5sMZ`#dezo9x4A zV=R^u6r$e~6es8fb|kvP7CE*B=ig6$MBUIs*fmnX+mNSU z$@aShnONhF$*cpKe+XKtYDKU10X~xS5vjj) zhnPId4}J<-LQ(W;zu=|Y0mP;7L@KV2lK&_&bb7U~@Rp-k?6+niHKKU6HI>Pg%RCP{g)Tb92& zDYHmNLYy`rl2AB?_4fkt!W~|Ry`~To>GpNM6b%Ezh9u@5=8`$ihy4I(ywIP3)0XZp@xY|R)a|3H`)Hg zFR2KQ+whNqq=y -#include -#include -#include -#include - -bool h2_codeGenerationOK; // Does code generation fail ? -typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) -static uint32_t h2_insnGenerated; -typedef unsigned long long ticks_t; -static ticks_t h2_codeGenTime; - -typedef enum { H2REGISTER, H2VALUE, } VALORREG; -typedef struct -{ - int ValOrReg; // is H2REGISTER or immediate VALUE ? - char arith; // int, flt or other arithmetic - int vLen; // vector len - int wLen; // word len - int regNro; // register number (if register) - int valueImm; // immediate value (if not register) - bool dontFree; // if register, don't free -} h2_sValue_t; -#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) -#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) -#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) -#define immValueZero intsValue(0) -// Usefull macro instruction to simplify instruction selector code -#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) -#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) -#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) -#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) -#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) -#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) -#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) -#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - - -typedef union { - float f; - unsigned long i; -} h2_float_int_u; - -static int h2_log2(int value) -{ // integer logarithm - int log = 0; - while (value >>= 1) { ++log; } - return log; -} -// Print register map : F for free register, . for allocated -void printRev (int value, int pos) -{ // Print a bitset in reversal order (recursive) - if (pos != 0) - printRev (value >> 1, pos - 1); - printf ("%1c", (value % 2)?'.':'F'); -} - -// Dynamic register allocation handling -// h2_regSet mask : 0 mean free register, 1 register set -// 3 2 1 Bit position = reg Number -// 1098 7654 3210 9876 5432 1098 7654 3210 -// 1111 1111 1111 1111 0000 0001 0011 1111 -typedef struct -{ // Register allocation sets for - // int, float, vector of ints, vector of floats - int intSet, fltSet, vintSet, vfltSet ; -} h2_RegSets_t; - -h2_RegSets_t h2_regSet, h2_regSetInit; - -// Print integer register set -void printRegState(char * msg, int regNo, int registerSet) -{ - int count = 8 * sizeof (registerSet) - 1; - h2_regSet_t tmpReg = registerSet; - printf ("%02d : Reg %s\n", regNo, msg); - for (int i = count; i >= 0; i--) // Tens - (0 == (i % 10))?printf ("%d", i/10):printf (" "); - printf ("\n"); - for (int i = count; i >= 0; i--) // Unit - printf ("%d", i%10); - printf ("\n"); - printRev (tmpReg, count); // Bit set - printf ("\n"); -} - -// Initialize registers sets allocation -static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) -{ // See H2SymbolTable & H2RegisterBank - h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; -} - -static void h2_resetRegisterMasks() // Reset register set from initializers -{ - h2_regSet = h2_regSetInit; -#ifdef H2_DEBUG_REGISTER - printRegState("RESET", -1, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER -} -int h2_getReg () // Get new register -{ - /* Search for the 1st free register */ - h2_regSet_t tmpReg = h2_regSet.intSet; - for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) - { - if (tmpReg % 2 == 0) - { /* Free register found */ - h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("GET", i, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - return i; - } - tmpReg >>= 1; - } - printf ("Register allocation failed\n"); - h2_codeGenerationOK = false; - return -1; -} - -// h2_regSet_t regToBeFreed[32]; - -void h2_freeReg (h2_regSet_t v) // Free a register -{ -#if 1 // TODO : To be rethinked - // Is the register freeable ? - int isOK = (h2_regSetInit.intSet >> v) & 1; - if (0 == isOK) - { - h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ -#ifdef H2_DEBUG_REGISTER - printRegState("FREE", v, h2_regSet.intSet); -#endif // H2_DEBUG_REGISTER - } -#endif -} -#endif /*H2_COMMON*/ -#ifndef H2_AARCH64 -#define H2_AARCH64 - -#define H2SYS /* Has operating system */ - -#ifdef H2SYS -#include -#endif - -typedef uint32_t h2_insn_t; /* Instruction size */ -static h2_insn_t *h2_asm_pc; /* PC for code generation */ -static h2_insn_t *h2_save_asm_pc; -#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} -/* aarch64 / power examples : - https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ - -static inline ticks_t h2_getticks(void) -{ - uint64_t Rt; - asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); - return Rt; -} - -static void h2_iflush(void *addr, void *last) -{ - h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); -#ifdef H2SYS - __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written - long pageSize= getpagesize(); // Make the page executable - void *ptmp= (char *)((long)addr & ~(pageSize - 1)); - if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) - { - perror("iflush: mprotect"); - exit(-1); - } - /* Gcc function to clear data cache after code generation */ - __clear_cache((char *)addr, (char *)last); -#endif -#ifdef H2_DEBUG - printf ("Flush data cache from %p to %p\n", addr, last); - printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); -#endif - if (!h2_codeGenerationOK) - { - fprintf (stderr, "(iflush) Failed code generation\n"); - exit(-5); - } -} - -static h2_insn_t *h2_malloc (size_t size) -{ - return malloc (size); -} - - -#endif /* H2_AARCH64 */ -/* In memory instruction generator */ -#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} - -/* Single instruction binary code generator*/ -#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ - } while(0); -#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xe & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FSUB_RRR_F_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xe & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x2 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_64_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMUL_RRR_F_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x2 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x72 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x272 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_ADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FADD_RRI_F_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x6 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x6 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -#define A64_FDIV_RRR_F_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); -h2_sValue_t aarch64_genRET_0(); -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); -h2_sValue_t aarch64_genRET_0() -{ -// No generic optimisation for RET - -// No specific optimisation for RET/aarch64 - -A64_RET__I_64_1(); - -} -h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MUL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ - // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) - if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) - { - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; - } - /* if (isInt0(P2) || isInt0(P1)) */ - /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *0 P2 (generic)\n"); */ - /* #endif */ - /* return immValueZero; */ - /* } */ - /* if (isInt1(P2)) */ - /* { // X * 1 = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P2 (generic)\n"); */ - /* #endif */ - /* P1.dontFree = true; */ - /* return P1; */ - /* } */ - /* if (isInt1(P1)) */ - /* { // 1 * X = X propagate register result */ - /* #ifdef H2_DEBUG_INSN */ - /* printf ("Optim for *1 P1 (generic)\n"); */ - /* #endif */ - /* P2.dontFree = true; */ - /* return P2; */ - /* } */ - -/* -*- c -*- */ -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -if (isInt0(P2)) - { // X * 0 = 0 Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *0 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, immValueZero, P1); - } - -if (isInt1(P2)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P2 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P1, P1); - } - -if (isInt1(P1)) - { // X * 1 = X Avoid 1 operation mul -#ifdef H2_DEBUG_INSN - printf ("Optim for *1 P1 (aarch64)\n"); -#endif - return aarch64_genMV_3(P0, P2, P2); - } - -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSL_3(P0, P1, P2); - } - -// Mv constant value in register, then do division -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI mul (aarch64)\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); - // No return continue instruction selection -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FMUL_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MUL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SR instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SR - -// No specific optimisation for SR/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SR instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SUB instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; -} - -// No specific optimisation for SUB/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FSUB_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SUB instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for W instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for W - -/* -*- c -*- */ - -/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ -/* { */ -/* #ifdef H2_DEBUG_INSN */ -/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ -/* printf ("Store 0 (aarch64)\\n"); */ -/* #endif */ -/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ -/* return P0; */ -/* } */ - -if (isValue(P1)) - { // Store constant (Should use RRI variant) - h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RI W (aarch64)\n"); - #endif - // MV const in tmp register - P1 = aarch64_genMV_3(PTMP, P1, immValueZero); - // No return continue instruction selection - } - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P1; - } - - if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P1; - } - printf ("Warning, W instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for DIV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// if 2 operands are constants do division evaluation -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; -} -// Transform RIR in RRI : P1 & P2 permutation -if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) - { - h2_sValue_t PTMP = P2; - P2 = P1; - P1 = PTMP; - } - -/* -*- c -*- */ -// X * NPowerOf2 = X >> N (immediate shift left) -if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) - { - int shiftValue = h2_log2(P2.valueImm); - #ifdef H2_DEBUG_INSN - printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); - #endif - P2.valueImm = shiftValue; // Instruction shift left immediat - return aarch64_genSR_3(P0, P1, P2); - } -if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) -{ - h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; - #ifdef H2_DEBUG_INSN - printf ("Fallback for no RRI div (aarch64)\\n"); - #endif - P2 = aarch64_genMV_3(PTMP, P2, immValueZero); -} - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FDIV_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, DIV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for ADD instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -/* -*- c -*- */ -// If 2 operands are constants do addition -if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) -{ - return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); -} -if (isInt0 (P2)) - { // P0 = P1 + 0 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); - #endif - P1.dontFree = true; - return P1; - } -if (isInt0 (P1)) - { // P0 = 0 + P2 - #ifdef H2_DEBUG_INSN - printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); - #endif - P2.dontFree = true; - return P2; - } - -// No specific optimisation for ADD/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_ADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_FADD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - printf ("Warning, ADD instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for SL instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for SL - -// No specific optimisation for SL/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, SL instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for R instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for R - -// No specific optimisation for R/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) - { - A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, R instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} -h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) -{ -#ifdef H2_DEBUG_INSN - printf ("Start code gen for MV instruction\n"); - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); - printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); - printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); -#endif // H2_DEBUG_INSN -// No generic optimisation for MV - -// No specific optimisation for MV/aarch64 - - if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) - P0.regNro = h2_getReg(); - if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) - P1.regNro = h2_getReg(); - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MV_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) - { - A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); - return P0; - } - - if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) - { - A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - - if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) - { - A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); - return P0; - } - printf ("Warning, MV instruction generation failed\n"); - h2_codeGenerationOK = false; - printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; -} - -/* End Header autogenerated part */ -// -*- c -*- -#include -#include - -/* Pointer on function which take 2 floats and return float */ -typedef float (*pifff)(float, float); - -/* C compilette prototype */ -h2_insn_t * genAddf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genADD_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genMulf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genMUL_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genSubf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genSUB_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -h2_insn_t * genDivf(h2_insn_t * ptr) -{ - /* Code Generation of 3 instructions */ - /* Symbol table :*/ - /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ - h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; - h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; - h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; - h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; - - /* Label table :*/ -/* No label table to avoid C warning for empty table ... */ - h2_asm_pc = (h2_insn_t *) ptr; - h2_codeGenerationOK = true; - h2_codeGenTime = h2_getticks(); - h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); - h2_resetRegisterMasks(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask initialization\n"); - #endif // H2_DEBUG_REGISTER - - r = aarch64_genDIV_3(r, a, b); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - aarch64_genRET_0(); - #ifdef H2_DEBUG_REGISTER - printf("Tmp registers mask reset\n"); - #endif // H2_DEBUG_REGISTER - h2_resetRegisterMasks(); - /* Call back code for loops */ - h2_save_asm_pc = h2_asm_pc; - h2_asm_pc = h2_save_asm_pc; - h2_codeGenTime = h2_getticks() - h2_codeGenTime; - h2_iflush(ptr, h2_asm_pc); - - return (h2_insn_t *)ptr; -} - -int main(int argc, char * argv[]) -{ - h2_insn_t * ptr; - float fin0, fin1, fres; - pifff fPtrf; - int resultOK; - - if (argc < 3) - { - printf("Give 2 values\n"); - exit(-1); - } - resultOK = 0; - fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) - fin1 = atof (argv[2]); - - ptr = h2_malloc (1024); - fPtrf = (pifff) genAddf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple addition of 2 floating point values:\n"); - printf("%f + %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 + fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genSubf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple subraction of 2 floating point values:\n"); - printf("%f - %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 - fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genMulf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple multiplication of 2 floating point values:\n"); - printf("%f * %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 * fin1)) - resultOK += 1; - - ptr = h2_malloc (1024); - fPtrf = (pifff) genDivf (ptr); - fres = fPtrf(fin0, fin1); - printf ("Simple division of 2 floating point values:\n"); - printf("%f / %f = %f\n", fin0, fin1, fres); - if (fres != (fin0 / fin1)) - resultOK += 1; - - if (resultOK == 0) - return 0; - else - return -1; -} diff --git a/CodeExamples/Multiple-flt.power b/CodeExamples/Multiple-flt.power deleted file mode 100755 index 04c082a1413fd1a7d626f8f33069e7adbadf9924..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 78456 zcmeHw4SZY0mG4|hw&mDy+8s05cUT4k^r$c{1Sm zi1YAZhk&Y(acRVrc-7w*`TF}B$5&xJF@$5k3{^Q|kIH#uIgc!-!d}Uk3YB~$8=dQ< zdmY@rcgea%N;{wW5$Z-L?3gw8;(H=@^8)bdj^m0t{ zuR_%h6~REmqDv}*O^YrmkA=$@QoY0r(IuSK8@AxecsozvF>xXF7U3+!nU8ZKPV*tF z<1`4DWXi)yZBDwSI*48YPCBSAb#lNcFH~l7eL6DLmkGWUaMc&hr50tuugd~on*}~A z3;ZU)b)2aO=`9nVE3&}P$pW981zwf~&isi$oJIW6XgJCu?eQ308e4rxL<6CCGi&k3 zBfb`YEO4`*wMC-gxW6&Z+I+!axRJ%;O(@8kZ;A%ue&&mZo0->(j@0Ol#eLDZx6Ky_ zF-lXHTEtebtF2z{U0A;0QlPc8g+mg}3*Kx){>*7);?VHdfKc`GuXcY0O>1L8o{PR@ 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0000000..adb1b05 --- /dev/null +++ b/CodeExamples/Loop.riscv.c @@ -0,0 +1,790 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifii)(int, int); + +h2_insn_t * genMul(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 12 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t increment = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t res = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t k = {H2REGISTER, 'i', 1, 32, 28, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x10000FFF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + res = riscv_genMV_2(res, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + res = riscv_genADD_3(res, res, increment); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, res); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000001]; + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res, resultOK; + pifii fPtr; + + if (argc < 3) + { + printf("Give 2 increment values\n"); + exit(-1); + } + in0 = atoi (argv[1]); + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr = (pifii) genMul (ptr); // Generate instructions + res = fPtr(in0, in1); // Call generated code + printf("%d * %d = %d\n", in0, in1, res); + if (res == (in0 * in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/LoopNest.aarch64 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z5X=7zWy#dKyx!0MkjsZjI9%GlbiLXSeuX?j(dG5N|4ZAc)IfjH<#l)rIM(v|`M?P- z-%3O*moBHnSCD5dub(3{>`;X?pPGa&r_;v~A(-Z0uUj^9`5KMLVSM?w0jK(>#^LGm z@oN~urAvpWEOD8^w;f#n4von0d@B;-^dKP)MPj(VsSvNoP@%rZ<7NR64j;&CrbQhxq!Rlue@z9i)*a`|}uE%=ry@T7LUxbm8hsY&V=`&9vYh0A*BavC-# zN%^DHFmbUNR08*S{S&>oDkN^rf2blY)VOht!_SAG_8;9ZlX>D)3<&<7(UUR|^!Jmj YS3LhCkeR6bj}NI*^e%< +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_I_I_64_1(i0) do /* ba */ { aarch64_G32(((0x5 & 0x3f) << 26)|((i0 & 0x3ffffff) >> 0)); } while(0); +#define A64_CMP_RR_I_64_1(r1,r2) do /* cmp */ { aarch64_G32(((0x758 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((0x1f & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_B_GE_I_I_64_1(i0) do /* bge */ { aarch64_G32(((0x54 & 0xff) << 24)|((i0 & 0x7ffff) << 5)|((0xa & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_CMP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + A64_B_GE_I_I_64_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 64 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 11, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define aarch64_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_begin_00000009 */ + #define h2_begin_00000009 9 + 0, /* h2_end_00000010 */ + #define h2_end_00000010 10 + 0, /* h2_BA_00000011 */ + #define h2_BA_00000011 11 + 0, /* h2_prologue_00000012 */ + #define h2_prologue_00000012 12 + 0, /* h2_begin_00000013 */ + #define h2_begin_00000013 13 + 0, /* h2_end_00000014 */ + #define h2_end_00000014 14 + 0, /* h2_BA_00000015 */ + #define h2_BA_00000015 15 + 0, /* h2_prologue_00000016 */ + #define h2_prologue_00000016 16 + 0, /* h2_begin_00000017 */ + #define h2_begin_00000017 17 + 0, /* h2_end_00000018 */ + #define h2_end_00000018 18 + 0, /* h2_BA_00000019 */ + #define h2_BA_00000019 19 + 0, /* h2_prologue_00000020 */ + #define h2_prologue_00000020 20 + 0, /* h2_begin_00000021 */ + #define h2_begin_00000021 21 + 0, /* h2_end_00000022 */ + #define h2_end_00000022 22 + 0, /* h2_BA_00000023 */ + #define h2_BA_00000023 23 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0F01, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = aarch64_genMV_3(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000012); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000013); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000015); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000014); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000020); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genMV_3(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000021); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_prologue_00000016); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genMV_3(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_begin_00000017); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = aarch64_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = aarch64_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000019); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000018); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = aarch64_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_BA_00000023); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genLABEL_1(h2_end_00000022); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000013] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000009] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000011]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000015]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000021] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000017] + 1; + aarch64_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000019]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000023]; + aarch64_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resC, resD; + pifi fPtr; + + in0 = atoi(argv[1]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr = (pifi) genLoopNest(ptr); // Generate instructions + resD = fPtr(in0); // Call generated code + resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, + printf("Result C : %d Result D : %d\n", resC, resD); + printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); + if (resD == resC) + return 0; + else + return -1; +} diff --git a/CodeExamples/LoopNest.power b/CodeExamples/LoopNest.power new file mode 100755 index 0000000000000000000000000000000000000000..559ee8eddb71b73c267b94e7bb428a8a7b41c45e GIT binary patch literal 78376 zcmeHw4}4VBmH&M+lgxyKF#J(Ni!un<#0?=JrGtWm5F`=QRIswU?oL87BvX?~Oa?pH zM1o5{jV;|xcCp1SmbgWWyXY@==@whMrY^R$i~EaP+R|sJ0uQ222|xF9AVZ9x(qU52c&XdVrW1~k7o&|8)%`Rl8|5)=P{7< zNK4qU+rTO)q&CJc$?AE>$oIUXNqPkvNg!ND8LDz59+fNOa%Egj!2uRbL8Tw*M)yY6 z4^Y;ppa*$$dE~D_OUdeAhU%%DyNjMAl;!X&;gEqA3KA_{A4fTobG(;i2IAYfzI1ju z%knFz{IIwwuyy&e#ZC3gmzA`)lq{usrQCo-v;NjQ2qpbIMW&1&GVe6pQ*jeMAGi6U z>XZwJ5Ak&3CcBb;Ik?IHxw!Li6OFo&9QQ?KX4H%(r#e#MD}YzAXfAbo8v0df@OP%c z&r5?ZOoP84cn|L6i|m?8{tapHA4-Ftkp{mk4PN-efsknRx3#sjiPr6*cKWGnti?lH zAQ;*vn*Gh~{*Y+!hgxeJ{Oy7J{Gz$FttI5I3yJ31rlyuU(H^Qtd9m$NZGn(q)P`CD z!skPr)%n^(wQV6^b8R3f=$RsJxmdrks(h_)X~~k0fvlmqCCFqxh$w7H|CuqAui?J{ zplSzS>ir^IZxij5iOZ!M{lhg#Q_QKW(1cfUN_lQ!ldLX7nqo^`1tvTr*^2WMiZW5 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autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_BGE_I_I_32_1(i0) do /* bge */ { power_G32(((0x4080 & 0xffff) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_CMPW_RR_I_32_1(r0,r1) do /* cmp */ { power_G32(((0x3e0 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPWI_RI_I_32_1(r0,i1) do /* cmp */ { power_G32(((0x160 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_CMPD_RR_I_64_1(r0,r1) do /* cmp */ { power_G32(((0x3e1 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((r1 & 0x1f) << 11)|((0x0 & 0x7ff) >> 0)); } while(0); +#define P1_CMPDI_RI_I_64_1(r0,i1) do /* cmp */ { power_G32(((0x161 & 0x7ff) << 21)|((r0 & 0x1f) << 16)|((i1 & 0xffff) >> 0)); } while(0); +#define P1_BL_I_I_32_1(i0) do /* ba */ { power_G32(((0x12 & 0x3f) << 26)|((i0 & 0xffffff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genBGE_1(h2_sValue_t P0); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genBA_1(h2_sValue_t P0); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genBGE_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BGE_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genBA_1(h2_sValue_t P0) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2VALUE) + { + P1_BL_I_I_32_1(P0.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genCMP_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for CMP instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for CMP + +// No specific optimisation for CMP/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPW_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPWI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_CMPD_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_CMPDI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, CMP instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 64 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 15, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 16, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define power_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_begin_00000009 */ + #define h2_begin_00000009 9 + 0, /* h2_end_00000010 */ + #define h2_end_00000010 10 + 0, /* h2_BA_00000011 */ + #define h2_BA_00000011 11 + 0, /* h2_prologue_00000012 */ + #define h2_prologue_00000012 12 + 0, /* h2_begin_00000013 */ + #define h2_begin_00000013 13 + 0, /* h2_end_00000014 */ + #define h2_end_00000014 14 + 0, /* h2_BA_00000015 */ + #define h2_BA_00000015 15 + 0, /* h2_prologue_00000016 */ + #define h2_prologue_00000016 16 + 0, /* h2_begin_00000017 */ + #define h2_begin_00000017 17 + 0, /* h2_end_00000018 */ + #define h2_end_00000018 18 + 0, /* h2_BA_00000019 */ + #define h2_BA_00000019 19 + 0, /* h2_prologue_00000020 */ + #define h2_prologue_00000020 20 + 0, /* h2_begin_00000021 */ + #define h2_begin_00000021 21 + 0, /* h2_end_00000022 */ + #define h2_end_00000022 22 + 0, /* h2_BA_00000023 */ + #define h2_BA_00000023 23 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x1F80F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + tmp = power_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000012); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000013); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000015); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000014); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000020); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000021); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genCMP_2(i, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_prologue_00000016); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_begin_00000017); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genCMP_2(j, len); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = power_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = power_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000019); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000018); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = power_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_BA_00000023); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genLABEL_1(h2_end_00000022); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000013] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000001] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000005] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000009] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000011]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000015]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000021] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_begin_00000017] + 1; + power_genBGE_1(intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000019]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc))); + h2_asm_pc = labelAddresses [h2_BA_00000023]; + power_genBA_1(intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc))); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resC, resD; + pifi fPtr; + + in0 = atoi(argv[1]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr = (pifi) genLoopNest(ptr); // Generate instructions + resD = fPtr(in0); // Call generated code + resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, + printf("Result C : %d Result D : %d\n", resC, resD); + printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); + if (resD == resC) + return 0; + else + return -1; +} diff --git a/CodeExamples/LoopNest.riscv b/CodeExamples/LoopNest.riscv new file mode 100755 index 0000000000000000000000000000000000000000..a782ca2fd27bb2e325c12f423dd4b1d88d45da55 GIT binary patch literal 49712 zcmeI5dtemR^~Yy3n{0RpXteld&0|^95MGw5RSaPvpa>N3S#1bOfY^}4Bv7regjyTv&@SV=@i|S4qQ7JOJ!MdqRPF?Bc} zN8cKUDpO&rrpUacKSECQ_n}|P0ca`GZ_jZh{41H86gTZs?7oQ~7iSeLVUkN6s(eJB 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zGM|mm2k_@&ilve>HT-e&5o@LN5vHza9Fs2OZjb=o9&A&|eVLw!aiW&pi)38B+T1gDwces{*<* zOy8r>c0NBd;%sgJLmP##9h$oH%GcuOe$&Uwx%uo$XB2R~KGD@Vv#_|Rc=q(^T&T0M z`Fc@(UYTAzD?O82n(QL>j9K~VGjj8%W#p!373UYSsh&MoW3N?^n_Zlp#gp(8a->gZ zxb%#|!i>Apxoa%EOPgNEUOhc)_N-ZVAreM$3zk#dj&)pqe!=+cqT*z=gJEVfhrm>n z*Y>5JG{`4kJRx)QXACj^NM~$)M#`q>_>1pF8q;d~9 zVf5(9qo&vrj4{11JDa6x8O8ZIDQV-zrjAVK=6k4CFuPc8{=%Em)8*dWy!B>oIeDSZ z%gnbH>3rQfd0hI?5XI-Gkm>2ElP6pAFDPUaI6WjvZ??K=N>88c8!=@>dg`dOvEyZ- z>Fr2`pA0Z5T>teqrVr7S%1POC?8=PEY!irP*vV{&%!Se#ARit^KEX5?jYH*K0OT;p+fJ+rcB;Xdscvh%XU z>ZlikP_w+z`mT7wbs<>!QdhxhE=f5|dQN6W=FIGN8toV>$OrT6!uXH^K1)UcLltDq z$S%sc`#8C2MMc(n?GK;B^@{DoRJAim>Ie+N+=+UC(F(Zv&OgqJrd&VL@&zrq=&o7C z8Phly7nJ-|6lRC=hn5^(52YYAG*1Ay6En5V z$VYXNSuX-XEm{4@EhO2BQ6=7!Gm47~bEeHMCJiQMWlx(ugDjPihY@U2J(;q*rcEov zuPsWRjo5Wyva8aJwF=e6sgpk!z$aHTwgH;lHx)y~hRK>&I!%kCP2Rf-pX{$!(&46V zA6$0S@g08Uu1WahK1(i@bfnw@`mvs?_`Bf?!V;wE$=i!T)WgSx)MiLOC6yxYq2)X1CDcV9S6|g9_awO#nS;oi?~2WJK&nI5AmvVq z%_sYowJ5r +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_BGE_RRI_I_32_1(r1,r2,i1) do /* BGE */ { riscv_G32((((i1 >> 12) & 0x1) << 31)|(((i1 >> 5) & 0x3f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|(((i1 >> 1) & 0xf) << 8)|(((i1 >> 11) & 0x1) << 7)|((0x63 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_JAL_RI_I_32_1(r3,i1) do /* BA */ { riscv_G32((((i1 >> 20) & 0x1) << 31)|(((i1 >> 1) & 0x3ff) << 21)|(((i1 >> 11) & 0x1) << 20)|(((i1 >> 12) & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x6f & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBGE_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BGE instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BGE + +// No specific optimisation for BGE/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_BGE_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, BGE instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genBA_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for BA instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for BA + +// No specific optimisation for BA/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_JAL_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, BA instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genLoopNest(h2_insn_t * ptr) /* C compilette prototype */ +{ + /* Code Generation of 58 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t len = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t i = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t j = {H2REGISTER, 'i', 1, 32, 6, true}; + h2_sValue_t tmp = {H2REGISTER, 'i', 1, 32, 7, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0001 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0002 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0003 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0004 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0005 = {H2REGISTER, 'i', 1, 32, -1, false}; + h2_sValue_t tmp0006 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +#define riscv_genLABEL_1(LABEL_ID) labelAddresses[LABEL_ID] = h2_asm_pc; +h2_insn_t * labelAddresses []={ + 0, /* h2_prologue_00000000 */ + #define h2_prologue_00000000 0 + 0, /* h2_begin_00000001 */ + #define h2_begin_00000001 1 + 0, /* h2_end_00000002 */ + #define h2_end_00000002 2 + 0, /* h2_BA_00000003 */ + #define h2_BA_00000003 3 + 0, /* h2_prologue_00000004 */ + #define h2_prologue_00000004 4 + 0, /* h2_begin_00000005 */ + #define h2_begin_00000005 5 + 0, /* h2_end_00000006 */ + #define h2_end_00000006 6 + 0, /* h2_BA_00000007 */ + #define h2_BA_00000007 7 + 0, /* h2_prologue_00000008 */ + #define h2_prologue_00000008 8 + 0, /* h2_begin_00000009 */ + #define h2_begin_00000009 9 + 0, /* h2_end_00000010 */ + #define h2_end_00000010 10 + 0, /* h2_BA_00000011 */ + #define h2_BA_00000011 11 + 0, /* h2_prologue_00000012 */ + #define h2_prologue_00000012 12 + 0, /* h2_begin_00000013 */ + #define h2_begin_00000013 13 + 0, /* h2_end_00000014 */ + #define h2_end_00000014 14 + 0, /* h2_BA_00000015 */ + #define h2_BA_00000015 15 + 0, /* h2_prologue_00000016 */ + #define h2_prologue_00000016 16 + 0, /* h2_begin_00000017 */ + #define h2_begin_00000017 17 + 0, /* h2_end_00000018 */ + #define h2_end_00000018 18 + 0, /* h2_BA_00000019 */ + #define h2_BA_00000019 19 + 0, /* h2_prologue_00000020 */ + #define h2_prologue_00000020 20 + 0, /* h2_begin_00000021 */ + #define h2_begin_00000021 21 + 0, /* h2_end_00000022 */ + #define h2_end_00000022 22 + 0, /* h2_BA_00000023 */ + #define h2_BA_00000023 23 + }; + + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x7FF, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + tmp = riscv_genMV_2(tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000012); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000013); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000000); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000001); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(10)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000003); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000002); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000004); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000005); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(11)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000007); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000006); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000008); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000009); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000011); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000010); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000015); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000014); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000020); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genMV_2(i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000021); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_prologue_00000016); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genMV_2(j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(0)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_begin_00000017); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + tmp = riscv_genADD_3(tmp, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(7)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + j = riscv_genADD_3(j, j, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000019); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000018); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + i = riscv_genADD_3(i, i, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_BA_00000023); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc)*4)); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genLABEL_1(h2_end_00000022); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genADD_3(h2_outputVarName, tmp, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)(1)}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = labelAddresses [h2_begin_00000013]; + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000014] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000001]; + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000002] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000003]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000001] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000005]; + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000006] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000007]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000005] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000009]; + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000010] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000011]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000009] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000015]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000013] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000021]; + i = riscv_genBGE_3(i, len, intsValue((labelAddresses [h2_end_00000022] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_begin_00000017]; + j = riscv_genBGE_3(j, len, intsValue((labelAddresses [h2_end_00000018] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000019]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000017] - h2_asm_pc)*4)); + h2_asm_pc = labelAddresses [h2_BA_00000023]; + intReg32sValue(0) = riscv_genBA_2(intReg32sValue(0), intsValue((labelAddresses [h2_begin_00000021] - h2_asm_pc)*4)); + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, resC, resD; + pifi fPtr; + + in0 = atoi(argv[1]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + fPtr = (pifi) genLoopNest(ptr); // Generate instructions + resD = fPtr(in0); // Call generated code + resC = in0*(in0*10+1+in0*11+1+in0*1+1)+in0*7*in0+1, + printf("Result C : %d Result D : %d\n", resC, resD); + printf("Generated insn # %d code generation time :%d\n", h2_insnGenerated, h2_codeGenTime); + if (resD == resC) + return 0; + else + return -1; +} diff --git a/CodeExamples/Mult-With-Specialization.aarch64 b/CodeExamples/Mult-With-Specialization.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..0e59760f19f933831209c0fcb9084bb23b5f794a GIT binary patch literal 43968 zcmeHwdtg-6x$oMu=au(U-og%#f@l&zR1iE&5)e6}VuFgNz0ORMNisE=2{RJ}p=I#V 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zHT@@2=^I@fGu9{wXx?GIQq%tzMCRjGXlg$HUYnpw#aChFb_0#pb``yPfAYi->3 +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_8_16(r0,r1,r2) do /* mul */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xd8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x27 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MUL_RRR_I_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0x4d8 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MUL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genMult(h2_insn_t * ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 9, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0301, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genMUL_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res; + pifi fPtr; + + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = (pifi) genMult (ptr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d * %d = %d\n", in0, in1, res); + if (res == (in0 * in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Mult-With-Specialization.power b/CodeExamples/Mult-With-Specialization.power new file mode 100755 index 0000000000000000000000000000000000000000..7187df068ab3f7f066a0debe97737838454486b6 GIT binary patch literal 78208 zcmeHv3w%^px$oLDlVn033=nAguYbS+lVt2px-X6ssq@dQD*xDaet4X2k^Z(Xk zvNM@U0&Pz5+`VDXx7N45^{w^&*IM6t?47-1<=We9n#R;+W3w5>JWl2!o`-&L^_L16 z8^RvuX1VyC$F5`9h&wnBKZ2@!oDNCViaLcDvx8DTHz^d9%OlR|48dlKsu~i_l4+7~ zd4xGld{}T5W!xI^OLf)X66yL|8kbkpM-{?#P*RnTsz>=eGM`80Q?y@JOi^VY*+%zT zX&)#rPf;Cdbm{z8$WpNB#l4axs-lbs@bZvugbo{4(Co(|Aby5WI!B^Ks|mF2HTR zs5sRGq=$6o;3nG$TWWjKmxr4!l2JEjO!9~F%=C>FrgGBpmxHhRqB+-^4Dw4d@S8I5 zOEU2924BaWdJ%5v>RF$Ge^mzl%nbaB415;o4klPM5Q{}(EZUWb(@#r>ACXuvoM>b1 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z;<$pye&h}C(?32WyzPPTrnTN1STeS5 z3q`p>CM^;(6Nh)uje)zE476{8!$=+tnYxEL4?R}mMQ*7>A<}h-0iCSC9Y`^EY*T(X z5}aGgV>mt<+cyOgjdTQsqu&e*p^xGTT$CVv z133%0kqv7`aN1}Ft+u|N+tVD6%i7V%V6r=!icS`_iSj2+fWcw%T`*(wx)svJNf%(w zEeDQ?l^nGuUb2vlD>r+q8LNzM>rD8YK@%}SJ5&fx1`qmJC4a0{Th~}Y2d$Mj?XK+b z!&z0fZVMx`poy4BxhoKh1B_7-FVb+V>Zc4c1Xso?Ilh&NKsUm??^ebly!TZGI?##9 z)zcYnGR7*oGe?2s(|Nf#y~a^(djuLpPJj%tNM|P=TY(p7?rO*RtUnA#sG|H~he~R0 zj-i{%7#-lNFhEd2^2bs_YEqNqrBgbApd|(0R)DJWFHnA^u9?;PMx=_ziaCg={OX)c z?2pE-`7rH|y55f%ru<}nb)E*wFFFUHi)83h`*fve5qN*XJF}|%etEtI$}e@2lA2$n zGX9Vm?-?Y^KP~fv@{3+kql=bN6jbG_6QC8~(UM7(ug>v6`SnRblE10=tw9RC1FZ6^ z^FC01rPg1`DY_L>^iHvgt8+n6e(8dYslQ~ib_7UNihyC{L&>=WG4dV{HNu)B`Cj^sY7v@ zL6=k!dWpxJU!6aL@~d14N-AMVa_Oxk%CGQK=b)hcqL=E-m$F~+9z?*LU!9kN@=Kl5 zDEZX#znGF=ovVWKt0ATQ)cjwO`IVSDf7R)L376WxiP%W{sW|PksQxOyI;X9kWd3g< zFEy3Qug-HlGJiiQ$EEs*!cW!f2-3{uC(nK538(76TnYV1eM-+=U{P3=kCx=Bt7ZNu z=!bBiWu83C3KZR3Z&ZeYKHv%{EZ!YU3RqQ6m@JUL;jOaAt}zmMs%d+&jurv zN74`G39dM|%AB9xZYIf8{LUAO{K}6h4T3vT=6hs*m9FS~I&j6cQe}_{DN$CMA%AqX zknEHB6iLOOq?GSbGDOeH{D*0B!&QR23AgG$%74?}r;PM{MC5g#M3jG8Iey6(TqQ+k T3hDFjey@ +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_POWER +#define H2_POWER + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +typedef uint32_t h2_insn_t; +static h2_insn_t *h2_asm_pc; +static h2_insn_t *h2_save_asm_pc; + +static ticks_t h2_getticks(void) +{ + unsigned int tbl, tbu0, tbu1; + + do { + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu0)); + __asm__ __volatile__ ("mftb %0" : "=r"(tbl)); + __asm__ __volatile__ ("mftbu %0" : "=r"(tbu1)); + } while (tbu0 != tbu1); + + return (((unsigned long long)tbu0) << 32) | tbl; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + +#endif /*H2_POWER*/ +/* In memory instruction generator */ +#define power_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define P1_BLR__I_32_1() do /* ret */ { power_G32(((0x4e800020 >> 0) & 0xffffffff)); \ + } while(0); +#define V2_03_VADDSBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x300 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUBS_RRR_I_8_16(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x200 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDSHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x340 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUHS_RRR_I_16_8(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x240 & 0x7ff) >> 0)); } while(0); +#define V2_03_VADDUWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x280 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_32_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VADDSWS_RRR_I_32_4(r0,r1,r2) do /* add */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x380 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x214 & 0x7ff) >> 0)); } while(0); +#define P1_ADDI_RRI_I_64_1(r0,r1,i0) do /* add */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_SUBI_RRI_I_32_1(r0,r1,i0) do /* sub */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|(((-i0) & 0xffff) >> 0)); } while(0); +#define PPC_SUB_RRR_I_32_1(r0,r2,r1) do /* sub */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x50 & 0x7ff) >> 0)); } while(0); +#define P1_LBZ_RRI_I_8_1(r0,r1,i0) do /* r */ { power_G32(((0x22 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LBZX_RRR_I_8_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0xae & 0x7ff) >> 0)); } while(0); +#define P1_LHZ_RRI_I_16_1(r0,r1,i0) do /* r */ { power_G32(((0x28 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZ_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x20 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZU_RRI_I_32_1(r0,r1,i0) do /* r */ { power_G32(((0x21 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LWZUX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6e & 0x7ff) >> 0)); } while(0); +#define P1_LWZX_RRR_I_32_1(r0,r1,r2) do /* r */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2e & 0x7ff) >> 0)); } while(0); +#define P1_STB_RRI_I_8_1(r1,r0,i0) do /* w */ { power_G32(((0x26 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STBX_RRR_I_8_1(r1,r0,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1ae & 0x7ff) >> 0)); } while(0); +#define P1_STH_RRI_I_16_1(r1,r0,i0) do /* w */ { power_G32(((0x2c & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STW_RRI_I_32_1(r1,r0,i0) do /* w */ { power_G32(((0x24 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_STWX_RRR_I_32_1(r0,r1,r2) do /* w */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x12e & 0x7ff) >> 0)); } while(0); +#define PPC_STD_RRI_I_64_1(r1,r0,i0) do /* w */ { power_G32(((0x3e & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0x3fff) << 2)|((0x0 & 0x3) >> 0)); } while(0); +#define P1_MULLW_RRR_I_32_1(r0,r1,r2) do /* mul */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1d6 & 0x7ff) >> 0)); } while(0); +#define P1_MULLI_RRI_I_64_1(r0,r1,i0) do /* mul */ { power_G32(((0x7 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_32_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define P1_MV_RR_I_32_1(r0,r1) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((0x0 & 0xffff) >> 0)); } while(0); +#define P1_LI_RI_I_64_1(r0,i0) do /* mv */ { power_G32(((0xe & 0x3f) << 26)|((r0 & 0x1f) << 21)|((0x0 & 0x1f) << 16)|((i0 & 0xffff) >> 0)); } while(0); +#define V2_03_VSLB_RRR_I_8_16(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x104 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLH_RRR_I_16_8(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x144 & 0x7ff) >> 0)); } while(0); +#define P1_SLW_RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x30 & 0x7ff) >> 0)); } while(0); +#define P1_SLW__RRR_I_32_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x31 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSLW_RRR_I_32_4(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x184 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD_RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x36 & 0x7ff) >> 0)); } while(0); +#define PPC_SLD__RRR_I_64_1(r1,r0,r2) do /* sl */ { power_G32(((0x1f & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x37 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSLD_RRR_I_64_2(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x5c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSL_RRR_I_128_1(r0,r1,r2) do /* sl */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x1c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRB_RRR_I_8_16(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x204 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRH_RRR_I_16_8(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x244 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSRW_RRR_I_32_4(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x284 & 0x7ff) >> 0)); } while(0); +#define V2_07_VSRD_RRR_I_64_2(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x6c4 & 0x7ff) >> 0)); } while(0); +#define V2_03_VSR_RRR_I_128_1(r0,r1,r2) do /* sr */ { power_G32(((0x4 & 0x3f) << 26)|((r0 & 0x1f) << 21)|((r1 & 0x1f) << 16)|((r2 & 0x1f) << 11)|((0x2c4 & 0x7ff) >> 0)); } while(0); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genRET_0(); +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t power_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LBZ_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LBZX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LHZ_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZ_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_LWZU_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZUX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_LWZX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUBS_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUHS_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDUWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VADDSWS_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_ADDI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/power + +P1_BLR__I_32_1(); + +} +h2_sValue_t power_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (power)\\n"); + #endif + // MV const in tmp register + P1 = power_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STBX_RRR_I_8_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_STW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_STWX_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + PPC_STD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_SLW__RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSLW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SLD__RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSLD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSL_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +// No specific optimisation for MUL/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + P1_MULLW_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_MULLI_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRH_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSRW_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_07_VSRD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 128) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + V2_03_VSR_RRR_I_128_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + P1_SUBI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + PPC_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t power_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/power + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + P1_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + P1_LI_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genMult(h2_insn_t * ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 3, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 14, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x780F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = power_genMUL_3(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = power_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + power_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res; + pifi fPtr; + + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = (pifi) genMult (ptr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d * %d = %d\n", in0, in1, res); + if (res == (in0 * in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Mult-With-Specialization.riscv b/CodeExamples/Mult-With-Specialization.riscv new file mode 100755 index 0000000000000000000000000000000000000000..2a6a6a009ea4c5d988f3105be86fe46647641d81 GIT binary patch literal 29172 zcmeHwdwdi{wtw~XB$E&bfq?jC$RwRH8zvCc6snk2uENkAfTW}J_QlM4cLu(DZ~J#KxN3L@l(xsD=~N1>cTJzxq{uJO1K_zS@s1tan)Xk}x*b!U~NF;)ezPUO1(_ZZB%yDHtKOnhp zPHy3VD*}OV!Vo$k&_#8S?np00 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100644 index 0000000..b6a8bc2 --- /dev/null +++ b/CodeExamples/Mult-With-Specialization.riscv.c @@ -0,0 +1,755 @@ +/* Begin Header autogenerated part */ +#ifndef H2_COMMON +#define H2_COMMON +/* Common HybroGen inserted code */ +#include +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_RISCV_RV32G +#define H2_RISCV_RV32G + +#define H2SYS /* Has operating system */ + +#include +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +static int h2_riscvVectorLen = 1; +static int h2_riscvVectorWidth = 1; +static h2_sValue_t SP= {H2REGISTER, 'i', 1, 32, 2, 0}; + +#if 0 +/* +https://stackoverflow.com/questions/52187221/how-to-calculate-the-no-of-clock-cycles-in-riscv-clang +*/ + +ticks_t h2_getticks(void) +{ + unsigned long dst; + // output into any register, likely a0 + // regular instruction: + asm volatile ("csrrs %0, 0xc00, x0" : "=r" (dst) ); + // regular instruction with symbolic csr and register names + // asm volatile ("csrrs %0, cycle, zero" : "=r" (dst) ); + // pseudo-instruction: + // asm volatile ("csrr %0, cycle" : "=r" (dst) ); + // pseudo-instruction: + //asm volatile ("rdcycle %0" : "=r" (dst) ); + return dst; +} +#endif + +#if 1 +// From https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h +// HW counter measument +ticks_t h2_getticks(void) +{ + uint64_t result; +#if __riscv_xlen == 64 + asm volatile("rdtime %0" : "=r" (result)); +#elif __riscv_xlen == 32 + uint32_t l, h, h2; + do + { + asm volatile( + "rdtimeh %0 \n" + "rdtime %1 \n" + "rdtimeh %2 \n" + : "=r" (h), "=r" (l), "=r" (h2)); + } while (h2 != h); + result =(((uint64_t)h)<<32) | ((uint64_t)l); +#endif + return result; +} +#endif + + +#if 0 +// System level clock measurment +#include +ticks_t h2_getticks(void) +{ + int res; + struct timeval My_time; + uint64_t tick; + res = gettimeofday(&My_time, NULL); + tick = My_time.tv_sec * 1000000 + My_time.tv_usec; + if (0 == res) + { + return tick; + } else + { + return 0; + } +} +#endif + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + long pageSize= getpagesize(); + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%u insns generated in %lld ticks. %lld ticks / insn\n", (unsigned int)h2_insnGenerated, (long long) h2_codeGenTime, (long long) h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + perror("(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /*H2_RISCV_RV32G*/ +/* In memory instruction generator */ +#define riscv_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define RV32I_RET__I_32_1() do /* RET */ { riscv_G32(((0x8067 >> 0) & 0xffffffff)); \ + } while(0); +#define RV32I_ADDI_RRI_I_32_1(r1,r0,i0) do /* ADD */ { riscv_G32(((i0 & 0xfff) << 20)|((r0 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r1 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_ADD_RRR_I_32_1(r3,r1,r2) do /* ADD */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SUB_RRR_I_32_1(r3,r1,r2) do /* SUB */ { riscv_G32(((0x20 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SRLI_RRI_I_32_1(r3,r1,i0) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SRL_RRR_I_32_1(r3,r1,r2) do /* SR */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x5 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_SLLI_RRI_I_32_1(r3,r1,i0) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((i0 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SLL_RRR_I_32_1(r3,r1,r2) do /* SL */ { riscv_G32(((0x0 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32M_MUL_RRR_I_32_1(r3,r1,r2) do /* MUL */ { riscv_G32(((0x1 & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x33 & 0x7f) >> 0)); } while(0); +#define RV32I_LB_RRI_I_8_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LH_RRI_I_16_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_LW_RRI_I_32_1(r3,r1,i1) do /* R */ { riscv_G32(((i1 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((r3 & 0x1f) << 7)|((0x3 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RR_I_32_1(r0,r1) do /* MV */ { riscv_G32(((0x0 & 0xfff) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((r0 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_MV_RI_I_32_1(r3,i1) do /* MV */ { riscv_G32(((i1 & 0xfff) << 20)|((0x6 & 0xff) << 12)|((r3 & 0x1f) << 7)|((0x13 & 0x7f) >> 0)); } while(0); +#define RV32I_SB_RRI_I_8_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x0 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SH_RRI_I_16_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x1 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +#define RV32I_SW_RRI_I_32_1(r1,r2,i1) do /* W */ { riscv_G32((((i1 >> 5) & 0x7f) << 25)|((r2 & 0x1f) << 20)|((r1 & 0x1f) << 15)|((0x2 & 0x7) << 12)|((i1 & 0x1f) << 7)|((0x23 & 0x7f) >> 0)); } while(0); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3); +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genRET_0(); +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1); +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t riscv_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (riscv)\\n"); + #endif + // MV const in tmp register + P1 = riscv_genMV_2(PTMP, P1); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genMUL_4(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2,h2_sValue_t P3) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul & 1 mv +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (riscv)\n"); +#endif + return riscv_genMV_2(P0, immValueZero); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (riscv)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return riscv_genSL_3(P0, P1, P2); + } + +if (isValue(P2)) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (riscv)\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32M_MUL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_LW_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_ADDI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SRLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SRL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/riscv + +RV32I_RET__I_32_1(); + +} +h2_sValue_t riscv_genMV_2(h2_sValue_t P0,h2_sValue_t P1) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + RV32I_MV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + RV32I_MV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +/* -*- c -*- */ +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI sub (riscv)\\n"); + #endif + P2 = riscv_genMV_2(PTMP, P2); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t riscv_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/riscv + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + RV32I_SLLI_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + RV32I_SLL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +typedef int (*pifi)(int); + +h2_insn_t * genMult(h2_insn_t * ptr, int b) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'i', 1, 32, 10, true}; + h2_sValue_t r = {H2REGISTER, 'i', 1, 32, 5, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'i', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0x73F, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + riscv_genADD_3(SP, SP, intsValue(-48)); +riscv_genW_3(SP, intReg32sValue(18), intsValue(44)); +riscv_genW_3(SP, intReg32sValue(19), intsValue(40)); +riscv_genW_3(SP, intReg32sValue(20), intsValue(36)); +riscv_genW_3(SP, intReg32sValue(21), intsValue(32)); +riscv_genW_3(SP, intReg32sValue(22), intsValue(28)); +riscv_genW_3(SP, intReg32sValue(23), intsValue(24)); +riscv_genW_3(SP, intReg32sValue(24), intsValue(20)); +riscv_genW_3(SP, intReg32sValue(25), intsValue(16)); +riscv_genW_3(SP, intReg32sValue(26), intsValue(12)); +riscv_genW_3(SP, intReg32sValue(27), intsValue(8)); + r = riscv_genMUL_4(r, a, (h2_sValue_t) {H2VALUE, 'i', 1, 32, 0, (int)((b))}, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = riscv_genMV_2(h2_outputVarName, r); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + riscv_genR_3(intReg32sValue(18), SP, intsValue(44)); + riscv_genR_3(intReg32sValue(19), SP, intsValue(40)); + riscv_genR_3(intReg32sValue(20), SP, intsValue(36)); + riscv_genR_3(intReg32sValue(21), SP, intsValue(32)); + riscv_genR_3(intReg32sValue(22), SP, intsValue(28)); + riscv_genR_3(intReg32sValue(23), SP, intsValue(24)); + riscv_genR_3(intReg32sValue(24), SP, intsValue(20)); + riscv_genR_3(intReg32sValue(25), SP, intsValue(16)); + riscv_genR_3(intReg32sValue(26), SP, intsValue(12)); + riscv_genR_3(intReg32sValue(27), SP, intsValue(8)); + riscv_genADD_3(SP, SP, intsValue(48)); + riscv_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *) ptr; +} + + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + int in0, in1, res; + pifi fPtr; + + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + in0 = atoi (argv[1]); // Get the users values in1 & in2 + in1 = atoi (argv[2]); + ptr = h2_malloc (1024); // Allocate memory for 1024 instructions + printf("// Compilette for simple addition between 1 variable with\n"); + printf("// code specialization on value = %d\n", in0); + fPtr = (pifi) genMult (ptr, in0); // Generate instructions + res = fPtr(in1); // Call generated code + printf("%d * %d = %d\n", in0, in1, res); + if (res == (in0 * in1)) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-flt.aarch64 b/CodeExamples/Multiple-flt.aarch64 new file mode 100755 index 0000000000000000000000000000000000000000..5bfdddaab4100ce20e88d390e8ccda8490a3f8b6 GIT binary patch literal 52288 zcmeHw33yx8mH&Nuk}a?CmOUiTSxOqPorEocFp=$qkRd>@!_w&tvTVz?iX%Ic90Ey; zve42(OFRk7l+6L!l0c^!hW@Er7#yG-I?c41CbZ0yMG4R{L;G*a?n0{hox4a^vSiC^ zzkc7m{0g;F2j3hQ2D2 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z^<9lE6t41ZZehZzI@itsHc9Hdo0*KX*2AT-YAlzviEu5IrUCHYCjiK)Zfqca5rk9dQYDwCMS$`%X`*mlmRRFkBtGIdYYndsJ(^H?)@4o!#!%jUE1&nSdGW zaJPB<&DaOdL6t5sMZ`#dezo9x4A zV=R^u6r$e~6es8fb|kvP7CE*B=ig6$MBUIs*fmnX+mNSU z$@aShnONhF$*cpKe+XKtYDKU10X~xS5vjj) zhnPId4}J<-LQ(W;zu=|Y0mP;7L@KV2lK&_&bb7U~@Rp-k?6+niHKKU6HI>Pg%RCP{g)Tb92& zDYHmNLYy`rl2AB?_4fkt!W~|Ry`~To>GpNM6b%Ezh9u@5=8`$ihy4I(ywIP3)0XZp@xY|R)a|3H`)Hg zFR2KQ+whNqq=y +#include +#include +#include +#include + +bool h2_codeGenerationOK; // Does code generation fail ? +typedef int32_t h2_regSet_t; // Register set (signed, use -1 when not allocated) +static uint32_t h2_insnGenerated; +typedef unsigned long long ticks_t; +static ticks_t h2_codeGenTime; + +typedef enum { H2REGISTER, H2VALUE, } VALORREG; +typedef struct +{ + int ValOrReg; // is H2REGISTER or immediate VALUE ? + char arith; // int, flt or other arithmetic + int vLen; // vector len + int wLen; // word len + int regNro; // register number (if register) + int valueImm; // immediate value (if not register) + bool dontFree; // if register, don't free +} h2_sValue_t; +#define sValueDef(VALUE, ARITH, VECTORLEN, WORDLEN, REGNO, IMMVAL) ((h2_sValue_t){.ValOrReg = VALUE, .arith = ARITH, .vLen = VECTORLEN, .wLen = WORDLEN, .regNro = REGNO, .valueImm = IMMVAL}) +#define intsValue(V) sValueDef(H2VALUE, 'i', 1, 32, -1, V) +#define intReg32sValue(R) sValueDef(H2REGISTER, 'i', 1, 32, R, 0) +#define immValueZero intsValue(0) +// Usefull macro instruction to simplify instruction selector code +#define isInt64_1(P) ((P.arith == 'i') && (P.wLen <= 64) && (P.vLen == 1)) +#define isInt32_1(P) ((P.arith == 'i') && (P.wLen <= 32) && (P.vLen == 1)) +#define isInt0(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (0 == P.valueImm)) +#define isInt1(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE) && (1 == P.valueImm)) +#define isValue(P) ((P.arith == 'i') && (P.ValOrReg == H2VALUE)) +#define isReg32(P, X) ((P.arith == 'i') && (P.ValOrReg == H2REGISTER) && (X == P.regNro)) +#define isRRR(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) +#define isRRV(P0, P1, P2) (P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + + +typedef union { + float f; + unsigned long i; +} h2_float_int_u; + +static int h2_log2(int value) +{ // integer logarithm + int log = 0; + while (value >>= 1) { ++log; } + return log; +} +// Print register map : F for free register, . for allocated +void printRev (int value, int pos) +{ // Print a bitset in reversal order (recursive) + if (pos != 0) + printRev (value >> 1, pos - 1); + printf ("%1c", (value % 2)?'.':'F'); +} + +// Dynamic register allocation handling +// h2_regSet mask : 0 mean free register, 1 register set +// 3 2 1 Bit position = reg Number +// 1098 7654 3210 9876 5432 1098 7654 3210 +// 1111 1111 1111 1111 0000 0001 0011 1111 +typedef struct +{ // Register allocation sets for + // int, float, vector of ints, vector of floats + int intSet, fltSet, vintSet, vfltSet ; +} h2_RegSets_t; + +h2_RegSets_t h2_regSet, h2_regSetInit; + +// Print integer register set +void printRegState(char * msg, int regNo, int registerSet) +{ + int count = 8 * sizeof (registerSet) - 1; + h2_regSet_t tmpReg = registerSet; + printf ("%02d : Reg %s\n", regNo, msg); + for (int i = count; i >= 0; i--) // Tens + (0 == (i % 10))?printf ("%d", i/10):printf (" "); + printf ("\n"); + for (int i = count; i >= 0; i--) // Unit + printf ("%d", i%10); + printf ("\n"); + printRev (tmpReg, count); // Bit set + printf ("\n"); +} + +// Initialize registers sets allocation +static void h2_initRegisterMasks(int intmask, int fltmask, int vectorintmask, int vectorfltmask) +{ // See H2SymbolTable & H2RegisterBank + h2_regSetInit = (h2_RegSets_t){intmask, fltmask, vectorintmask, vectorfltmask}; +} + +static void h2_resetRegisterMasks() // Reset register set from initializers +{ + h2_regSet = h2_regSetInit; +#ifdef H2_DEBUG_REGISTER + printRegState("RESET", -1, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER +} +int h2_getReg () // Get new register +{ + /* Search for the 1st free register */ + h2_regSet_t tmpReg = h2_regSet.intSet; + for (int i = 0; i < 8 * sizeof (h2_regSet.intSet); i++) + { + if (tmpReg % 2 == 0) + { /* Free register found */ + h2_regSet.intSet = h2_regSet.intSet | (1 << i); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("GET", i, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + return i; + } + tmpReg >>= 1; + } + printf ("Register allocation failed\n"); + h2_codeGenerationOK = false; + return -1; +} + +// h2_regSet_t regToBeFreed[32]; + +void h2_freeReg (h2_regSet_t v) // Free a register +{ +#if 1 // TODO : To be rethinked + // Is the register freeable ? + int isOK = (h2_regSetInit.intSet >> v) & 1; + if (0 == isOK) + { + h2_regSet.intSet = h2_regSet.intSet & ~(1 << v); /* Update regSet */ +#ifdef H2_DEBUG_REGISTER + printRegState("FREE", v, h2_regSet.intSet); +#endif // H2_DEBUG_REGISTER + } +#endif +} +#endif /*H2_COMMON*/ +#ifndef H2_AARCH64 +#define H2_AARCH64 + +#define H2SYS /* Has operating system */ + +#ifdef H2SYS +#include +#endif + +typedef uint32_t h2_insn_t; /* Instruction size */ +static h2_insn_t *h2_asm_pc; /* PC for code generation */ +static h2_insn_t *h2_save_asm_pc; +#define H2Aarch64SP (h2_sValue_t) {REGISTER, 'i', 1, 32, 31, 0} +/* aarch64 / power examples : + https://github.com/FFTW/fftw3/blob/master/kernel/cycle.h */ + +static inline ticks_t h2_getticks(void) +{ + uint64_t Rt; + asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt)); + return Rt; +} + +static void h2_iflush(void *addr, void *last) +{ + h2_insnGenerated = (last-addr)/sizeof (h2_insn_t); +#ifdef H2SYS + __clear_cache((char *)addr, (char *)last); // Flush data cache where binary code were written + long pageSize= getpagesize(); // Make the page executable + void *ptmp= (char *)((long)addr & ~(pageSize - 1)); + if (mprotect(ptmp, (last - addr), PROT_READ | PROT_WRITE | PROT_EXEC)) + { + perror("iflush: mprotect"); + exit(-1); + } + /* Gcc function to clear data cache after code generation */ + __clear_cache((char *)addr, (char *)last); +#endif +#ifdef H2_DEBUG + printf ("Flush data cache from %p to %p\n", addr, last); + printf ("%ld insn generated in %ld ticks. %ld ticks / insn\n", h2_insnGenerated, h2_codeGenTime, h2_codeGenTime/h2_insnGenerated); +#endif + if (!h2_codeGenerationOK) + { + fprintf (stderr, "(iflush) Failed code generation\n"); + exit(-5); + } +} + +static h2_insn_t *h2_malloc (size_t size) +{ + return malloc (size); +} + + +#endif /* H2_AARCH64 */ +/* In memory instruction generator */ +#define aarch64_G32(INSN){ *(h2_asm_pc++) = (INSN);} + +/* Single instruction binary code generator*/ +#define A64_RET__I_64_1() do /* ret */ { aarch64_G32(((0xd65f03c0 >> 0) & 0xffffffff)); \ + } while(0); +#define A64_ADD_RRR_I_8_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_8_16(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x73 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_32_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x44 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x58 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_I_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0x458 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRI_I_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_8_16(r0,r1,r2) do /* sub */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x173 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x258 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_32_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x144 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x175 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x375 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x377 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x21 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRI_I_64_1(r0,r1,i0) do /* sub */ { aarch64_G32(((0x344 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_SUB_RRR_I_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0x658 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x0 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_8_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RRR_I_16_8(r0,r1,r2) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MV_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r1 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x44000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_I_32_2(r0,i0) do /* mv */ { aarch64_G32(((0x1e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x1 & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_4(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_32_1(r0,i0) do /* mv */ { aarch64_G32(((0x294 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x138207 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x178101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_32_2(r0,r1) do /* mv */ { aarch64_G32(((0x38101 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x244000 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOV_RI_I_64_1(r0,i0) do /* mv */ { aarch64_G32(((0x694 & 0x7ff) << 21)|((i0 & 0xffff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x178201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_DUP_RR_I_64_2(r0,r1) do /* mv */ { aarch64_G32(((0x138201 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_8(r0,r1) do /* w */ { aarch64_G32(((0x3001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_8_16(r0,r1) do /* w */ { aarch64_G32(((0x13001c & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRB_RRI_I_8_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x1c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_8(r0,r1) do /* w */ { aarch64_G32(((0x13001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_16_4(r0,r1) do /* w */ { aarch64_G32(((0x3001d & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STRH_RRI_I_16_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x3c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_32_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x5c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x5c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_32_2(r0,r1,i0) do /* w */ { aarch64_G32(((0x7e0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x0 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_32_4(r0,r1) do /* w */ { aarch64_G32(((0x13001e & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRR_I_64_1(r0,r1,r2) do /* w */ { aarch64_G32(((0x7c1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ST1_RR_I_64_2(r0,r1) do /* w */ { aarch64_G32(((0x3001f & 0x3fffff) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_STR_RRI_I_64_1(r0,r1,i0) do /* w */ { aarch64_G32(((0x7c0 & 0x7ff) << 21)|((i0 & 0x1ff) << 12)|((0x1 & 0x3) << 10)|((r0 & 0x1f) << 5)|((r1 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_16_8(r0,r1,r2) do /* sub */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_16_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_32_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xe & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_32_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x75 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_32_4(r0,r1,r2) do /* sub */ { aarch64_G32(((0x275 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_64_2(r0,r1,r2) do /* sub */ { aarch64_G32(((0x277 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FSUB_RRR_F_64_1(r0,r1,r2) do /* sub */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xe & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_16(r0,r1) do /* r */ { aarch64_G32(((0x13101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRB_RRI_I_8_1(r0,r1,i0) do /* r */ { aarch64_G32(((0xe5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_8_8(r0,r1) do /* r */ { aarch64_G32(((0x3101c & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_4(r0,r1) do /* r */ { aarch64_G32(((0x3101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDRH_RRI_I_16_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x1e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_16_8(r0,r1) do /* r */ { aarch64_G32(((0x13101d & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRI_I_32_1(r0,r1,i0) do /* r */ { aarch64_G32(((0x2e5 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDP_RRI_I_32_2(r0,r1,i0) do /* r */ { aarch64_G32(((0xb3 & 0x3ff) << 22)|((i0 & 0x7f) << 15)|((0x0 & 0x1f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_2(r0,r1) do /* r */ { aarch64_G32(((0x3101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_32_4(r0,r1) do /* r */ { aarch64_G32(((0x13101e & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LDR_RRR_I_64_1(r0,r1,r2) do /* r */ { aarch64_G32(((0x7e3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x36 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LD1_RR_I_64_2(r0,r1) do /* r */ { aarch64_G32(((0x13101f & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_16_8(r0,r1,r2) do /* mul */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_16_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x7 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_32_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x2 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_32_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_32_4(r0,r1,r2) do /* mul */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_64_2(r0,r1,r2) do /* mul */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x37 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMUL_RRR_F_64_1(r0,r1,r2) do /* mul */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x2 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_32_1(r0,r1) do /* mv */ { aarch64_G32(((0x78810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_32_1(r0,i0) do /* mv */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_MOVI_RI_F_32_4(r0,i0) do /* mv */ { aarch64_G32(((0x9e0 & 0x1fff) << 19)|(((i0 >> 5) & 0x7) << 16)|((0x3d & 0x3f) << 10)|((i0 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RR_F_64_1(r0,r1) do /* mv */ { aarch64_G32(((0x79810 & 0x3fffff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FMOV_RI_F_64_1(r0,i0) do /* mv */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((i0 & 0xff) << 13)|((0x80 & 0xff) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_16_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x72 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_16_8(r0,r1,r2) do /* add */ { aarch64_G32(((0x272 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x5 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x71 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_4(r0,r1,r2) do /* add */ { aarch64_G32(((0x271 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_ADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_32_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_64_2(r0,r1,r2) do /* add */ { aarch64_G32(((0x273 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x35 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRR_F_64_1(r0,r1,r2) do /* add */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xa & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FADD_RRI_F_64_1(r0,r1,i0) do /* add */ { aarch64_G32(((0x244 & 0x3ff) << 22)|((i0 & 0xfff) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_32_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x1f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_32_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRI_I_64_1(r0,r1,i0) do /* sr */ { aarch64_G32(((0x34c & 0x3ff) << 22)|((i0 & 0x3f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSR_RRR_I_64_1(r0,r1,r2) do /* sr */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x9 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_32_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x14c & 0x3ff) << 22)|((((32 - i0)% 32) & 0x3f) << 16)|(((31 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_32_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0xd6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRI_I_64_1(r0,r1,i0) do /* sl */ { aarch64_G32(((0x34d & 0x3ff) << 22)|((((64 - i0)% 64) & 0x3f) << 16)|(((63 - i0) & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_LSL_RRR_I_64_1(r0,r1,r2) do /* sl */ { aarch64_G32(((0x4d6 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x8 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_16_8(r0,r1,r2) do /* div */ { aarch64_G32(((0x372 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_16_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x172 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0xf & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_32_4(r0,r1,r2) do /* div */ { aarch64_G32(((0x371 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_32_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x171 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_32_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xf1 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x6 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_64_1(r0,r1,r2) do /* div */ { aarch64_G32(((0xf3 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x6 & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +#define A64_FDIV_RRR_F_64_2(r0,r1,r2) do /* div */ { aarch64_G32(((0x373 & 0x7ff) << 21)|((r2 & 0x1f) << 16)|((0x3f & 0x3f) << 10)|((r1 & 0x1f) << 5)|((r0 & 0x1f) >> 0)); } while(0); +h2_sValue_t aarch64_genRET_0(); +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2); +h2_sValue_t aarch64_genRET_0() +{ +// No generic optimisation for RET + +// No specific optimisation for RET/aarch64 + +A64_RET__I_64_1(); + +} +h2_sValue_t aarch64_genMUL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MUL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ + // if 2 operands are constants do multiplication evaluation (Thanks Kilian for the bug report) + if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) + { + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm * P2.valueImm }; + } + /* if (isInt0(P2) || isInt0(P1)) */ + /* { // X * 0 = 0 Avoid 1 operation mul & 1 mv */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *0 P2 (generic)\n"); */ + /* #endif */ + /* return immValueZero; */ + /* } */ + /* if (isInt1(P2)) */ + /* { // X * 1 = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P2 (generic)\n"); */ + /* #endif */ + /* P1.dontFree = true; */ + /* return P1; */ + /* } */ + /* if (isInt1(P1)) */ + /* { // 1 * X = X propagate register result */ + /* #ifdef H2_DEBUG_INSN */ + /* printf ("Optim for *1 P1 (generic)\n"); */ + /* #endif */ + /* P2.dontFree = true; */ + /* return P2; */ + /* } */ + +/* -*- c -*- */ +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +if (isInt0(P2)) + { // X * 0 = 0 Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *0 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, immValueZero, P1); + } + +if (isInt1(P2)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P2 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P1, P1); + } + +if (isInt1(P1)) + { // X * 1 = X Avoid 1 operation mul +#ifdef H2_DEBUG_INSN + printf ("Optim for *1 P1 (aarch64)\n"); +#endif + return aarch64_genMV_3(P0, P2, P2); + } + +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for MUL %d (power of 2) -> sl %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSL_3(P0, P1, P2); + } + +// Mv constant value in register, then do division +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI mul (aarch64)\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); + // No return continue instruction selection +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FMUL_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MUL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SR instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SR + +// No specific optimisation for SR/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SR instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSUB_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SUB instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do substraction evaluation (Thanks Kilian for the bug report) +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm - P2.valueImm }; +} + +// No specific optimisation for SUB/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_SUB_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_SUB_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FSUB_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SUB instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genW_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for W instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for W + +/* -*- c -*- */ + +/* if (isInt32_1(P0) && isInt0(P1) && isInt0(P2) ) */ +/* { */ +/* #ifdef H2_DEBUG_INSN */ +/* // Store const 0 in memory (alias store, r31 interpreted as 0) */ +/* printf ("Store 0 (aarch64)\\n"); */ +/* #endif */ +/* A64_STR_RRI_I_32_1(P0.regNro, 31, 0); */ +/* return P0; */ +/* } */ + +if (isValue(P1)) + { // Store constant (Should use RRI variant) + h2_sValue_t PTMP = {H2REGISTER, P1.arith, P1.vLen, P1.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RI W (aarch64)\n"); + #endif + // MV const in tmp register + P1 = aarch64_genMV_3(PTMP, P1, immValueZero); + // No return continue instruction selection + } + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_8_16(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_8(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_16_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_32_4(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_ST1_RR_I_64_2(P0.regNro, P1.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 8) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 16) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 32) && (P1.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_STR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P1; + } + + if ((P1.arith == 'i') && (P1.wLen <= 64) && (P1.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_STR_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P1; + } + printf ("Warning, W instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genDIV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for DIV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// if 2 operands are constants do division evaluation +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return (h2_sValue_t) {H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm / P2.valueImm }; +} +// Transform RIR in RRI : P1 & P2 permutation +if ((P1.ValOrReg == H2VALUE) && (P2.ValOrReg == H2REGISTER)) + { + h2_sValue_t PTMP = P2; + P2 = P1; + P1 = PTMP; + } + +/* -*- c -*- */ +// X * NPowerOf2 = X >> N (immediate shift left) +if (isValue(P2) && ((P2.valueImm != 0) && !(P2.valueImm & (P2.valueImm - 1)))) + { + int shiftValue = h2_log2(P2.valueImm); + #ifdef H2_DEBUG_INSN + printf ("Optim for DIV %d (power of 2) -> sr %d (aarch64)\n", P2.valueImm, shiftValue); + #endif + P2.valueImm = shiftValue; // Instruction shift left immediat + return aarch64_genSR_3(P0, P1, P2); + } +if ((P2.ValOrReg == H2VALUE) && (P2.arith == 'i')) +{ + h2_sValue_t PTMP = {H2REGISTER, P2.arith, P2.vLen, P2.wLen, h2_getReg()}; + #ifdef H2_DEBUG_INSN + printf ("Fallback for no RRI div (aarch64)\\n"); + #endif + P2 = aarch64_genMV_3(PTMP, P2, immValueZero); +} + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FDIV_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, DIV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genADD_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for ADD instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +/* -*- c -*- */ +// If 2 operands are constants do addition +if ((P2.ValOrReg == H2VALUE) && (P1.ValOrReg == H2VALUE) && (P1.arith == 'i')&& (P2.arith == 'i')) +{ + return sValueDef(H2VALUE, P1.arith, P1.vLen, P1.wLen, -1, P1.valueImm + P2.valueImm ); +} +if (isInt0 (P2)) + { // P0 = P1 + 0 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P1.regNro); + #endif + P1.dontFree = true; + return P1; + } +if (isInt0 (P1)) + { // P0 = 0 + P2 + #ifdef H2_DEBUG_INSN + printf ("Optim add for 0 (generic) return reg %d\n", P2.regNro); + #endif + P2.dontFree = true; + return P2; + } + +// No specific optimisation for ADD/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_8_16(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_ADD_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_16_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_4(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_ADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_64_2(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_FADD_RRR_F_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_FADD_RRI_F_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + printf ("Warning, ADD instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genSL_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for SL instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for SL + +// No specific optimisation for SL/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_32_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LSL_RRI_I_64_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LSL_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, SL instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 2, (0==P2.ValOrReg)?"REG":"VAL", P2.arith, P2.wLen, P2.vLen, P2.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genR_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for R instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for R + +// No specific optimisation for R/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 16) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_16(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_8_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_16_8(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_LD1_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRB_RRI_I_8_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDRH_RRI_I_16_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDR_RRI_I_32_1(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2VALUE) + { + A64_LDP_RRI_I_32_2(P0.regNro, P1.regNro, P2.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_LDR_RRR_I_64_1(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, R instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} +h2_sValue_t aarch64_genMV_3(h2_sValue_t P0,h2_sValue_t P1,h2_sValue_t P2) +{ +#ifdef H2_DEBUG_INSN + printf ("Start code gen for MV instruction\n"); + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); + printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); + printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm); +#endif // H2_DEBUG_INSN +// No generic optimisation for MV + +// No specific optimisation for MV/aarch64 + + if ((P0.ValOrReg == H2REGISTER) && (P0.regNro == -1)) + P0.regNro = h2_getReg(); + if ((P1.ValOrReg == H2REGISTER) && (P1.regNro == -1)) + P1.regNro = h2_getReg(); + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MV_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_I_32_2(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_4(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 32) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_32_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_MOV_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOV_RI_I_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 64) && (P0.vLen == 2) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_DUP_RR_I_64_2(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_32_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_32_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 32) && (P0.vLen == 4) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_MOVI_RI_F_32_4(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER) + { + A64_FMOV_RR_F_64_1(P0.regNro, P1.regNro); + return P0; + } + + if ((P0.arith == 'f') && (P0.wLen <= 64) && (P0.vLen == 1) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2VALUE) + { + A64_FMOV_RI_F_64_1(P0.regNro, P1.valueImm); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 8) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_8_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + + if ((P0.arith == 'i') && (P0.wLen <= 16) && (P0.vLen == 8) && P0.ValOrReg == H2REGISTER && P1.ValOrReg == H2REGISTER && P2.ValOrReg == H2REGISTER) + { + A64_MOV_RRR_I_16_8(P0.regNro, P1.regNro, P2.regNro); + return P0; + } + printf ("Warning, MV instruction generation failed\n"); + h2_codeGenerationOK = false; + printf ("ValOrReg / arith / wLen / vLen / regNro / valueImm\n"); printf ("P%d: %s/%c/%d/%d/%d\n", 0, (0==P0.ValOrReg)?"REG":"VAL", P0.arith, P0.wLen, P0.vLen, P0.valueImm); printf ("P%d: %s/%c/%d/%d/%d\n", 1, (0==P1.ValOrReg)?"REG":"VAL", P1.arith, P1.wLen, P1.vLen, P1.valueImm);return immValueZero; +} + +/* End Header autogenerated part */ +// -*- c -*- +#include +#include + +/* Pointer on function which take 2 floats and return float */ +typedef float (*pifff)(float, float); + +/* C compilette prototype */ +h2_insn_t * genAddf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genADD_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genMulf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genMUL_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genSubf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genSUB_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +h2_insn_t * genDivf(h2_insn_t * ptr) +{ + /* Code Generation of 3 instructions */ + /* Symbol table :*/ + /*VarName = {ValOrLen, arith, vectorLen, wordLen, regNo, ValueImm, dontFree} */ + h2_sValue_t a = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t b = {H2REGISTER, 'f', 1, 32, 1, true}; + h2_sValue_t h2_outputVarName = {H2REGISTER, 'f', 1, 32, 0, true}; + h2_sValue_t r = {H2REGISTER, 'f', 1, 32, 12, true}; + h2_sValue_t tmp0000 = {H2REGISTER, 'f', 1, 32, -1, false}; + + /* Label table :*/ +/* No label table to avoid C warning for empty table ... */ + h2_asm_pc = (h2_insn_t *) ptr; + h2_codeGenerationOK = true; + h2_codeGenTime = h2_getticks(); + h2_initRegisterMasks(0xFFFF0100, 0, 0, 0); + h2_resetRegisterMasks(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask initialization\n"); + #endif // H2_DEBUG_REGISTER + + r = aarch64_genDIV_3(r, a, b); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + h2_outputVarName = aarch64_genMV_3(h2_outputVarName, r, immValueZero); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + aarch64_genRET_0(); + #ifdef H2_DEBUG_REGISTER + printf("Tmp registers mask reset\n"); + #endif // H2_DEBUG_REGISTER + h2_resetRegisterMasks(); + /* Call back code for loops */ + h2_save_asm_pc = h2_asm_pc; + h2_asm_pc = h2_save_asm_pc; + h2_codeGenTime = h2_getticks() - h2_codeGenTime; + h2_iflush(ptr, h2_asm_pc); + + return (h2_insn_t *)ptr; +} + +int main(int argc, char * argv[]) +{ + h2_insn_t * ptr; + float fin0, fin1, fres; + pifff fPtrf; + int resultOK; + + if (argc < 3) + { + printf("Give 2 values\n"); + exit(-1); + } + resultOK = 0; + fin0 = atof (argv[1]); // Get the users values in1 & in2 (flt) + fin1 = atof (argv[2]); + + ptr = h2_malloc (1024); + fPtrf = (pifff) genAddf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple addition of 2 floating point values:\n"); + printf("%f + %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 + fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genSubf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple subraction of 2 floating point values:\n"); + printf("%f - %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 - fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genMulf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple multiplication of 2 floating point values:\n"); + printf("%f * %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 * fin1)) + resultOK += 1; + + ptr = h2_malloc (1024); + fPtrf = (pifff) genDivf (ptr); + fres = fPtrf(fin0, fin1); + printf ("Simple division of 2 floating point values:\n"); + printf("%f / %f = %f\n", fin0, fin1, fres); + if (fres != (fin0 / fin1)) + resultOK += 1; + + if (resultOK == 0) + return 0; + else + return -1; +} diff --git a/CodeExamples/Multiple-flt.power b/CodeExamples/Multiple-flt.power new file mode 100755 index 0000000000000000000000000000000000000000..04c082a1413fd1a7d626f8f33069e7adbadf9924 GIT binary patch literal 78456 zcmeHw4SZY0mG4|hw&mDy+8s05cUT4k^r$c{1Sm zi1YAZhk&Y(acRVrc-7w*`TF}B$5&xJF@$5k3{^Q|kIH#uIgc!-!d}Uk3YB~$8=dQ< zdmY@rcgea%N;{wW5$Z-L?3gw8;(H=@^8)bdj^m0t{ zuR_%h6~REmqDv}*O^YrmkA=$@QoY0r(IuSK8@AxecsozvF>xXF7U3+!nU8ZKPV*tF z<1`4DWXi)yZBDwSI*48YPCBSAb#lNcFH~l7eL6DLmkGWUaMc&hr50tuugd~on*}~A z3;ZU)b)2aO=`9nVE3&}P$pW981zwf~&isi$oJIW6XgJCu?eQ308e4rxL<6CCGi&k3 zBfb`YEO4`*wMC-gxW6&Z+I+!axRJ%;O(@8kZ;A%ue&&mZo0->(j@0Ol#eLDZx6Ky_ zF-lXHTEtebtF2z{U0A;0QlPc8g+mg}3*Kx){>*7);?VHdfKc`GuXcY0O>1L8o{PR@ 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