From ecb79dda039092c707497cd3c5d36e6d779c5851 Mon Sep 17 00:00:00 2001
From: klin02 <youkunlin20@mails.ucas.ac.cn>
Date: Wed, 17 Dec 2025 14:23:47 +0800
Subject: [PATCH] Bump difftest: auto topIO connection and refactor checker

---
 difftest                             | 2 +-
 src/main/scala/sim/NutShellSim.scala | 3 +--
 src/test/scala/TopMain.scala         | 3 ---
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/difftest b/difftest
index 43a308e8..9b058bd0 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 43a308e89ae28dfb52425c26e6995c7db2291daa
+Subproject commit 9b058bd01a349c715ed83aadd9a4dadbd7b0f4e9
diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala
index b175e9b3..51b84872 100644
--- a/src/main/scala/sim/NutShellSim.scala
+++ b/src/main/scala/sim/NutShellSim.scala
@@ -45,8 +45,7 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart
-  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
+  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
     difftest.uart <> uart
-    Seq.empty
   }
 }
diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala
index 4678e81a..72c0b4cc 100644
--- a/src/test/scala/TopMain.scala
+++ b/src/test/scala/TopMain.scala
@@ -39,9 +39,6 @@ class Top extends Module {
 class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
   override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
-  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
-    Seq(io)
-  }
 }
 
 object TopMain extends App {