From ba39efa2a49b5a37133ed657290cacd9d7075a6f Mon Sep 17 00:00:00 2001 From: JLP Date: Mon, 5 Oct 2026 19:47:42 -0400 Subject: [PATCH] F4 uart: mask received data to 8 bits, align with F7/H7 With parity enabled the F4 data register holds the parity bit in bit 8, and it was passed through to the rx callback. F7/H7 drivers already mask to 8 bits. Protocol handlers comparing the received value directly, e.g. the SBUS 0x2F start byte, never matched on F4. --- src/main/drivers/serial_uart_stm32f4xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/drivers/serial_uart_stm32f4xx.c b/src/main/drivers/serial_uart_stm32f4xx.c index 0f54fb69142..6b5bc7fddcf 100644 --- a/src/main/drivers/serial_uart_stm32f4xx.c +++ b/src/main/drivers/serial_uart_stm32f4xx.c @@ -217,7 +217,7 @@ void uartIrqHandler(uartPort_t *s) { if (USART_GetITStatus(s->USARTx, USART_IT_RXNE) == SET) { if (s->port.rxCallback) { - s->port.rxCallback(s->USARTx->DR, s->port.rxCallbackData); + s->port.rxCallback(s->USARTx->DR & 0xFF, s->port.rxCallbackData); // mask out parity bit } else { s->port.rxBuffer[s->port.rxBufferHead] = s->USARTx->DR; s->port.rxBufferHead = (s->port.rxBufferHead + 1) % s->port.rxBufferSize;