From 38abc0f6a72b694ec41743c92cd29486665d3ba8 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Wed, 22 Apr 2026 14:26:28 +0500 Subject: [PATCH 01/11] completed rename stage --- Design/BS.sv | 28 +++---- Design/FL.sv | 16 ++-- Design/ID_Stage.sv | 5 +- Design/RMT.sv | 6 +- Design/RN_Stage.sv | 188 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 217 insertions(+), 26 deletions(-) create mode 100644 Design/RN_Stage.sv diff --git a/Design/BS.sv b/Design/BS.sv index 9664a39..5cb3c9d 100644 --- a/Design/BS.sv +++ b/Design/BS.sv @@ -2,30 +2,32 @@ module BS #( parameter PRF_ADDRESS = 6, parameter NUM_PHY_REG = 1 << PRF_ADDRESS, parameter MAX_BRANCHES = 4, - parameter BTAG_SIZE = $clog2(MAX_BRANCHES) + parameter BTAG_SIZE = $clog2(MAX_BRANCHES), + parameter FL_ROWS = NUM_PHY_REG - 32, + parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), + parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 ) ( input logic CLK, reset, id_take_snap, ex_branch_resolved, input logic [BTAG_SIZE-1:0] ex_btag, input logic [PRF_ADDRESS-1:0] rmt_snap [0:31], - input logic [NUM_PHY_REG-1:0] busy_table_snap, - input logic [PRF_ADDRESS-1:0] freelist_head_snap, + input logic [FL_PTR_WIDTH-1:0] freelist_head_snap, + output logic bs_full, output logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31], - output logic [NUM_PHY_REG-1:0] bs_busytable_snap, - output logic [PRF_ADDRESS-1:0] bs_freelist_head_snap, + output logic [FL_PTR_WIDTH-1:0] bs_freelist_head_snap, output logic [BTAG_SIZE-1:0] bs_branch_tag, output logic [MAX_BRANCHES-1:0] bs_branch_mask ); typedef struct { logic [PRF_ADDRESS-1:0] rmt_snapshot [0:31]; - logic [NUM_PHY_REG-1:0] busy_table_snapshot; - logic [PRF_ADDRESS-1:0] freelist_head_snapshot; + logic [FL_PTR_WIDTH-1:0] freelist_head_snapshot; } bs_organization; bs_organization BS [0:MAX_BRANCHES-1]; logic [MAX_BRANCHES-1:0] BMR; logic [BTAG_SIZE-1:0] current_btag; + always_comb begin current_btag = '0; @@ -36,15 +38,16 @@ module BS #( end end end - //to dispatch stage - assign bs_branch_tag = current_btag; - assign bs_branch_mask = BMR; + //to rename map table assign bs_rmt_snap = BS[ex_btag].rmt_snapshot; - assign bs_busytable_snap = BS[ex_btag].busy_table_snapshot; assign bs_freelist_head_snap = BS[ex_btag].freelist_head_snapshot; - + assign bs_full = &BMR; always_ff @(posedge CLK) begin + //to dispatch stage + bs_branch_tag <= current_btag; + bs_branch_mask <= BMR; + if (reset) begin BMR <= '0; end @@ -56,7 +59,6 @@ module BS #( if (id_take_snap) begin BMR[current_btag] <= 1'b1; BS[current_btag].rmt_snapshot <= rmt_snap; - BS[current_btag].busy_table_snapshot <= busy_table_snap; BS[current_btag].freelist_head_snapshot <= freelist_head_snap; end end diff --git a/Design/FL.sv b/Design/FL.sv index c55b910..7aa264d 100644 --- a/Design/FL.sv +++ b/Design/FL.sv @@ -5,24 +5,25 @@ module FL #( parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 ) ( - input logic CLK, flush, reset, push1, push2, pop, + input logic CLK, flush, reset, push1, push2, pop1, pop2, + input logic stall_frontend, input logic [PRF_ADDRESS-1:0] comm_free_reg1, comm_free_reg2, input logic [FL_PTR_WIDTH-1:0] bs_head_ptr_snap, output logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, output logic [FL_PTR_WIDTH-1:0] fl_head_ptr, - output logic stall_frontend + output logic fl_empty ); logic [PRF_ADDRESS-1:0] FL [0:FL_ROWS-1]; logic [FL_PTR_WIDTH-1:0] head, tail; - assign stall_frontend = (head == tail); - + + assign fl_empty = (tail - head) < 2; assign fl_head_ptr = head; assign fl_freed_reg1 = FL[head[FL_INDEX_WIDTH-1:0]]; assign fl_freed_reg2 = FL[FL_INDEX_WIDTH'(head[FL_INDEX_WIDTH-1:0]+1)]; always_ff @(posedge CLK) begin if (reset) begin - for (int i = 32; i < (1 << PRF_ADDRESS); i++) begin + for (int i = 32; i < NUM_PHY_REG; i++) begin FL[i-32] <= i; end head <= '0; // ALL ZEROS @@ -33,9 +34,12 @@ module FL #( if (flush) begin head <= bs_head_ptr_snap; end - else if (pop) begin + else if (pop1 && pop2 && !stall_frontend) begin head <= head + 2; end + else if ((pop1 || pop2) && !stall_frontend) begin + head <= head + 1; + end //from the commit stage we push registers back to free list if (push1 && push2) begin FL[tail[FL_INDEX_WIDTH-1:0]] <= comm_free_reg1; diff --git a/Design/ID_Stage.sv b/Design/ID_Stage.sv index f6041f9..c4c8214 100644 --- a/Design/ID_Stage.sv +++ b/Design/ID_Stage.sv @@ -27,9 +27,9 @@ module ID_Stage #( output logic [BIQ_ADDRESS-1:0] id_biq_address, output logic [XLEN-1:0] id_biq_pred_target, output logic [XLEN-3:0] id_pc, - output logic [2:0] id_alu_op1, id_alu_op2, - output logic [GHR_SIZE-1:0] id_biq_restore_ghr, + output logic [GHR_SIZE-1:0] id_biq_restore_ghr, output logic [PHT_ADDRESS-1:0] id_biq_pht_index, + output logic [2:0] id_alu_op1, id_alu_op2, output logic id_jump_reg1, id_jump_reg2, id_jump1, id_jump2, id_branch1, id_branch2, id_regsrc1_1, output logic id_immtype1, id_memwrite1, id_immtype2, id_biq_valid, id_biq_pred_taken, id_regsrc2_1, output logic id_regsrc1_2, id_regsrc2_2, id_upperimm1, id_upperimm2, id_regwrite1, id_regwrite2, @@ -188,6 +188,7 @@ module ID_Stage #( .biq_valid (id_biq_valid), .biq_pred_taken (id_biq_pred_taken), .biq_pred_target (id_biq_pred_target), + //for prediction stage .biq_restore_ghr (id_biq_restore_ghr), .biq_pht_index (id_biq_pht_index), .biq_sp_snap (id_biq_sp_snap), diff --git a/Design/RMT.sv b/Design/RMT.sv index 2c5b2b2..ce9b1ef 100644 --- a/Design/RMT.sv +++ b/Design/RMT.sv @@ -7,19 +7,16 @@ module RMT #( input logic [4:0] rd2, rs1_2, rs2_2, input logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, cdb_waked_reg1, cdb_waked_reg2, input logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31], - input logic [NUM_PHY_REG-1:0] bs_busy_table_snap, output logic prs1_busy1, prs2_busy1, prs1_busy2, prs2_busy2, output logic [PRF_ADDRESS-1:0] prd1, prs1_1, prs2_1, output logic [PRF_ADDRESS-1:0] prd2, prs1_2, prs2_2, - output logic [PRF_ADDRESS-1:0] rmt_snap [0:31], - output logic [NUM_PHY_REG-1:0] busy_table_snap + output logic [PRF_ADDRESS-1:0] rmt_snap [0:31] ); logic [PRF_ADDRESS-1:0] RMT [0:31]; logic [NUM_PHY_REG-1:0] busy_table; logic wake_rs1_1, wake_rs1_2, wake_rs2_1, wake_rs2_2; - assign busy_table_snap = busy_table; assign rmt_snap = RMT; assign wake_rs1_1 = (((cdb_waked_reg1 != '0) && cdb_wakeup1 && (cdb_waked_reg1 == RMT[rs1_1])) || @@ -49,7 +46,6 @@ module RMT #( else begin if (restore_rmt) begin RMT <= bs_rmt_snap; - busy_table <= bs_busy_table_snap; end else begin //updating Rename Map Table diff --git a/Design/RN_Stage.sv b/Design/RN_Stage.sv new file mode 100644 index 0000000..922595a --- /dev/null +++ b/Design/RN_Stage.sv @@ -0,0 +1,188 @@ +module RN_Stage #( + parameter PRF_ADDRESS = 6, + parameter INIT_IMMEDIATE_SIZE = 21, + parameter MAX_BRANCHES = 4, + parameter BTAG_SIZE = $clog2(MAX_BRANCHES), + parameter BIQ_ADDRESS = 5, + parameter XLEN = 32, + parameter NUM_PHY_REG = 1 << PRF_ADDRESS, + parameter FL_ROWS = NUM_PHY_REG - 32, + parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), + parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 +) ( + input logic CLK, + input logic reset, + input logic flush, + input logic id_take_snap, id_valid1, id_valid2, + input logic cdb_wakeup1, cdb_wakeup2, comm_free_push1, comm_free_push2, ex_branch_resolved, + input logic [PRF_ADDRESS-1:0] cdb_waked_reg1, cdb_waked_reg2, comm_free_reg1, comm_free_reg2, + input logic [BTAG_SIZE-1:0] ex_btag, + input logic [2:0] id_funct3_1, id_funct3_2, + input logic [6:0] id_funct7_1, id_funct7_2, + input logic [4:0] id_rs1_1, id_rs2_1, id_rd_1, + input logic [4:0] id_rs1_2, id_rs2_2, id_rd_2, + input logic [INIT_IMMEDIATE_SIZE-1:0] id_immout1, id_immout2, + input logic [BIQ_ADDRESS-1:0] id_biq_address, + input logic [XLEN-3:0] id_pc, + input logic [2:0] id_alu_op1, id_alu_op2, + input logic id_jump_reg1, id_jump_reg2, id_jump1, id_jump2, id_branch1, id_branch2, id_regsrc1_1, + input logic id_immtype1, id_memwrite1, id_immtype2, id_regsrc2_1, + input logic id_regsrc1_2, id_regsrc2_2, id_upperimm1, id_upperimm2, id_regwrite1, id_regwrite2, + input logic id_memwrite2, id_memtoreg1, id_memtoreg2, id_retaddr1, id_retaddr2, id_isimm1, id_isimm2, + output logic stall_frontend, + output logic [PRF_ADDRESS-1:0] rn_prd1, rn_prs1_1, rn_prs2_1, rn_prd2, rn_prs1_2, rn_prs2_2, + output logic rn_prs1_busy1, rn_prs2_busy1, rn_prs1_busy2, rn_prs2_busy2, + output logic [BTAG_SIZE-1:0] rn_branch_tag, + output logic [MAX_BRANCHES-1:0] rn_branch_mask, + output logic [BIQ_ADDRESS-1:0] rn_biq_address, + output logic [XLEN-3:0] rn_pc, + output logic [2:0] rn_funct3_1, rn_funct3_2, + output logic [6:0] rn_funct7_1, rn_funct7_2, + output logic [INIT_IMMEDIATE_SIZE-1:0] rn_immout1, rn_immout2, + output logic [2:0] rn_alu_op1, rn_alu_op2, + output logic rn_valid1, rn_jump_reg1, rn_jump1, rn_branch1, + output logic rn_regsrc1_1, rn_regsrc2_1, rn_immtype1, rn_isimm1, rn_retaddr1, + output logic rn_upperimm1, rn_regwrite1, rn_memwrite1, rn_memtoreg1, + + output logic rn_valid2, rn_jump_reg2, rn_jump2, rn_branch2, + output logic rn_regsrc1_2, rn_regsrc2_2, rn_immtype2, rn_isimm2, rn_retaddr2, + output logic rn_upperimm2, rn_regwrite2, rn_memwrite2, rn_memtoreg2 +); + logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2; + logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31]; + logic [PRF_ADDRESS-1:0] rmt_snap [0:31]; + logic [FL_PTR_WIDTH-1:0] fl_head_ptr, bs_head_ptr_snap; + logic [PRF_ADDRESS-1:0] routed_freed_reg1, routed_freed_reg2; + + logic pop1, pop2; + + assign pop1 = id_valid1 && id_regwrite1 && (id_rd_1 != 5'b0); + assign pop2 = id_valid2 && id_regwrite2 && (id_rd_2 != 5'b0); + + assign routed_freed_reg1 = fl_freed_reg1; + assign routed_freed_reg2 = (pop1) ? fl_freed_reg2 : fl_freed_reg1; + assign stall_frontend = bs_full || fl_empty; + + always_ff @(posedge CLK) begin + rn_biq_address <= id_biq_address; + rn_pc <= id_pc; + // Instruction 1 Control Signals + rn_funct3_1 <= id_funct3_1; + rn_funct7_1 <= id_funct7_1; + rn_valid1 <= id_valid1 && !flush && !stall_frontend; + rn_immout1 <= id_immout1; + rn_alu_op1 <= id_alu_op1; + rn_jump_reg1 <= id_jump_reg1; + rn_jump1 <= id_jump1; + rn_branch1 <= id_branch1; + rn_regsrc1_1 <= id_regsrc1_1; + rn_regsrc2_1 <= id_regsrc2_1; + rn_immtype1 <= id_immtype1; + rn_isimm1 <= id_isimm1; + rn_upperimm1 <= id_upperimm1; + rn_regwrite1 <= id_regwrite1; + rn_memwrite1 <= id_memwrite1; + rn_memtoreg1 <= id_memtoreg1; + rn_retaddr1 <= id_retaddr1; + // Instruction 2 Control Signals + rn_funct3_2 <= id_funct3_2; + rn_funct7_2 <= id_funct7_2; + rn_valid2 <= id_valid2 && !flush && !stall_frontend; + rn_immout2 <= id_immout2; + rn_alu_op2 <= id_alu_op2; + rn_jump_reg2 <= id_jump_reg2; + rn_jump2 <= id_jump2; + rn_branch2 <= id_branch2; + rn_regsrc1_2 <= id_regsrc1_2; + rn_regsrc2_2 <= id_regsrc2_2; + rn_immtype2 <= id_immtype2; + rn_isimm2 <= id_isimm2; + rn_upperimm2 <= id_upperimm2; + rn_regwrite2 <= id_regwrite2; + rn_memwrite2 <= id_memwrite2; + rn_memtoreg2 <= id_memtoreg2; + rn_retaddr2 <= id_retaddr2; + end + RMT rmt_instantiation ( + .CLK (CLK), + .reset (reset), + .restore_rmt (flush), + + .reg_write1 (id_regwrite1), + .reg_write2 (id_regwrite2), + .cdb_wakeup1 (cdb_wakeup1), + .cdb_wakeup2 (cdb_wakeup2), + + .rd1 (id_rd_1), + .rs1_1 (id_rs1_1), + .rs2_1 (id_rs2_1), + + .rd2 (id_rd_2), + .rs1_2 (id_rs1_2), + .rs2_2 (id_rs2_2), + + .fl_freed_reg1 (routed_freed_reg1), + .fl_freed_reg2 (routed_freed_reg2), + .cdb_waked_reg1 (cdb_waked_reg1), + .cdb_waked_reg2 (cdb_waked_reg2), + + .bs_rmt_snap (bs_rmt_snap), + + .prd1 (rn_prd1), + .prs1_1 (rn_prs1_1), + .prs2_1 (rn_prs2_1), + .prs1_busy1 (rn_prs1_busy1), + .prs2_busy1 (rn_prs2_busy1), + + .prd2 (rn_prd2), + .prs1_2 (rn_prs1_2), + .prs2_2 (rn_prs2_2), + .prs1_busy2 (rn_prs1_busy2), + .prs2_busy2 (rn_prs2_busy2), + + .rmt_snap (rmt_snap) + ); + + FL fl_instantiation ( + .CLK (CLK), + .reset (reset), + .flush (flush), + .stall_frontend (stall_frontend), + .pop1 (pop1), + .pop2 (pop2), + .bs_head_ptr_snap (bs_head_ptr_snap), + + .push1 (comm_free_push1), + .push2 (comm_free_push2), + .comm_free_reg1 (comm_free_reg1), + .comm_free_reg2 (comm_free_reg2), + //output + .fl_head_ptr (fl_head_ptr), + .fl_freed_reg1 (fl_freed_reg1), + .fl_freed_reg2 (fl_freed_reg2), + .fl_empty (fl_empty) //signal for frontend + + ); + + BS bs_instantiation ( + .CLK (CLK), + .reset (reset), + .id_take_snap (id_take_snap && !stall_frontend && !flush), //if branch instructions then take snapshot + + .rmt_snap (rmt_snap), + .freelist_head_snap (fl_head_ptr), + //from ex stage to reset branch mask register when branch gets resolved + .ex_branch_resolved (ex_branch_resolved), + .ex_btag (ex_btag), + + //output + .bs_branch_tag (rn_branch_tag), + .bs_branch_mask (rn_branch_mask), + + // Restoring the rat and busytable and free list + .bs_rmt_snap (bs_rmt_snap), + .bs_freelist_head_snap (bs_head_ptr_snap), + .bs_full (bs_full) + ); + +endmodule \ No newline at end of file From cde5d4c6a26ee18bc4b89f2199037ebbd5f45bc5 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Thu, 23 Apr 2026 22:11:20 +0500 Subject: [PATCH 02/11] completed rename stage --- Design/BS.sv | 18 +++++- Design/FL.sv | 44 +++++++++------ Design/RMT.sv | 135 ++++++++++++++++++++++++++++----------------- Design/RN_Stage.sv | 36 ++++++++---- 4 files changed, 151 insertions(+), 82 deletions(-) diff --git a/Design/BS.sv b/Design/BS.sv index 5cb3c9d..c86c586 100644 --- a/Design/BS.sv +++ b/Design/BS.sv @@ -7,7 +7,8 @@ module BS #( parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 ) ( - input logic CLK, reset, id_take_snap, ex_branch_resolved, + input logic CLK, reset, flush, id_take_snap, ex_branch_resolved, pop1, pop2, + input logic id_branch1, id_jump1, id_valid1, input logic [BTAG_SIZE-1:0] ex_btag, input logic [PRF_ADDRESS-1:0] rmt_snap [0:31], input logic [FL_PTR_WIDTH-1:0] freelist_head_snap, @@ -21,14 +22,14 @@ module BS #( typedef struct { logic [PRF_ADDRESS-1:0] rmt_snapshot [0:31]; logic [FL_PTR_WIDTH-1:0] freelist_head_snapshot; + logic [MAX_BRANCHES-1:0] bmr_snapshot; } bs_organization; bs_organization BS [0:MAX_BRANCHES-1]; logic [MAX_BRANCHES-1:0] BMR; logic [BTAG_SIZE-1:0] current_btag; - - + always_comb begin current_btag = '0; for (int i = 0; i < MAX_BRANCHES; i++) begin @@ -43,6 +44,7 @@ module BS #( assign bs_rmt_snap = BS[ex_btag].rmt_snapshot; assign bs_freelist_head_snap = BS[ex_btag].freelist_head_snapshot; assign bs_full = &BMR; + always_ff @(posedge CLK) begin //to dispatch stage bs_branch_tag <= current_btag; @@ -53,13 +55,23 @@ module BS #( end else begin //when branch is resolved we make the tag bit zero back again + if (flush) begin + BMR <= BS[ex_btag].bmr_snapshot; + end if (ex_branch_resolved) begin BMR[ex_btag] <= 1'b0; + //all the branches that took snapshot of BMR should also get 0 because branch is resolved + for (int i = 0; i < MAX_BRANCHES; i++) begin + if (!(id_take_snap && (i == current_btag))) begin + BS[i].bmr_snapshot[ex_btag] <= 1'b0; + end + end end if (id_take_snap) begin BMR[current_btag] <= 1'b1; BS[current_btag].rmt_snapshot <= rmt_snap; BS[current_btag].freelist_head_snapshot <= freelist_head_snap; + BS[current_btag].bmr_snapshot <= (ex_branch_resolved) ? (BMR & ~(1 << ex_btag)) : BMR; end end end diff --git a/Design/FL.sv b/Design/FL.sv index 7aa264d..81a11d6 100644 --- a/Design/FL.sv +++ b/Design/FL.sv @@ -5,22 +5,41 @@ module FL #( parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 ) ( - input logic CLK, flush, reset, push1, push2, pop1, pop2, - input logic stall_frontend, + input logic CLK, reset, flush, stall_frontend, push1, push2, pop1, pop2, + input logic id_branch1, id_jump1, id_valid1, input logic [PRF_ADDRESS-1:0] comm_free_reg1, comm_free_reg2, input logic [FL_PTR_WIDTH-1:0] bs_head_ptr_snap, output logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, output logic [FL_PTR_WIDTH-1:0] fl_head_ptr, output logic fl_empty ); + logic [PRF_ADDRESS-1:0] FL [0:FL_ROWS-1]; - logic [FL_PTR_WIDTH-1:0] head, tail; - - assign fl_empty = (tail - head) < 2; - assign fl_head_ptr = head; + logic [FL_PTR_WIDTH-1:0] head, next_head, tail; + logic valid_pop1, valid_pop2; + logic [FL_PTR_WIDTH-1:0] registers_required; + + assign registers_required = {{(FL_PTR_WIDTH-1){1'b0}}, pop1} + {{(FL_PTR_WIDTH-1){1'b0}}, pop2}; + assign fl_empty = (tail - head) < registers_required; assign fl_freed_reg1 = FL[head[FL_INDEX_WIDTH-1:0]]; assign fl_freed_reg2 = FL[FL_INDEX_WIDTH'(head[FL_INDEX_WIDTH-1:0]+1)]; + + assign valid_pop1 = pop1 && !stall_frontend && !flush; + assign valid_pop2 = pop2 && !stall_frontend && !flush; + + always_comb begin + //during flush, we fetch instruction from correct path, so we dont pop register in this cycle + next_head = (flush) ? bs_head_ptr_snap : (head + valid_pop1 + valid_pop2); + + if ((id_branch1 || id_jump1) && id_valid1) begin + fl_head_ptr = head + valid_pop1; + end else begin + fl_head_ptr = next_head; // Same as head + valid_pop1 + valid_pop2 + end + end + + always_ff @(posedge CLK) begin if (reset) begin for (int i = 32; i < NUM_PHY_REG; i++) begin @@ -30,16 +49,7 @@ module FL #( tail <= {1'b1, {FL_INDEX_WIDTH{1'b0}}}; // IS FULL (BACK TO HEAD) end else begin - //during flush, we fetch instruction from correct path, so we dont pop register in this cycle - if (flush) begin - head <= bs_head_ptr_snap; - end - else if (pop1 && pop2 && !stall_frontend) begin - head <= head + 2; - end - else if ((pop1 || pop2) && !stall_frontend) begin - head <= head + 1; - end + head <= next_head; //from the commit stage we push registers back to free list if (push1 && push2) begin FL[tail[FL_INDEX_WIDTH-1:0]] <= comm_free_reg1; @@ -50,8 +60,6 @@ module FL #( FL[tail[FL_INDEX_WIDTH-1:0]] <= (push1)? comm_free_reg1 : comm_free_reg2; tail <= tail + 1; end - - end end diff --git a/Design/RMT.sv b/Design/RMT.sv index ce9b1ef..48ec6c8 100644 --- a/Design/RMT.sv +++ b/Design/RMT.sv @@ -2,23 +2,24 @@ module RMT #( parameter PRF_ADDRESS = 6, parameter NUM_PHY_REG = 1 << PRF_ADDRESS ) ( - input logic CLK, reset, restore_rmt, reg_write1, reg_write2, cdb_wakeup1, cdb_wakeup2, + input logic CLK, reset, restore_rmt, stall_frontend, reg_write1, reg_write2, cdb_wakeup1, cdb_wakeup2, + input logic id_branch1, id_jump1, id_valid1, id_valid2, input logic [4:0] rd1, rs1_1, rs2_1, input logic [4:0] rd2, rs1_2, rs2_2, input logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, cdb_waked_reg1, cdb_waked_reg2, input logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31], output logic prs1_busy1, prs2_busy1, prs1_busy2, prs2_busy2, - output logic [PRF_ADDRESS-1:0] prd1, prs1_1, prs2_1, - output logic [PRF_ADDRESS-1:0] prd2, prs1_2, prs2_2, + output logic [PRF_ADDRESS-1:0] prd1, prs1_1, prs2_1, old_prd1, + output logic [PRF_ADDRESS-1:0] prd2, prs1_2, prs2_2, old_prd2, output logic [PRF_ADDRESS-1:0] rmt_snap [0:31] ); logic [PRF_ADDRESS-1:0] RMT [0:31]; + logic [PRF_ADDRESS-1:0] next_RMT [0:31]; + logic [PRF_ADDRESS-1:0] next_RMT_inst1 [0:31]; logic [NUM_PHY_REG-1:0] busy_table; logic wake_rs1_1, wake_rs1_2, wake_rs2_1, wake_rs2_2; - assign rmt_snap = RMT; - assign wake_rs1_1 = (((cdb_waked_reg1 != '0) && cdb_wakeup1 && (cdb_waked_reg1 == RMT[rs1_1])) || ((cdb_waked_reg2 != '0) && cdb_wakeup2 && (cdb_waked_reg2 == RMT[rs1_1]))); @@ -31,73 +32,105 @@ module RMT #( assign wake_rs2_2 = (((cdb_waked_reg1 != '0) && cdb_wakeup1 && (cdb_waked_reg1 == RMT[rs2_2])) || ((cdb_waked_reg2 != '0) && cdb_wakeup2 && (cdb_waked_reg2 == RMT[rs2_2]))); - always_ff @(posedge CLK) begin + always_comb begin + // Calculate the state after Instruction 1 + next_RMT_inst1 = RMT; + + if (restore_rmt) begin + next_RMT_inst1 = bs_rmt_snap; + end + else if (reg_write1 && (rd1 != 5'b0) && !stall_frontend && id_valid1) begin + next_RMT_inst1[rd1] = fl_freed_reg1; + end + + // Calculate the NORMAL state (Inst 1 + Inst 2) + // THIS MUST HAPPEN UNCONDITIONALLY! (Removed the 'else begin' wrapper) + next_RMT = next_RMT_inst1; + + if (!restore_rmt && reg_write2 && (rd2 != 5'b0) && !stall_frontend && id_valid2) begin + next_RMT[rd2] = fl_freed_reg2; + end + // Conditional Snapshot MUST HAPPEN UNCONDITIONALLY! + if ((id_branch1 || id_jump1) && id_valid1) begin + rmt_snap = next_RMT_inst1; + end else begin + rmt_snap = next_RMT; + end + end + + always_ff @(posedge CLK) begin if (reset) begin for (int i = 0; i < 32; i++) begin RMT[i] <= i; end + old_prd1 <= '0; + old_prd2 <= '0; busy_table <= 0; - prd1 <= '0; prd2 <= '0; - prs1_1 <= '0; prs2_1 <= '0; prs1_2 <= '0; prs2_2 <= '0; - prs1_busy1 <= 0; prs2_busy1 <= 0; prs1_busy2 <= 0; prs2_busy2 <= 0; + prd1 <= '0; + prd2 <= '0; + prs1_1 <= '0; + prs2_1 <= '0; + prs1_2 <= '0; + prs2_2 <= '0; + prs1_busy1 <= 0; + prs2_busy1 <= 0; + prs1_busy2 <= 0; + prs2_busy2 <= 0; end - else begin - if (restore_rmt) begin - RMT <= bs_rmt_snap; - end - else begin - //updating Rename Map Table - if (reg_write1 && (rd1 != 5'b0)) begin - RMT[rd1] <= fl_freed_reg1; - busy_table[fl_freed_reg1] <= 1; - end - if (reg_write2 && (rd2 != 5'b0)) begin - RMT[rd2] <= fl_freed_reg2; - busy_table[fl_freed_reg2] <= 1; - end - end - //updating busy table from CDB + // 1. CDB Wakeups happen NO MATTER WHAT if (cdb_wakeup1 && (cdb_waked_reg1 != '0)) begin busy_table[cdb_waked_reg1] <= 0; end if (cdb_wakeup2 && (cdb_waked_reg2 != '0)) begin busy_table[cdb_waked_reg2] <= 0; end - - - //renaming instruction1 - - prd1 <= (rd1!= 5'b0)? fl_freed_reg1 : '0; + // 2. Map Table Update (Flushes bypass stalls) + if (restore_rmt || !stall_frontend) begin + RMT <= next_RMT; + end - prs1_1 <= RMT[rs1_1]; - prs1_busy1 <= (!wake_rs1_1 && busy_table[RMT[rs1_1]]); + // 3. Busy Table New Allocations + if (reg_write1 && (rd1 != 5'b0) && !stall_frontend && id_valid1 && !restore_rmt) begin + busy_table[fl_freed_reg1] <= 1; + end + if (reg_write2 && (rd2 != 5'b0) && !stall_frontend && id_valid2 && !restore_rmt) begin + busy_table[fl_freed_reg2] <= 1; + end + + // 4. Output Pipeline Registers (Only update if not stalled!) + if (!stall_frontend) begin + old_prd1 <= RMT[rd1]; + old_prd2 <= (reg_write1 && (rd1 == rd2) && (rd1 != 5'b0) && id_valid1) ? fl_freed_reg1 : RMT[rd2]; + + prd1 <= (rd1!= 5'b0)? fl_freed_reg1 : '0; + prd2 <= (rd2!= 5'b0)? fl_freed_reg2 : '0; - prs2_1 <= RMT[rs2_1]; - prs2_busy1 <= (!wake_rs2_1 && busy_table[RMT[rs2_1]]); + prs1_1 <= RMT[rs1_1]; + prs1_busy1 <= (!wake_rs1_1 && busy_table[RMT[rs1_1]]); - //renaming instruction2 - prd2 <= (rd2!= 5'b0)? fl_freed_reg2 : '0; + prs2_1 <= RMT[rs2_1]; + prs2_busy1 <= (!wake_rs2_1 && busy_table[RMT[rs2_1]]); - if (reg_write1 && (rd1 == rs1_2) && (rs1_2 != 5'b0)) begin - prs1_2 <= fl_freed_reg1; - prs1_busy2 <= 1; - end - else begin - prs1_2 <= RMT[rs1_2]; - prs1_busy2 <= (!wake_rs1_2 && busy_table[RMT[rs1_2]]); - end + if (reg_write1 && (rd1 == rs1_2) && (rs1_2 != 5'b0) && id_valid1) begin + prs1_2 <= fl_freed_reg1; + prs1_busy2 <= 1; + end else begin + prs1_2 <= RMT[rs1_2]; + prs1_busy2 <= (!wake_rs1_2 && busy_table[RMT[rs1_2]]); + end - if (reg_write1 && (rd1 == rs2_2) && (rs2_2 != 5'b0)) begin - prs2_2 <= fl_freed_reg1; - prs2_busy2 <= 1; - end - else begin - prs2_2 <= RMT[rs2_2]; - prs2_busy2 <= (!wake_rs2_2 && busy_table[RMT[rs2_2]]); + if (reg_write1 && (rd1 == rs2_2) && (rs2_2 != 5'b0) && id_valid1) begin + prs2_2 <= fl_freed_reg1; + prs2_busy2 <= 1; + end else begin + prs2_2 <= RMT[rs2_2]; + prs2_busy2 <= (!wake_rs2_2 && busy_table[RMT[rs2_2]]); + end end + end end diff --git a/Design/RN_Stage.sv b/Design/RN_Stage.sv index 922595a..02279a1 100644 --- a/Design/RN_Stage.sv +++ b/Design/RN_Stage.sv @@ -30,7 +30,8 @@ module RN_Stage #( input logic id_regsrc1_2, id_regsrc2_2, id_upperimm1, id_upperimm2, id_regwrite1, id_regwrite2, input logic id_memwrite2, id_memtoreg1, id_memtoreg2, id_retaddr1, id_retaddr2, id_isimm1, id_isimm2, output logic stall_frontend, - output logic [PRF_ADDRESS-1:0] rn_prd1, rn_prs1_1, rn_prs2_1, rn_prd2, rn_prs1_2, rn_prs2_2, + output logic [PRF_ADDRESS-1:0] rn_prd1, rn_prs1_1, rn_prs2_1, rn_old_prd1, + output logic [PRF_ADDRESS-1:0] rn_prd2, rn_prs1_2, rn_prs2_2, rn_old_prd2, output logic rn_prs1_busy1, rn_prs2_busy1, rn_prs1_busy2, rn_prs2_busy2, output logic [BTAG_SIZE-1:0] rn_branch_tag, output logic [MAX_BRANCHES-1:0] rn_branch_mask, @@ -54,7 +55,7 @@ module RN_Stage #( logic [FL_PTR_WIDTH-1:0] fl_head_ptr, bs_head_ptr_snap; logic [PRF_ADDRESS-1:0] routed_freed_reg1, routed_freed_reg2; - logic pop1, pop2; + logic pop1, pop2, bs_full, fl_empty; assign pop1 = id_valid1 && id_regwrite1 && (id_rd_1 != 5'b0); assign pop2 = id_valid2 && id_regwrite2 && (id_rd_2 != 5'b0); @@ -107,11 +108,15 @@ module RN_Stage #( .CLK (CLK), .reset (reset), .restore_rmt (flush), - - .reg_write1 (id_regwrite1), - .reg_write2 (id_regwrite2), + .stall_frontend (stall_frontend), + .reg_write1 (id_regwrite1 && id_valid1), + .reg_write2 (id_regwrite2 && id_valid2), + .id_valid1 (id_valid1), + .id_valid2 (id_valid2), .cdb_wakeup1 (cdb_wakeup1), .cdb_wakeup2 (cdb_wakeup2), + .id_branch1 (id_branch1), + .id_jump1 (id_jump1), .rd1 (id_rd_1), .rs1_1 (id_rs1_1), @@ -129,12 +134,14 @@ module RN_Stage #( .bs_rmt_snap (bs_rmt_snap), .prd1 (rn_prd1), + .old_prd1 (rn_old_prd1), .prs1_1 (rn_prs1_1), .prs2_1 (rn_prs2_1), .prs1_busy1 (rn_prs1_busy1), .prs2_busy1 (rn_prs2_busy1), .prd2 (rn_prd2), + .old_prd2 (rn_old_prd2), .prs1_2 (rn_prs1_2), .prs2_2 (rn_prs2_2), .prs1_busy2 (rn_prs1_busy2), @@ -150,8 +157,11 @@ module RN_Stage #( .stall_frontend (stall_frontend), .pop1 (pop1), .pop2 (pop2), - .bs_head_ptr_snap (bs_head_ptr_snap), - + .id_branch1 (id_branch1), + .id_jump1 (id_jump1), + .id_valid1 (id_valid1), + .bs_head_ptr_snap (bs_head_ptr_snap), + .push1 (comm_free_push1), .push2 (comm_free_push2), .comm_free_reg1 (comm_free_reg1), @@ -160,7 +170,7 @@ module RN_Stage #( .fl_head_ptr (fl_head_ptr), .fl_freed_reg1 (fl_freed_reg1), .fl_freed_reg2 (fl_freed_reg2), - .fl_empty (fl_empty) //signal for frontend + .fl_empty (fl_empty) //signal for frontend ); @@ -168,12 +178,18 @@ module RN_Stage #( .CLK (CLK), .reset (reset), .id_take_snap (id_take_snap && !stall_frontend && !flush), //if branch instructions then take snapshot - + .flush (flush), .rmt_snap (rmt_snap), - .freelist_head_snap (fl_head_ptr), + .freelist_head_snap (fl_head_ptr), + .id_branch1 (id_branch1), + .id_jump1 (id_jump1), + .id_valid1 (id_valid1), //from ex stage to reset branch mask register when branch gets resolved .ex_branch_resolved (ex_branch_resolved), .ex_btag (ex_btag), + //to store the updated mapping of map table + .pop1 (pop1 && !stall_frontend), + .pop2 (pop2 && !stall_frontend), //output .bs_branch_tag (rn_branch_tag), From 644d0a9d2aa0c5c35ca53e3546b720629f8094d4 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Thu, 23 Apr 2026 23:11:07 +0500 Subject: [PATCH 03/11] resolved some bit mismatching and changed rmt to packed array --- Design/BS.sv | 12 ++++++------ Design/FL.sv | 12 ++++++------ Design/RMT.sv | 13 +++++++------ Design/RN_Stage.sv | 3 +-- 4 files changed, 20 insertions(+), 20 deletions(-) diff --git a/Design/BS.sv b/Design/BS.sv index c86c586..bc263fc 100644 --- a/Design/BS.sv +++ b/Design/BS.sv @@ -10,17 +10,17 @@ module BS #( input logic CLK, reset, flush, id_take_snap, ex_branch_resolved, pop1, pop2, input logic id_branch1, id_jump1, id_valid1, input logic [BTAG_SIZE-1:0] ex_btag, - input logic [PRF_ADDRESS-1:0] rmt_snap [0:31], + input logic [31:0][PRF_ADDRESS-1:0] rmt_snap, input logic [FL_PTR_WIDTH-1:0] freelist_head_snap, output logic bs_full, - output logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31], + output logic [31:0][PRF_ADDRESS-1:0] bs_rmt_snap, output logic [FL_PTR_WIDTH-1:0] bs_freelist_head_snap, output logic [BTAG_SIZE-1:0] bs_branch_tag, output logic [MAX_BRANCHES-1:0] bs_branch_mask ); - typedef struct { - logic [PRF_ADDRESS-1:0] rmt_snapshot [0:31]; + typedef struct packed{ + logic [31:0][PRF_ADDRESS-1:0] rmt_snapshot; logic [FL_PTR_WIDTH-1:0] freelist_head_snapshot; logic [MAX_BRANCHES-1:0] bmr_snapshot; } bs_organization; @@ -34,7 +34,7 @@ module BS #( current_btag = '0; for (int i = 0; i < MAX_BRANCHES; i++) begin if (!BMR[i]) begin - current_btag = i; + current_btag = BTAG_SIZE'(i); break; end end @@ -62,7 +62,7 @@ module BS #( BMR[ex_btag] <= 1'b0; //all the branches that took snapshot of BMR should also get 0 because branch is resolved for (int i = 0; i < MAX_BRANCHES; i++) begin - if (!(id_take_snap && (i == current_btag))) begin + if (!(id_take_snap && (BTAG_SIZE'(i) == current_btag))) begin BS[i].bmr_snapshot[ex_btag] <= 1'b0; end end diff --git a/Design/FL.sv b/Design/FL.sv index 81a11d6..63c55a8 100644 --- a/Design/FL.sv +++ b/Design/FL.sv @@ -18,11 +18,11 @@ module FL #( logic [FL_PTR_WIDTH-1:0] head, next_head, tail; logic valid_pop1, valid_pop2; logic [FL_PTR_WIDTH-1:0] registers_required; - + assign registers_required = {{(FL_PTR_WIDTH-1){1'b0}}, pop1} + {{(FL_PTR_WIDTH-1){1'b0}}, pop2}; assign fl_empty = (tail - head) < registers_required; assign fl_freed_reg1 = FL[head[FL_INDEX_WIDTH-1:0]]; - assign fl_freed_reg2 = FL[FL_INDEX_WIDTH'(head[FL_INDEX_WIDTH-1:0]+1)]; + assign fl_freed_reg2 = FL[FL_INDEX_WIDTH'(head[FL_INDEX_WIDTH-1:0] + FL_INDEX_WIDTH'(1))]; assign valid_pop1 = pop1 && !stall_frontend && !flush; @@ -30,10 +30,10 @@ module FL #( always_comb begin //during flush, we fetch instruction from correct path, so we dont pop register in this cycle - next_head = (flush) ? bs_head_ptr_snap : (head + valid_pop1 + valid_pop2); + next_head = (flush) ? bs_head_ptr_snap : (head + FL_PTR_WIDTH'(valid_pop1) + FL_PTR_WIDTH'(valid_pop2)); if ((id_branch1 || id_jump1) && id_valid1) begin - fl_head_ptr = head + valid_pop1; + fl_head_ptr = head + FL_PTR_WIDTH'(valid_pop1); end else begin fl_head_ptr = next_head; // Same as head + valid_pop1 + valid_pop2 end @@ -43,7 +43,7 @@ module FL #( always_ff @(posedge CLK) begin if (reset) begin for (int i = 32; i < NUM_PHY_REG; i++) begin - FL[i-32] <= i; + FL[i-32] <= PRF_ADDRESS'(i); end head <= '0; // ALL ZEROS tail <= {1'b1, {FL_INDEX_WIDTH{1'b0}}}; // IS FULL (BACK TO HEAD) @@ -53,7 +53,7 @@ module FL #( //from the commit stage we push registers back to free list if (push1 && push2) begin FL[tail[FL_INDEX_WIDTH-1:0]] <= comm_free_reg1; - FL[FL_INDEX_WIDTH'(tail[FL_INDEX_WIDTH-1:0]+1)] <= comm_free_reg2; + FL[FL_INDEX_WIDTH'(tail[FL_INDEX_WIDTH-1:0] + FL_INDEX_WIDTH'(1))] <= comm_free_reg2; tail <= tail + 2; end else if (push1 || push2) begin diff --git a/Design/RMT.sv b/Design/RMT.sv index 48ec6c8..565c0fa 100644 --- a/Design/RMT.sv +++ b/Design/RMT.sv @@ -7,15 +7,16 @@ module RMT #( input logic [4:0] rd1, rs1_1, rs2_1, input logic [4:0] rd2, rs1_2, rs2_2, input logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, cdb_waked_reg1, cdb_waked_reg2, - input logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31], + input logic [31:0][PRF_ADDRESS-1:0] bs_rmt_snap, output logic prs1_busy1, prs2_busy1, prs1_busy2, prs2_busy2, output logic [PRF_ADDRESS-1:0] prd1, prs1_1, prs2_1, old_prd1, output logic [PRF_ADDRESS-1:0] prd2, prs1_2, prs2_2, old_prd2, - output logic [PRF_ADDRESS-1:0] rmt_snap [0:31] + output logic [31:0][PRF_ADDRESS-1:0] rmt_snap ); - logic [PRF_ADDRESS-1:0] RMT [0:31]; - logic [PRF_ADDRESS-1:0] next_RMT [0:31]; - logic [PRF_ADDRESS-1:0] next_RMT_inst1 [0:31]; + + logic [31:0][PRF_ADDRESS-1:0] RMT; + logic [31:0][PRF_ADDRESS-1:0] next_RMT; + logic [31:0][PRF_ADDRESS-1:0] next_RMT_inst1; logic [NUM_PHY_REG-1:0] busy_table; logic wake_rs1_1, wake_rs1_2, wake_rs2_1, wake_rs2_2; @@ -62,7 +63,7 @@ module RMT #( always_ff @(posedge CLK) begin if (reset) begin for (int i = 0; i < 32; i++) begin - RMT[i] <= i; + RMT[i] <= PRF_ADDRESS'(i); end old_prd1 <= '0; old_prd2 <= '0; diff --git a/Design/RN_Stage.sv b/Design/RN_Stage.sv index 02279a1..67c9883 100644 --- a/Design/RN_Stage.sv +++ b/Design/RN_Stage.sv @@ -50,8 +50,7 @@ module RN_Stage #( output logic rn_upperimm2, rn_regwrite2, rn_memwrite2, rn_memtoreg2 ); logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2; - logic [PRF_ADDRESS-1:0] bs_rmt_snap [0:31]; - logic [PRF_ADDRESS-1:0] rmt_snap [0:31]; + logic [31:0][PRF_ADDRESS-1:0] rmt_snap, bs_rmt_snap; logic [FL_PTR_WIDTH-1:0] fl_head_ptr, bs_head_ptr_snap; logic [PRF_ADDRESS-1:0] routed_freed_reg1, routed_freed_reg2; From e3084801159f6756c318f92ec92f2bb4c900cfa2 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Thu, 30 Apr 2026 01:26:45 +0500 Subject: [PATCH 04/11] enhanced btb and removed the dual-issue bug --- Design/BTB.sv | 101 ++++++++++++++++++++++++-------------------------- 1 file changed, 48 insertions(+), 53 deletions(-) diff --git a/Design/BTB.sv b/Design/BTB.sv index 691bfbb..5dbe6ba 100644 --- a/Design/BTB.sv +++ b/Design/BTB.sv @@ -1,66 +1,61 @@ -//direct-mapped BTB +//direct-mapped cache BTB module BTB #( - parameter BTB_ADDRESS = 6, + parameter BTB_ROWS = 64, parameter XLEN = 32, - parameter TAG_SIZE = XLEN - BTB_ADDRESS - 2 + parameter BTB_ADDRESS = $clog2(BTB_ROWS), + parameter TAG_SIZE = XLEN - BTB_ADDRESS - 3 ) ( - input logic CLK, reset, update_btb, ex_is_ret, ex_is_branch, - input logic [XLEN-1:0] pc1, pc2, ex_pc, - input logic [XLEN-1:0] actual_target_address, - output logic btb_hit1, btb_hit2, is_ret1, is_ret2, is_branch1, is_branch2, - output logic [XLEN-1:0] pred_target1, pred_target2 + input logic CLK, reset, if_is_jal1, if_is_jal2, ex_is_taken_branch, ex_is_jalr, ex_is_not_ret, + input logic [XLEN-1:0] pd_pc, if_pc, ex_pc, + input logic [XLEN-3:0] ex_target_address, if_target_address1, if_target_address2, + output logic btb_hit, + output logic [XLEN-1:0] pred_target_address ); - typedef struct packed { - logic [TAG_SIZE-1:0] tag; - logic [XLEN-1:0] target_address; - logic valid; - logic is_ret; - logic is_branch; - } btb_organization; - (* ram_style = "block" *) btb_organization BTB [0:(1< Date: Fri, 26 Jun 2026 17:08:38 +0500 Subject: [PATCH 05/11] corrected prediction stage --- Design/BTB.sv | 48 +- Design/GHR.sv | 11 +- Design/IF_Stage.sv | 13 + Design/PC.sv | 42 +- Design/PD_Stage.sv | 176 ++- Design/PHT.sv | 11 +- Design/PreDecode.sv | 40 + Design/RAS.sv | 19 +- Design/main_datapath.sv | 297 ++--- Design/tb_main_datapath.sv | 283 ++--- Design/waveform.vcd | 2251 ++++++++++++++++++++++++++++++++++++ 11 files changed, 2697 insertions(+), 494 deletions(-) create mode 100644 Design/PreDecode.sv create mode 100644 Design/waveform.vcd diff --git a/Design/BTB.sv b/Design/BTB.sv index 5dbe6ba..2fe7c15 100644 --- a/Design/BTB.sv +++ b/Design/BTB.sv @@ -7,54 +7,66 @@ module BTB #( ) ( input logic CLK, reset, if_is_jal1, if_is_jal2, ex_is_taken_branch, ex_is_jalr, ex_is_not_ret, input logic [XLEN-1:0] pd_pc, if_pc, ex_pc, - input logic [XLEN-3:0] ex_target_address, if_target_address1, if_target_address2, - output logic btb_hit, + input logic [XLEN-3:0] ex_target_address, if_target_address, + + + output logic btb_hit, squash_instruction, output logic [XLEN-1:0] pred_target_address ); logic [TAG_SIZE-1:0] pd_tag, if_tag, ex_tag; - logic [XLEN-3:0] if_target_address; logic [BTB_ADDRESS-1:0] btb_read_address, ex_btb_write_address, if_btb_write_address; typedef struct packed { logic [TAG_SIZE-1:0] bundled_tag; logic [XLEN-3:0] target_address; //for bundled pc and not storing the 2 bits cuz they are always zero - logic valid; + logic offset; // which among the bundle is branch so that ahead instruction is squashed + logic valid; } btb_organization; btb_organization BTB [0:BTB_ROWS-1]; + always_comb begin pd_tag = pd_pc[XLEN-1: BTB_ADDRESS+3]; if_tag = if_pc[XLEN-1: BTB_ADDRESS+3]; ex_tag = ex_pc[XLEN-1: BTB_ADDRESS+3]; - btb_read_address = pd_pc[BTB_ADDRESS+2:3]; if_btb_write_address = if_pc[BTB_ADDRESS+2:3]; ex_btb_write_address = ex_pc[BTB_ADDRESS+2:3]; - - if_target_address = (if_is_jal1)? if_target_address1 : if_target_address2; end always_ff @(posedge CLK) begin - //writing btb from ex stage - if(ex_is_taken_branch || ex_is_jalr && ex_is_not_ret) begin - BTB[ex_btb_write_address].bundled_tag <= ex_tag; - BTB[ex_btb_write_address].target_address <= ex_target_address; - BTB[ex_btb_write_address].valid <= 1; - end - //writing btb from fetch stage - if (if_is_jal1 || if_is_jal2) begin - BTB[if_btb_write_address].bundled_tag <= if_tag; - BTB[if_btb_write_address].target_address <= if_target_address; - BTB[if_btb_write_address].valid <= 1; + if (reset) begin + for (int i = 0; i < BTB_ROWS; i++) begin + BTB[i].valid <= 0; + end end + + else begin + //writing btb from ex stage + if(ex_is_taken_branch || ex_is_jalr && ex_is_not_ret) begin + BTB[ex_btb_write_address].bundled_tag <= ex_tag; + BTB[ex_btb_write_address].target_address <= ex_target_address; + BTB[ex_btb_write_address].valid <= 1; + BTB[ex_btb_write_address].offset <= ex_pc[29]; + end + //writing btb from fetch stage + if (if_is_jal1 || if_is_jal2) begin + BTB[if_btb_write_address].bundled_tag <= if_tag; + BTB[if_btb_write_address].target_address <= if_target_address; + BTB[if_btb_write_address].valid <= 1; + BTB[ex_btb_write_address].offset <= if_pc[29]; + end + end // read btb if (BTB[btb_read_address].valid && BTB[btb_read_address].bundled_tag == pd_tag) begin btb_hit <= 1; pred_target_address <= {BTB[btb_read_address].target_address, 2'b00}; + squash_instruction <= ~BTB[btb_read_address].offset; //if (offset = 0): squash; else: dont squash; end else begin btb_hit <= 0; + squash_instruction <= 0; end end diff --git a/Design/GHR.sv b/Design/GHR.sv index 06539ad..402ca15 100644 --- a/Design/GHR.sv +++ b/Design/GHR.sv @@ -1,23 +1,22 @@ module GHR #( parameter GHR_SIZE = 9 )( - input logic CLK, reset, stall_frontend, restore_ghr, actual_taken, pred_taken1, - input logic pred_taken2, pred_branch1, pred_branch2, + input logic CLK, reset, stall_frontend, restore_ghr, ex_actual_taken, ex_is_branch, input logic [GHR_SIZE-1:0] ghr_snap, output logic [GHR_SIZE-1:0] ghr_out, prev_ghr ); logic pred_taken; - assign pred_taken = (pred_branch1)? pred_taken1 : pred_taken2; assign prev_ghr = ghr_out; + always_ff @(posedge CLK) begin if (reset) begin ghr_out <= '0; end else if (restore_ghr) begin - ghr_out <= {ghr_snap[GHR_SIZE-2:0], actual_taken}; + ghr_out <= {ghr_snap[GHR_SIZE-2:0], ex_actual_taken}; end - else if (!stall_frontend && (pred_branch1 || pred_branch2)) begin - ghr_out <= {ghr_out[GHR_SIZE-2:0], pred_taken}; + else if (!stall_frontend && ex_is_branch) begin + ghr_out <= {ghr_out[GHR_SIZE-2:0], ex_actual_taken}; end end endmodule \ No newline at end of file diff --git a/Design/IF_Stage.sv b/Design/IF_Stage.sv index 7f91837..f86b8ef 100644 --- a/Design/IF_Stage.sv +++ b/Design/IF_Stage.sv @@ -13,6 +13,7 @@ module IF_Stage #( input logic [GHR_SIZE-1:0] pd_prev_ghr, output logic if_pred_taken1, if_pred_taken2, if_btb_hit1, if_btb_hit2, if_valid1, if_valid2, + output logic [1:0] if_predecode_instr1, if_predecode_instr2, output logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target1, if_pred_target2, output logic [XLEN-3:0] if_pc, output logic [PHT_ADDRESS-1:0] if_pht_index1, if_pht_index2, @@ -55,4 +56,16 @@ module IF_Stage #( .instr_1 (if_instr1), .instr_2 (if_instr2) ); + + PreDecode predecode_instantiation( + //input + .opcode1 (if_instr1[6:0]), + .opcode2 (if_instr2[6:0]), + .rd1 (if_instr1[11:7]), + .rd2 (if_instr2[11:7]), + //output + .predecode_instr1 (if_predecode_instr1), + .predecode_instr2 (if_predecode_instr2) + ); + endmodule \ No newline at end of file diff --git a/Design/PC.sv b/Design/PC.sv index fea8e0e..fe2f1c3 100644 --- a/Design/PC.sv +++ b/Design/PC.sv @@ -2,45 +2,27 @@ module PC #( parameter XLEN = 32 )( - input logic CLK, reset, stall_frontend, mispredict, btb_hit1, btb_hit2, is_ret1, is_ret2, is_branch1, is_branch2, pred_taken1, pred_taken2, - input logic [XLEN-1:0] pred_target1, pred_target2, ret_addr1, ret_addr2, actual_target_address, - output logic [XLEN-1:0] pc, write_pc_data, next_pc, final_pred_target1, final_pred_target2 + input logic CLK, reset, mispredict, stall_frontend, is_return_instr, btb_hit, + input logic [XLEN-1:0] ras_target_address, btb_target_address, ex_actual_target_address, + output logic [XLEN-1:0] next_pc ); - logic is_branch_or_jump1, is_branch_or_jump2; - assign is_branch_or_jump1 = is_branch1 && pred_taken1 || !is_branch1; //!is_branch = jal, jalr - assign is_branch_or_jump2 = is_branch2 && pred_taken2 || !is_branch2; - assign final_pred_target1 = (is_ret1)? ret_addr1: pred_target1; - assign final_pred_target2 = (is_ret2)? ret_addr2: pred_target2; - - always_comb begin + always_ff @(posedge CLK) begin if (reset) begin - write_pc_data = 0; + next_pc <= 0; end else if (mispredict) begin - write_pc_data = actual_target_address; //from ex stage - end - else if (btb_hit1 && (is_ret1 || is_branch_or_jump1)) begin - write_pc_data = final_pred_target1; //from btb or ras + next_pc <= ex_actual_target_address; //from EX stage(actual target address) end - else if (btb_hit2 && (is_ret2 || is_branch_or_jump2)) begin - write_pc_data = final_pred_target2; //from btb or ras + else if (is_return_instr) begin + next_pc <= ras_target_address; //from RAS end - else begin - write_pc_data = pc; //from pc register - end - - next_pc = write_pc_data + 8; - end - always_ff @(posedge CLK) begin - if (reset) begin - pc <= 0; - end - else if (mispredict) begin - pc <= write_pc_data; + else if (btb_hit) begin + next_pc <= btb_target_address; //from BTB end else if (!stall_frontend) begin - pc <= next_pc; + next_pc <= next_pc + 8; end + end endmodule diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 5536c4d..7e97716 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -4,16 +4,17 @@ module PD_Stage #( parameter XLEN = 32, parameter RAS_ADDRESS = 3 )( - input logic CLK, reset, stall_frontend, actual_taken, restore_ghr, restore_ras, update_pht, - input logic update_btb, update_ras, ex_is_ret, ex_is_branch, mispredict, //mispredict = flush(from ex) - input logic [XLEN-1:0] actual_target_address, actual_return_address, ex_pc, + input logic CLK, reset, stall_frontend, ex_actual_taken, restore_ghr, restore_ras, update_pht, + input logic ex_is_jalr, ex_is_ret, ex_is_branch, mispredict, //mispredict = flush(from ex) + input logic [1:0] if_predecode_instr1, if_predecode_instr2, + input logic [XLEN-1:0] ex_actual_target_address, if_target_address, if_pc, ex_pc, input logic [GHR_SIZE-1:0] ghr_snap, input logic [PHT_ADDRESS-1:0] rb_pht_index, input logic [RAS_ADDRESS-1:0] rb_sp_snap, input logic [2*XLEN-1:0] rb_ras_snap, - output logic pd_pred_taken1, pd_pred_taken2, pd_btb_hit1, pd_btb_hit2, pd_valid1, pd_valid2, - output logic [XLEN-1:0] pd_pc, pd_pred_target1, pd_pred_target2, - output logic [PHT_ADDRESS-1:0] pd_pht_index1, pd_pht_index2, + output logic pd_pred_taken, pd_btb_hit, pd_valid1, pd_valid2, + output logic [XLEN-1:0] pd_pc, pd_pred_target, + output logic [PHT_ADDRESS-1:0] pd_pht_index, output logic [RAS_ADDRESS-1:0] pd_sp_snap, output logic [2*XLEN-1:0] pd_ras_snap, output logic [GHR_SIZE-1:0] pd_prev_ghr @@ -21,138 +22,119 @@ module PD_Stage #( logic [GHR_SIZE-1:0] ghr_out, prev_ghr; - logic [PHT_ADDRESS-1:0] pht_index1, pht_index2; - logic [XLEN-1:0] final_pred_target1, final_pred_target2, pc; - logic pred_taken1, pred_taken2, btb_hit1, btb_hit2; - logic is_branch1, is_branch2, is_ret1, is_ret2; - logic [XLEN-1:0] pred_target1, pred_target2, pred_return_address; + logic [PHT_ADDRESS-1:0] pht_index; + logic pred_taken, btb_hit, is_return_instr, squash_instruction; + logic [XLEN-1:0] pred_return_address, pred_target_address; logic [RAS_ADDRESS-1:0] sp_snap; logic [2*XLEN-1:0] ras_snap; - logic [XLEN-1:0] write_pc_data, next_pc, pc1, pc2; + logic [XLEN-1:0] next_pc; - assign pc1 = pd_pc; - assign pc2 = pd_pc + 4; - assign pht_index1 = ghr_out ^ pc1[PHT_ADDRESS+1:2]; - assign pht_index2 = ghr_out ^ pc2[PHT_ADDRESS+1:2]; - assign pd_pred_taken1 = pred_taken1; - assign pd_pred_taken2 = pred_taken2; - assign pd_pc = (btb_hit1 || btb_hit2 || mispredict)? write_pc_data: pc; - assign pd_btb_hit1 = btb_hit1; - assign pd_btb_hit2 = btb_hit2; + assign pht_index = ghr_out ^ next_pc[PHT_ADDRESS+1:2]; + assign pd_pred_taken = pred_taken; + assign pd_pred_target = (is_return_instr)? pred_return_address : pred_target_address; + assign pd_pc = next_pc; + assign pd_btb_hit = btb_hit; assign pd_sp_snap = sp_snap; assign pd_ras_snap = ras_snap; - always_ff @( posedge CLK ) begin + always_ff @(posedge CLK) begin if (reset) begin pd_valid1 <= 0; pd_valid2 <= 0; end else if (!stall_frontend) begin pd_valid1 <= !mispredict; - pd_valid2 <= !mispredict && (!btb_hit1 || !pred_taken1); - pd_pht_index1 <= pht_index1; - pd_pht_index2 <= pht_index2; - pd_pred_target1 <= final_pred_target1; - pd_pred_target2 <= final_pred_target2; + pd_valid2 <= !mispredict && squash_instruction; + pd_pht_index <= pht_index; pd_prev_ghr <= prev_ghr; end end GHR ghr_instantiation( //inputs - .CLK (CLK), - .reset (reset), - .stall_frontend (stall_frontend), - .restore_ghr (restore_ghr), - .actual_taken (actual_taken), - .pred_taken1 (pred_taken1), - .pred_taken2 (pred_taken2), - .pred_branch1 (is_branch1), - .pred_branch2 (is_branch2), - .ghr_snap (ghr_snap), + .CLK (CLK), + .reset (reset), + .stall_frontend (stall_frontend), + .ex_is_branch (ex_is_branch), + .restore_ghr (restore_ghr), + .ex_actual_taken (ex_actual_taken), + .ghr_snap (ghr_snap), //outputs - .ghr_out (ghr_out), - .prev_ghr (prev_ghr) + .ghr_out (ghr_out), + .prev_ghr (prev_ghr) ); PC pc_instantiation ( //inputs - .CLK (CLK), - .reset (reset), - .mispredict (mispredict), - .stall_frontend (stall_frontend), - .btb_hit1 (btb_hit1), - .btb_hit2 (btb_hit2), - .is_ret1 (is_ret1), - .is_ret2 (is_ret2), - .is_branch1 (is_branch1), - .is_branch2 (is_branch2), - .pred_taken1 (pred_taken1), - .pred_taken2 (pred_taken2), - .pred_target1 (pred_target1), - .pred_target2 (pred_target2), - .ret_addr1 (pred_return_address), - .ret_addr2 (pred_return_address), - .actual_target_address (actual_target_address), + .CLK (CLK), + .reset (reset), + .mispredict (mispredict), + .stall_frontend (stall_frontend), + .ras_target_address (pred_return_address), + .btb_target_address (pred_target_address), + .ex_actual_target_address (ex_actual_target_address), + .is_return_instr (is_return_instr), + .btb_hit (btb_hit), //outputs - .pc (pc), - .write_pc_data (write_pc_data), - .next_pc (next_pc), - .final_pred_target1 (final_pred_target1), - .final_pred_target2 (final_pred_target2) + .next_pc (next_pc) + ); PHT pht_instantiation ( //inputs - .CLK (CLK), - .reset (reset), - .actual_taken (actual_taken), - .update_pht (update_pht), - .pht_index1 (pht_index1), - .pht_index2 (pht_index2), - .rb_pht_index (rb_pht_index), + .CLK (CLK), + .reset (reset), + .ex_actual_taken (ex_actual_taken), + .update_pht (update_pht), + .pht_index (pht_index), + .rb_pht_index (rb_pht_index), //outputs - .pred_taken1 (pred_taken1), - .pred_taken2 (pred_taken2) + .pred_taken (pred_taken) ); BTB btb_instantiation ( //inputs .CLK (CLK), .reset (reset), - .update_btb (update_btb), - .ex_is_ret (ex_is_ret), - .ex_is_branch (ex_is_branch), - .pc1 (pc1), - .pc2 (pc2), + .if_is_jal1 (if_predecode_instr1 == 2'b11), + .if_is_jal2 (if_predecode_instr2 == 2'b11), + + .ex_is_not_ret (~ex_is_ret), + .ex_is_taken_branch (ex_actual_taken), + .ex_is_jalr (ex_is_jalr), + + .pd_pc (pd_pc), + .if_pc (if_pc), .ex_pc (ex_pc), - .actual_target_address (actual_target_address), + + .ex_target_address (ex_actual_target_address), + .if_target_address (if_target_address), + //outputs - .btb_hit1 (btb_hit1), - .btb_hit2 (btb_hit2), - .is_ret1 (is_ret1), - .is_ret2 (is_ret2), - .is_branch1 (is_branch1), - .is_branch2 (is_branch2), - .pred_target1 (pred_target1), - .pred_target2 (pred_target2) + .btb_hit (btb_hit), + .squash_instruction (squash_instruction), + .pred_target_address (pred_target_address) ); RAS ras_instantiation ( //inputs - .CLK (CLK), - .reset (reset), - .stall_frontend (stall_frontend), - .update_ras (update_ras), - .restore_ras (restore_ras), - .rb_sp_snap (rb_sp_snap), - .rb_ras_snap (rb_ras_snap), - .btb_is_ret1 (is_ret1), - .btb_is_ret2 (is_ret2), - .actual_return_address (actual_return_address), + .CLK (CLK), + .reset (reset), + + .stall_frontend (stall_frontend), + .restore_ras (restore_ras), + + .rb_sp_snap (rb_sp_snap), + .rb_ras_snap (rb_ras_snap), + + .if_predecode_instr1 (if_predecode_instr1), + .if_predecode_instr2 (if_predecode_instr2), + + .if_actual_return_address (if_target_address), //outputs - .pred_return_address (pred_return_address), - .sp_snap (sp_snap), - .ras_snap (ras_snap) + .pred_return_address (pred_return_address), + .is_return_instr (is_return_instr), + .sp_snap (sp_snap), + .ras_snap (ras_snap) ); endmodule \ No newline at end of file diff --git a/Design/PHT.sv b/Design/PHT.sv index a67ad19..3b2f278 100644 --- a/Design/PHT.sv +++ b/Design/PHT.sv @@ -2,9 +2,9 @@ module PHT #( parameter PHT_ADDRESS = 9, parameter COUNTER_SIZE = 2 )( - input logic CLK, reset, actual_taken, update_pht, - input logic [PHT_ADDRESS-1:0] pht_index1, pht_index2, rb_pht_index, - output logic pred_taken1, pred_taken2 + input logic CLK, reset, ex_actual_taken, update_pht, + input logic [PHT_ADDRESS-1:0] pht_index, rb_pht_index, + output logic pred_taken ); (* ram_style = "distributed" *) logic [COUNTER_SIZE-1:0] PHT [0:(1< IF_Stage + + // PD/IF Signals... (Omitted declarations for brevity, assuming they match your previous code) logic pd_valid1, pd_valid2; logic [XLEN-1:0] pd_pc, pd_pred_target1, pd_pred_target2; logic pd_pred_taken1, pd_pred_taken2, pd_btb_hit1, pd_btb_hit2; @@ -95,7 +105,6 @@ module main_datapath #( logic [2*XLEN-1:0] pd_ras_snap; logic [GHR_SIZE-1:0] pd_prev_ghr; - // Wires: IF_Stage -> ID_Stage logic if_valid1, if_valid2; logic [XLEN-3:0] if_pc; logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target1, if_pred_target2; @@ -105,75 +114,72 @@ module main_datapath #( logic [2*XLEN-1:0] if_ras_snap; logic [GHR_SIZE-1:0] if_prev_ghr; - // ============================================================================ - // COMBINATIONAL LOGIC: SPECULATIVE RAS RETURN ADDRESS - // ============================================================================ - // Convert word-aligned PC back to full 32-bit address + // Decode -> Rename Wires + logic id_take_snap, id_valid1, id_valid2; + logic [XLEN-3:0] id_pc; + logic [BIQ_ADDRESS-1:0] id_biq_address; - // If the jump is in Slot 1, return to PC+4. If in Slot 2, return to PC+8. - // (We prioritize Slot 1. If Slot 1 jumps, Slot 2 is dead anyway). - assign spec_return_address = (id_jump1) ? ({id_pc,2'b00} + 32'd4) : ({id_pc,2'b00} + 32'd8); + logic [2:0] id_funct3_1, id_alu_op1; logic [6:0] id_funct7_1; logic [4:0] id_rs1_1, id_rs2_1, id_rd_1; + logic id_jump_reg1, id_jump1, id_branch1, id_regsrc1_1, id_regsrc2_1, id_immtype1, id_memwrite1, id_regwrite1, id_memtoreg1, id_retaddr1, id_isimm1, id_upperimm1; + logic [INIT_IMMEDIATE_SIZE-1:0] id_immout1; + logic [2:0] id_funct3_2, id_alu_op2; logic [6:0] id_funct7_2; logic [4:0] id_rs1_2, id_rs2_2, id_rd_2; + logic id_jump_reg2, id_jump2, id_branch2, id_regsrc1_2, id_regsrc2_2, id_immtype2, id_memwrite2, id_regwrite2, id_memtoreg2, id_retaddr2, id_isimm2, id_upperimm2; + logic [INIT_IMMEDIATE_SIZE-1:0] id_immout2; + + assign spec_return_address = (id_jump1) ? ({id_pc,2'b00} + 32'd4) : ({id_pc,2'b00} + 32'd8); // ============================================================================ // MODULE INSTANTIATIONS // ============================================================================ PD_Stage #( - .PHT_ADDRESS (PHT_ADDRESS), - .GHR_SIZE (GHR_SIZE), - .XLEN (XLEN), - .RAS_ADDRESS (RAS_ADDRESS) + .PHT_ADDRESS (9), + .GHR_SIZE (9), + .XLEN (32), + .RAS_ADDRESS (3) ) pd_stage_inst ( + // Inputs .CLK (CLK), .reset (reset), - .stall_frontend (stall_frontend), // Sourced from ID_Stage output - - .actual_taken (actual_taken), + .stall_frontend (stall_frontend), + .ex_actual_taken (actual_taken), + .restore_ghr (restore_ghr), + .restore_ras (restore_ras), .update_pht (update_pht), - .update_btb (update_btb), - .update_ras (update_ras), + .ex_is_jalr (/* connect to top-level ex_is_jalr */), .ex_is_ret (ex_is_ret), .ex_is_branch (ex_is_branch), - .ex_pc (ex_pc), - .actual_target_address (actual_target_address), - .actual_return_address (spec_return_address), // CONNECTED: Speculative ID logic! - .mispredict (mispredict), - .restore_ghr (restore_ghr), - .restore_ras (restore_ras), + .if_predecode_instr1 (/* connect to top-level if_predecode_instr1 */), + .if_predecode_instr2 (/* connect to top-level if_predecode_instr2 */), + .ex_actual_target_address(actual_target_address), + .if_target_address (/* connect to top-level if_target_address */), + .if_pc (pd_pc), // Assuming pd_pc maps to if_pc, adjust if needed + .ex_pc (ex_pc), .ghr_snap (ghr_snap), .rb_pht_index (rb_pht_index), .rb_sp_snap (rb_sp_snap), .rb_ras_snap (rb_ras_snap), + // Outputs + .pd_pred_taken (pd_pred_taken1), // Verify if this maps to channel 1 or combined + .pd_btb_hit (pd_btb_hit1), // Verify if this maps to channel 1 or combined .pd_valid1 (pd_valid1), .pd_valid2 (pd_valid2), .pd_pc (pd_pc), - .pd_pred_taken1 (pd_pred_taken1), - .pd_pred_taken2 (pd_pred_taken2), - .pd_btb_hit1 (pd_btb_hit1), - .pd_btb_hit2 (pd_btb_hit2), - .pd_pred_target1 (pd_pred_target1), - .pd_pred_target2 (pd_pred_target2), - .pd_pht_index1 (pd_pht_index1), - .pd_pht_index2 (pd_pht_index2), + .pd_pred_target (pd_pred_target1), // Verify if this maps to channel 1 or combined + .pd_pht_index (pd_pht_index1), // Verify if this maps to channel 1 or combined .pd_sp_snap (pd_sp_snap), .pd_ras_snap (pd_ras_snap), .pd_prev_ghr (pd_prev_ghr) ); - IF_Stage #( - .PHT_ADDRESS (PHT_ADDRESS), - .GHR_SIZE (GHR_SIZE), - .XLEN (XLEN), - .RAS_ADDRESS (RAS_ADDRESS) - ) if_stage_inst ( + IF_Stage #( /* ... Parameters ... */ ) if_stage_inst ( .CLK (CLK), .reset (reset), .flush (flush), - .stall_frontend (stall_frontend), // Sourced from ID_Stage output - + .stall_frontend (stall_frontend), // Uses COMBINED stall .pd_valid1 (pd_valid1), .pd_valid2 (pd_valid2), .pd_pc (pd_pc), @@ -188,7 +194,6 @@ module main_datapath #( .pd_sp_snap (pd_sp_snap), .pd_ras_snap (pd_ras_snap), .pd_prev_ghr (pd_prev_ghr), - .if_valid1 (if_valid1), .if_valid2 (if_valid2), .if_pc (if_pc), @@ -207,19 +212,10 @@ module main_datapath #( .if_prev_ghr (if_prev_ghr) ); - ID_Stage #( - .OPCODE_SIZE (OPCODE_SIZE), - .PHT_ADDRESS (PHT_ADDRESS), - .GHR_SIZE (GHR_SIZE), - .XLEN (XLEN), - .RAS_ADDRESS (RAS_ADDRESS), - .INIT_IMMEDIATE_SIZE (INIT_IMMEDIATE_SIZE), - .BIQ_ADDRESS (BIQ_ADDRESS) - ) id_stage_inst ( + ID_Stage #( /* ... Parameters ... */ ) id_stage_inst ( .CLK (CLK), .reset (reset), .flush (flush), - .if_valid1 (if_valid1), .if_valid2 (if_valid2), .if_instr1 (if_instr1), @@ -236,68 +232,95 @@ module main_datapath #( .if_sp_snap (if_sp_snap), .if_ras_snap (if_ras_snap), .if_prev_ghr (if_prev_ghr), - .dis_biq_dealloc (dis_biq_dealloc), .rr_biq_id (rr_biq_id), .rr_slot_id (rr_slot_id), - - .stall_frontend (stall_frontend), // Loops back to PD and IF stages + .stall_frontend (id_stall_frontend), // Dedicated ID stall .id_take_snap (id_take_snap), - .id_valid1 (id_valid1), .id_valid2 (id_valid2), .id_pc (id_pc), + .id_funct3_1 (id_funct3_1), .id_funct7_1(id_funct7_1), .id_rs1_1(id_rs1_1), .id_rs2_1(id_rs2_1), .id_rd_1(id_rd_1), + .id_immout1 (id_immout1), .id_alu_op1(id_alu_op1), .id_jump_reg1(id_jump_reg1), .id_jump1(id_jump1), .id_branch1(id_branch1), + .id_regsrc1_1 (id_regsrc1_1), .id_regsrc2_1(id_regsrc2_1), .id_immtype1(id_immtype1), .id_memwrite1(id_memwrite1), .id_regwrite1(id_regwrite1), + .id_memtoreg1 (id_memtoreg1), .id_retaddr1(id_retaddr1), .id_isimm1(id_isimm1), .id_upperimm1(id_upperimm1), + .id_funct3_2 (id_funct3_2), .id_funct7_2(id_funct7_2), .id_rs1_2(id_rs1_2), .id_rs2_2(id_rs2_2), .id_rd_2(id_rd_2), + .id_immout2 (id_immout2), .id_alu_op2(id_alu_op2), .id_jump_reg2(id_jump_reg2), .id_jump2(id_jump2), .id_branch2(id_branch2), + .id_regsrc1_2 (id_regsrc1_2), .id_regsrc2_2(id_regsrc2_2), .id_immtype2(id_immtype2), .id_memwrite2(id_memwrite2), .id_regwrite2(id_regwrite2), + .id_memtoreg2 (id_memtoreg2), .id_retaddr2(id_retaddr2), .id_isimm2(id_isimm2), .id_upperimm2(id_upperimm2), + .id_biq_address (id_biq_address), .id_biq_valid(id_biq_valid), .id_biq_pred_taken(id_biq_pred_taken), .id_biq_pred_target(id_biq_pred_target), + .id_biq_pht_index (id_biq_pht_index), .id_biq_restore_ghr(id_biq_restore_ghr), .id_biq_sp_snap(id_biq_sp_snap), .id_biq_ras_snap(id_biq_ras_snap) + ); + + RN_Stage #( + .PRF_ADDRESS (PRF_ADDRESS), + .INIT_IMMEDIATE_SIZE (INIT_IMMEDIATE_SIZE), + .MAX_BRANCHES (MAX_BRANCHES), + .BIQ_ADDRESS (BIQ_ADDRESS), + .XLEN (XLEN) + ) rn_stage_inst ( + .CLK (CLK), + .reset (reset), + .flush (flush), - .id_funct3_1 (id_funct3_1), - .id_funct7_1 (id_funct7_1), - .id_rs1_1 (id_rs1_1), - .id_rs2_1 (id_rs2_1), - .id_rd_1 (id_rd_1), - .id_immout1 (id_immout1), - .id_alu_op1 (id_alu_op1), - .id_jump_reg1 (id_jump_reg1), - .id_jump1 (id_jump1), - .id_branch1 (id_branch1), - .id_regsrc1_1 (id_regsrc1_1), - .id_regsrc2_1 (id_regsrc2_1), - .id_immtype1 (id_immtype1), - .id_memwrite1 (id_memwrite1), - .id_regwrite1 (id_regwrite1), - .id_memtoreg1 (id_memtoreg1), - .id_retaddr1 (id_retaddr1), - .id_isimm1 (id_isimm1), - .id_upperimm1 (id_upperimm1), + .id_take_snap (id_take_snap), + .id_valid1 (id_valid1), + .id_valid2 (id_valid2), - .id_funct3_2 (id_funct3_2), - .id_funct7_2 (id_funct7_2), - - .id_rs1_2 (id_rs1_2), - .id_rs2_2 (id_rs2_2), - .id_rd_2 (id_rd_2), + .cdb_wakeup1 (cdb_wakeup1), + .cdb_wakeup2 (cdb_wakeup2), + .comm_free_push1 (comm_free_push1), + .comm_free_push2 (comm_free_push2), + .ex_branch_resolved (ex_branch_resolved), + .cdb_waked_reg1 (cdb_waked_reg1), + .cdb_waked_reg2 (cdb_waked_reg2), + .comm_free_reg1 (comm_free_reg1), + .comm_free_reg2 (comm_free_reg2), + .ex_btag (ex_btag), + + // Decode logic inputs + .id_funct3_1 (id_funct3_1), .id_funct3_2(id_funct3_2), + .id_funct7_1 (id_funct7_1), .id_funct7_2(id_funct7_2), + .id_rs1_1 (id_rs1_1), .id_rs2_1(id_rs2_1), .id_rd_1(id_rd_1), + .id_rs1_2 (id_rs1_2), .id_rs2_2(id_rs2_2), .id_rd_2(id_rd_2), + .id_immout1 (id_immout1), .id_immout2(id_immout2), + .id_biq_address (id_biq_address), + .id_pc (id_pc), + .id_alu_op1 (id_alu_op1), .id_alu_op2(id_alu_op2), + .id_jump_reg1 (id_jump_reg1), .id_jump_reg2(id_jump_reg2), + .id_jump1 (id_jump1), .id_jump2(id_jump2), + .id_branch1 (id_branch1), .id_branch2(id_branch2), + .id_regsrc1_1 (id_regsrc1_1), .id_immtype1(id_immtype1), .id_memwrite1(id_memwrite1), + .id_immtype2 (id_immtype2), .id_regsrc2_1(id_regsrc2_1), + .id_regsrc1_2 (id_regsrc1_2), .id_regsrc2_2(id_regsrc2_2), + .id_upperimm1 (id_upperimm1), .id_upperimm2(id_upperimm2), + .id_regwrite1 (id_regwrite1), .id_regwrite2(id_regwrite2), + .id_memwrite2 (id_memwrite2), .id_memtoreg1(id_memtoreg1), .id_memtoreg2(id_memtoreg2), + .id_retaddr1 (id_retaddr1), .id_retaddr2(id_retaddr2), + .id_isimm1 (id_isimm1), .id_isimm2(id_isimm2), + + .stall_frontend (rn_stall_frontend), // Dedicated RN stall - .id_immout2 (id_immout2), - .id_alu_op2 (id_alu_op2), - .id_jump_reg2 (id_jump_reg2), - .id_jump2 (id_jump2), - .id_branch2 (id_branch2), - .id_regsrc1_2 (id_regsrc1_2), - .id_regsrc2_2 (id_regsrc2_2), - .id_immtype2 (id_immtype2), - .id_memwrite2 (id_memwrite2), - .id_regwrite2 (id_regwrite2), - .id_memtoreg2 (id_memtoreg2), - .id_retaddr2 (id_retaddr2), - .id_isimm2 (id_isimm2), - .id_upperimm2 (id_upperimm2), + // Renamed outputs mapped directly to main_datapath outputs + .rn_prd1 (rn_prd1), .rn_prs1_1(rn_prs1_1), .rn_prs2_1(rn_prs2_1), .rn_old_prd1(rn_old_prd1), + .rn_prd2 (rn_prd2), .rn_prs1_2(rn_prs1_2), .rn_prs2_2(rn_prs2_2), .rn_old_prd2(rn_old_prd2), + .rn_prs1_busy1 (rn_prs1_busy1), .rn_prs2_busy1(rn_prs2_busy1), .rn_prs1_busy2(rn_prs1_busy2), .rn_prs2_busy2(rn_prs2_busy2), + .rn_branch_tag (rn_branch_tag), + .rn_branch_mask (rn_branch_mask), + .rn_biq_address (rn_biq_address), + .rn_pc (rn_pc), + .rn_funct3_1 (rn_funct3_1), .rn_funct3_2(rn_funct3_2), + .rn_funct7_1 (rn_funct7_1), .rn_funct7_2(rn_funct7_2), + .rn_immout1 (rn_immout1), .rn_immout2(rn_immout2), + .rn_alu_op1 (rn_alu_op1), .rn_alu_op2(rn_alu_op2), + + .rn_valid1 (rn_valid1), .rn_jump_reg1(rn_jump_reg1), .rn_jump1(rn_jump1), .rn_branch1(rn_branch1), + .rn_regsrc1_1 (rn_regsrc1_1), .rn_regsrc2_1(rn_regsrc2_1), .rn_immtype1(rn_immtype1), .rn_isimm1(rn_isimm1), .rn_retaddr1(rn_retaddr1), + .rn_upperimm1 (rn_upperimm1), .rn_regwrite1(rn_regwrite1), .rn_memwrite1(rn_memwrite1), .rn_memtoreg1(rn_memtoreg1), - .id_biq_address (id_biq_address), - .id_biq_valid (id_biq_valid), - .id_biq_pred_taken (id_biq_pred_taken), - .id_biq_pred_target (id_biq_pred_target), - .id_biq_pht_index (id_biq_pht_index), - .id_biq_restore_ghr (id_biq_restore_ghr), - .id_biq_sp_snap (id_biq_sp_snap), - .id_biq_ras_snap (id_biq_ras_snap) + .rn_valid2 (rn_valid2), .rn_jump_reg2(rn_jump_reg2), .rn_jump2(rn_jump2), .rn_branch2(rn_branch2), + .rn_regsrc1_2 (rn_regsrc1_2), .rn_regsrc2_2(rn_regsrc2_2), .rn_immtype2(rn_immtype2), .rn_isimm2(rn_isimm2), .rn_retaddr2(rn_retaddr2), + .rn_upperimm2 (rn_upperimm2), .rn_regwrite2(rn_regwrite2), .rn_memwrite2(rn_memwrite2), .rn_memtoreg2(rn_memtoreg2) ); endmodule \ No newline at end of file diff --git a/Design/tb_main_datapath.sv b/Design/tb_main_datapath.sv index d538ce7..c71b8f6 100644 --- a/Design/tb_main_datapath.sv +++ b/Design/tb_main_datapath.sv @@ -1,230 +1,123 @@ module tb_main_datapath(); - // ----------------------------------------- - // Parameters (Matching DUT) - // ----------------------------------------- - parameter XLEN = 32; - parameter OPCODE_SIZE = 7; - parameter PHT_ADDRESS = 9; - parameter GHR_SIZE = 9; - parameter RAS_ADDRESS = 3; - parameter INIT_IMMEDIATE_SIZE = 21; - parameter BIQ_ADDRESS = 5; - - // ----------------------------------------- - // Testbench Signals (Inputs to DUT) - // ----------------------------------------- + // Parameters + localparam XLEN = 32; + localparam OPCODE_SIZE = 7; + localparam PHT_ADDRESS = 9; + localparam GHR_SIZE = 9; + localparam RAS_ADDRESS = 3; + localparam INIT_IMMEDIATE_SIZE = 21; + localparam BIQ_ADDRESS = 5; + localparam PRF_ADDRESS = 6; + localparam MAX_BRANCHES = 4; + localparam BTAG_SIZE = $clog2(MAX_BRANCHES); + + // Clock and Reset logic CLK; logic reset; logic flush; - - logic actual_taken; - logic mispredict; - logic restore_ghr; - logic restore_ras; - logic update_pht; - logic update_btb; - logic update_ras; - logic ex_is_ret; - logic ex_is_branch; - - logic [XLEN-1:0] actual_target_address; - logic [XLEN-1:0] ex_pc; + + // Backend Predictor Updates + logic actual_taken, mispredict, restore_ghr, restore_ras, update_pht; + logic update_btb, update_ras, ex_is_ret, ex_is_branch; + logic [XLEN-1:0] actual_target_address, ex_pc; logic [GHR_SIZE-1:0] ghr_snap; logic [PHT_ADDRESS-1:0] rb_pht_index; logic [RAS_ADDRESS-1:0] rb_sp_snap; logic [2*XLEN-1:0] rb_ras_snap; + // Dispatch/RR logic dis_biq_dealloc; logic [BIQ_ADDRESS-1:0] rr_biq_id; logic rr_slot_id; - // ----------------------------------------- - // Testbench Signals (Outputs from DUT) - // ----------------------------------------- + // Rename Stage specific + logic cdb_wakeup1, cdb_wakeup2, comm_free_push1, comm_free_push2, ex_branch_resolved; + logic [PRF_ADDRESS-1:0] cdb_waked_reg1, cdb_waked_reg2, comm_free_reg1, comm_free_reg2; + logic [BTAG_SIZE-1:0] ex_btag; + + // Outputs logic stall_frontend; - logic id_valid1; - logic id_valid2; - logic [XLEN-3:0] id_pc; - logic id_take_snap; - - // Slot 1 - logic [2:0] id_funct3_1, id_alu_op1; - logic [6:0] id_funct7_1; - logic [4:0] id_rs1_1, id_rs2_1, id_rd_1; - - logic [INIT_IMMEDIATE_SIZE-1:0] id_immout1; - logic id_jump_reg1, id_jump1, id_branch1, id_regsrc1_1, id_regsrc2_1; - logic id_immtype1, id_memwrite1, id_regwrite1, id_memtoreg1, id_retaddr1, id_isimm1, id_upperimm1; - - // Slot 2 - logic [2:0] id_funct3_2, id_alu_op2; - logic [4:0] id_rs1_2, id_rs2_2, id_rd_2; - logic [6:0] id_funct7_2; - logic [INIT_IMMEDIATE_SIZE-1:0] id_immout2; - logic id_jump_reg2, id_jump2, id_branch2, id_regsrc1_2, id_regsrc2_2; - logic id_immtype2, id_memwrite2, id_regwrite2, id_memtoreg2, id_retaddr2, id_isimm2, id_upperimm2; - - // BIQ Metadata Outputs - logic [BIQ_ADDRESS-1:0] id_biq_address; - logic id_biq_valid; - logic id_biq_pred_taken; + logic [PRF_ADDRESS-1:0] rn_prd1, rn_prs1_1, rn_prs2_1, rn_old_prd1; + logic [PRF_ADDRESS-1:0] rn_prd2, rn_prs1_2, rn_prs2_2, rn_old_prd2; + logic rn_prs1_busy1, rn_prs2_busy1, rn_prs1_busy2, rn_prs2_busy2; + logic [BTAG_SIZE-1:0] rn_branch_tag; + logic [MAX_BRANCHES-1:0] rn_branch_mask; + logic [BIQ_ADDRESS-1:0] rn_biq_address; + logic [XLEN-3:0] rn_pc; + logic rn_valid1, rn_valid2; + + // Output stubs + logic [2:0] rn_funct3_1, rn_alu_op1, rn_funct3_2, rn_alu_op2; + logic [6:0] rn_funct7_1, rn_funct7_2; + logic [INIT_IMMEDIATE_SIZE-1:0] rn_immout1, rn_immout2; + logic rn_jump_reg1, rn_jump1, rn_branch1, rn_regsrc1_1, rn_regsrc2_1, rn_immtype1, rn_isimm1, rn_retaddr1, rn_upperimm1, rn_regwrite1, rn_memwrite1, rn_memtoreg1; + logic rn_jump_reg2, rn_jump2, rn_branch2, rn_regsrc1_2, rn_regsrc2_2, rn_immtype2, rn_isimm2, rn_retaddr2, rn_upperimm2, rn_regwrite2, rn_memwrite2, rn_memtoreg2; + logic id_biq_valid, id_biq_pred_taken; logic [XLEN-1:0] id_biq_pred_target; logic [PHT_ADDRESS-1:0] id_biq_pht_index; logic [GHR_SIZE-1:0] id_biq_restore_ghr; logic [RAS_ADDRESS-1:0] id_biq_sp_snap; logic [2*XLEN-1:0] id_biq_ras_snap; - // ----------------------------------------- - // Instantiate the Device Under Test (DUT) - // ----------------------------------------- + // DUT Instantiation main_datapath #( - .XLEN(XLEN), - .OPCODE_SIZE(OPCODE_SIZE), - .PHT_ADDRESS(PHT_ADDRESS), - .GHR_SIZE(GHR_SIZE), - .RAS_ADDRESS(RAS_ADDRESS), - .INIT_IMMEDIATE_SIZE(INIT_IMMEDIATE_SIZE), - .BIQ_ADDRESS(BIQ_ADDRESS) - ) dut ( - .CLK(CLK), - .reset(reset), - .flush(flush), - - // Predictor Updates - .actual_taken(actual_taken), - .mispredict(mispredict), - .restore_ghr(restore_ghr), - .restore_ras(restore_ras), - .update_pht(update_pht), - .update_btb(update_btb), - .update_ras(update_ras), - .ex_is_ret(ex_is_ret), - .ex_is_branch(ex_is_branch), - .actual_target_address(actual_target_address), - .ex_pc(ex_pc), - .ghr_snap(ghr_snap), - .rb_pht_index(rb_pht_index), - .rb_sp_snap(rb_sp_snap), - .rb_ras_snap(rb_ras_snap), - - // Dispatch Inputs - .dis_biq_dealloc(dis_biq_dealloc), - .rr_biq_id(rr_biq_id), - .rr_slot_id(rr_slot_id), - - // Frontend Control Outputs - .stall_frontend(stall_frontend), - .id_valid1(id_valid1), - .id_valid2(id_valid2), - .id_pc(id_pc), - .id_take_snap(id_take_snap), - - // Slot 1 Outputs - .id_funct3_1(id_funct3_1), .id_alu_op1(id_alu_op1), .id_funct7_1(id_funct7_1), - - .id_rs1_1(id_rs1_1), .id_rs2_1(id_rs2_1), .id_rd_1(id_rd_1), - .id_rs1_2(id_rs1_2), .id_rs2_2(id_rs2_2), .id_rd_2(id_rd_2), - - .id_immout1(id_immout1), .id_jump_reg1(id_jump_reg1), .id_jump1(id_jump1), - .id_branch1(id_branch1), .id_regsrc1_1(id_regsrc1_1), .id_regsrc2_1(id_regsrc2_1), - .id_immtype1(id_immtype1), .id_memwrite1(id_memwrite1), .id_regwrite1(id_regwrite1), - .id_memtoreg1(id_memtoreg1), .id_retaddr1(id_retaddr1), .id_isimm1(id_isimm1), .id_upperimm1(id_upperimm1), - - // Slot 2 Outputs - .id_funct3_2(id_funct3_2), .id_alu_op2(id_alu_op2), .id_funct7_2(id_funct7_2), // Typo fixed here - .id_immout2(id_immout2), .id_jump_reg2(id_jump_reg2), .id_jump2(id_jump2), - .id_branch2(id_branch2), .id_regsrc1_2(id_regsrc1_2), .id_regsrc2_2(id_regsrc2_2), - .id_immtype2(id_immtype2), .id_memwrite2(id_memwrite2), .id_regwrite2(id_regwrite2), - .id_memtoreg2(id_memtoreg2), .id_retaddr2(id_retaddr2), .id_isimm2(id_isimm2), .id_upperimm2(id_upperimm2), - - // BIQ Metadata Outputs - .id_biq_address(id_biq_address), .id_biq_valid(id_biq_valid), - .id_biq_pred_taken(id_biq_pred_taken), .id_biq_pred_target(id_biq_pred_target), - .id_biq_pht_index(id_biq_pht_index), .id_biq_restore_ghr(id_biq_restore_ghr), - .id_biq_sp_snap(id_biq_sp_snap), .id_biq_ras_snap(id_biq_ras_snap) - ); - - // ----------------------------------------- - // Clock Generation (100 MHz) - // ----------------------------------------- - initial CLK = 0; + .XLEN(XLEN), .OPCODE_SIZE(OPCODE_SIZE), .PHT_ADDRESS(PHT_ADDRESS), + .GHR_SIZE(GHR_SIZE), .RAS_ADDRESS(RAS_ADDRESS), + .INIT_IMMEDIATE_SIZE(INIT_IMMEDIATE_SIZE), .BIQ_ADDRESS(BIQ_ADDRESS), + .PRF_ADDRESS(PRF_ADDRESS), .MAX_BRANCHES(MAX_BRANCHES) + ) dut (.*); + + // Clock Generation always #5 CLK = ~CLK; - // ----------------------------------------- - // Test Sequence - // ----------------------------------------- + // VCD Generation Block initial begin - // Waveform Dump for Vivado/GTKWave - $dumpfile("main_datapath.vcd"); - $dumpvars(0, tb_main_datapath); + $dumpfile("waveform.vcd"); + $dumpvars(0, main_datapath_tb); + end - // 1. Initialize all inputs (Zero the Backend) + initial begin + // Initialize Inputs + CLK = 0; reset = 1; flush = 0; - mispredict = 0; - actual_taken = 0; - restore_ghr = 0; - restore_ras = 0; - update_pht = 0; - update_btb = 0; - update_ras = 0; - ex_is_ret = 0; - ex_is_branch = 0; - actual_target_address = 0; - ex_pc = 0; - ghr_snap = 0; - rb_pht_index = 0; - rb_sp_snap = 0; - rb_ras_snap = 0; - dis_biq_dealloc = 0; - rr_biq_id = 0; - rr_slot_id = 0; - - // 2. Hold reset for a few cycles - #20; - reset = 0; - - // 3. Let the processor freely fetch and decode - // (Assuming instructions.hex is loaded into InstructionMemory) - #50; - - // 4. MOCK: Backend Detects a Branch Misprediction - // Simulate the Execute stage overriding the PC and restoring the GHR - @(posedge CLK); - flush = 1; - mispredict = 1; - actual_target_address = 32'h0000_00A4; // The correct path it should have taken - restore_ghr = 1; - ghr_snap = 9'b000000010; // Snapshot from the BIQ - actual_taken = 1; // The branch was actually taken - - // Update predictors - update_btb = 1; - ex_pc = 32'h0000_0020; // Address of the failed branch - ex_is_branch = 1; - - @(posedge CLK); - // De-assert backend signals; let frontend recover and fetch new path - flush = 0; - mispredict = 0; - restore_ghr = 0; - update_btb = 0; - actual_target_address = 0; - - #50; - // 5. MOCK: Backend Dispatch Queue Retires a Branch - // Free up a slot in the BIQ - @(posedge CLK); - dis_biq_dealloc = 1; + // Zero-out Execution/Backend Feedbacks + actual_taken = 0; mispredict = 0; restore_ghr = 0; restore_ras = 0; + update_pht = 0; update_btb = 0; update_ras = 0; ex_is_ret = 0; ex_is_branch = 0; + actual_target_address = '0; ex_pc = '0; ghr_snap = '0; + rb_pht_index = '0; rb_sp_snap = '0; rb_ras_snap = '0; + + dis_biq_dealloc = 0; rr_biq_id = '0; rr_slot_id = 0; + + // Zero-out CDB & Rename Backend Signals + cdb_wakeup1 = 0; cdb_wakeup2 = 0; + comm_free_push1 = 0; comm_free_push2 = 0; + ex_branch_resolved = 0; ex_btag = '0; + cdb_waked_reg1 = '0; cdb_waked_reg2 = '0; + comm_free_reg1 = '0; comm_free_reg2 = '0; + + // Apply Reset + #15 reset = 0; + + // Wait a few cycles to let PD, IF, and ID stages fill + #60; + + // Simulate a commit waking up the Free List + comm_free_push1 = 1; + comm_free_reg1 = 6'd35; + #10; + comm_free_push1 = 0; - @(posedge CLK); - dis_biq_dealloc = 0; + // Simulate a CDB broadcast + cdb_wakeup1 = 1; + cdb_waked_reg1 = 6'd1; + #10; + cdb_wakeup1 = 0; + // Run until pipeline establishes steady-state valid signals #100; - - $display("Simulation Finished Successfully."); $finish; end diff --git a/Design/waveform.vcd b/Design/waveform.vcd new file mode 100644 index 0000000..e5a188c --- /dev/null +++ b/Design/waveform.vcd @@ -0,0 +1,2251 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module TOP $end + $scope module tb_main_datapath $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 N& BIQ_ADDRESS [31:0] $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 P& MAX_BRANCHES [31:0] $end + $var wire 32 Q& BTAG_SIZE [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 % actual_taken $end + $var wire 1 & mispredict $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 * update_btb $end + $var wire 1 + update_ras $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 32 . actual_target_address [31:0] $end + $var wire 32 / ex_pc [31:0] $end + $var wire 9 0 ghr_snap [8:0] $end + $var wire 9 1 rb_pht_index [8:0] $end + $var wire 3 2 rb_sp_snap [2:0] $end + $var wire 64 3 rb_ras_snap [63:0] $end + $var wire 1 5 dis_biq_dealloc $end + $var wire 5 6 rr_biq_id [4:0] $end + $var wire 1 7 rr_slot_id $end + $var wire 1 8 cdb_wakeup1 $end + $var wire 1 9 cdb_wakeup2 $end + $var wire 1 : comm_free_push1 $end + $var wire 1 ; comm_free_push2 $end + $var wire 1 < ex_branch_resolved $end + $var wire 6 = cdb_waked_reg1 [5:0] $end + $var wire 6 > cdb_waked_reg2 [5:0] $end + $var wire 6 ? comm_free_reg1 [5:0] $end + $var wire 6 @ comm_free_reg2 [5:0] $end + $var wire 2 A ex_btag [1:0] $end + $var wire 1 s stall_frontend $end + $var wire 6 t rn_prd1 [5:0] $end + $var wire 6 u rn_prs1_1 [5:0] $end + $var wire 6 v rn_prs2_1 [5:0] $end + $var wire 6 w rn_old_prd1 [5:0] $end + $var wire 6 x rn_prd2 [5:0] $end + $var wire 6 y rn_prs1_2 [5:0] $end + $var wire 6 z rn_prs2_2 [5:0] $end + $var wire 6 { rn_old_prd2 [5:0] $end + $var wire 1 | rn_prs1_busy1 $end + $var wire 1 } rn_prs2_busy1 $end + $var wire 1 ~ rn_prs1_busy2 $end + $var wire 1 !! rn_prs2_busy2 $end + $var wire 2 "! rn_branch_tag [1:0] $end + $var wire 4 #! rn_branch_mask [3:0] $end + $var wire 5 $! rn_biq_address [4:0] $end + $var wire 30 %! rn_pc [29:0] $end + $var wire 1 &! rn_valid1 $end + $var wire 1 '! rn_valid2 $end + $var wire 3 (! rn_funct3_1 [2:0] $end + $var wire 3 )! rn_alu_op1 [2:0] $end + $var wire 3 *! rn_funct3_2 [2:0] $end + $var wire 3 +! rn_alu_op2 [2:0] $end + $var wire 7 ,! rn_funct7_1 [6:0] $end + $var wire 7 -! rn_funct7_2 [6:0] $end + $var wire 21 .! rn_immout1 [20:0] $end + $var wire 21 /! rn_immout2 [20:0] $end + $var wire 1 0! rn_jump_reg1 $end + $var wire 1 1! rn_jump1 $end + $var wire 1 2! rn_branch1 $end + $var wire 1 3! rn_regsrc1_1 $end + $var wire 1 4! rn_regsrc2_1 $end + $var wire 1 5! rn_immtype1 $end + $var wire 1 6! rn_isimm1 $end + $var wire 1 7! rn_retaddr1 $end + $var wire 1 8! rn_upperimm1 $end + $var wire 1 9! rn_regwrite1 $end + $var wire 1 :! rn_memwrite1 $end + $var wire 1 ;! rn_memtoreg1 $end + $var wire 1 ! rn_branch2 $end + $var wire 1 ?! rn_regsrc1_2 $end + $var wire 1 @! rn_regsrc2_2 $end + $var wire 1 A! rn_immtype2 $end + $var wire 1 B! rn_isimm2 $end + $var wire 1 C! rn_retaddr2 $end + $var wire 1 D! rn_upperimm2 $end + $var wire 1 E! rn_regwrite2 $end + $var wire 1 F! rn_memwrite2 $end + $var wire 1 G! rn_memtoreg2 $end + $var wire 1 H! id_biq_valid $end + $var wire 1 I! id_biq_pred_taken $end + $var wire 32 J! id_biq_pred_target [31:0] $end + $var wire 9 K! id_biq_pht_index [8:0] $end + $var wire 9 L! id_biq_restore_ghr [8:0] $end + $var wire 3 M! id_biq_sp_snap [2:0] $end + $var wire 64 N! id_biq_ras_snap [63:0] $end + $scope module dut $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 N& BIQ_ADDRESS [31:0] $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 P& MAX_BRANCHES [31:0] $end + $var wire 32 Q& BTAG_SIZE [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 % actual_taken $end + $var wire 1 & mispredict $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 * update_btb $end + $var wire 1 + update_ras $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 32 . actual_target_address [31:0] $end + $var wire 32 / ex_pc [31:0] $end + $var wire 9 0 ghr_snap [8:0] $end + $var wire 9 1 rb_pht_index [8:0] $end + $var wire 3 2 rb_sp_snap [2:0] $end + $var wire 64 3 rb_ras_snap [63:0] $end + $var wire 1 5 dis_biq_dealloc $end + $var wire 5 6 rr_biq_id [4:0] $end + $var wire 1 7 rr_slot_id $end + $var wire 1 8 cdb_wakeup1 $end + $var wire 1 9 cdb_wakeup2 $end + $var wire 1 : comm_free_push1 $end + $var wire 1 ; comm_free_push2 $end + $var wire 1 < ex_branch_resolved $end + $var wire 6 = cdb_waked_reg1 [5:0] $end + $var wire 6 > cdb_waked_reg2 [5:0] $end + $var wire 6 ? comm_free_reg1 [5:0] $end + $var wire 6 @ comm_free_reg2 [5:0] $end + $var wire 2 A ex_btag [1:0] $end + $var wire 1 s stall_frontend $end + $var wire 6 t rn_prd1 [5:0] $end + $var wire 6 u rn_prs1_1 [5:0] $end + $var wire 6 v rn_prs2_1 [5:0] $end + $var wire 6 w rn_old_prd1 [5:0] $end + $var wire 6 x rn_prd2 [5:0] $end + $var wire 6 y rn_prs1_2 [5:0] $end + $var wire 6 z rn_prs2_2 [5:0] $end + $var wire 6 { rn_old_prd2 [5:0] $end + $var wire 1 | rn_prs1_busy1 $end + $var wire 1 } rn_prs2_busy1 $end + $var wire 1 ~ rn_prs1_busy2 $end + $var wire 1 !! rn_prs2_busy2 $end + $var wire 2 "! rn_branch_tag [1:0] $end + $var wire 4 #! rn_branch_mask [3:0] $end + $var wire 1 &! rn_valid1 $end + $var wire 1 0! rn_jump_reg1 $end + $var wire 1 1! rn_jump1 $end + $var wire 1 2! rn_branch1 $end + $var wire 1 3! rn_regsrc1_1 $end + $var wire 1 4! rn_regsrc2_1 $end + $var wire 1 5! rn_immtype1 $end + $var wire 1 6! rn_isimm1 $end + $var wire 1 7! rn_retaddr1 $end + $var wire 1 8! rn_upperimm1 $end + $var wire 1 9! rn_regwrite1 $end + $var wire 1 :! rn_memwrite1 $end + $var wire 1 ;! rn_memtoreg1 $end + $var wire 3 (! rn_funct3_1 [2:0] $end + $var wire 3 )! rn_alu_op1 [2:0] $end + $var wire 7 ,! rn_funct7_1 [6:0] $end + $var wire 21 .! rn_immout1 [20:0] $end + $var wire 1 '! rn_valid2 $end + $var wire 1 ! rn_branch2 $end + $var wire 1 ?! rn_regsrc1_2 $end + $var wire 1 @! rn_regsrc2_2 $end + $var wire 1 A! rn_immtype2 $end + $var wire 1 B! rn_isimm2 $end + $var wire 1 C! rn_retaddr2 $end + $var wire 1 D! rn_upperimm2 $end + $var wire 1 E! rn_regwrite2 $end + $var wire 1 F! rn_memwrite2 $end + $var wire 1 G! rn_memtoreg2 $end + $var wire 3 *! rn_funct3_2 [2:0] $end + $var wire 3 +! rn_alu_op2 [2:0] $end + $var wire 7 -! rn_funct7_2 [6:0] $end + $var wire 21 /! rn_immout2 [20:0] $end + $var wire 5 $! rn_biq_address [4:0] $end + $var wire 30 %! rn_pc [29:0] $end + $var wire 1 H! id_biq_valid $end + $var wire 1 I! id_biq_pred_taken $end + $var wire 32 J! id_biq_pred_target [31:0] $end + $var wire 9 K! id_biq_pht_index [8:0] $end + $var wire 9 L! id_biq_restore_ghr [8:0] $end + $var wire 3 M! id_biq_sp_snap [2:0] $end + $var wire 64 N! id_biq_ras_snap [63:0] $end + $var wire 1 P! id_stall_frontend $end + $var wire 1 Q! rn_stall_frontend $end + $var wire 32 R! spec_return_address [31:0] $end + $var wire 1 S! pd_valid1 $end + $var wire 1 T! pd_valid2 $end + $var wire 32 D pd_pc [31:0] $end + $var wire 32 U! pd_pred_target1 [31:0] $end + $var wire 32 V! pd_pred_target2 [31:0] $end + $var wire 1 W! pd_pred_taken1 $end + $var wire 1 X! pd_pred_taken2 $end + $var wire 1 Y! pd_btb_hit1 $end + $var wire 1 Z! pd_btb_hit2 $end + $var wire 9 [! pd_pht_index1 [8:0] $end + $var wire 9 \! pd_pht_index2 [8:0] $end + $var wire 3 ]! pd_sp_snap [2:0] $end + $var wire 64 ^! pd_ras_snap [63:0] $end + $var wire 9 `! pd_prev_ghr [8:0] $end + $var wire 1 a! if_valid1 $end + $var wire 1 b! if_valid2 $end + $var wire 30 c! if_pc [29:0] $end + $var wire 32 d! if_instr1 [31:0] $end + $var wire 32 e! if_instr2 [31:0] $end + $var wire 32 f! if_pred_target1 [31:0] $end + $var wire 32 g! if_pred_target2 [31:0] $end + $var wire 1 h! if_pred_taken1 $end + $var wire 1 i! if_pred_taken2 $end + $var wire 1 j! if_btb_hit1 $end + $var wire 1 k! if_btb_hit2 $end + $var wire 9 l! if_pht_index1 [8:0] $end + $var wire 9 m! if_pht_index2 [8:0] $end + $var wire 3 n! if_sp_snap [2:0] $end + $var wire 64 o! if_ras_snap [63:0] $end + $var wire 9 q! if_prev_ghr [8:0] $end + $var wire 1 r! id_take_snap $end + $var wire 1 s! id_valid1 $end + $var wire 1 t! id_valid2 $end + $var wire 30 u! id_pc [29:0] $end + $var wire 5 v! id_biq_address [4:0] $end + $var wire 3 w! id_funct3_1 [2:0] $end + $var wire 3 x! id_alu_op1 [2:0] $end + $var wire 7 y! id_funct7_1 [6:0] $end + $var wire 5 z! id_rs1_1 [4:0] $end + $var wire 5 {! id_rs2_1 [4:0] $end + $var wire 5 |! id_rd_1 [4:0] $end + $var wire 1 }! id_jump_reg1 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 !" id_branch1 $end + $var wire 1 "" id_regsrc1_1 $end + $var wire 1 #" id_regsrc2_1 $end + $var wire 1 $" id_immtype1 $end + $var wire 1 %" id_memwrite1 $end + $var wire 1 &" id_regwrite1 $end + $var wire 1 '" id_memtoreg1 $end + $var wire 1 (" id_retaddr1 $end + $var wire 1 )" id_isimm1 $end + $var wire 1 *" id_upperimm1 $end + $var wire 21 +" id_immout1 [20:0] $end + $var wire 3 ," id_funct3_2 [2:0] $end + $var wire 3 -" id_alu_op2 [2:0] $end + $var wire 7 ." id_funct7_2 [6:0] $end + $var wire 5 /" id_rs1_2 [4:0] $end + $var wire 5 0" id_rs2_2 [4:0] $end + $var wire 5 1" id_rd_2 [4:0] $end + $var wire 1 2" id_jump_reg2 $end + $var wire 1 3" id_jump2 $end + $var wire 1 4" id_branch2 $end + $var wire 1 5" id_regsrc1_2 $end + $var wire 1 6" id_regsrc2_2 $end + $var wire 1 7" id_immtype2 $end + $var wire 1 8" id_memwrite2 $end + $var wire 1 9" id_regwrite2 $end + $var wire 1 :" id_memtoreg2 $end + $var wire 1 ;" id_retaddr2 $end + $var wire 1 <" id_isimm2 $end + $var wire 1 =" id_upperimm2 $end + $var wire 21 >" id_immout2 [20:0] $end + $scope module id_stage_inst $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 N& BIQ_ADDRESS [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 7 rr_slot_id $end + $var wire 1 5 dis_biq_dealloc $end + $var wire 1 h! if_pred_taken1 $end + $var wire 1 i! if_pred_taken2 $end + $var wire 1 a! if_valid1 $end + $var wire 1 b! if_valid2 $end + $var wire 1 j! if_btb_hit1 $end + $var wire 1 k! if_btb_hit2 $end + $var wire 32 d! if_instr1 [31:0] $end + $var wire 32 e! if_instr2 [31:0] $end + $var wire 32 f! if_pred_target1 [31:0] $end + $var wire 32 g! if_pred_target2 [31:0] $end + $var wire 30 c! if_pc [29:0] $end + $var wire 5 6 rr_biq_id [4:0] $end + $var wire 9 l! if_pht_index1 [8:0] $end + $var wire 9 m! if_pht_index2 [8:0] $end + $var wire 3 n! if_sp_snap [2:0] $end + $var wire 64 o! if_ras_snap [63:0] $end + $var wire 9 q! if_prev_ghr [8:0] $end + $var wire 3 M! id_biq_sp_snap [2:0] $end + $var wire 64 N! id_biq_ras_snap [63:0] $end + $var wire 1 P! stall_frontend $end + $var wire 1 r! id_take_snap $end + $var wire 1 s! id_valid1 $end + $var wire 1 t! id_valid2 $end + $var wire 3 w! id_funct3_1 [2:0] $end + $var wire 3 ," id_funct3_2 [2:0] $end + $var wire 7 y! id_funct7_1 [6:0] $end + $var wire 7 ." id_funct7_2 [6:0] $end + $var wire 5 z! id_rs1_1 [4:0] $end + $var wire 5 {! id_rs2_1 [4:0] $end + $var wire 5 |! id_rd_1 [4:0] $end + $var wire 5 /" id_rs1_2 [4:0] $end + $var wire 5 0" id_rs2_2 [4:0] $end + $var wire 5 1" id_rd_2 [4:0] $end + $var wire 21 +" id_immout1 [20:0] $end + $var wire 21 >" id_immout2 [20:0] $end + $var wire 5 v! id_biq_address [4:0] $end + $var wire 32 J! id_biq_pred_target [31:0] $end + $var wire 30 u! id_pc [29:0] $end + $var wire 9 L! id_biq_restore_ghr [8:0] $end + $var wire 9 K! id_biq_pht_index [8:0] $end + $var wire 3 x! id_alu_op1 [2:0] $end + $var wire 3 -" id_alu_op2 [2:0] $end + $var wire 1 }! id_jump_reg1 $end + $var wire 1 2" id_jump_reg2 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 3" id_jump2 $end + $var wire 1 !" id_branch1 $end + $var wire 1 4" id_branch2 $end + $var wire 1 "" id_regsrc1_1 $end + $var wire 1 $" id_immtype1 $end + $var wire 1 %" id_memwrite1 $end + $var wire 1 7" id_immtype2 $end + $var wire 1 H! id_biq_valid $end + $var wire 1 I! id_biq_pred_taken $end + $var wire 1 #" id_regsrc2_1 $end + $var wire 1 5" id_regsrc1_2 $end + $var wire 1 6" id_regsrc2_2 $end + $var wire 1 *" id_upperimm1 $end + $var wire 1 =" id_upperimm2 $end + $var wire 1 &" id_regwrite1 $end + $var wire 1 9" id_regwrite2 $end + $var wire 1 8" id_memwrite2 $end + $var wire 1 '" id_memtoreg1 $end + $var wire 1 :" id_memtoreg2 $end + $var wire 1 (" id_retaddr1 $end + $var wire 1 ;" id_retaddr2 $end + $var wire 1 )" id_isimm1 $end + $var wire 1 <" id_isimm2 $end + $var wire 7 ?" opcode_1 [6:0] $end + $var wire 7 @" opcode_2 [6:0] $end + $var wire 3 R& funct3_1 [2:0] $end + $var wire 3 S& funct3_2 [2:0] $end + $var wire 7 T& funct7_1 [6:0] $end + $var wire 7 U& funct7_2 [6:0] $end + $var wire 3 A" ALUOp_1 [2:0] $end + $var wire 3 B" ALUOp_2 [2:0] $end + $var wire 21 C" imm_out1 [20:0] $end + $var wire 21 D" imm_out2 [20:0] $end + $var wire 1 E" is_control_flow_instr1 $end + $var wire 1 F" is_control_flow_instr2 $end + $var wire 1 G" pred_valid1 $end + $var wire 1 H" pred_valid2 $end + $var wire 1 I" JumpReg_1 $end + $var wire 1 J" JumpReg_2 $end + $var wire 1 K" Jump_1 $end + $var wire 1 L" Jump_2 $end + $var wire 1 M" Branch_1 $end + $var wire 1 N" Branch_2 $end + $var wire 1 O" RegSrc1_1 $end + $var wire 1 P" RegSrc2_1 $end + $var wire 1 Q" RegSrc1_2 $end + $var wire 1 R" RegSrc2_2 $end + $var wire 1 S" RetAddr_1 $end + $var wire 1 T" UpperImm_1 $end + $var wire 1 U" UpperImm_2 $end + $var wire 1 V" RegWrite_1 $end + $var wire 1 W" RegWrite_2 $end + $var wire 1 X" MemWrite_1 $end + $var wire 1 Y" MemWrite_2 $end + $var wire 1 Z" MemToReg_1 $end + $var wire 1 [" MemToReg_2 $end + $var wire 1 \" RetAddr_2 $end + $var wire 1 ]" Imm_1 $end + $var wire 1 ^" Imm_2 $end + $var wire 1 _" imm_type1 $end + $var wire 1 `" imm_type2 $end + $scope module biq_instantiation $end + $var wire 32 N& BIQ_ADDRESS [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 5 biq_dealloc $end + $var wire 1 $ flush $end + $var wire 1 G" pred_valid1 $end + $var wire 1 H" pred_valid2 $end + $var wire 1 E" biq_alloc1 $end + $var wire 1 F" biq_alloc2 $end + $var wire 1 h! pred_taken1 $end + $var wire 1 i! pred_taken2 $end + $var wire 6 C& biq_id [5:0] $end + $var wire 32 f! pred_target1 [31:0] $end + $var wire 32 g! pred_target2 [31:0] $end + $var wire 9 l! pht_index1 [8:0] $end + $var wire 9 m! pht_index2 [8:0] $end + $var wire 9 q! prev_ghr [8:0] $end + $var wire 3 n! sp_snap [2:0] $end + $var wire 64 o! ras_snap [63:0] $end + $var wire 5 v! biq_address [4:0] $end + $var wire 1 H! biq_valid $end + $var wire 1 I! biq_pred_taken $end + $var wire 1 P! stall_frontend $end + $var wire 32 J! biq_pred_target [31:0] $end + $var wire 9 L! biq_restore_ghr [8:0] $end + $var wire 3 M! biq_sp_snap [2:0] $end + $var wire 64 N! biq_ras_snap [63:0] $end + $var wire 9 K! biq_pht_index [8:0] $end + $var wire 43 a" BIQ_BANK0[0] [42:0] $end + $var wire 43 c" BIQ_BANK0[1] [42:0] $end + $var wire 43 e" BIQ_BANK0[2] [42:0] $end + $var wire 43 g" BIQ_BANK0[3] [42:0] $end + $var wire 43 i" BIQ_BANK0[4] [42:0] $end + $var wire 43 k" BIQ_BANK0[5] [42:0] $end + $var wire 43 m" BIQ_BANK0[6] [42:0] $end + $var wire 43 o" BIQ_BANK0[7] [42:0] $end + $var wire 43 q" BIQ_BANK0[8] [42:0] $end + $var wire 43 s" BIQ_BANK0[9] [42:0] $end + $var wire 43 u" BIQ_BANK0[10] [42:0] $end + $var wire 43 w" BIQ_BANK0[11] [42:0] $end + $var wire 43 y" BIQ_BANK0[12] [42:0] $end + $var wire 43 {" BIQ_BANK0[13] [42:0] $end + $var wire 43 }" BIQ_BANK0[14] [42:0] $end + $var wire 43 !# BIQ_BANK0[15] [42:0] $end + $var wire 43 ## BIQ_BANK0[16] [42:0] $end + $var wire 43 %# BIQ_BANK0[17] [42:0] $end + $var wire 43 '# BIQ_BANK0[18] [42:0] $end + $var wire 43 )# BIQ_BANK0[19] [42:0] $end + $var wire 43 +# BIQ_BANK0[20] [42:0] $end + $var wire 43 -# BIQ_BANK0[21] [42:0] $end + $var wire 43 /# BIQ_BANK0[22] [42:0] $end + $var wire 43 1# BIQ_BANK0[23] [42:0] $end + $var wire 43 3# BIQ_BANK0[24] [42:0] $end + $var wire 43 5# BIQ_BANK0[25] [42:0] $end + $var wire 43 7# BIQ_BANK0[26] [42:0] $end + $var wire 43 9# BIQ_BANK0[27] [42:0] $end + $var wire 43 ;# BIQ_BANK0[28] [42:0] $end + $var wire 43 =# BIQ_BANK0[29] [42:0] $end + $var wire 43 ?# BIQ_BANK0[30] [42:0] $end + $var wire 43 A# BIQ_BANK0[31] [42:0] $end + $var wire 43 C# BIQ_BANK1[0] [42:0] $end + $var wire 43 E# BIQ_BANK1[1] [42:0] $end + $var wire 43 G# BIQ_BANK1[2] [42:0] $end + $var wire 43 I# BIQ_BANK1[3] [42:0] $end + $var wire 43 K# BIQ_BANK1[4] [42:0] $end + $var wire 43 M# BIQ_BANK1[5] [42:0] $end + $var wire 43 O# BIQ_BANK1[6] [42:0] $end + $var wire 43 Q# BIQ_BANK1[7] [42:0] $end + $var wire 43 S# BIQ_BANK1[8] [42:0] $end + $var wire 43 U# BIQ_BANK1[9] [42:0] $end + $var wire 43 W# BIQ_BANK1[10] [42:0] $end + $var wire 43 Y# BIQ_BANK1[11] [42:0] $end + $var wire 43 [# BIQ_BANK1[12] [42:0] $end + $var wire 43 ]# BIQ_BANK1[13] [42:0] $end + $var wire 43 _# BIQ_BANK1[14] [42:0] $end + $var wire 43 a# BIQ_BANK1[15] [42:0] $end + $var wire 43 c# BIQ_BANK1[16] [42:0] $end + $var wire 43 e# BIQ_BANK1[17] [42:0] $end + $var wire 43 g# BIQ_BANK1[18] [42:0] $end + $var wire 43 i# BIQ_BANK1[19] [42:0] $end + $var wire 43 k# BIQ_BANK1[20] [42:0] $end + $var wire 43 m# BIQ_BANK1[21] [42:0] $end + $var wire 43 o# BIQ_BANK1[22] [42:0] $end + $var wire 43 q# BIQ_BANK1[23] [42:0] $end + $var wire 43 s# BIQ_BANK1[24] [42:0] $end + $var wire 43 u# BIQ_BANK1[25] [42:0] $end + $var wire 43 w# BIQ_BANK1[26] [42:0] $end + $var wire 43 y# BIQ_BANK1[27] [42:0] $end + $var wire 43 {# BIQ_BANK1[28] [42:0] $end + $var wire 43 }# BIQ_BANK1[29] [42:0] $end + $var wire 43 !$ BIQ_BANK1[30] [42:0] $end + $var wire 43 #$ BIQ_BANK1[31] [42:0] $end + $var wire 76 %$ BIQ_SHARED[0] [75:0] $end + $var wire 76 ($ BIQ_SHARED[1] [75:0] $end + $var wire 76 +$ BIQ_SHARED[2] [75:0] $end + $var wire 76 .$ BIQ_SHARED[3] [75:0] $end + $var wire 76 1$ BIQ_SHARED[4] [75:0] $end + $var wire 76 4$ BIQ_SHARED[5] [75:0] $end + $var wire 76 7$ BIQ_SHARED[6] [75:0] $end + $var wire 76 :$ BIQ_SHARED[7] [75:0] $end + $var wire 76 =$ BIQ_SHARED[8] [75:0] $end + $var wire 76 @$ BIQ_SHARED[9] [75:0] $end + $var wire 76 C$ BIQ_SHARED[10] [75:0] $end + $var wire 76 F$ BIQ_SHARED[11] [75:0] $end + $var wire 76 I$ BIQ_SHARED[12] [75:0] $end + $var wire 76 L$ BIQ_SHARED[13] [75:0] $end + $var wire 76 O$ BIQ_SHARED[14] [75:0] $end + $var wire 76 R$ BIQ_SHARED[15] [75:0] $end + $var wire 76 U$ BIQ_SHARED[16] [75:0] $end + $var wire 76 X$ BIQ_SHARED[17] [75:0] $end + $var wire 76 [$ BIQ_SHARED[18] [75:0] $end + $var wire 76 ^$ BIQ_SHARED[19] [75:0] $end + $var wire 76 a$ BIQ_SHARED[20] [75:0] $end + $var wire 76 d$ BIQ_SHARED[21] [75:0] $end + $var wire 76 g$ BIQ_SHARED[22] [75:0] $end + $var wire 76 j$ BIQ_SHARED[23] [75:0] $end + $var wire 76 m$ BIQ_SHARED[24] [75:0] $end + $var wire 76 p$ BIQ_SHARED[25] [75:0] $end + $var wire 76 s$ BIQ_SHARED[26] [75:0] $end + $var wire 76 v$ BIQ_SHARED[27] [75:0] $end + $var wire 76 y$ BIQ_SHARED[28] [75:0] $end + $var wire 76 |$ BIQ_SHARED[29] [75:0] $end + $var wire 76 !% BIQ_SHARED[30] [75:0] $end + $var wire 76 $% BIQ_SHARED[31] [75:0] $end + $var wire 5 6 biq_read_address [4:0] $end + $var wire 6 '% biq_head_ptr [5:0] $end + $var wire 6 (% biq_tail_ptr [5:0] $end + $var wire 1 P! biq_full $end + $upscope $end + $scope module cu_instantiation1 $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 7 ?" opcode [6:0] $end + $var wire 3 A" ALUOp [2:0] $end + $var wire 1 I" JumpReg $end + $var wire 1 K" Jump $end + $var wire 1 M" Branch $end + $var wire 1 O" RegSrc1 $end + $var wire 1 P" RegSrc2 $end + $var wire 1 T" UpperImm $end + $var wire 1 V" RegWrite $end + $var wire 1 X" MemWrite $end + $var wire 1 Z" MemToReg $end + $var wire 1 S" RetAddr $end + $var wire 1 ]" imm $end + $upscope $end + $scope module cu_instantiation2 $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 7 @" opcode [6:0] $end + $var wire 3 B" ALUOp [2:0] $end + $var wire 1 J" JumpReg $end + $var wire 1 L" Jump $end + $var wire 1 N" Branch $end + $var wire 1 Q" RegSrc1 $end + $var wire 1 R" RegSrc2 $end + $var wire 1 U" UpperImm $end + $var wire 1 W" RegWrite $end + $var wire 1 Y" MemWrite $end + $var wire 1 [" MemToReg $end + $var wire 1 \" RetAddr $end + $var wire 1 ^" imm $end + $upscope $end + $scope module ig_instantiation1 $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 d! instruction [31:0] $end + $var wire 21 C" immediate_output [20:0] $end + $var wire 1 _" imm_type $end + $var wire 7 )% opcode [6:0] $end + $upscope $end + $scope module ig_instantiation2 $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 J& OPCODE_SIZE [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 e! instruction [31:0] $end + $var wire 21 D" immediate_output [20:0] $end + $var wire 1 `" imm_type $end + $var wire 7 *% opcode [6:0] $end + $upscope $end + $upscope $end + $scope module if_stage_inst $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 S! pd_valid1 $end + $var wire 1 T! pd_valid2 $end + $var wire 1 s stall_frontend $end + $var wire 1 W! pd_pred_taken1 $end + $var wire 1 X! pd_pred_taken2 $end + $var wire 1 Y! pd_btb_hit1 $end + $var wire 1 Z! pd_btb_hit2 $end + $var wire 32 D pd_pc [31:0] $end + $var wire 32 U! pd_pred_target1 [31:0] $end + $var wire 32 V! pd_pred_target2 [31:0] $end + $var wire 9 [! pd_pht_index1 [8:0] $end + $var wire 9 \! pd_pht_index2 [8:0] $end + $var wire 3 ]! pd_sp_snap [2:0] $end + $var wire 64 ^! pd_ras_snap [63:0] $end + $var wire 9 `! pd_prev_ghr [8:0] $end + $var wire 1 h! if_pred_taken1 $end + $var wire 1 i! if_pred_taken2 $end + $var wire 1 j! if_btb_hit1 $end + $var wire 1 k! if_btb_hit2 $end + $var wire 1 a! if_valid1 $end + $var wire 1 b! if_valid2 $end + $var wire 32 d! if_instr1 [31:0] $end + $var wire 32 e! if_instr2 [31:0] $end + $var wire 32 f! if_pred_target1 [31:0] $end + $var wire 32 g! if_pred_target2 [31:0] $end + $var wire 30 c! if_pc [29:0] $end + $var wire 9 l! if_pht_index1 [8:0] $end + $var wire 9 m! if_pht_index2 [8:0] $end + $var wire 3 n! if_sp_snap [2:0] $end + $var wire 64 o! if_ras_snap [63:0] $end + $var wire 9 q! if_prev_ghr [8:0] $end + $var wire 30 E instr1_addr [29:0] $end + $var wire 30 F instr2_addr [29:0] $end + $scope module im_instantiation $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 V& MEM_ROWS [31:0] $end + $var wire 1 B& CLK $end + $var wire 32 G instr1_addr [31:0] $end + $var wire 32 H instr2_addr [31:0] $end + $var wire 32 d! instr_1 [31:0] $end + $var wire 32 e! instr_2 [31:0] $end + $upscope $end + $upscope $end + $scope module pd_stage_inst $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 s stall_frontend $end + $var wire 1 % actual_taken $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 * update_btb $end + $var wire 1 + update_ras $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 1 & mispredict $end + $var wire 32 . actual_target_address [31:0] $end + $var wire 32 R! actual_return_address [31:0] $end + $var wire 32 / ex_pc [31:0] $end + $var wire 9 0 ghr_snap [8:0] $end + $var wire 9 1 rb_pht_index [8:0] $end + $var wire 3 2 rb_sp_snap [2:0] $end + $var wire 64 3 rb_ras_snap [63:0] $end + $var wire 1 W! pd_pred_taken1 $end + $var wire 1 X! pd_pred_taken2 $end + $var wire 1 Y! pd_btb_hit1 $end + $var wire 1 Z! pd_btb_hit2 $end + $var wire 1 S! pd_valid1 $end + $var wire 1 T! pd_valid2 $end + $var wire 32 D pd_pc [31:0] $end + $var wire 32 U! pd_pred_target1 [31:0] $end + $var wire 32 V! pd_pred_target2 [31:0] $end + $var wire 9 [! pd_pht_index1 [8:0] $end + $var wire 9 \! pd_pht_index2 [8:0] $end + $var wire 3 ]! pd_sp_snap [2:0] $end + $var wire 64 ^! pd_ras_snap [63:0] $end + $var wire 9 `! pd_prev_ghr [8:0] $end + $var wire 9 +% ghr_out [8:0] $end + $var wire 9 +% prev_ghr [8:0] $end + $var wire 9 I pht_index1 [8:0] $end + $var wire 9 J pht_index2 [8:0] $end + $var wire 32 K final_pred_target1 [31:0] $end + $var wire 32 L final_pred_target2 [31:0] $end + $var wire 32 ,% pc [31:0] $end + $var wire 1 W! pred_taken1 $end + $var wire 1 X! pred_taken2 $end + $var wire 1 Y! btb_hit1 $end + $var wire 1 Z! btb_hit2 $end + $var wire 1 -% is_branch1 $end + $var wire 1 .% is_branch2 $end + $var wire 1 /% is_ret1 $end + $var wire 1 0% is_ret2 $end + $var wire 32 1% pred_target1 [31:0] $end + $var wire 32 2% pred_target2 [31:0] $end + $var wire 32 M pred_return_address [31:0] $end + $var wire 3 ]! sp_snap [2:0] $end + $var wire 64 ^! ras_snap [63:0] $end + $var wire 32 N write_pc_data [31:0] $end + $var wire 32 O next_pc [31:0] $end + $var wire 32 D pc1 [31:0] $end + $var wire 32 P pc2 [31:0] $end + $scope module btb_instantiation $end + $var wire 32 O& BTB_ADDRESS [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 W& TAG_SIZE [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 * update_btb $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 32 D pc1 [31:0] $end + $var wire 32 P pc2 [31:0] $end + $var wire 32 / ex_pc [31:0] $end + $var wire 32 . actual_target_address [31:0] $end + $var wire 1 Y! btb_hit1 $end + $var wire 1 Z! btb_hit2 $end + $var wire 1 /% is_ret1 $end + $var wire 1 0% is_ret2 $end + $var wire 1 -% is_branch1 $end + $var wire 1 .% is_branch2 $end + $var wire 32 1% pred_target1 [31:0] $end + $var wire 32 2% pred_target2 [31:0] $end + $var wire 59 3% btb_entry1 [58:0] $end + $var wire 59 5% btb_entry2 [58:0] $end + $var wire 1 7% tag_matched1 $end + $var wire 1 8% tag_matched2 $end + $var wire 24 Q btb_tag1 [23:0] $end + $var wire 24 R btb_tag2 [23:0] $end + $var wire 24 9% reg_btb_tag1 [23:0] $end + $var wire 24 :% reg_btb_tag2 [23:0] $end + $var wire 6 S btb_index1 [5:0] $end + $var wire 6 T btb_index2 [5:0] $end + $var wire 24 B ex_tag [23:0] $end + $var wire 6 C ex_btb_index [5:0] $end + $upscope $end + $scope module ghr_instantiation $end + $var wire 32 K& GHR_SIZE [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 s stall_frontend $end + $var wire 1 ' restore_ghr $end + $var wire 1 % actual_taken $end + $var wire 1 W! pred_taken1 $end + $var wire 1 X! pred_taken2 $end + $var wire 1 -% pred_branch1 $end + $var wire 1 .% pred_branch2 $end + $var wire 9 0 ghr_snap [8:0] $end + $var wire 9 +% ghr_out [8:0] $end + $var wire 9 +% prev_ghr [8:0] $end + $var wire 1 ;% pred_taken $end + $upscope $end + $scope module pc_instantiation $end + $var wire 32 I& XLEN [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 s stall_frontend $end + $var wire 1 & mispredict $end + $var wire 1 Y! btb_hit1 $end + $var wire 1 Z! btb_hit2 $end + $var wire 1 /% is_ret1 $end + $var wire 1 0% is_ret2 $end + $var wire 1 -% is_branch1 $end + $var wire 1 .% is_branch2 $end + $var wire 1 W! pred_taken1 $end + $var wire 1 X! pred_taken2 $end + $var wire 32 1% pred_target1 [31:0] $end + $var wire 32 2% pred_target2 [31:0] $end + $var wire 32 M ret_addr1 [31:0] $end + $var wire 32 M ret_addr2 [31:0] $end + $var wire 32 . actual_target_address [31:0] $end + $var wire 32 ,% pc [31:0] $end + $var wire 32 N write_pc_data [31:0] $end + $var wire 32 O next_pc [31:0] $end + $var wire 32 K final_pred_target1 [31:0] $end + $var wire 32 L final_pred_target2 [31:0] $end + $var wire 1 <% is_branch_or_jump1 $end + $var wire 1 =% is_branch_or_jump2 $end + $upscope $end + $scope module pht_instantiation $end + $var wire 32 K& PHT_ADDRESS [31:0] $end + $var wire 32 Q& COUNTER_SIZE [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 % actual_taken $end + $var wire 1 ) update_pht $end + $var wire 9 I pht_index1 [8:0] $end + $var wire 9 J pht_index2 [8:0] $end + $var wire 9 1 rb_pht_index [8:0] $end + $var wire 1 W! pred_taken1 $end + $var wire 1 X! pred_taken2 $end + $upscope $end + $scope module ras_instantiation $end + $var wire 32 L& RAS_ADDRESS [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 X& RAS_LEN [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 s stall_frontend $end + $var wire 1 + update_ras $end + $var wire 1 ( restore_ras $end + $var wire 1 /% btb_is_ret1 $end + $var wire 1 0% btb_is_ret2 $end + $var wire 32 R! actual_return_address [31:0] $end + $var wire 3 2 rb_sp_snap [2:0] $end + $var wire 64 3 rb_ras_snap [63:0] $end + $var wire 32 M pred_return_address [31:0] $end + $var wire 3 ]! sp_snap [2:0] $end + $var wire 64 ^! ras_snap [63:0] $end + $var wire 32 >% RAS[0] [31:0] $end + $var wire 32 ?% RAS[1] [31:0] $end + $var wire 32 @% RAS[2] [31:0] $end + $var wire 32 A% RAS[3] [31:0] $end + $var wire 32 B% RAS[4] [31:0] $end + $var wire 32 C% RAS[5] [31:0] $end + $var wire 32 D% RAS[6] [31:0] $end + $var wire 32 E% RAS[7] [31:0] $end + $var wire 3 F% sp [2:0] $end + $var wire 3 U next_sp [2:0] $end + $var wire 1 G% pop $end + $var wire 1 + push $end + $upscope $end + $upscope $end + $scope module rn_stage_inst $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 P& MAX_BRANCHES [31:0] $end + $var wire 32 Q& BTAG_SIZE [31:0] $end + $var wire 32 N& BIQ_ADDRESS [31:0] $end + $var wire 32 I& XLEN [31:0] $end + $var wire 32 Y& NUM_PHY_REG [31:0] $end + $var wire 32 I& FL_ROWS [31:0] $end + $var wire 32 N& FL_INDEX_WIDTH [31:0] $end + $var wire 32 O& FL_PTR_WIDTH [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 r! id_take_snap $end + $var wire 1 s! id_valid1 $end + $var wire 1 t! id_valid2 $end + $var wire 1 8 cdb_wakeup1 $end + $var wire 1 9 cdb_wakeup2 $end + $var wire 1 : comm_free_push1 $end + $var wire 1 ; comm_free_push2 $end + $var wire 1 < ex_branch_resolved $end + $var wire 6 = cdb_waked_reg1 [5:0] $end + $var wire 6 > cdb_waked_reg2 [5:0] $end + $var wire 6 ? comm_free_reg1 [5:0] $end + $var wire 6 @ comm_free_reg2 [5:0] $end + $var wire 2 A ex_btag [1:0] $end + $var wire 3 w! id_funct3_1 [2:0] $end + $var wire 3 ," id_funct3_2 [2:0] $end + $var wire 7 y! id_funct7_1 [6:0] $end + $var wire 7 ." id_funct7_2 [6:0] $end + $var wire 5 z! id_rs1_1 [4:0] $end + $var wire 5 {! id_rs2_1 [4:0] $end + $var wire 5 |! id_rd_1 [4:0] $end + $var wire 5 /" id_rs1_2 [4:0] $end + $var wire 5 0" id_rs2_2 [4:0] $end + $var wire 5 1" id_rd_2 [4:0] $end + $var wire 21 +" id_immout1 [20:0] $end + $var wire 21 >" id_immout2 [20:0] $end + $var wire 5 v! id_biq_address [4:0] $end + $var wire 30 u! id_pc [29:0] $end + $var wire 3 x! id_alu_op1 [2:0] $end + $var wire 3 -" id_alu_op2 [2:0] $end + $var wire 1 }! id_jump_reg1 $end + $var wire 1 2" id_jump_reg2 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 3" id_jump2 $end + $var wire 1 !" id_branch1 $end + $var wire 1 4" id_branch2 $end + $var wire 1 "" id_regsrc1_1 $end + $var wire 1 $" id_immtype1 $end + $var wire 1 %" id_memwrite1 $end + $var wire 1 7" id_immtype2 $end + $var wire 1 #" id_regsrc2_1 $end + $var wire 1 5" id_regsrc1_2 $end + $var wire 1 6" id_regsrc2_2 $end + $var wire 1 *" id_upperimm1 $end + $var wire 1 =" id_upperimm2 $end + $var wire 1 &" id_regwrite1 $end + $var wire 1 9" id_regwrite2 $end + $var wire 1 8" id_memwrite2 $end + $var wire 1 '" id_memtoreg1 $end + $var wire 1 :" id_memtoreg2 $end + $var wire 1 (" id_retaddr1 $end + $var wire 1 ;" id_retaddr2 $end + $var wire 1 )" id_isimm1 $end + $var wire 1 <" id_isimm2 $end + $var wire 1 Q! stall_frontend $end + $var wire 6 t rn_prd1 [5:0] $end + $var wire 6 u rn_prs1_1 [5:0] $end + $var wire 6 v rn_prs2_1 [5:0] $end + $var wire 6 w rn_old_prd1 [5:0] $end + $var wire 6 x rn_prd2 [5:0] $end + $var wire 6 y rn_prs1_2 [5:0] $end + $var wire 6 z rn_prs2_2 [5:0] $end + $var wire 6 { rn_old_prd2 [5:0] $end + $var wire 1 | rn_prs1_busy1 $end + $var wire 1 } rn_prs2_busy1 $end + $var wire 1 ~ rn_prs1_busy2 $end + $var wire 1 !! rn_prs2_busy2 $end + $var wire 2 "! rn_branch_tag [1:0] $end + $var wire 4 #! rn_branch_mask [3:0] $end + $var wire 5 $! rn_biq_address [4:0] $end + $var wire 30 %! rn_pc [29:0] $end + $var wire 3 (! rn_funct3_1 [2:0] $end + $var wire 3 *! rn_funct3_2 [2:0] $end + $var wire 7 ,! rn_funct7_1 [6:0] $end + $var wire 7 -! rn_funct7_2 [6:0] $end + $var wire 21 .! rn_immout1 [20:0] $end + $var wire 21 /! rn_immout2 [20:0] $end + $var wire 3 )! rn_alu_op1 [2:0] $end + $var wire 3 +! rn_alu_op2 [2:0] $end + $var wire 1 &! rn_valid1 $end + $var wire 1 0! rn_jump_reg1 $end + $var wire 1 1! rn_jump1 $end + $var wire 1 2! rn_branch1 $end + $var wire 1 3! rn_regsrc1_1 $end + $var wire 1 4! rn_regsrc2_1 $end + $var wire 1 5! rn_immtype1 $end + $var wire 1 6! rn_isimm1 $end + $var wire 1 7! rn_retaddr1 $end + $var wire 1 8! rn_upperimm1 $end + $var wire 1 9! rn_regwrite1 $end + $var wire 1 :! rn_memwrite1 $end + $var wire 1 ;! rn_memtoreg1 $end + $var wire 1 '! rn_valid2 $end + $var wire 1 ! rn_branch2 $end + $var wire 1 ?! rn_regsrc1_2 $end + $var wire 1 @! rn_regsrc2_2 $end + $var wire 1 A! rn_immtype2 $end + $var wire 1 B! rn_isimm2 $end + $var wire 1 C! rn_retaddr2 $end + $var wire 1 D! rn_upperimm2 $end + $var wire 1 E! rn_regwrite2 $end + $var wire 1 F! rn_memwrite2 $end + $var wire 1 G! rn_memtoreg2 $end + $var wire 6 H% fl_freed_reg1 [5:0] $end + $var wire 6 I% fl_freed_reg2 [5:0] $end + $var wire 192 V rmt_snap [191:0] $end + $var wire 192 \ bs_rmt_snap [191:0] $end + $var wire 6 b fl_head_ptr [5:0] $end + $var wire 6 c bs_head_ptr_snap [5:0] $end + $var wire 6 H% routed_freed_reg1 [5:0] $end + $var wire 6 J% routed_freed_reg2 [5:0] $end + $var wire 1 K% pop1 $end + $var wire 1 L% pop2 $end + $var wire 1 M% bs_full $end + $var wire 1 N% fl_empty $end + $scope module bs_instantiation $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 Y& NUM_PHY_REG [31:0] $end + $var wire 32 P& MAX_BRANCHES [31:0] $end + $var wire 32 Q& BTAG_SIZE [31:0] $end + $var wire 32 I& FL_ROWS [31:0] $end + $var wire 32 N& FL_INDEX_WIDTH [31:0] $end + $var wire 32 O& FL_PTR_WIDTH [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 d id_take_snap $end + $var wire 1 < ex_branch_resolved $end + $var wire 1 O% pop1 $end + $var wire 1 P% pop2 $end + $var wire 1 !" id_branch1 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 s! id_valid1 $end + $var wire 2 A ex_btag [1:0] $end + $var wire 192 V rmt_snap [191:0] $end + $var wire 6 b freelist_head_snap [5:0] $end + $var wire 1 M% bs_full $end + $var wire 192 \ bs_rmt_snap [191:0] $end + $var wire 6 c bs_freelist_head_snap [5:0] $end + $var wire 2 "! bs_branch_tag [1:0] $end + $var wire 4 #! bs_branch_mask [3:0] $end + $var wire 202 Q% BS[0] [201:0] $end + $var wire 202 X% BS[1] [201:0] $end + $var wire 202 _% BS[2] [201:0] $end + $var wire 202 f% BS[3] [201:0] $end + $var wire 4 m% BMR [3:0] $end + $var wire 2 n% current_btag [1:0] $end + $scope module unnamedblk1 $end + $var wire 32 o% i [31:0] $end + $upscope $end + $scope module unnamedblk2 $end + $var wire 32 p% i [31:0] $end + $upscope $end + $upscope $end + $scope module fl_instantiation $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 Y& NUM_PHY_REG [31:0] $end + $var wire 32 I& FL_ROWS [31:0] $end + $var wire 32 N& FL_INDEX_WIDTH [31:0] $end + $var wire 32 O& FL_PTR_WIDTH [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 Q! stall_frontend $end + $var wire 1 : push1 $end + $var wire 1 ; push2 $end + $var wire 1 K% pop1 $end + $var wire 1 L% pop2 $end + $var wire 1 !" id_branch1 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 s! id_valid1 $end + $var wire 6 ? comm_free_reg1 [5:0] $end + $var wire 6 @ comm_free_reg2 [5:0] $end + $var wire 6 c bs_head_ptr_snap [5:0] $end + $var wire 6 H% fl_freed_reg1 [5:0] $end + $var wire 6 I% fl_freed_reg2 [5:0] $end + $var wire 6 b fl_head_ptr [5:0] $end + $var wire 1 N% fl_empty $end + $var wire 6 q% FL[0] [5:0] $end + $var wire 6 r% FL[1] [5:0] $end + $var wire 6 s% FL[2] [5:0] $end + $var wire 6 t% FL[3] [5:0] $end + $var wire 6 u% FL[4] [5:0] $end + $var wire 6 v% FL[5] [5:0] $end + $var wire 6 w% FL[6] [5:0] $end + $var wire 6 x% FL[7] [5:0] $end + $var wire 6 y% FL[8] [5:0] $end + $var wire 6 z% FL[9] [5:0] $end + $var wire 6 {% FL[10] [5:0] $end + $var wire 6 |% FL[11] [5:0] $end + $var wire 6 }% FL[12] [5:0] $end + $var wire 6 ~% FL[13] [5:0] $end + $var wire 6 !& FL[14] [5:0] $end + $var wire 6 "& FL[15] [5:0] $end + $var wire 6 #& FL[16] [5:0] $end + $var wire 6 $& FL[17] [5:0] $end + $var wire 6 %& FL[18] [5:0] $end + $var wire 6 && FL[19] [5:0] $end + $var wire 6 '& FL[20] [5:0] $end + $var wire 6 (& FL[21] [5:0] $end + $var wire 6 )& FL[22] [5:0] $end + $var wire 6 *& FL[23] [5:0] $end + $var wire 6 +& FL[24] [5:0] $end + $var wire 6 ,& FL[25] [5:0] $end + $var wire 6 -& FL[26] [5:0] $end + $var wire 6 .& FL[27] [5:0] $end + $var wire 6 /& FL[28] [5:0] $end + $var wire 6 0& FL[29] [5:0] $end + $var wire 6 1& FL[30] [5:0] $end + $var wire 6 2& FL[31] [5:0] $end + $var wire 6 3& head [5:0] $end + $var wire 6 e next_head [5:0] $end + $var wire 6 4& tail [5:0] $end + $var wire 1 f valid_pop1 $end + $var wire 1 D& valid_pop2 $end + $var wire 6 5& registers_required [5:0] $end + $scope module unnamedblk1 $end + $var wire 32 6& i [31:0] $end + $upscope $end + $upscope $end + $scope module rmt_instantiation $end + $var wire 32 O& PRF_ADDRESS [31:0] $end + $var wire 32 Y& NUM_PHY_REG [31:0] $end + $var wire 1 B& CLK $end + $var wire 1 # reset $end + $var wire 1 $ restore_rmt $end + $var wire 1 Q! stall_frontend $end + $var wire 1 7& reg_write1 $end + $var wire 1 8& reg_write2 $end + $var wire 1 8 cdb_wakeup1 $end + $var wire 1 9 cdb_wakeup2 $end + $var wire 1 !" id_branch1 $end + $var wire 1 ~! id_jump1 $end + $var wire 1 s! id_valid1 $end + $var wire 1 t! id_valid2 $end + $var wire 5 |! rd1 [4:0] $end + $var wire 5 z! rs1_1 [4:0] $end + $var wire 5 {! rs2_1 [4:0] $end + $var wire 5 1" rd2 [4:0] $end + $var wire 5 /" rs1_2 [4:0] $end + $var wire 5 0" rs2_2 [4:0] $end + $var wire 6 H% fl_freed_reg1 [5:0] $end + $var wire 6 J% fl_freed_reg2 [5:0] $end + $var wire 6 = cdb_waked_reg1 [5:0] $end + $var wire 6 > cdb_waked_reg2 [5:0] $end + $var wire 192 \ bs_rmt_snap [191:0] $end + $var wire 1 | prs1_busy1 $end + $var wire 1 } prs2_busy1 $end + $var wire 1 ~ prs1_busy2 $end + $var wire 1 !! prs2_busy2 $end + $var wire 6 t prd1 [5:0] $end + $var wire 6 u prs1_1 [5:0] $end + $var wire 6 v prs2_1 [5:0] $end + $var wire 6 w old_prd1 [5:0] $end + $var wire 6 x prd2 [5:0] $end + $var wire 6 y prs1_2 [5:0] $end + $var wire 6 z prs2_2 [5:0] $end + $var wire 6 { old_prd2 [5:0] $end + $var wire 192 V rmt_snap [191:0] $end + $var wire 192 9& RMT [191:0] $end + $var wire 192 g next_RMT [191:0] $end + $var wire 192 m next_RMT_inst1 [191:0] $end + $var wire 64 ?& busy_table [63:0] $end + $var wire 1 E& wake_rs1_1 $end + $var wire 1 F& wake_rs1_2 $end + $var wire 1 G& wake_rs2_1 $end + $var wire 1 H& wake_rs2_2 $end + $scope module unnamedblk1 $end + $var wire 32 A& i [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +1# +0$ +0% +0& +0' +0( +0) +0* +0+ +0, +0- +b00000000000000000000000000000000 . +b00000000000000000000000000000000 / +b000000000 0 +b000000000 1 +b000 2 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[! +b000100011 \! +b000000000000000000000000100010 c! +b000100000 l! +b000100001 m! +b000000000000000000000000100000 u! +b00000000000000000000000010010000 ,% +1B& +#190 +0B& +#195 +b00000000000000000000000010011000 D +b000000000000000000000000100110 E +b000000000000000000000000100111 F +b00000000000000000000000000100110 G +b00000000000000000000000000100111 H +b000100110 I +b000100111 J +b00000000000000000000000010011000 N +b00000000000000000000000010100000 O +b00000000000000000000000010011100 P +b100110 S +b100111 T +b000000000000000000000000100000 %! +b00000000000000000000000010010000 R! +b000100100 [! +b000100101 \! +b000000000000000000000000100100 c! +b000100010 l! +b000100011 m! +b000000000000000000000000100010 u! +b00000000000000000000000010011000 ,% +1B& From c0aebd84c41770fe81782f6925e21a6853965bb2 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Tue, 30 Jun 2026 13:10:50 +0500 Subject: [PATCH 06/11] updated prediction and fetch stage --- Design/ID_Stage.sv | 9 +++++---- Design/IF_Stage.sv | 24 ++++++++++-------------- Design/PD_Stage.sv | 1 + 3 files changed, 16 insertions(+), 18 deletions(-) diff --git a/Design/ID_Stage.sv b/Design/ID_Stage.sv index c4c8214..1dceedd 100644 --- a/Design/ID_Stage.sv +++ b/Design/ID_Stage.sv @@ -7,15 +7,16 @@ module ID_Stage #( parameter INIT_IMMEDIATE_SIZE = 21, parameter BIQ_ADDRESS = 5 ) ( - input logic CLK, reset, flush, rr_slot_id, dis_biq_dealloc, if_pred_taken1, if_pred_taken2, - input logic if_valid1, if_valid2, if_btb_hit1, if_btb_hit2, - input logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target1, if_pred_target2, + input logic CLK, reset, flush, rr_slot_id, dis_biq_dealloc, if_pred_taken, + input logic if_valid1, if_valid2, if_btb_hit, + input logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target, input logic [XLEN-3:0] if_pc, input logic [BIQ_ADDRESS-1:0] rr_biq_id, - input logic [PHT_ADDRESS-1:0] if_pht_index1, if_pht_index2, + input logic [PHT_ADDRESS-1:0] if_pht_index, input logic [RAS_ADDRESS-1:0] if_sp_snap, input logic [2*XLEN-1:0] if_ras_snap, input logic [GHR_SIZE-1:0] if_prev_ghr, + output logic [RAS_ADDRESS-1:0] id_biq_sp_snap, output logic [2*XLEN-1:0] id_biq_ras_snap, output logic stall_frontend, id_take_snap, id_valid1, id_valid2, diff --git a/Design/IF_Stage.sv b/Design/IF_Stage.sv index f86b8ef..e9a80b9 100644 --- a/Design/IF_Stage.sv +++ b/Design/IF_Stage.sv @@ -5,18 +5,18 @@ module IF_Stage #( parameter RAS_ADDRESS = 3 ) ( input logic CLK, reset, flush, pd_valid1, pd_valid2, stall_frontend, - input logic pd_pred_taken1, pd_pred_taken2, pd_btb_hit1, pd_btb_hit2, - input logic [XLEN-1:0] pd_pc, pd_pred_target1, pd_pred_target2, - input logic [PHT_ADDRESS-1:0] pd_pht_index1, pd_pht_index2, + input logic pd_pred_taken, pd_btb_hit, + input logic [XLEN-1:0] pd_pc, pd_pred_target, + input logic [PHT_ADDRESS-1:0] pd_pht_index, input logic [RAS_ADDRESS-1:0] pd_sp_snap, input logic [2*XLEN-1:0] pd_ras_snap, input logic [GHR_SIZE-1:0] pd_prev_ghr, - output logic if_pred_taken1, if_pred_taken2, if_btb_hit1, if_btb_hit2, if_valid1, if_valid2, + output logic if_pred_taken, if_btb_hit, if_valid1, if_valid2, output logic [1:0] if_predecode_instr1, if_predecode_instr2, - output logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target1, if_pred_target2, + output logic [XLEN-1:0] if_instr1, if_instr2, if_pred_target, output logic [XLEN-3:0] if_pc, - output logic [PHT_ADDRESS-1:0] if_pht_index1, if_pht_index2, + output logic [PHT_ADDRESS-1:0] if_pht_index, output logic [RAS_ADDRESS-1:0] if_sp_snap, output logic [2*XLEN-1:0] if_ras_snap, output logic [GHR_SIZE-1:0] if_prev_ghr @@ -34,15 +34,11 @@ module IF_Stage #( else if(!stall_frontend) begin if_valid1 <= (!flush && pd_valid1); if_valid2 <= (!flush && pd_valid2); - if_pred_taken1 <= pd_pred_taken1; - if_pred_taken2 <= pd_pred_taken2; - if_btb_hit1 <= pd_btb_hit1; - if_btb_hit2 <= pd_btb_hit2; + if_pred_taken <= pd_pred_taken; + if_btb_hit <= pd_btb_hit; if_pc <= instr1_addr; - if_pred_target1 <= pd_pred_target1; - if_pred_target2 <= pd_pred_target2; - if_pht_index1 <= pd_pht_index1; - if_pht_index2 <= pd_pht_index2; + if_pred_target <= pd_pred_target; + if_pht_index <= pd_pht_index; if_sp_snap <= pd_sp_snap; if_ras_snap <= pd_ras_snap; if_prev_ghr <= pd_prev_ghr; diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 7e97716..34d9142 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -12,6 +12,7 @@ module PD_Stage #( input logic [PHT_ADDRESS-1:0] rb_pht_index, input logic [RAS_ADDRESS-1:0] rb_sp_snap, input logic [2*XLEN-1:0] rb_ras_snap, + output logic pd_pred_taken, pd_btb_hit, pd_valid1, pd_valid2, output logic [XLEN-1:0] pd_pc, pd_pred_target, output logic [PHT_ADDRESS-1:0] pd_pht_index, From 0e3449122d9eeeab02bd8599d030b15ad664a606 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Tue, 30 Jun 2026 15:06:47 +0500 Subject: [PATCH 07/11] renamed mispredict to flush for consistency --- Design/PC.sv | 4 ++-- Design/PD_Stage.sv | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Design/PC.sv b/Design/PC.sv index fe2f1c3..9355087 100644 --- a/Design/PC.sv +++ b/Design/PC.sv @@ -2,7 +2,7 @@ module PC #( parameter XLEN = 32 )( - input logic CLK, reset, mispredict, stall_frontend, is_return_instr, btb_hit, + input logic CLK, reset, flush, stall_frontend, is_return_instr, btb_hit, input logic [XLEN-1:0] ras_target_address, btb_target_address, ex_actual_target_address, output logic [XLEN-1:0] next_pc ); @@ -11,7 +11,7 @@ module PC #( if (reset) begin next_pc <= 0; end - else if (mispredict) begin + else if (flush) begin next_pc <= ex_actual_target_address; //from EX stage(actual target address) end else if (is_return_instr) begin diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 34d9142..ae70ee3 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -5,14 +5,14 @@ module PD_Stage #( parameter RAS_ADDRESS = 3 )( input logic CLK, reset, stall_frontend, ex_actual_taken, restore_ghr, restore_ras, update_pht, - input logic ex_is_jalr, ex_is_ret, ex_is_branch, mispredict, //mispredict = flush(from ex) + input logic ex_is_jalr, ex_is_ret, ex_is_branch, flush, //flush = flush(from ex) input logic [1:0] if_predecode_instr1, if_predecode_instr2, input logic [XLEN-1:0] ex_actual_target_address, if_target_address, if_pc, ex_pc, input logic [GHR_SIZE-1:0] ghr_snap, input logic [PHT_ADDRESS-1:0] rb_pht_index, input logic [RAS_ADDRESS-1:0] rb_sp_snap, input logic [2*XLEN-1:0] rb_ras_snap, - + output logic pd_pred_taken, pd_btb_hit, pd_valid1, pd_valid2, output logic [XLEN-1:0] pd_pc, pd_pred_target, output logic [PHT_ADDRESS-1:0] pd_pht_index, @@ -44,8 +44,8 @@ module PD_Stage #( pd_valid2 <= 0; end else if (!stall_frontend) begin - pd_valid1 <= !mispredict; - pd_valid2 <= !mispredict && squash_instruction; + pd_valid1 <= !flush; + pd_valid2 <= !flush && squash_instruction; pd_pht_index <= pht_index; pd_prev_ghr <= prev_ghr; end @@ -68,7 +68,7 @@ module PD_Stage #( //inputs .CLK (CLK), .reset (reset), - .mispredict (mispredict), + .flush (flush), .stall_frontend (stall_frontend), .ras_target_address (pred_return_address), .btb_target_address (pred_target_address), From 6d46a010769b123be9f2a1bb4c403a4ffd6badf9 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Thu, 2 Jul 2026 13:52:04 +0500 Subject: [PATCH 08/11] removed unnecessary pins and added is_branch signal to prediction stage --- Design/BIQ.sv | 74 +++++++++++++++------------------------------- Design/BTB.sv | 15 ++++++---- Design/ID_Stage.sv | 29 ++++++------------ Design/PC.sv | 4 +-- Design/PD_Stage.sv | 7 +++-- 5 files changed, 50 insertions(+), 79 deletions(-) diff --git a/Design/BIQ.sv b/Design/BIQ.sv index 172b4dd..f943054 100644 --- a/Design/BIQ.sv +++ b/Design/BIQ.sv @@ -5,15 +5,15 @@ module BIQ #( parameter GHR_SIZE = 9, parameter RAS_ADDRESS = 3 ) ( - input logic CLK, reset, biq_dealloc, flush, pred_valid1, pred_valid2, biq_alloc1, biq_alloc2, pred_taken1, pred_taken2, - input logic [BIQ_ADDRESS:0] biq_id, // biq id(5 bits) + slot id (1bit)=6 - input logic [XLEN-1:0] pred_target1, pred_target2, - input logic [PHT_ADDRESS-1:0] pht_index1, pht_index2, + input logic CLK, reset, biq_dealloc, flush, biq_alloc, pred_taken, + input logic [XLEN-1:0] pred_target, + input logic [PHT_ADDRESS-1:0] pht_index, input logic [GHR_SIZE-1:0] prev_ghr, input logic [RAS_ADDRESS-1:0] sp_snap, input logic [2*XLEN-1:0] ras_snap, + + output logic biq_pred_taken, stall_frontend, output logic [BIQ_ADDRESS-1:0] biq_address, //without slot id cuz 2 slots combined - output logic biq_valid, biq_pred_taken, stall_frontend, output logic [XLEN-1:0] biq_pred_target, output logic [GHR_SIZE-1:0] biq_restore_ghr, output logic [RAS_ADDRESS-1:0] biq_sp_snap, @@ -22,22 +22,15 @@ module BIQ #( ); typedef struct packed { - logic predicted_valid; logic predicted_taken; logic [XLEN-1:0] predicted_target; logic [PHT_ADDRESS-1:0] pht_table_index; - } biq_bank_organization; - - typedef struct packed { logic [GHR_SIZE-1:0] previous_ghr; logic [2*XLEN-1:0] ras_snapshot; logic [RAS_ADDRESS-1:0] sp_snapshot; - } biq_shared_organization; - - (* ram_style = "distributed" *) biq_bank_organization BIQ_BANK0 [0:(1< Date: Thu, 2 Jul 2026 15:43:38 +0500 Subject: [PATCH 09/11] removed unnecessary signals from biq and decode stage --- Design/BIQ.sv | 7 ++++--- Design/ID_Stage.sv | 32 ++++++++++++++++---------------- Design/PD_Stage.sv | 2 +- 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/Design/BIQ.sv b/Design/BIQ.sv index f943054..5c04c9d 100644 --- a/Design/BIQ.sv +++ b/Design/BIQ.sv @@ -7,13 +7,14 @@ module BIQ #( ) ( input logic CLK, reset, biq_dealloc, flush, biq_alloc, pred_taken, input logic [XLEN-1:0] pred_target, + input logic [BIQ_ADDRESS-1:0] biq_id, input logic [PHT_ADDRESS-1:0] pht_index, input logic [GHR_SIZE-1:0] prev_ghr, input logic [RAS_ADDRESS-1:0] sp_snap, input logic [2*XLEN-1:0] ras_snap, output logic biq_pred_taken, stall_frontend, - output logic [BIQ_ADDRESS-1:0] biq_address, //without slot id cuz 2 slots combined + output logic [BIQ_ADDRESS-1:0] biq_address, output logic [XLEN-1:0] biq_pred_target, output logic [GHR_SIZE-1:0] biq_restore_ghr, output logic [RAS_ADDRESS-1:0] biq_sp_snap, @@ -35,7 +36,7 @@ module BIQ #( logic [BIQ_ADDRESS:0] biq_head_ptr, biq_tail_ptr; logic biq_full; - assign biq_read_address = biq_id[BIQ_ADDRESS:1]; + assign biq_read_address = biq_id; assign biq_full = (biq_head_ptr[BIQ_ADDRESS-1:0] == biq_tail_ptr[BIQ_ADDRESS-1:0]) && (biq_head_ptr[BIQ_ADDRESS]!= biq_tail_ptr[BIQ_ADDRESS]); assign biq_address = biq_tail_ptr[BIQ_ADDRESS-1:0]; assign stall_frontend = biq_full; @@ -52,7 +53,7 @@ module BIQ #( if (biq_dealloc) begin biq_head_ptr <= biq_head_ptr + 1; end - if(!biq_full && biq_alloc) begin + if ((!biq_full || biq_dealloc) && biq_alloc) begin BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].predicted_taken <= pred_taken; BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].predicted_target <= pred_target; BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].pht_table_index <= pht_index; diff --git a/Design/ID_Stage.sv b/Design/ID_Stage.sv index d424d07..dc84934 100644 --- a/Design/ID_Stage.sv +++ b/Design/ID_Stage.sv @@ -1,11 +1,11 @@ module ID_Stage #( - parameter OPCODE_SIZE = 7, - parameter PHT_ADDRESS = 9, - parameter GHR_SIZE = 9, - parameter XLEN = 32, - parameter RAS_ADDRESS = 3, - parameter INIT_IMMEDIATE_SIZE = 21, - parameter BIQ_ADDRESS = 5 + parameter OPCODE_SIZE = 7, + parameter PHT_ADDRESS = 9, + parameter GHR_SIZE = 9, + parameter XLEN = 32, + parameter RAS_ADDRESS = 3, + parameter INIT_IMMEDIATE_SIZE = 21, + parameter BIQ_ADDRESS = 5 ) ( input logic CLK, reset, flush, rr_slot_id, dis_biq_dealloc, if_pred_taken, input logic if_valid1, if_valid2, if_btb_hit, @@ -41,16 +41,17 @@ module ID_Stage #( logic [6:0] funct7_1, funct7_2; logic [2:0] ALUOp_1, ALUOp_2; logic [INIT_IMMEDIATE_SIZE-1:0] imm_out1, imm_out2; - logic is_control_flow_instr, pred_valid1, pred_valid2; + logic is_control_flow_instr; logic JumpReg_1, JumpReg_2, Jump_1, Jump_2, Branch_1, Branch_2, RegSrc1_1, RegSrc2_1, RegSrc1_2, RegSrc2_2; logic RetAddr_1, UpperImm_1, UpperImm_2, RegWrite_1, RegWrite_2, MemWrite_1, MemWrite_2, MemToReg_1; logic MemToReg_2, RetAddr_2, Imm_1, Imm_2, imm_type1, imm_type2; assign opcode_1 = if_instr1[OPCODE_SIZE-1:0]; assign opcode_2 = if_instr2[OPCODE_SIZE-1:0]; - assign is_control_flow_instr1 = (Branch_1 || Jump_1 || Branch_2 || Jump_2) && if_valid1 && !stall_frontend; - assign pred_valid1 = (is_control_flow_instr1 && if_btb_hit); - assign pred_valid2 = (is_control_flow_instr2 && if_btb_hit); + assign is_control_flow_instr = !stall_frontend && + (if_valid1 && (Branch_1 || Jump_1) || + if_valid2 && (Branch_2 || Jump_2)); + always_ff @(posedge CLK) begin if (reset) begin @@ -61,7 +62,7 @@ module ID_Stage #( else if (!stall_frontend) begin id_valid1 <= (!flush && if_valid1); id_valid2 <= (!flush && if_valid2); - id_take_snap <= (is_control_flow_instr1 || is_control_flow_instr2); + id_take_snap <= is_control_flow_instr; id_pc <= if_pc; id_funct3_1 <= if_instr1[14:12]; @@ -160,10 +161,10 @@ module ID_Stage #( .flush (flush), // from dispatch stage .biq_dealloc (dis_biq_dealloc), + //from register read stage + .biq_id (rr_biq_id), //Allocation - .biq_alloc (is_control_flow_instr) - .pred_valid1 (pred_valid1), - .pred_valid2 (pred_valid2), + .biq_alloc (is_control_flow_instr), .pred_taken (if_pred_taken), .pred_target (if_pred_target), .pht_index (if_pht_index), @@ -175,7 +176,6 @@ module ID_Stage #( .biq_address (id_biq_address), .stall_frontend (stall_frontend), //signal generated instantly // Outputs (to Execute for Verification) - .biq_valid (id_biq_valid), .biq_pred_taken (id_biq_pred_taken), .biq_pred_target (id_biq_pred_target), //for prediction stage diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 92b6268..3c69430 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -23,7 +23,7 @@ module PD_Stage #( logic [GHR_SIZE-1:0] ghr_out, prev_ghr; logic [PHT_ADDRESS-1:0] pht_index; - logic pred_taken, btb_hit, is_return_instr, squash_instruction; + logic pred_taken, btb_hit,btb_is_branch, is_return_instr, squash_instruction; logic [XLEN-1:0] pred_return_address, pred_target_address; logic [RAS_ADDRESS-1:0] sp_snap; logic [2*XLEN-1:0] ras_snap; From 20b25829132ff8fb01b7e57fcab6d1b17182a6c7 Mon Sep 17 00:00:00 2001 From: Mutahir Date: Thu, 2 Jul 2026 20:44:32 +0500 Subject: [PATCH 10/11] removed obj_dir and updated ports of datapath.sv --- Design/PD_Stage.sv | 4 +- Design/RMT.sv | 1 + Design/RN_Stage.sv | 14 +- Design/main_datapath.sv | 164 ++- Design/tb_main_datapath.sv | 3 +- Design/waveform.vcd | 2251 ------------------------------------ 6 files changed, 116 insertions(+), 2321 deletions(-) delete mode 100644 Design/waveform.vcd diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 3c69430..6833a8a 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -108,8 +108,8 @@ module PD_Stage #( .if_pc (if_pc), .ex_pc (ex_pc), - .ex_target_address (ex_actual_target_address), - .if_target_address (if_target_address), + .ex_target_address (ex_actual_target_address[XLEN-1:2]), // or [31:2] if XLEN isn't a parameter here + .if_target_address (if_target_address[XLEN-1:2]), // or [31:2] //outputs diff --git a/Design/RMT.sv b/Design/RMT.sv index 565c0fa..cf678eb 100644 --- a/Design/RMT.sv +++ b/Design/RMT.sv @@ -8,6 +8,7 @@ module RMT #( input logic [4:0] rd2, rs1_2, rs2_2, input logic [PRF_ADDRESS-1:0] fl_freed_reg1, fl_freed_reg2, cdb_waked_reg1, cdb_waked_reg2, input logic [31:0][PRF_ADDRESS-1:0] bs_rmt_snap, + output logic prs1_busy1, prs2_busy1, prs1_busy2, prs2_busy2, output logic [PRF_ADDRESS-1:0] prd1, prs1_1, prs2_1, old_prd1, output logic [PRF_ADDRESS-1:0] prd2, prs1_2, prs2_2, old_prd2, diff --git a/Design/RN_Stage.sv b/Design/RN_Stage.sv index 67c9883..27f31df 100644 --- a/Design/RN_Stage.sv +++ b/Design/RN_Stage.sv @@ -10,11 +10,12 @@ module RN_Stage #( parameter FL_INDEX_WIDTH = $clog2(FL_ROWS), parameter FL_PTR_WIDTH = FL_INDEX_WIDTH + 1 ) ( - input logic CLK, - input logic reset, - input logic flush, - input logic id_take_snap, id_valid1, id_valid2, + input logic CLK, reset, flush, id_take_snap, id_valid1, id_valid2, input logic cdb_wakeup1, cdb_wakeup2, comm_free_push1, comm_free_push2, ex_branch_resolved, + input logic id_jump_reg1, id_jump_reg2, id_jump1, id_jump2, id_branch1, id_branch2, id_regsrc1_1, + input logic id_immtype1, id_memwrite1, id_immtype2, id_regsrc2_1, + input logic id_regsrc1_2, id_regsrc2_2, id_upperimm1, id_upperimm2, id_regwrite1, id_regwrite2, + input logic id_memwrite2, id_memtoreg1, id_memtoreg2, id_retaddr1, id_retaddr2, id_isimm1, id_isimm2, input logic [PRF_ADDRESS-1:0] cdb_waked_reg1, cdb_waked_reg2, comm_free_reg1, comm_free_reg2, input logic [BTAG_SIZE-1:0] ex_btag, input logic [2:0] id_funct3_1, id_funct3_2, @@ -25,10 +26,7 @@ module RN_Stage #( input logic [BIQ_ADDRESS-1:0] id_biq_address, input logic [XLEN-3:0] id_pc, input logic [2:0] id_alu_op1, id_alu_op2, - input logic id_jump_reg1, id_jump_reg2, id_jump1, id_jump2, id_branch1, id_branch2, id_regsrc1_1, - input logic id_immtype1, id_memwrite1, id_immtype2, id_regsrc2_1, - input logic id_regsrc1_2, id_regsrc2_2, id_upperimm1, id_upperimm2, id_regwrite1, id_regwrite2, - input logic id_memwrite2, id_memtoreg1, id_memtoreg2, id_retaddr1, id_retaddr2, id_isimm1, id_isimm2, + output logic stall_frontend, output logic [PRF_ADDRESS-1:0] rn_prd1, rn_prs1_1, rn_prs2_1, rn_old_prd1, output logic [PRF_ADDRESS-1:0] rn_prd2, rn_prs1_2, rn_prs2_2, rn_old_prd2, diff --git a/Design/main_datapath.sv b/Design/main_datapath.sv index 3fabaaf..3f32ded 100644 --- a/Design/main_datapath.sv +++ b/Design/main_datapath.sv @@ -21,7 +21,7 @@ module main_datapath #( // Backend Predictor Updates (From Execute/Commit) // ----------------------------------------- input logic actual_taken, mispredict, restore_ghr, restore_ras, update_pht, - input logic update_btb, update_ras, ex_is_ret, ex_is_branch, + input logic update_btb, update_ras, ex_is_ret, ex_is_branch, ex_is_jalr, input logic [XLEN-1:0] actual_target_address, ex_pc, input logic [GHR_SIZE-1:0] ghr_snap, input logic [PHT_ADDRESS-1:0] rb_pht_index, @@ -93,7 +93,8 @@ module main_datapath #( // ============================================================================ logic id_stall_frontend, rn_stall_frontend; assign stall_frontend = id_stall_frontend | rn_stall_frontend; - + logic [1:0] if_predecode_instr1, if_predecode_instr2; + logic [XLEN-1:0] if_target_address; logic [XLEN-1:0] spec_return_address; // PD/IF Signals... (Omitted declarations for brevity, assuming they match your previous code) @@ -133,7 +134,7 @@ module main_datapath #( // MODULE INSTANTIATIONS // ============================================================================ - PD_Stage #( + PD_Stage #( .PHT_ADDRESS (9), .GHR_SIZE (9), .XLEN (32), @@ -147,15 +148,16 @@ module main_datapath #( .restore_ghr (restore_ghr), .restore_ras (restore_ras), .update_pht (update_pht), - .ex_is_jalr (/* connect to top-level ex_is_jalr */), + .ex_is_jalr (ex_is_jalr), .ex_is_ret (ex_is_ret), .ex_is_branch (ex_is_branch), - .mispredict (mispredict), - .if_predecode_instr1 (/* connect to top-level if_predecode_instr1 */), - .if_predecode_instr2 (/* connect to top-level if_predecode_instr2 */), - .ex_actual_target_address(actual_target_address), - .if_target_address (/* connect to top-level if_target_address */), - .if_pc (pd_pc), // Assuming pd_pc maps to if_pc, adjust if needed + .flush (mispredict), + .if_predecode_instr1 (if_predecode_instr1), + .if_predecode_instr2 (if_predecode_instr2), + .ex_actual_target_address(actual_target_address), + .if_target_address (if_target_address), + + .if_pc (pd_pc), .ex_pc (ex_pc), .ghr_snap (ghr_snap), .rb_pht_index (rb_pht_index), @@ -163,93 +165,137 @@ module main_datapath #( .rb_ras_snap (rb_ras_snap), // Outputs - .pd_pred_taken (pd_pred_taken1), // Verify if this maps to channel 1 or combined - .pd_btb_hit (pd_btb_hit1), // Verify if this maps to channel 1 or combined + .pd_pred_taken (pd_pred_taken1), + .pd_btb_hit (pd_btb_hit1), .pd_valid1 (pd_valid1), .pd_valid2 (pd_valid2), .pd_pc (pd_pc), - .pd_pred_target (pd_pred_target1), // Verify if this maps to channel 1 or combined - .pd_pht_index (pd_pht_index1), // Verify if this maps to channel 1 or combined + .pd_pred_target (pd_pred_target1), + .pd_pht_index (pd_pht_index1), .pd_sp_snap (pd_sp_snap), .pd_ras_snap (pd_ras_snap), .pd_prev_ghr (pd_prev_ghr) ); - - IF_Stage #( /* ... Parameters ... */ ) if_stage_inst ( + IF_Stage #( + .PHT_ADDRESS (9), + .GHR_SIZE (9), + .XLEN (32), + .RAS_ADDRESS (3) + ) if_stage_inst ( + // Inputs .CLK (CLK), .reset (reset), .flush (flush), - .stall_frontend (stall_frontend), // Uses COMBINED stall .pd_valid1 (pd_valid1), .pd_valid2 (pd_valid2), + .stall_frontend (stall_frontend), // Uses COMBINED stall + .pd_pred_taken (pd_pred_taken1), // Collapsed from channels 1 & 2 + .pd_btb_hit (pd_btb_hit1), // Collapsed from channels 1 & 2 .pd_pc (pd_pc), - .pd_pred_taken1 (pd_pred_taken1), - .pd_pred_taken2 (pd_pred_taken2), - .pd_btb_hit1 (pd_btb_hit1), - .pd_btb_hit2 (pd_btb_hit2), - .pd_pred_target1 (pd_pred_target1), - .pd_pred_target2 (pd_pred_target2), - .pd_pht_index1 (pd_pht_index1), - .pd_pht_index2 (pd_pht_index2), + .pd_pred_target (pd_pred_target1), // Collapsed from channels 1 & 2 + .pd_pht_index (pd_pht_index1), // Collapsed from channels 1 & 2 .pd_sp_snap (pd_sp_snap), .pd_ras_snap (pd_ras_snap), .pd_prev_ghr (pd_prev_ghr), + + // Outputs + .if_pred_taken (if_pred_taken1), // Collapsed from channels 1 & 2 + .if_btb_hit (if_btb_hit1), // Collapsed from channels 1 & 2 .if_valid1 (if_valid1), .if_valid2 (if_valid2), - .if_pc (if_pc), + .if_predecode_instr1 (if_predecode_instr1), // NEW port + .if_predecode_instr2 (if_predecode_instr2), // NEW port .if_instr1 (if_instr1), .if_instr2 (if_instr2), - .if_pred_taken1 (if_pred_taken1), - .if_pred_taken2 (if_pred_taken2), - .if_btb_hit1 (if_btb_hit1), - .if_btb_hit2 (if_btb_hit2), - .if_pred_target1 (if_pred_target1), - .if_pred_target2 (if_pred_target2), - .if_pht_index1 (if_pht_index1), - .if_pht_index2 (if_pht_index2), + .if_pred_target (if_pred_target1), // Collapsed from channels 1 & 2 + .if_pc (if_pc), // Note: internal width changed to [XLEN-3:0] + .if_pht_index (if_pht_index1), // Collapsed from channels 1 & 2 .if_sp_snap (if_sp_snap), .if_ras_snap (if_ras_snap), .if_prev_ghr (if_prev_ghr) ); - ID_Stage #( /* ... Parameters ... */ ) id_stage_inst ( + ID_Stage #( + .OPCODE_SIZE (7), + .PHT_ADDRESS (9), + .GHR_SIZE (9), + .XLEN (32), + .RAS_ADDRESS (3), + .INIT_IMMEDIATE_SIZE (21), + .BIQ_ADDRESS (5) + ) id_stage_inst ( + // Inputs .CLK (CLK), .reset (reset), .flush (flush), + .rr_slot_id (rr_slot_id), + .dis_biq_dealloc (dis_biq_dealloc), + .if_pred_taken (if_pred_taken1), // Collapsed from channels 1 & 2 .if_valid1 (if_valid1), .if_valid2 (if_valid2), + .if_btb_hit (if_btb_hit1), // Collapsed from channels 1 & 2 .if_instr1 (if_instr1), .if_instr2 (if_instr2), - .if_pc (if_pc), - .if_pred_taken1 (if_pred_taken1), - .if_pred_taken2 (if_pred_taken2), - .if_btb_hit1 (if_btb_hit1), - .if_btb_hit2 (if_btb_hit2), - .if_pred_target1 (if_pred_target1), - .if_pred_target2 (if_pred_target2), - .if_pht_index1 (if_pht_index1), - .if_pht_index2 (if_pht_index2), + .if_pred_target (if_pred_target1), // Collapsed from channels 1 & 2 + .if_pc (if_pc), // Note: internal width changed to [XLEN-3:0] + .rr_biq_id (rr_biq_id), + .if_pht_index (if_pht_index1), // Collapsed from channels 1 & 2 .if_sp_snap (if_sp_snap), .if_ras_snap (if_ras_snap), .if_prev_ghr (if_prev_ghr), - .dis_biq_dealloc (dis_biq_dealloc), - .rr_biq_id (rr_biq_id), - .rr_slot_id (rr_slot_id), - .stall_frontend (id_stall_frontend), // Dedicated ID stall + + // Outputs + .id_biq_sp_snap (id_biq_sp_snap), + .id_biq_ras_snap (id_biq_ras_snap), + .stall_frontend (id_stall_frontend), // Dedicated ID stall mapped to output .id_take_snap (id_take_snap), .id_valid1 (id_valid1), .id_valid2 (id_valid2), - .id_pc (id_pc), - .id_funct3_1 (id_funct3_1), .id_funct7_1(id_funct7_1), .id_rs1_1(id_rs1_1), .id_rs2_1(id_rs2_1), .id_rd_1(id_rd_1), - .id_immout1 (id_immout1), .id_alu_op1(id_alu_op1), .id_jump_reg1(id_jump_reg1), .id_jump1(id_jump1), .id_branch1(id_branch1), - .id_regsrc1_1 (id_regsrc1_1), .id_regsrc2_1(id_regsrc2_1), .id_immtype1(id_immtype1), .id_memwrite1(id_memwrite1), .id_regwrite1(id_regwrite1), - .id_memtoreg1 (id_memtoreg1), .id_retaddr1(id_retaddr1), .id_isimm1(id_isimm1), .id_upperimm1(id_upperimm1), - .id_funct3_2 (id_funct3_2), .id_funct7_2(id_funct7_2), .id_rs1_2(id_rs1_2), .id_rs2_2(id_rs2_2), .id_rd_2(id_rd_2), - .id_immout2 (id_immout2), .id_alu_op2(id_alu_op2), .id_jump_reg2(id_jump_reg2), .id_jump2(id_jump2), .id_branch2(id_branch2), - .id_regsrc1_2 (id_regsrc1_2), .id_regsrc2_2(id_regsrc2_2), .id_immtype2(id_immtype2), .id_memwrite2(id_memwrite2), .id_regwrite2(id_regwrite2), - .id_memtoreg2 (id_memtoreg2), .id_retaddr2(id_retaddr2), .id_isimm2(id_isimm2), .id_upperimm2(id_upperimm2), - .id_biq_address (id_biq_address), .id_biq_valid(id_biq_valid), .id_biq_pred_taken(id_biq_pred_taken), .id_biq_pred_target(id_biq_pred_target), - .id_biq_pht_index (id_biq_pht_index), .id_biq_restore_ghr(id_biq_restore_ghr), .id_biq_sp_snap(id_biq_sp_snap), .id_biq_ras_snap(id_biq_ras_snap) + .id_funct3_1 (id_funct3_1), + .id_funct3_2 (id_funct3_2), + .id_funct7_1 (id_funct7_1), + .id_funct7_2 (id_funct7_2), + .id_rs1_1 (id_rs1_1), + .id_rs2_1 (id_rs2_1), + .id_rd_1 (id_rd_1), + .id_rs1_2 (id_rs1_2), + .id_rs2_2 (id_rs2_2), + .id_rd_2 (id_rd_2), + .id_immout1 (id_immout1), + .id_immout2 (id_immout2), + .id_biq_address (id_biq_address), + .id_biq_pred_target (id_biq_pred_target), + .id_pc (id_pc), // Note: internal width changed to [XLEN-3:0] + .id_biq_restore_ghr (id_biq_restore_ghr), + .id_biq_pht_index (id_biq_pht_index), + .id_alu_op1 (id_alu_op1), + .id_alu_op2 (id_alu_op2), + .id_jump_reg1 (id_jump_reg1), + .id_jump_reg2 (id_jump_reg2), + .id_jump1 (id_jump1), + .id_jump2 (id_jump2), + .id_branch1 (id_branch1), + .id_branch2 (id_branch2), + .id_regsrc1_1 (id_regsrc1_1), + .id_immtype1 (id_immtype1), + .id_memwrite1 (id_memwrite1), + .id_immtype2 (id_immtype2), + .id_biq_valid (id_biq_valid), + .id_biq_pred_taken (id_biq_pred_taken), + .id_regsrc2_1 (id_regsrc2_1), + .id_regsrc1_2 (id_regsrc1_2), + .id_regsrc2_2 (id_regsrc2_2), + .id_upperimm1 (id_upperimm1), + .id_upperimm2 (id_upperimm2), + .id_regwrite1 (id_regwrite1), + .id_regwrite2 (id_regwrite2), + .id_memwrite2 (id_memwrite2), + .id_memtoreg1 (id_memtoreg1), + .id_memtoreg2 (id_memtoreg2), + .id_retaddr1 (id_retaddr1), + .id_retaddr2 (id_retaddr2), + .id_isimm1 (id_isimm1), + .id_isimm2 (id_isimm2) ); RN_Stage #( diff --git a/Design/tb_main_datapath.sv b/Design/tb_main_datapath.sv index c71b8f6..91b2911 100644 --- a/Design/tb_main_datapath.sv +++ b/Design/tb_main_datapath.sv @@ -19,7 +19,7 @@ module tb_main_datapath(); // Backend Predictor Updates logic actual_taken, mispredict, restore_ghr, restore_ras, update_pht; - logic update_btb, update_ras, ex_is_ret, ex_is_branch; + logic update_btb, update_ras, ex_is_ret, ex_is_branch, ex_is_jalr; logic [XLEN-1:0] actual_target_address, ex_pc; logic [GHR_SIZE-1:0] ghr_snap; logic [PHT_ADDRESS-1:0] rb_pht_index; @@ -86,6 +86,7 @@ module tb_main_datapath(); // Zero-out Execution/Backend Feedbacks actual_taken = 0; mispredict = 0; restore_ghr = 0; restore_ras = 0; update_pht = 0; update_btb = 0; update_ras = 0; ex_is_ret = 0; ex_is_branch = 0; + ex_is_jalr = 0; actual_target_address = '0; ex_pc = '0; ghr_snap = '0; rb_pht_index = '0; rb_sp_snap = '0; rb_ras_snap = '0; diff --git a/Design/waveform.vcd b/Design/waveform.vcd deleted file mode 100644 index e5a188c..0000000 --- a/Design/waveform.vcd +++ /dev/null @@ -1,2251 +0,0 @@ -$version Generated by VerilatedVcd $end -$timescale 1ps $end - $scope module TOP $end - $scope module tb_main_datapath $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 N& BIQ_ADDRESS [31:0] $end - $var wire 32 O& PRF_ADDRESS [31:0] $end - $var wire 32 P& MAX_BRANCHES [31:0] $end - $var wire 32 Q& BTAG_SIZE [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 % actual_taken $end - $var wire 1 & mispredict $end - $var wire 1 ' restore_ghr $end - $var wire 1 ( restore_ras $end - $var wire 1 ) update_pht $end - $var wire 1 * update_btb $end - $var wire 1 + update_ras $end - $var wire 1 , ex_is_ret $end - $var wire 1 - ex_is_branch $end - $var wire 32 . actual_target_address [31:0] $end - $var wire 32 / ex_pc [31:0] $end - $var wire 9 0 ghr_snap [8:0] $end - $var wire 9 1 rb_pht_index [8:0] $end - $var wire 3 2 rb_sp_snap [2:0] $end - $var wire 64 3 rb_ras_snap [63:0] $end - $var wire 1 5 dis_biq_dealloc $end - $var wire 5 6 rr_biq_id [4:0] $end - $var wire 1 7 rr_slot_id $end - $var wire 1 8 cdb_wakeup1 $end - $var wire 1 9 cdb_wakeup2 $end - $var wire 1 : comm_free_push1 $end - $var wire 1 ; comm_free_push2 $end - $var wire 1 < ex_branch_resolved $end - $var wire 6 = cdb_waked_reg1 [5:0] $end - $var wire 6 > cdb_waked_reg2 [5:0] $end - $var wire 6 ? comm_free_reg1 [5:0] $end - $var wire 6 @ comm_free_reg2 [5:0] $end - $var wire 2 A ex_btag [1:0] $end - $var wire 1 s stall_frontend $end - $var wire 6 t rn_prd1 [5:0] $end - $var wire 6 u rn_prs1_1 [5:0] $end - $var wire 6 v rn_prs2_1 [5:0] $end - $var wire 6 w rn_old_prd1 [5:0] $end - $var wire 6 x rn_prd2 [5:0] $end - $var wire 6 y rn_prs1_2 [5:0] $end - $var wire 6 z rn_prs2_2 [5:0] $end - $var wire 6 { rn_old_prd2 [5:0] $end - $var wire 1 | rn_prs1_busy1 $end - $var wire 1 } rn_prs2_busy1 $end - $var wire 1 ~ rn_prs1_busy2 $end - $var wire 1 !! rn_prs2_busy2 $end - $var wire 2 "! rn_branch_tag [1:0] $end - $var wire 4 #! rn_branch_mask [3:0] $end - $var wire 5 $! rn_biq_address [4:0] $end - $var wire 30 %! rn_pc [29:0] $end - $var wire 1 &! rn_valid1 $end - $var wire 1 '! rn_valid2 $end - $var wire 3 (! rn_funct3_1 [2:0] $end - $var wire 3 )! rn_alu_op1 [2:0] $end - $var wire 3 *! rn_funct3_2 [2:0] $end - $var wire 3 +! rn_alu_op2 [2:0] $end - $var wire 7 ,! rn_funct7_1 [6:0] $end - $var wire 7 -! rn_funct7_2 [6:0] $end - $var wire 21 .! rn_immout1 [20:0] $end - $var wire 21 /! rn_immout2 [20:0] $end - $var wire 1 0! rn_jump_reg1 $end - $var wire 1 1! rn_jump1 $end - $var wire 1 2! rn_branch1 $end - $var wire 1 3! rn_regsrc1_1 $end - $var wire 1 4! rn_regsrc2_1 $end - $var wire 1 5! rn_immtype1 $end - $var wire 1 6! rn_isimm1 $end - $var wire 1 7! rn_retaddr1 $end - $var wire 1 8! rn_upperimm1 $end - $var wire 1 9! rn_regwrite1 $end - $var wire 1 :! rn_memwrite1 $end - $var wire 1 ;! rn_memtoreg1 $end - $var wire 1 ! rn_branch2 $end - $var wire 1 ?! rn_regsrc1_2 $end - $var wire 1 @! rn_regsrc2_2 $end - $var wire 1 A! rn_immtype2 $end - $var wire 1 B! rn_isimm2 $end - $var wire 1 C! rn_retaddr2 $end - $var wire 1 D! rn_upperimm2 $end - $var wire 1 E! rn_regwrite2 $end - $var wire 1 F! rn_memwrite2 $end - $var wire 1 G! rn_memtoreg2 $end - $var wire 1 H! id_biq_valid $end - $var wire 1 I! id_biq_pred_taken $end - $var wire 32 J! id_biq_pred_target [31:0] $end - $var wire 9 K! id_biq_pht_index [8:0] $end - $var wire 9 L! id_biq_restore_ghr [8:0] $end - $var wire 3 M! id_biq_sp_snap [2:0] $end - $var wire 64 N! id_biq_ras_snap [63:0] $end - $scope module dut $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 N& BIQ_ADDRESS [31:0] $end - $var wire 32 O& PRF_ADDRESS [31:0] $end - $var wire 32 P& MAX_BRANCHES [31:0] $end - $var wire 32 Q& BTAG_SIZE [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 % actual_taken $end - $var wire 1 & mispredict $end - $var wire 1 ' restore_ghr $end - $var wire 1 ( restore_ras $end - $var wire 1 ) update_pht $end - $var wire 1 * update_btb $end - $var wire 1 + update_ras $end - $var wire 1 , ex_is_ret $end - $var wire 1 - ex_is_branch $end - $var wire 32 . actual_target_address [31:0] $end - $var wire 32 / ex_pc [31:0] $end - $var wire 9 0 ghr_snap [8:0] $end - $var wire 9 1 rb_pht_index [8:0] $end - $var wire 3 2 rb_sp_snap [2:0] $end - $var wire 64 3 rb_ras_snap [63:0] $end - $var wire 1 5 dis_biq_dealloc $end - $var wire 5 6 rr_biq_id [4:0] $end - $var wire 1 7 rr_slot_id $end - $var wire 1 8 cdb_wakeup1 $end - $var wire 1 9 cdb_wakeup2 $end - $var wire 1 : comm_free_push1 $end - $var wire 1 ; comm_free_push2 $end - $var wire 1 < ex_branch_resolved $end - $var wire 6 = cdb_waked_reg1 [5:0] $end - $var wire 6 > cdb_waked_reg2 [5:0] $end - $var wire 6 ? comm_free_reg1 [5:0] $end - $var wire 6 @ comm_free_reg2 [5:0] $end - $var wire 2 A ex_btag [1:0] $end - $var wire 1 s stall_frontend $end - $var wire 6 t rn_prd1 [5:0] $end - $var wire 6 u rn_prs1_1 [5:0] $end - $var wire 6 v rn_prs2_1 [5:0] $end - $var wire 6 w rn_old_prd1 [5:0] $end - $var wire 6 x rn_prd2 [5:0] $end - $var wire 6 y rn_prs1_2 [5:0] $end - $var wire 6 z rn_prs2_2 [5:0] $end - $var wire 6 { rn_old_prd2 [5:0] $end - $var wire 1 | rn_prs1_busy1 $end - $var wire 1 } rn_prs2_busy1 $end - $var wire 1 ~ rn_prs1_busy2 $end - $var wire 1 !! rn_prs2_busy2 $end - $var wire 2 "! rn_branch_tag [1:0] $end - $var wire 4 #! rn_branch_mask [3:0] $end - $var wire 1 &! rn_valid1 $end - $var wire 1 0! rn_jump_reg1 $end - $var wire 1 1! rn_jump1 $end - $var wire 1 2! rn_branch1 $end - $var wire 1 3! rn_regsrc1_1 $end - $var wire 1 4! rn_regsrc2_1 $end - $var wire 1 5! rn_immtype1 $end - $var wire 1 6! rn_isimm1 $end - $var wire 1 7! rn_retaddr1 $end - $var wire 1 8! rn_upperimm1 $end - $var wire 1 9! rn_regwrite1 $end - $var wire 1 :! rn_memwrite1 $end - $var wire 1 ;! rn_memtoreg1 $end - $var wire 3 (! rn_funct3_1 [2:0] $end - $var wire 3 )! rn_alu_op1 [2:0] $end - $var wire 7 ,! rn_funct7_1 [6:0] $end - $var wire 21 .! rn_immout1 [20:0] $end - $var wire 1 '! rn_valid2 $end - $var wire 1 ! rn_branch2 $end - $var wire 1 ?! rn_regsrc1_2 $end - $var wire 1 @! rn_regsrc2_2 $end - $var wire 1 A! rn_immtype2 $end - $var wire 1 B! rn_isimm2 $end - $var wire 1 C! rn_retaddr2 $end - $var wire 1 D! rn_upperimm2 $end - $var wire 1 E! rn_regwrite2 $end - $var wire 1 F! rn_memwrite2 $end - $var wire 1 G! rn_memtoreg2 $end - $var wire 3 *! rn_funct3_2 [2:0] $end - $var wire 3 +! rn_alu_op2 [2:0] $end - $var wire 7 -! rn_funct7_2 [6:0] $end - $var wire 21 /! rn_immout2 [20:0] $end - $var wire 5 $! rn_biq_address [4:0] $end - $var wire 30 %! rn_pc [29:0] $end - $var wire 1 H! id_biq_valid $end - $var wire 1 I! id_biq_pred_taken $end - $var wire 32 J! id_biq_pred_target [31:0] $end - $var wire 9 K! id_biq_pht_index [8:0] $end - $var wire 9 L! id_biq_restore_ghr [8:0] $end - $var wire 3 M! id_biq_sp_snap [2:0] $end - $var wire 64 N! id_biq_ras_snap [63:0] $end - $var wire 1 P! id_stall_frontend $end - $var wire 1 Q! rn_stall_frontend $end - $var wire 32 R! spec_return_address [31:0] $end - $var wire 1 S! pd_valid1 $end - $var wire 1 T! pd_valid2 $end - $var wire 32 D pd_pc [31:0] $end - $var wire 32 U! pd_pred_target1 [31:0] $end - $var wire 32 V! pd_pred_target2 [31:0] $end - $var wire 1 W! pd_pred_taken1 $end - $var wire 1 X! pd_pred_taken2 $end - $var wire 1 Y! pd_btb_hit1 $end - $var wire 1 Z! pd_btb_hit2 $end - $var wire 9 [! pd_pht_index1 [8:0] $end - $var wire 9 \! pd_pht_index2 [8:0] $end - $var wire 3 ]! pd_sp_snap [2:0] $end - $var wire 64 ^! pd_ras_snap [63:0] $end - $var wire 9 `! pd_prev_ghr [8:0] $end - $var wire 1 a! if_valid1 $end - $var wire 1 b! if_valid2 $end - $var wire 30 c! if_pc [29:0] $end - $var wire 32 d! if_instr1 [31:0] $end - $var wire 32 e! if_instr2 [31:0] $end - $var wire 32 f! if_pred_target1 [31:0] $end - $var wire 32 g! if_pred_target2 [31:0] $end - $var wire 1 h! if_pred_taken1 $end - $var wire 1 i! if_pred_taken2 $end - $var wire 1 j! if_btb_hit1 $end - $var wire 1 k! if_btb_hit2 $end - $var wire 9 l! if_pht_index1 [8:0] $end - $var wire 9 m! if_pht_index2 [8:0] $end - $var wire 3 n! if_sp_snap [2:0] $end - $var wire 64 o! if_ras_snap [63:0] $end - $var wire 9 q! if_prev_ghr [8:0] $end - $var wire 1 r! id_take_snap $end - $var wire 1 s! id_valid1 $end - $var wire 1 t! id_valid2 $end - $var wire 30 u! id_pc [29:0] $end - $var wire 5 v! id_biq_address [4:0] $end - $var wire 3 w! id_funct3_1 [2:0] $end - $var wire 3 x! id_alu_op1 [2:0] $end - $var wire 7 y! id_funct7_1 [6:0] $end - $var wire 5 z! id_rs1_1 [4:0] $end - $var wire 5 {! id_rs2_1 [4:0] $end - $var wire 5 |! id_rd_1 [4:0] $end - $var wire 1 }! id_jump_reg1 $end - $var wire 1 ~! id_jump1 $end - $var wire 1 !" id_branch1 $end - $var wire 1 "" id_regsrc1_1 $end - $var wire 1 #" id_regsrc2_1 $end - $var wire 1 $" id_immtype1 $end - $var wire 1 %" id_memwrite1 $end - $var wire 1 &" id_regwrite1 $end - $var wire 1 '" id_memtoreg1 $end - $var wire 1 (" id_retaddr1 $end - $var wire 1 )" id_isimm1 $end - $var wire 1 *" id_upperimm1 $end - $var wire 21 +" id_immout1 [20:0] $end - $var wire 3 ," id_funct3_2 [2:0] $end - $var wire 3 -" id_alu_op2 [2:0] $end - $var wire 7 ." id_funct7_2 [6:0] $end - $var wire 5 /" id_rs1_2 [4:0] $end - $var wire 5 0" id_rs2_2 [4:0] $end - $var wire 5 1" id_rd_2 [4:0] $end - $var wire 1 2" id_jump_reg2 $end - $var wire 1 3" id_jump2 $end - $var wire 1 4" id_branch2 $end - $var wire 1 5" id_regsrc1_2 $end - $var wire 1 6" id_regsrc2_2 $end - $var wire 1 7" id_immtype2 $end - $var wire 1 8" id_memwrite2 $end - $var wire 1 9" id_regwrite2 $end - $var wire 1 :" id_memtoreg2 $end - $var wire 1 ;" id_retaddr2 $end - $var wire 1 <" id_isimm2 $end - $var wire 1 =" id_upperimm2 $end - $var wire 21 >" id_immout2 [20:0] $end - $scope module id_stage_inst $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 N& BIQ_ADDRESS [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 7 rr_slot_id $end - $var wire 1 5 dis_biq_dealloc $end - $var wire 1 h! if_pred_taken1 $end - $var wire 1 i! if_pred_taken2 $end - $var wire 1 a! if_valid1 $end - $var wire 1 b! if_valid2 $end - $var wire 1 j! if_btb_hit1 $end - $var wire 1 k! if_btb_hit2 $end - $var wire 32 d! if_instr1 [31:0] $end - $var wire 32 e! if_instr2 [31:0] $end - $var wire 32 f! if_pred_target1 [31:0] $end - $var wire 32 g! if_pred_target2 [31:0] $end - $var wire 30 c! if_pc [29:0] $end - $var wire 5 6 rr_biq_id [4:0] $end - $var wire 9 l! if_pht_index1 [8:0] $end - $var wire 9 m! if_pht_index2 [8:0] $end - $var wire 3 n! if_sp_snap [2:0] $end - $var wire 64 o! if_ras_snap [63:0] $end - $var wire 9 q! if_prev_ghr [8:0] $end - $var wire 3 M! id_biq_sp_snap [2:0] $end - $var wire 64 N! id_biq_ras_snap [63:0] $end - $var wire 1 P! stall_frontend $end - $var wire 1 r! id_take_snap $end - $var wire 1 s! id_valid1 $end - $var wire 1 t! id_valid2 $end - $var wire 3 w! id_funct3_1 [2:0] $end - $var wire 3 ," id_funct3_2 [2:0] $end - $var wire 7 y! id_funct7_1 [6:0] $end - $var wire 7 ." id_funct7_2 [6:0] $end - $var wire 5 z! id_rs1_1 [4:0] $end - $var wire 5 {! id_rs2_1 [4:0] $end - $var wire 5 |! id_rd_1 [4:0] $end - $var wire 5 /" id_rs1_2 [4:0] $end - $var wire 5 0" id_rs2_2 [4:0] $end - $var wire 5 1" id_rd_2 [4:0] $end - $var wire 21 +" id_immout1 [20:0] $end - $var wire 21 >" id_immout2 [20:0] $end - $var wire 5 v! id_biq_address [4:0] $end - $var wire 32 J! id_biq_pred_target [31:0] $end - $var wire 30 u! id_pc [29:0] $end - $var wire 9 L! id_biq_restore_ghr [8:0] $end - $var wire 9 K! id_biq_pht_index [8:0] $end - $var wire 3 x! id_alu_op1 [2:0] $end - $var wire 3 -" id_alu_op2 [2:0] $end - $var wire 1 }! id_jump_reg1 $end - $var wire 1 2" id_jump_reg2 $end - $var wire 1 ~! id_jump1 $end - $var wire 1 3" id_jump2 $end - $var wire 1 !" id_branch1 $end - $var wire 1 4" id_branch2 $end - $var wire 1 "" id_regsrc1_1 $end - $var wire 1 $" id_immtype1 $end - $var wire 1 %" id_memwrite1 $end - $var wire 1 7" id_immtype2 $end - $var wire 1 H! id_biq_valid $end - $var wire 1 I! id_biq_pred_taken $end - $var wire 1 #" id_regsrc2_1 $end - $var wire 1 5" id_regsrc1_2 $end - $var wire 1 6" id_regsrc2_2 $end - $var wire 1 *" id_upperimm1 $end - $var wire 1 =" id_upperimm2 $end - $var wire 1 &" id_regwrite1 $end - $var wire 1 9" id_regwrite2 $end - $var wire 1 8" id_memwrite2 $end - $var wire 1 '" id_memtoreg1 $end - $var wire 1 :" id_memtoreg2 $end - $var wire 1 (" id_retaddr1 $end - $var wire 1 ;" id_retaddr2 $end - $var wire 1 )" id_isimm1 $end - $var wire 1 <" id_isimm2 $end - $var wire 7 ?" opcode_1 [6:0] $end - $var wire 7 @" opcode_2 [6:0] $end - $var wire 3 R& funct3_1 [2:0] $end - $var wire 3 S& funct3_2 [2:0] $end - $var wire 7 T& funct7_1 [6:0] $end - $var wire 7 U& funct7_2 [6:0] $end - $var wire 3 A" ALUOp_1 [2:0] $end - $var wire 3 B" ALUOp_2 [2:0] $end - $var wire 21 C" imm_out1 [20:0] $end - $var wire 21 D" imm_out2 [20:0] $end - $var wire 1 E" is_control_flow_instr1 $end - $var wire 1 F" is_control_flow_instr2 $end - $var wire 1 G" pred_valid1 $end - $var wire 1 H" pred_valid2 $end - $var wire 1 I" JumpReg_1 $end - $var wire 1 J" JumpReg_2 $end - $var wire 1 K" Jump_1 $end - $var wire 1 L" Jump_2 $end - $var wire 1 M" Branch_1 $end - $var wire 1 N" Branch_2 $end - $var wire 1 O" RegSrc1_1 $end - $var wire 1 P" RegSrc2_1 $end - $var wire 1 Q" RegSrc1_2 $end - $var wire 1 R" RegSrc2_2 $end - $var wire 1 S" RetAddr_1 $end - $var wire 1 T" UpperImm_1 $end - $var wire 1 U" UpperImm_2 $end - $var wire 1 V" RegWrite_1 $end - $var wire 1 W" RegWrite_2 $end - $var wire 1 X" MemWrite_1 $end - $var wire 1 Y" MemWrite_2 $end - $var wire 1 Z" MemToReg_1 $end - $var wire 1 [" MemToReg_2 $end - $var wire 1 \" RetAddr_2 $end - $var wire 1 ]" Imm_1 $end - $var wire 1 ^" Imm_2 $end - $var wire 1 _" imm_type1 $end - $var wire 1 `" imm_type2 $end - $scope module biq_instantiation $end - $var wire 32 N& BIQ_ADDRESS [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 5 biq_dealloc $end - $var wire 1 $ flush $end - $var wire 1 G" pred_valid1 $end - $var wire 1 H" pred_valid2 $end - $var wire 1 E" biq_alloc1 $end - $var wire 1 F" biq_alloc2 $end - $var wire 1 h! pred_taken1 $end - $var wire 1 i! pred_taken2 $end - $var wire 6 C& biq_id [5:0] $end - $var wire 32 f! pred_target1 [31:0] $end - $var wire 32 g! pred_target2 [31:0] $end - $var wire 9 l! pht_index1 [8:0] $end - $var wire 9 m! pht_index2 [8:0] $end - $var wire 9 q! prev_ghr [8:0] $end - $var wire 3 n! sp_snap [2:0] $end - $var wire 64 o! ras_snap [63:0] $end - $var wire 5 v! biq_address [4:0] $end - $var wire 1 H! biq_valid $end - $var wire 1 I! biq_pred_taken $end - $var wire 1 P! stall_frontend $end - $var wire 32 J! biq_pred_target [31:0] $end - $var wire 9 L! biq_restore_ghr [8:0] $end - $var wire 3 M! biq_sp_snap [2:0] $end - $var wire 64 N! biq_ras_snap [63:0] $end - $var wire 9 K! biq_pht_index [8:0] $end - $var wire 43 a" BIQ_BANK0[0] [42:0] $end - $var wire 43 c" BIQ_BANK0[1] [42:0] $end - $var wire 43 e" BIQ_BANK0[2] [42:0] $end - $var wire 43 g" BIQ_BANK0[3] [42:0] $end - $var wire 43 i" BIQ_BANK0[4] [42:0] $end - $var wire 43 k" BIQ_BANK0[5] [42:0] $end - $var wire 43 m" BIQ_BANK0[6] [42:0] $end - $var wire 43 o" BIQ_BANK0[7] [42:0] $end - $var wire 43 q" BIQ_BANK0[8] [42:0] $end - $var wire 43 s" BIQ_BANK0[9] [42:0] $end - $var wire 43 u" BIQ_BANK0[10] [42:0] $end - $var wire 43 w" BIQ_BANK0[11] [42:0] $end - $var wire 43 y" BIQ_BANK0[12] [42:0] $end - $var wire 43 {" BIQ_BANK0[13] [42:0] $end - $var wire 43 }" BIQ_BANK0[14] [42:0] $end - $var wire 43 !# BIQ_BANK0[15] [42:0] $end - $var wire 43 ## BIQ_BANK0[16] [42:0] $end - $var wire 43 %# BIQ_BANK0[17] [42:0] $end - $var wire 43 '# BIQ_BANK0[18] [42:0] $end - $var wire 43 )# BIQ_BANK0[19] [42:0] $end - $var wire 43 +# BIQ_BANK0[20] [42:0] $end - $var wire 43 -# BIQ_BANK0[21] [42:0] $end - $var wire 43 /# BIQ_BANK0[22] [42:0] $end - $var wire 43 1# BIQ_BANK0[23] [42:0] $end - $var wire 43 3# BIQ_BANK0[24] [42:0] $end - $var wire 43 5# BIQ_BANK0[25] [42:0] $end - $var wire 43 7# BIQ_BANK0[26] [42:0] $end - $var wire 43 9# BIQ_BANK0[27] [42:0] $end - $var wire 43 ;# BIQ_BANK0[28] [42:0] $end - $var wire 43 =# BIQ_BANK0[29] [42:0] $end - $var wire 43 ?# BIQ_BANK0[30] [42:0] $end - $var wire 43 A# BIQ_BANK0[31] [42:0] $end - $var wire 43 C# BIQ_BANK1[0] [42:0] $end - $var wire 43 E# BIQ_BANK1[1] [42:0] $end - $var wire 43 G# BIQ_BANK1[2] [42:0] $end - $var wire 43 I# BIQ_BANK1[3] [42:0] $end - $var wire 43 K# BIQ_BANK1[4] [42:0] $end - $var wire 43 M# BIQ_BANK1[5] [42:0] $end - $var wire 43 O# BIQ_BANK1[6] [42:0] $end - $var wire 43 Q# BIQ_BANK1[7] [42:0] $end - $var wire 43 S# BIQ_BANK1[8] [42:0] $end - $var wire 43 U# BIQ_BANK1[9] [42:0] $end - $var wire 43 W# BIQ_BANK1[10] [42:0] $end - $var wire 43 Y# BIQ_BANK1[11] [42:0] $end - $var wire 43 [# BIQ_BANK1[12] [42:0] $end - $var wire 43 ]# BIQ_BANK1[13] [42:0] $end - $var wire 43 _# BIQ_BANK1[14] [42:0] $end - $var wire 43 a# BIQ_BANK1[15] [42:0] $end - $var wire 43 c# BIQ_BANK1[16] [42:0] $end - $var wire 43 e# BIQ_BANK1[17] [42:0] $end - $var wire 43 g# BIQ_BANK1[18] [42:0] $end - $var wire 43 i# BIQ_BANK1[19] [42:0] $end - $var wire 43 k# BIQ_BANK1[20] [42:0] $end - $var wire 43 m# BIQ_BANK1[21] [42:0] $end - $var wire 43 o# BIQ_BANK1[22] [42:0] $end - $var wire 43 q# BIQ_BANK1[23] [42:0] $end - $var wire 43 s# BIQ_BANK1[24] [42:0] $end - $var wire 43 u# BIQ_BANK1[25] [42:0] $end - $var wire 43 w# BIQ_BANK1[26] [42:0] $end - $var wire 43 y# BIQ_BANK1[27] [42:0] $end - $var wire 43 {# BIQ_BANK1[28] [42:0] $end - $var wire 43 }# BIQ_BANK1[29] [42:0] $end - $var wire 43 !$ BIQ_BANK1[30] [42:0] $end - $var wire 43 #$ BIQ_BANK1[31] [42:0] $end - $var wire 76 %$ BIQ_SHARED[0] [75:0] $end - $var wire 76 ($ BIQ_SHARED[1] [75:0] $end - $var wire 76 +$ BIQ_SHARED[2] [75:0] $end - $var wire 76 .$ BIQ_SHARED[3] [75:0] $end - $var wire 76 1$ BIQ_SHARED[4] [75:0] $end - $var wire 76 4$ BIQ_SHARED[5] [75:0] $end - $var wire 76 7$ BIQ_SHARED[6] [75:0] $end - $var wire 76 :$ BIQ_SHARED[7] [75:0] $end - $var wire 76 =$ BIQ_SHARED[8] [75:0] $end - $var wire 76 @$ BIQ_SHARED[9] [75:0] $end - $var wire 76 C$ BIQ_SHARED[10] [75:0] $end - $var wire 76 F$ BIQ_SHARED[11] [75:0] $end - $var wire 76 I$ BIQ_SHARED[12] [75:0] $end - $var wire 76 L$ BIQ_SHARED[13] [75:0] $end - $var wire 76 O$ BIQ_SHARED[14] [75:0] $end - $var wire 76 R$ BIQ_SHARED[15] [75:0] $end - $var wire 76 U$ BIQ_SHARED[16] [75:0] $end - $var wire 76 X$ BIQ_SHARED[17] [75:0] $end - $var wire 76 [$ BIQ_SHARED[18] [75:0] $end - $var wire 76 ^$ BIQ_SHARED[19] [75:0] $end - $var wire 76 a$ BIQ_SHARED[20] [75:0] $end - $var wire 76 d$ BIQ_SHARED[21] [75:0] $end - $var wire 76 g$ BIQ_SHARED[22] [75:0] $end - $var wire 76 j$ BIQ_SHARED[23] [75:0] $end - $var wire 76 m$ BIQ_SHARED[24] [75:0] $end - $var wire 76 p$ BIQ_SHARED[25] [75:0] $end - $var wire 76 s$ BIQ_SHARED[26] [75:0] $end - $var wire 76 v$ BIQ_SHARED[27] [75:0] $end - $var wire 76 y$ BIQ_SHARED[28] [75:0] $end - $var wire 76 |$ BIQ_SHARED[29] [75:0] $end - $var wire 76 !% BIQ_SHARED[30] [75:0] $end - $var wire 76 $% BIQ_SHARED[31] [75:0] $end - $var wire 5 6 biq_read_address [4:0] $end - $var wire 6 '% biq_head_ptr [5:0] $end - $var wire 6 (% biq_tail_ptr [5:0] $end - $var wire 1 P! biq_full $end - $upscope $end - $scope module cu_instantiation1 $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 7 ?" opcode [6:0] $end - $var wire 3 A" ALUOp [2:0] $end - $var wire 1 I" JumpReg $end - $var wire 1 K" Jump $end - $var wire 1 M" Branch $end - $var wire 1 O" RegSrc1 $end - $var wire 1 P" RegSrc2 $end - $var wire 1 T" UpperImm $end - $var wire 1 V" RegWrite $end - $var wire 1 X" MemWrite $end - $var wire 1 Z" MemToReg $end - $var wire 1 S" RetAddr $end - $var wire 1 ]" imm $end - $upscope $end - $scope module cu_instantiation2 $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 7 @" opcode [6:0] $end - $var wire 3 B" ALUOp [2:0] $end - $var wire 1 J" JumpReg $end - $var wire 1 L" Jump $end - $var wire 1 N" Branch $end - $var wire 1 Q" RegSrc1 $end - $var wire 1 R" RegSrc2 $end - $var wire 1 U" UpperImm $end - $var wire 1 W" RegWrite $end - $var wire 1 Y" MemWrite $end - $var wire 1 [" MemToReg $end - $var wire 1 \" RetAddr $end - $var wire 1 ^" imm $end - $upscope $end - $scope module ig_instantiation1 $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 d! instruction [31:0] $end - $var wire 21 C" immediate_output [20:0] $end - $var wire 1 _" imm_type $end - $var wire 7 )% opcode [6:0] $end - $upscope $end - $scope module ig_instantiation2 $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 J& OPCODE_SIZE [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 e! instruction [31:0] $end - $var wire 21 D" immediate_output [20:0] $end - $var wire 1 `" imm_type $end - $var wire 7 *% opcode [6:0] $end - $upscope $end - $upscope $end - $scope module if_stage_inst $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 S! pd_valid1 $end - $var wire 1 T! pd_valid2 $end - $var wire 1 s stall_frontend $end - $var wire 1 W! pd_pred_taken1 $end - $var wire 1 X! pd_pred_taken2 $end - $var wire 1 Y! pd_btb_hit1 $end - $var wire 1 Z! pd_btb_hit2 $end - $var wire 32 D pd_pc [31:0] $end - $var wire 32 U! pd_pred_target1 [31:0] $end - $var wire 32 V! pd_pred_target2 [31:0] $end - $var wire 9 [! pd_pht_index1 [8:0] $end - $var wire 9 \! pd_pht_index2 [8:0] $end - $var wire 3 ]! pd_sp_snap [2:0] $end - $var wire 64 ^! pd_ras_snap [63:0] $end - $var wire 9 `! pd_prev_ghr [8:0] $end - $var wire 1 h! if_pred_taken1 $end - $var wire 1 i! if_pred_taken2 $end - $var wire 1 j! if_btb_hit1 $end - $var wire 1 k! if_btb_hit2 $end - $var wire 1 a! if_valid1 $end - $var wire 1 b! if_valid2 $end - $var wire 32 d! if_instr1 [31:0] $end - $var wire 32 e! if_instr2 [31:0] $end - $var wire 32 f! if_pred_target1 [31:0] $end - $var wire 32 g! if_pred_target2 [31:0] $end - $var wire 30 c! if_pc [29:0] $end - $var wire 9 l! if_pht_index1 [8:0] $end - $var wire 9 m! if_pht_index2 [8:0] $end - $var wire 3 n! if_sp_snap [2:0] $end - $var wire 64 o! if_ras_snap [63:0] $end - $var wire 9 q! if_prev_ghr [8:0] $end - $var wire 30 E instr1_addr [29:0] $end - $var wire 30 F instr2_addr [29:0] $end - $scope module im_instantiation $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 V& MEM_ROWS [31:0] $end - $var wire 1 B& CLK $end - $var wire 32 G instr1_addr [31:0] $end - $var wire 32 H instr2_addr [31:0] $end - $var wire 32 d! instr_1 [31:0] $end - $var wire 32 e! instr_2 [31:0] $end - $upscope $end - $upscope $end - $scope module pd_stage_inst $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 s stall_frontend $end - $var wire 1 % actual_taken $end - $var wire 1 ' restore_ghr $end - $var wire 1 ( restore_ras $end - $var wire 1 ) update_pht $end - $var wire 1 * update_btb $end - $var wire 1 + update_ras $end - $var wire 1 , ex_is_ret $end - $var wire 1 - ex_is_branch $end - $var wire 1 & mispredict $end - $var wire 32 . actual_target_address [31:0] $end - $var wire 32 R! actual_return_address [31:0] $end - $var wire 32 / ex_pc [31:0] $end - $var wire 9 0 ghr_snap [8:0] $end - $var wire 9 1 rb_pht_index [8:0] $end - $var wire 3 2 rb_sp_snap [2:0] $end - $var wire 64 3 rb_ras_snap [63:0] $end - $var wire 1 W! pd_pred_taken1 $end - $var wire 1 X! pd_pred_taken2 $end - $var wire 1 Y! pd_btb_hit1 $end - $var wire 1 Z! pd_btb_hit2 $end - $var wire 1 S! pd_valid1 $end - $var wire 1 T! pd_valid2 $end - $var wire 32 D pd_pc [31:0] $end - $var wire 32 U! pd_pred_target1 [31:0] $end - $var wire 32 V! pd_pred_target2 [31:0] $end - $var wire 9 [! pd_pht_index1 [8:0] $end - $var wire 9 \! pd_pht_index2 [8:0] $end - $var wire 3 ]! pd_sp_snap [2:0] $end - $var wire 64 ^! pd_ras_snap [63:0] $end - $var wire 9 `! pd_prev_ghr [8:0] $end - $var wire 9 +% ghr_out [8:0] $end - $var wire 9 +% prev_ghr [8:0] $end - $var wire 9 I pht_index1 [8:0] $end - $var wire 9 J pht_index2 [8:0] $end - $var wire 32 K final_pred_target1 [31:0] $end - $var wire 32 L final_pred_target2 [31:0] $end - $var wire 32 ,% pc [31:0] $end - $var wire 1 W! pred_taken1 $end - $var wire 1 X! pred_taken2 $end - $var wire 1 Y! btb_hit1 $end - $var wire 1 Z! btb_hit2 $end - $var wire 1 -% is_branch1 $end - $var wire 1 .% is_branch2 $end - $var wire 1 /% is_ret1 $end - $var wire 1 0% is_ret2 $end - $var wire 32 1% pred_target1 [31:0] $end - $var wire 32 2% pred_target2 [31:0] $end - $var wire 32 M pred_return_address [31:0] $end - $var wire 3 ]! sp_snap [2:0] $end - $var wire 64 ^! ras_snap [63:0] $end - $var wire 32 N write_pc_data [31:0] $end - $var wire 32 O next_pc [31:0] $end - $var wire 32 D pc1 [31:0] $end - $var wire 32 P pc2 [31:0] $end - $scope module btb_instantiation $end - $var wire 32 O& BTB_ADDRESS [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 W& TAG_SIZE [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 * update_btb $end - $var wire 1 , ex_is_ret $end - $var wire 1 - ex_is_branch $end - $var wire 32 D pc1 [31:0] $end - $var wire 32 P pc2 [31:0] $end - $var wire 32 / ex_pc [31:0] $end - $var wire 32 . actual_target_address [31:0] $end - $var wire 1 Y! btb_hit1 $end - $var wire 1 Z! btb_hit2 $end - $var wire 1 /% is_ret1 $end - $var wire 1 0% is_ret2 $end - $var wire 1 -% is_branch1 $end - $var wire 1 .% is_branch2 $end - $var wire 32 1% pred_target1 [31:0] $end - $var wire 32 2% pred_target2 [31:0] $end - $var wire 59 3% btb_entry1 [58:0] $end - $var wire 59 5% btb_entry2 [58:0] $end - $var wire 1 7% tag_matched1 $end - $var wire 1 8% tag_matched2 $end - $var wire 24 Q btb_tag1 [23:0] $end - $var wire 24 R btb_tag2 [23:0] $end - $var wire 24 9% reg_btb_tag1 [23:0] $end - $var wire 24 :% reg_btb_tag2 [23:0] $end - $var wire 6 S btb_index1 [5:0] $end - $var wire 6 T btb_index2 [5:0] $end - $var wire 24 B ex_tag [23:0] $end - $var wire 6 C ex_btb_index [5:0] $end - $upscope $end - $scope module ghr_instantiation $end - $var wire 32 K& GHR_SIZE [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 s stall_frontend $end - $var wire 1 ' restore_ghr $end - $var wire 1 % actual_taken $end - $var wire 1 W! pred_taken1 $end - $var wire 1 X! pred_taken2 $end - $var wire 1 -% pred_branch1 $end - $var wire 1 .% pred_branch2 $end - $var wire 9 0 ghr_snap [8:0] $end - $var wire 9 +% ghr_out [8:0] $end - $var wire 9 +% prev_ghr [8:0] $end - $var wire 1 ;% pred_taken $end - $upscope $end - $scope module pc_instantiation $end - $var wire 32 I& XLEN [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 s stall_frontend $end - $var wire 1 & mispredict $end - $var wire 1 Y! btb_hit1 $end - $var wire 1 Z! btb_hit2 $end - $var wire 1 /% is_ret1 $end - $var wire 1 0% is_ret2 $end - $var wire 1 -% is_branch1 $end - $var wire 1 .% is_branch2 $end - $var wire 1 W! pred_taken1 $end - $var wire 1 X! pred_taken2 $end - $var wire 32 1% pred_target1 [31:0] $end - $var wire 32 2% pred_target2 [31:0] $end - $var wire 32 M ret_addr1 [31:0] $end - $var wire 32 M ret_addr2 [31:0] $end - $var wire 32 . actual_target_address [31:0] $end - $var wire 32 ,% pc [31:0] $end - $var wire 32 N write_pc_data [31:0] $end - $var wire 32 O next_pc [31:0] $end - $var wire 32 K final_pred_target1 [31:0] $end - $var wire 32 L final_pred_target2 [31:0] $end - $var wire 1 <% is_branch_or_jump1 $end - $var wire 1 =% is_branch_or_jump2 $end - $upscope $end - $scope module pht_instantiation $end - $var wire 32 K& PHT_ADDRESS [31:0] $end - $var wire 32 Q& COUNTER_SIZE [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 % actual_taken $end - $var wire 1 ) update_pht $end - $var wire 9 I pht_index1 [8:0] $end - $var wire 9 J pht_index2 [8:0] $end - $var wire 9 1 rb_pht_index [8:0] $end - $var wire 1 W! pred_taken1 $end - $var wire 1 X! pred_taken2 $end - $upscope $end - $scope module ras_instantiation $end - $var wire 32 L& RAS_ADDRESS [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 X& RAS_LEN [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 s stall_frontend $end - $var wire 1 + update_ras $end - $var wire 1 ( restore_ras $end - $var wire 1 /% btb_is_ret1 $end - $var wire 1 0% btb_is_ret2 $end - $var wire 32 R! actual_return_address [31:0] $end - $var wire 3 2 rb_sp_snap [2:0] $end - $var wire 64 3 rb_ras_snap [63:0] $end - $var wire 32 M pred_return_address [31:0] $end - $var wire 3 ]! sp_snap [2:0] $end - $var wire 64 ^! ras_snap [63:0] $end - $var wire 32 >% RAS[0] [31:0] $end - $var wire 32 ?% RAS[1] [31:0] $end - $var wire 32 @% RAS[2] [31:0] $end - $var wire 32 A% RAS[3] [31:0] $end - $var wire 32 B% RAS[4] [31:0] $end - $var wire 32 C% RAS[5] [31:0] $end - $var wire 32 D% RAS[6] [31:0] $end - $var wire 32 E% RAS[7] [31:0] $end - $var wire 3 F% sp [2:0] $end - $var wire 3 U next_sp [2:0] $end - $var wire 1 G% pop $end - $var wire 1 + push $end - $upscope $end - $upscope $end - $scope module rn_stage_inst $end - $var wire 32 O& PRF_ADDRESS [31:0] $end - $var wire 32 M& INIT_IMMEDIATE_SIZE [31:0] $end - $var wire 32 P& MAX_BRANCHES [31:0] $end - $var wire 32 Q& BTAG_SIZE [31:0] $end - $var wire 32 N& BIQ_ADDRESS [31:0] $end - $var wire 32 I& XLEN [31:0] $end - $var wire 32 Y& NUM_PHY_REG [31:0] $end - $var wire 32 I& FL_ROWS [31:0] $end - $var wire 32 N& FL_INDEX_WIDTH [31:0] $end - $var wire 32 O& FL_PTR_WIDTH [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 r! id_take_snap $end - $var wire 1 s! id_valid1 $end - $var wire 1 t! id_valid2 $end - $var wire 1 8 cdb_wakeup1 $end - $var wire 1 9 cdb_wakeup2 $end - $var wire 1 : comm_free_push1 $end - $var wire 1 ; comm_free_push2 $end - $var wire 1 < ex_branch_resolved $end - $var wire 6 = cdb_waked_reg1 [5:0] $end - $var wire 6 > cdb_waked_reg2 [5:0] $end - $var wire 6 ? comm_free_reg1 [5:0] $end - $var wire 6 @ comm_free_reg2 [5:0] $end - $var wire 2 A ex_btag [1:0] $end - $var wire 3 w! id_funct3_1 [2:0] $end - $var wire 3 ," id_funct3_2 [2:0] $end - $var wire 7 y! id_funct7_1 [6:0] $end - $var wire 7 ." id_funct7_2 [6:0] $end - $var wire 5 z! id_rs1_1 [4:0] $end - $var wire 5 {! id_rs2_1 [4:0] $end - $var wire 5 |! id_rd_1 [4:0] $end - $var wire 5 /" id_rs1_2 [4:0] $end - $var wire 5 0" id_rs2_2 [4:0] $end - $var wire 5 1" id_rd_2 [4:0] $end - $var wire 21 +" id_immout1 [20:0] $end - $var wire 21 >" id_immout2 [20:0] $end - $var wire 5 v! id_biq_address [4:0] $end - $var wire 30 u! id_pc [29:0] $end - $var wire 3 x! id_alu_op1 [2:0] $end - $var wire 3 -" id_alu_op2 [2:0] $end - $var wire 1 }! id_jump_reg1 $end - $var wire 1 2" id_jump_reg2 $end - $var wire 1 ~! id_jump1 $end - $var wire 1 3" id_jump2 $end - $var wire 1 !" id_branch1 $end - $var wire 1 4" id_branch2 $end - $var wire 1 "" id_regsrc1_1 $end - $var wire 1 $" id_immtype1 $end - $var wire 1 %" id_memwrite1 $end - $var wire 1 7" id_immtype2 $end - $var wire 1 #" id_regsrc2_1 $end - $var wire 1 5" id_regsrc1_2 $end - $var wire 1 6" id_regsrc2_2 $end - $var wire 1 *" id_upperimm1 $end - $var wire 1 =" id_upperimm2 $end - $var wire 1 &" id_regwrite1 $end - $var wire 1 9" id_regwrite2 $end - $var wire 1 8" id_memwrite2 $end - $var wire 1 '" id_memtoreg1 $end - $var wire 1 :" id_memtoreg2 $end - $var wire 1 (" id_retaddr1 $end - $var wire 1 ;" id_retaddr2 $end - $var wire 1 )" id_isimm1 $end - $var wire 1 <" id_isimm2 $end - $var wire 1 Q! stall_frontend $end - $var wire 6 t rn_prd1 [5:0] $end - $var wire 6 u rn_prs1_1 [5:0] $end - $var wire 6 v rn_prs2_1 [5:0] $end - $var wire 6 w rn_old_prd1 [5:0] $end - $var wire 6 x rn_prd2 [5:0] $end - $var wire 6 y rn_prs1_2 [5:0] $end - $var wire 6 z rn_prs2_2 [5:0] $end - $var wire 6 { rn_old_prd2 [5:0] $end - $var wire 1 | rn_prs1_busy1 $end - $var wire 1 } rn_prs2_busy1 $end - $var wire 1 ~ rn_prs1_busy2 $end - $var wire 1 !! rn_prs2_busy2 $end - $var wire 2 "! rn_branch_tag [1:0] $end - $var wire 4 #! rn_branch_mask [3:0] $end - $var wire 5 $! rn_biq_address [4:0] $end - $var wire 30 %! rn_pc [29:0] $end - $var wire 3 (! rn_funct3_1 [2:0] $end - $var wire 3 *! rn_funct3_2 [2:0] $end - $var wire 7 ,! rn_funct7_1 [6:0] $end - $var wire 7 -! rn_funct7_2 [6:0] $end - $var wire 21 .! rn_immout1 [20:0] $end - $var wire 21 /! rn_immout2 [20:0] $end - $var wire 3 )! rn_alu_op1 [2:0] $end - $var wire 3 +! rn_alu_op2 [2:0] $end - $var wire 1 &! rn_valid1 $end - $var wire 1 0! rn_jump_reg1 $end - $var wire 1 1! rn_jump1 $end - $var wire 1 2! rn_branch1 $end - $var wire 1 3! rn_regsrc1_1 $end - $var wire 1 4! rn_regsrc2_1 $end - $var wire 1 5! rn_immtype1 $end - $var wire 1 6! rn_isimm1 $end - $var wire 1 7! rn_retaddr1 $end - $var wire 1 8! rn_upperimm1 $end - $var wire 1 9! rn_regwrite1 $end - $var wire 1 :! rn_memwrite1 $end - $var wire 1 ;! rn_memtoreg1 $end - $var wire 1 '! rn_valid2 $end - $var wire 1 ! rn_branch2 $end - $var wire 1 ?! rn_regsrc1_2 $end - $var wire 1 @! rn_regsrc2_2 $end - $var wire 1 A! rn_immtype2 $end - $var wire 1 B! rn_isimm2 $end - $var wire 1 C! rn_retaddr2 $end - $var wire 1 D! rn_upperimm2 $end - $var wire 1 E! rn_regwrite2 $end - $var wire 1 F! rn_memwrite2 $end - $var wire 1 G! rn_memtoreg2 $end - $var wire 6 H% fl_freed_reg1 [5:0] $end - $var wire 6 I% fl_freed_reg2 [5:0] $end - $var wire 192 V rmt_snap [191:0] $end - $var wire 192 \ bs_rmt_snap [191:0] $end - $var wire 6 b fl_head_ptr [5:0] $end - $var wire 6 c bs_head_ptr_snap [5:0] $end - $var wire 6 H% routed_freed_reg1 [5:0] $end - $var wire 6 J% routed_freed_reg2 [5:0] $end - $var wire 1 K% pop1 $end - $var wire 1 L% pop2 $end - $var wire 1 M% bs_full $end - $var wire 1 N% fl_empty $end - $scope module bs_instantiation $end - $var wire 32 O& PRF_ADDRESS [31:0] $end - $var wire 32 Y& NUM_PHY_REG [31:0] $end - $var wire 32 P& MAX_BRANCHES [31:0] $end - $var wire 32 Q& BTAG_SIZE [31:0] $end - $var wire 32 I& FL_ROWS [31:0] $end - $var wire 32 N& FL_INDEX_WIDTH [31:0] $end - $var wire 32 O& FL_PTR_WIDTH [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 d id_take_snap $end - $var wire 1 < ex_branch_resolved $end - $var wire 1 O% pop1 $end - $var wire 1 P% pop2 $end - $var wire 1 !" id_branch1 $end - $var wire 1 ~! id_jump1 $end - $var wire 1 s! id_valid1 $end - $var wire 2 A ex_btag [1:0] $end - $var wire 192 V rmt_snap [191:0] $end - $var wire 6 b freelist_head_snap [5:0] $end - $var wire 1 M% bs_full $end - $var wire 192 \ bs_rmt_snap [191:0] $end - $var wire 6 c bs_freelist_head_snap [5:0] $end - $var wire 2 "! bs_branch_tag [1:0] $end - $var wire 4 #! bs_branch_mask [3:0] $end - $var wire 202 Q% BS[0] [201:0] $end - $var wire 202 X% BS[1] [201:0] $end - $var wire 202 _% BS[2] [201:0] $end - $var wire 202 f% BS[3] [201:0] $end - $var wire 4 m% BMR [3:0] $end - $var wire 2 n% current_btag [1:0] $end - $scope module unnamedblk1 $end - $var wire 32 o% i [31:0] $end - $upscope $end - $scope module unnamedblk2 $end - $var wire 32 p% i [31:0] $end - $upscope $end - $upscope $end - $scope module fl_instantiation $end - $var wire 32 O& PRF_ADDRESS [31:0] $end - $var wire 32 Y& NUM_PHY_REG [31:0] $end - $var wire 32 I& FL_ROWS [31:0] $end - $var wire 32 N& FL_INDEX_WIDTH [31:0] $end - $var wire 32 O& FL_PTR_WIDTH [31:0] $end - $var wire 1 B& CLK $end - $var wire 1 # reset $end - $var wire 1 $ flush $end - $var wire 1 Q! stall_frontend $end - $var wire 1 : push1 $end - $var wire 1 ; push2 $end - $var wire 1 K% pop1 $end - $var wire 1 L% pop2 $end - $var wire 1 !" id_branch1 $end - $var wire 1 ~! id_jump1 $end - $var wire 1 s! id_valid1 $end - $var wire 6 ? comm_free_reg1 [5:0] $end - $var wire 6 @ comm_free_reg2 [5:0] $end - $var wire 6 c bs_head_ptr_snap [5:0] $end - $var wire 6 H% fl_freed_reg1 [5:0] $end - $var wire 6 I% fl_freed_reg2 [5:0] $end - $var wire 6 b fl_head_ptr [5:0] $end - $var wire 1 N% fl_empty $end - $var wire 6 q% FL[0] [5:0] $end - $var wire 6 r% FL[1] [5:0] $end - $var wire 6 s% FL[2] [5:0] $end - $var wire 6 t% FL[3] [5:0] $end - $var wire 6 u% FL[4] [5:0] $end - $var wire 6 v% FL[5] [5:0] $end - $var wire 6 w% FL[6] [5:0] $end - $var wire 6 x% FL[7] [5:0] $end - $var wire 6 y% FL[8] [5:0] $end - $var wire 6 z% FL[9] [5:0] $end - $var wire 6 {% FL[10] [5:0] $end - $var wire 6 |% FL[11] [5:0] $end - $var wire 6 }% FL[12] [5:0] $end - $var wire 6 ~% FL[13] [5:0] $end - $var wire 6 !& FL[14] [5:0] $end - $var wire 6 "& FL[15] [5:0] $end - $var wire 6 #& FL[16] [5:0] $end - $var wire 6 $& FL[17] [5:0] $end - $var wire 6 %& FL[18] [5:0] $end - $var wire 6 && FL[19] [5:0] $end - $var wire 6 '& FL[20] [5:0] $end - $var wire 6 (& FL[21] [5:0] $end - $var wire 6 )& FL[22] [5:0] $end - $var wire 6 *& FL[23] [5:0] $end - $var wire 6 +& FL[24] [5:0] $end - $var wire 6 ,& FL[25] [5:0] $end - $var wire 6 -& FL[26] [5:0] $end - $var wire 6 .& FL[27] [5:0] $end - $var wire 6 /& FL[28] [5:0] $end - $var wire 6 0& FL[29] [5:0] $end - $var wire 6 1& FL[30] [5:0] $end - $var wire 6 2& FL[31] [5:0] $end - $var wire 6 3& head [5:0] $end - $var wire 6 e next_head [5:0] $end - $var wire 6 4& tail [5:0] $end - $var wire 1 f valid_pop1 $end - $var wire 1 D& valid_pop2 $end - $var wire 6 5& registers_required [5:0] $end - $scope module unnamedblk1 $end - $var wire 32 6& i [31:0] $end - $upscope $end - $upscope $end - $scope module rmt_instantiation $end - $var wire 32 O& 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-b00000000000000000000000001111100 P -b011110 S -b011111 T -b000000000000000000000000011000 %! -b00000000000000000000000001110000 R! -b000011100 [! -b000011101 \! -b000000000000000000000000011100 c! -b000011010 l! -b000011011 m! -b000000000000000000000000011010 u! -b00000000000000000000000001111000 ,% -1B& -#160 -0B& -#165 -b00000000000000000000000010000000 D -b000000000000000000000000100000 E -b000000000000000000000000100001 F -b00000000000000000000000000100000 G -b00000000000000000000000000100001 H -b000100000 I -b000100001 J -b00000000000000000000000010000000 N -b00000000000000000000000010001000 O -b00000000000000000000000010000100 P -b100000 S -b100001 T -b000000000000000000000000011010 %! -b00000000000000000000000001111000 R! -b000011110 [! -b000011111 \! -b000000000000000000000000011110 c! -b000011100 l! -b000011101 m! -b000000000000000000000000011100 u! -b00000000000000000000000010000000 ,% -1B& -#170 -0B& -#175 -b00000000000000000000000010001000 D -b000000000000000000000000100010 E -b000000000000000000000000100011 F -b00000000000000000000000000100010 G -b00000000000000000000000000100011 H -b000100010 I -b000100011 J -b00000000000000000000000010001000 N -b00000000000000000000000010010000 O -b00000000000000000000000010001100 P -b100010 S -b100011 T -b000000000000000000000000011100 %! -b00000000000000000000000010000000 R! -b000100000 [! -b000100001 \! -b000000000000000000000000100000 c! -b000011110 l! -b000011111 m! -b000000000000000000000000011110 u! -b00000000000000000000000010001000 ,% -1B& -#180 -0B& -#185 -b00000000000000000000000010010000 D -b000000000000000000000000100100 E -b000000000000000000000000100101 F -b00000000000000000000000000100100 G -b00000000000000000000000000100101 H -b000100100 I -b000100101 J -b00000000000000000000000010010000 N -b00000000000000000000000010011000 O -b00000000000000000000000010010100 P -b100100 S -b100101 T -b000000000000000000000000011110 %! -b00000000000000000000000010001000 R! -b000100010 [! -b000100011 \! -b000000000000000000000000100010 c! -b000100000 l! -b000100001 m! -b000000000000000000000000100000 u! -b00000000000000000000000010010000 ,% -1B& -#190 -0B& -#195 -b00000000000000000000000010011000 D -b000000000000000000000000100110 E -b000000000000000000000000100111 F -b00000000000000000000000000100110 G -b00000000000000000000000000100111 H -b000100110 I -b000100111 J -b00000000000000000000000010011000 N -b00000000000000000000000010100000 O -b00000000000000000000000010011100 P -b100110 S -b100111 T -b000000000000000000000000100000 %! -b00000000000000000000000010010000 R! -b000100100 [! -b000100101 \! -b000000000000000000000000100100 c! -b000100010 l! -b000100011 m! -b000000000000000000000000100010 u! -b00000000000000000000000010011000 ,% -1B& From 3d59b559a751fa23dfd0d44f5cf797320b30946f Mon Sep 17 00:00:00 2001 From: Mutahir Date: Fri, 3 Jul 2026 15:48:12 +0500 Subject: [PATCH 11/11] resolved and verified issues of 4 stages --- Design/BIQ.sv | 12 +- Design/BS.sv | 8 +- Design/IF_Stage.sv | 2 +- Design/PC.sv | 2 +- Design/PD_Stage.sv | 17 +- Design/tb_main_datapath.sv | 2 +- Design/waveform.vcd | 2053 ++++++++++++++++++++++++++++++++++++ 7 files changed, 2075 insertions(+), 21 deletions(-) create mode 100644 Design/waveform.vcd diff --git a/Design/BIQ.sv b/Design/BIQ.sv index 5c04c9d..d8c6e69 100644 --- a/Design/BIQ.sv +++ b/Design/BIQ.sv @@ -54,12 +54,12 @@ module BIQ #( biq_head_ptr <= biq_head_ptr + 1; end if ((!biq_full || biq_dealloc) && biq_alloc) begin - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].predicted_taken <= pred_taken; - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].predicted_target <= pred_target; - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].pht_table_index <= pht_index; - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].previous_ghr <= prev_ghr; - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].ras_snapshot <= ras_snap; - BIQ[biq_tail_ptr[BIQ_ADDRESS-1:0]].sp_snapshot <= sp_snap; + BIQ[biq_address].predicted_taken <= pred_taken; + BIQ[biq_address].predicted_target <= pred_target; + BIQ[biq_address].pht_table_index <= pht_index; + BIQ[biq_address].previous_ghr <= prev_ghr; + BIQ[biq_address].ras_snapshot <= ras_snap; + BIQ[biq_address].sp_snapshot <= sp_snap; biq_tail_ptr <= biq_tail_ptr + 1; end end diff --git a/Design/BS.sv b/Design/BS.sv index bc263fc..0299f6c 100644 --- a/Design/BS.sv +++ b/Design/BS.sv @@ -12,6 +12,7 @@ module BS #( input logic [BTAG_SIZE-1:0] ex_btag, input logic [31:0][PRF_ADDRESS-1:0] rmt_snap, input logic [FL_PTR_WIDTH-1:0] freelist_head_snap, + output logic bs_full, output logic [31:0][PRF_ADDRESS-1:0] bs_rmt_snap, output logic [FL_PTR_WIDTH-1:0] bs_freelist_head_snap, @@ -44,12 +45,11 @@ module BS #( assign bs_rmt_snap = BS[ex_btag].rmt_snapshot; assign bs_freelist_head_snap = BS[ex_btag].freelist_head_snapshot; assign bs_full = &BMR; + //to dispatch stage + assign bs_branch_tag = current_btag; + assign bs_branch_mask = BMR; always_ff @(posedge CLK) begin - //to dispatch stage - bs_branch_tag <= current_btag; - bs_branch_mask <= BMR; - if (reset) begin BMR <= '0; end diff --git a/Design/IF_Stage.sv b/Design/IF_Stage.sv index e9a80b9..03ac876 100644 --- a/Design/IF_Stage.sv +++ b/Design/IF_Stage.sv @@ -36,7 +36,7 @@ module IF_Stage #( if_valid2 <= (!flush && pd_valid2); if_pred_taken <= pd_pred_taken; if_btb_hit <= pd_btb_hit; - if_pc <= instr1_addr; + if_pc <= pd_pc[XLEN-1:2]; if_pred_target <= pd_pred_target; if_pht_index <= pd_pht_index; if_sp_snap <= pd_sp_snap; diff --git a/Design/PC.sv b/Design/PC.sv index 6b28615..0e5a5b0 100644 --- a/Design/PC.sv +++ b/Design/PC.sv @@ -9,7 +9,7 @@ module PC #( always_ff @(posedge CLK) begin if (reset) begin - next_pc <= 0; + next_pc <= -8; end else if (flush) begin next_pc <= ex_actual_target_address; //from EX stage(actual target address) diff --git a/Design/PD_Stage.sv b/Design/PD_Stage.sv index 6833a8a..2fec23c 100644 --- a/Design/PD_Stage.sv +++ b/Design/PD_Stage.sv @@ -29,13 +29,7 @@ module PD_Stage #( logic [2*XLEN-1:0] ras_snap; logic [XLEN-1:0] next_pc; - assign pht_index = ghr_out ^ next_pc[PHT_ADDRESS+1:2]; - assign pd_pred_taken = btb_hit && pred_taken && btb_is_branch; - assign pd_pred_target = (is_return_instr)? pred_return_address : pred_target_address; - assign pd_pc = next_pc; - assign pd_btb_hit = btb_hit; - assign pd_sp_snap = sp_snap; - assign pd_ras_snap = ras_snap; + always_ff @(posedge CLK) begin if (reset) begin @@ -44,9 +38,16 @@ module PD_Stage #( end else if (!stall_frontend) begin pd_valid1 <= !flush; - pd_valid2 <= !flush && squash_instruction; + pd_valid2 <= !flush && !squash_instruction; pd_pht_index <= pht_index; pd_prev_ghr <= prev_ghr; + pht_index <= ghr_out ^ next_pc[PHT_ADDRESS+1:2]; + pd_pred_taken <= btb_hit && pred_taken && btb_is_branch; + pd_pred_target <= (is_return_instr)? pred_return_address : pred_target_address; + pd_pc <= next_pc; + pd_btb_hit <= btb_hit; + pd_sp_snap <= sp_snap; + pd_ras_snap <= ras_snap; end end GHR ghr_instantiation( diff --git a/Design/tb_main_datapath.sv b/Design/tb_main_datapath.sv index 91b2911..e43d7db 100644 --- a/Design/tb_main_datapath.sv +++ b/Design/tb_main_datapath.sv @@ -100,7 +100,7 @@ module tb_main_datapath(); comm_free_reg1 = '0; comm_free_reg2 = '0; // Apply Reset - #15 reset = 0; + #10 reset = 0; // Wait a few cycles to let PD, IF, and ID stages fill #60; diff --git a/Design/waveform.vcd b/Design/waveform.vcd new file mode 100644 index 0000000..c76991a --- /dev/null +++ b/Design/waveform.vcd @@ -0,0 +1,2053 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + $scope module TOP $end + $scope module tb_main_datapath $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 ;% BIQ_ADDRESS [31:0] $end + $var wire 32 <% PRF_ADDRESS [31:0] $end + $var wire 32 =% MAX_BRANCHES [31:0] $end + $var wire 32 >% BTAG_SIZE [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 % actual_taken $end + $var wire 1 & mispredict $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 * update_btb $end + $var wire 1 + update_ras $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 1 . ex_is_jalr $end + $var wire 32 / actual_target_address [31:0] $end + $var wire 32 0 ex_pc [31:0] $end + $var wire 9 1 ghr_snap [8:0] $end + $var wire 9 2 rb_pht_index [8:0] $end + $var wire 3 3 rb_sp_snap [2:0] $end + $var wire 64 4 rb_ras_snap [63:0] $end + $var wire 1 6 dis_biq_dealloc $end + $var wire 5 7 rr_biq_id [4:0] $end + $var wire 1 8 rr_slot_id $end + $var wire 1 9 cdb_wakeup1 $end + $var wire 1 : cdb_wakeup2 $end + $var wire 1 ; comm_free_push1 $end + $var wire 1 < comm_free_push2 $end + $var wire 1 = ex_branch_resolved $end + $var wire 6 > cdb_waked_reg1 [5:0] $end + $var wire 6 ? cdb_waked_reg2 [5:0] $end + $var wire 6 @ comm_free_reg1 [5:0] $end + $var wire 6 A comm_free_reg2 [5:0] $end + $var wire 2 B ex_btag [1:0] $end + $var wire 1 d stall_frontend $end + $var wire 6 e rn_prd1 [5:0] $end + $var wire 6 f rn_prs1_1 [5:0] $end + $var wire 6 g rn_prs2_1 [5:0] $end + $var wire 6 h rn_old_prd1 [5:0] $end + $var wire 6 i rn_prd2 [5:0] $end + $var wire 6 j rn_prs1_2 [5:0] $end + $var wire 6 k rn_prs2_2 [5:0] $end + $var wire 6 l rn_old_prd2 [5:0] $end + $var wire 1 m rn_prs1_busy1 $end + $var wire 1 n rn_prs2_busy1 $end + $var wire 1 o rn_prs1_busy2 $end + $var wire 1 p rn_prs2_busy2 $end + $var wire 2 q rn_branch_tag [1:0] $end + $var wire 4 r rn_branch_mask [3:0] $end + $var wire 5 s rn_biq_address [4:0] $end + $var wire 30 t rn_pc [29:0] $end + $var wire 1 u rn_valid1 $end + $var wire 1 v rn_valid2 $end + $var wire 3 w rn_funct3_1 [2:0] $end + $var wire 3 x rn_alu_op1 [2:0] $end + $var wire 3 y rn_funct3_2 [2:0] $end + $var wire 3 z rn_alu_op2 [2:0] $end + $var wire 7 { rn_funct7_1 [6:0] $end + $var wire 7 | rn_funct7_2 [6:0] $end + $var wire 21 } rn_immout1 [20:0] $end + $var wire 21 ~ rn_immout2 [20:0] $end + $var wire 1 !! rn_jump_reg1 $end + $var wire 1 "! rn_jump1 $end + $var wire 1 #! rn_branch1 $end + $var wire 1 $! rn_regsrc1_1 $end + $var wire 1 %! rn_regsrc2_1 $end + $var wire 1 &! rn_immtype1 $end + $var wire 1 '! rn_isimm1 $end + $var wire 1 (! rn_retaddr1 $end + $var wire 1 )! rn_upperimm1 $end + $var wire 1 *! rn_regwrite1 $end + $var wire 1 +! rn_memwrite1 $end + $var wire 1 ,! rn_memtoreg1 $end + $var wire 1 -! rn_jump_reg2 $end + $var wire 1 .! rn_jump2 $end + $var wire 1 /! rn_branch2 $end + $var wire 1 0! rn_regsrc1_2 $end + $var wire 1 1! rn_regsrc2_2 $end + $var wire 1 2! rn_immtype2 $end + $var wire 1 3! rn_isimm2 $end + $var wire 1 4! rn_retaddr2 $end + $var wire 1 5! rn_upperimm2 $end + $var wire 1 6! rn_regwrite2 $end + $var wire 1 7! rn_memwrite2 $end + $var wire 1 8! rn_memtoreg2 $end + $var wire 1 ?% id_biq_valid $end + $var wire 1 9! id_biq_pred_taken $end + $var wire 32 :! id_biq_pred_target [31:0] $end + $var wire 9 ;! id_biq_pht_index [8:0] $end + $var wire 9 ! id_biq_ras_snap [63:0] $end + $scope module dut $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 ;% BIQ_ADDRESS [31:0] $end + $var wire 32 <% PRF_ADDRESS [31:0] $end + $var wire 32 =% MAX_BRANCHES [31:0] $end + $var wire 32 >% BTAG_SIZE [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 % actual_taken $end + $var wire 1 & mispredict $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 * update_btb $end + $var wire 1 + update_ras $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 1 . ex_is_jalr $end + $var wire 32 / actual_target_address [31:0] $end + $var wire 32 0 ex_pc [31:0] $end + $var wire 9 1 ghr_snap [8:0] $end + $var wire 9 2 rb_pht_index [8:0] $end + $var wire 3 3 rb_sp_snap [2:0] $end + $var wire 64 4 rb_ras_snap [63:0] $end + $var wire 1 6 dis_biq_dealloc $end + $var wire 5 7 rr_biq_id [4:0] $end + $var wire 1 8 rr_slot_id $end + $var wire 1 9 cdb_wakeup1 $end + $var wire 1 : cdb_wakeup2 $end + $var wire 1 ; comm_free_push1 $end + $var wire 1 < comm_free_push2 $end + $var wire 1 = ex_branch_resolved $end + $var wire 6 > cdb_waked_reg1 [5:0] $end + $var wire 6 ? cdb_waked_reg2 [5:0] $end + $var wire 6 @ comm_free_reg1 [5:0] $end + $var wire 6 A comm_free_reg2 [5:0] $end + $var wire 2 B ex_btag [1:0] $end + $var wire 1 d stall_frontend $end + $var wire 6 e rn_prd1 [5:0] $end + $var wire 6 f rn_prs1_1 [5:0] $end + $var wire 6 g rn_prs2_1 [5:0] $end + $var wire 6 h rn_old_prd1 [5:0] $end + $var wire 6 i rn_prd2 [5:0] $end + $var wire 6 j rn_prs1_2 [5:0] $end + $var wire 6 k rn_prs2_2 [5:0] $end + $var wire 6 l rn_old_prd2 [5:0] $end + $var wire 1 m rn_prs1_busy1 $end + $var wire 1 n rn_prs2_busy1 $end + $var wire 1 o rn_prs1_busy2 $end + $var wire 1 p rn_prs2_busy2 $end + $var wire 2 q rn_branch_tag [1:0] $end + $var wire 4 r rn_branch_mask [3:0] $end + $var wire 1 u rn_valid1 $end + $var wire 1 !! rn_jump_reg1 $end + $var wire 1 "! rn_jump1 $end + $var wire 1 #! rn_branch1 $end + $var wire 1 $! rn_regsrc1_1 $end + $var wire 1 %! rn_regsrc2_1 $end + $var wire 1 &! rn_immtype1 $end + $var wire 1 '! rn_isimm1 $end + $var wire 1 (! rn_retaddr1 $end + $var wire 1 )! rn_upperimm1 $end + $var wire 1 *! rn_regwrite1 $end + $var wire 1 +! rn_memwrite1 $end + $var wire 1 ,! rn_memtoreg1 $end + $var wire 3 w rn_funct3_1 [2:0] $end + $var wire 3 x rn_alu_op1 [2:0] $end + $var wire 7 { rn_funct7_1 [6:0] $end + $var wire 21 } rn_immout1 [20:0] $end + $var wire 1 v rn_valid2 $end + $var wire 1 -! rn_jump_reg2 $end + $var wire 1 .! rn_jump2 $end + $var wire 1 /! rn_branch2 $end + $var wire 1 0! rn_regsrc1_2 $end + $var wire 1 1! rn_regsrc2_2 $end + $var wire 1 2! rn_immtype2 $end + $var wire 1 3! rn_isimm2 $end + $var wire 1 4! rn_retaddr2 $end + $var wire 1 5! rn_upperimm2 $end + $var wire 1 6! rn_regwrite2 $end + $var wire 1 7! rn_memwrite2 $end + $var wire 1 8! rn_memtoreg2 $end + $var wire 3 y rn_funct3_2 [2:0] $end + $var wire 3 z rn_alu_op2 [2:0] $end + $var wire 7 | rn_funct7_2 [6:0] $end + $var wire 21 ~ rn_immout2 [20:0] $end + $var wire 5 s rn_biq_address [4:0] $end + $var wire 30 t rn_pc [29:0] $end + $var wire 1 ?% id_biq_valid $end + $var wire 1 9! id_biq_pred_taken $end + $var wire 32 :! id_biq_pred_target [31:0] $end + $var wire 9 ;! id_biq_pht_index [8:0] $end + $var wire 9 ! id_biq_ras_snap [63:0] $end + $var wire 1 @! id_stall_frontend $end + $var wire 1 A! rn_stall_frontend $end + $var wire 2 B! if_predecode_instr1 [1:0] $end + $var wire 2 C! if_predecode_instr2 [1:0] $end + $var wire 32 @% if_target_address [31:0] $end + $var wire 32 D! spec_return_address [31:0] $end + $var wire 1 E! pd_valid1 $end + $var wire 1 F! pd_valid2 $end + $var wire 32 G! pd_pc [31:0] $end + $var wire 32 H! pd_pred_target1 [31:0] $end + $var wire 32 A% pd_pred_target2 [31:0] $end + $var wire 1 I! pd_pred_taken1 $end + $var wire 1 B% pd_pred_taken2 $end + $var wire 1 J! pd_btb_hit1 $end + $var wire 1 C% pd_btb_hit2 $end + $var wire 9 K! pd_pht_index1 [8:0] $end + $var wire 9 D% pd_pht_index2 [8:0] $end + $var wire 3 L! pd_sp_snap [2:0] $end + $var wire 64 M! pd_ras_snap [63:0] $end + $var wire 9 O! pd_prev_ghr [8:0] $end + $var wire 1 P! if_valid1 $end + $var wire 1 Q! if_valid2 $end + $var wire 30 R! if_pc [29:0] $end + $var wire 32 S! if_instr1 [31:0] $end + $var wire 32 T! if_instr2 [31:0] $end + $var wire 32 U! if_pred_target1 [31:0] $end + $var wire 32 E% if_pred_target2 [31:0] $end + $var wire 1 V! if_pred_taken1 $end + $var wire 1 F% if_pred_taken2 $end + $var wire 1 W! if_btb_hit1 $end + $var wire 1 G% if_btb_hit2 $end + $var wire 9 X! if_pht_index1 [8:0] $end + $var wire 9 H% if_pht_index2 [8:0] $end + $var wire 3 Y! if_sp_snap [2:0] $end + $var wire 64 Z! if_ras_snap [63:0] $end + $var wire 9 \! if_prev_ghr [8:0] $end + $var wire 1 ]! id_take_snap $end + $var wire 1 ^! id_valid1 $end + $var wire 1 _! id_valid2 $end + $var wire 30 `! id_pc [29:0] $end + $var wire 5 a! id_biq_address [4:0] $end + $var wire 3 b! id_funct3_1 [2:0] $end + $var wire 3 c! id_alu_op1 [2:0] $end + $var wire 7 d! id_funct7_1 [6:0] $end + $var wire 5 e! id_rs1_1 [4:0] $end + $var wire 5 f! id_rs2_1 [4:0] $end + $var wire 5 g! id_rd_1 [4:0] $end + $var wire 1 h! id_jump_reg1 $end + $var wire 1 i! id_jump1 $end + $var wire 1 j! id_branch1 $end + $var wire 1 k! id_regsrc1_1 $end + $var wire 1 l! id_regsrc2_1 $end + $var wire 1 m! id_immtype1 $end + $var wire 1 n! id_memwrite1 $end + $var wire 1 o! id_regwrite1 $end + $var wire 1 p! id_memtoreg1 $end + $var wire 1 q! id_retaddr1 $end + $var wire 1 r! id_isimm1 $end + $var wire 1 s! id_upperimm1 $end + $var wire 21 t! id_immout1 [20:0] $end + $var wire 3 u! id_funct3_2 [2:0] $end + $var wire 3 v! id_alu_op2 [2:0] $end + $var wire 7 w! id_funct7_2 [6:0] $end + $var wire 5 x! id_rs1_2 [4:0] $end + $var wire 5 y! id_rs2_2 [4:0] $end + $var wire 5 z! id_rd_2 [4:0] $end + $var wire 1 {! id_jump_reg2 $end + $var wire 1 |! id_jump2 $end + $var wire 1 }! id_branch2 $end + $var wire 1 ~! id_regsrc1_2 $end + $var wire 1 !" id_regsrc2_2 $end + $var wire 1 "" id_immtype2 $end + $var wire 1 #" id_memwrite2 $end + $var wire 1 $" id_regwrite2 $end + $var wire 1 %" id_memtoreg2 $end + $var wire 1 &" id_retaddr2 $end + $var wire 1 '" id_isimm2 $end + $var wire 1 (" id_upperimm2 $end + $var wire 21 )" id_immout2 [20:0] $end + $scope module id_stage_inst $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 ;% BIQ_ADDRESS [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 8 rr_slot_id $end + $var wire 1 6 dis_biq_dealloc $end + $var wire 1 V! if_pred_taken $end + $var wire 1 P! if_valid1 $end + $var wire 1 Q! if_valid2 $end + $var wire 1 W! if_btb_hit $end + $var wire 32 S! if_instr1 [31:0] $end + $var wire 32 T! if_instr2 [31:0] $end + $var wire 32 U! if_pred_target [31:0] $end + $var wire 30 R! if_pc [29:0] $end + $var wire 5 7 rr_biq_id [4:0] $end + $var wire 9 X! if_pht_index [8:0] $end + $var wire 3 Y! if_sp_snap [2:0] $end + $var wire 64 Z! if_ras_snap [63:0] $end + $var wire 9 \! if_prev_ghr [8:0] $end + $var wire 3 =! id_biq_sp_snap [2:0] $end + $var wire 64 >! id_biq_ras_snap [63:0] $end + $var wire 1 @! stall_frontend $end + $var wire 1 ]! id_take_snap $end + $var wire 1 ^! id_valid1 $end + $var wire 1 _! id_valid2 $end + $var wire 3 b! id_funct3_1 [2:0] $end + $var wire 3 u! id_funct3_2 [2:0] $end + $var wire 7 d! id_funct7_1 [6:0] $end + $var wire 7 w! id_funct7_2 [6:0] $end + $var wire 5 e! id_rs1_1 [4:0] $end + $var wire 5 f! id_rs2_1 [4:0] $end + $var wire 5 g! id_rd_1 [4:0] $end + $var wire 5 x! id_rs1_2 [4:0] $end + $var wire 5 y! id_rs2_2 [4:0] $end + $var wire 5 z! id_rd_2 [4:0] $end + $var wire 21 t! id_immout1 [20:0] $end + $var wire 21 )" id_immout2 [20:0] $end + $var wire 5 a! id_biq_address [4:0] $end + $var wire 32 :! id_biq_pred_target [31:0] $end + $var wire 30 `! id_pc [29:0] $end + $var wire 9 " RegWrite_1 $end + $var wire 1 ?" RegWrite_2 $end + $var wire 1 @" MemWrite_1 $end + $var wire 1 A" MemWrite_2 $end + $var wire 1 B" MemToReg_1 $end + $var wire 1 C" MemToReg_2 $end + $var wire 1 D" RetAddr_2 $end + $var wire 1 E" Imm_1 $end + $var wire 1 F" Imm_2 $end + $var wire 1 G" imm_type1 $end + $var wire 1 H" imm_type2 $end + $scope module biq_instantiation $end + $var wire 32 ;% BIQ_ADDRESS [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 6 biq_dealloc $end + $var wire 1 $ flush $end + $var wire 1 0" biq_alloc $end + $var wire 1 V! pred_taken $end + $var wire 32 U! pred_target [31:0] $end + $var wire 5 7 biq_id [4:0] $end + $var wire 9 X! pht_index [8:0] $end + $var wire 9 \! prev_ghr [8:0] $end + $var wire 3 Y! sp_snap [2:0] $end + $var wire 64 Z! ras_snap [63:0] $end + $var wire 1 9! biq_pred_taken $end + $var wire 1 @! stall_frontend $end + $var wire 5 a! biq_address [4:0] $end + $var wire 32 :! biq_pred_target [31:0] $end + $var wire 9 ! biq_ras_snap [63:0] $end + $var wire 9 ;! biq_pht_index [8:0] $end + $var wire 118 I" BIQ[0] [117:0] $end + $var wire 118 M" BIQ[1] [117:0] $end + $var wire 118 Q" BIQ[2] [117:0] $end + $var wire 118 U" BIQ[3] [117:0] $end + $var wire 118 Y" BIQ[4] [117:0] $end + $var wire 118 ]" BIQ[5] [117:0] $end + $var wire 118 a" BIQ[6] [117:0] $end + $var wire 118 e" BIQ[7] [117:0] $end + $var wire 118 i" BIQ[8] [117:0] $end + $var wire 118 m" BIQ[9] [117:0] $end + $var wire 118 q" BIQ[10] [117:0] $end + $var wire 118 u" BIQ[11] [117:0] $end + $var wire 118 y" BIQ[12] [117:0] $end + $var wire 118 }" BIQ[13] [117:0] $end + $var wire 118 ## BIQ[14] [117:0] $end + $var wire 118 '# BIQ[15] [117:0] $end + $var wire 118 +# BIQ[16] [117:0] $end + $var wire 118 /# BIQ[17] [117:0] $end + $var wire 118 3# BIQ[18] [117:0] $end + $var wire 118 7# BIQ[19] [117:0] $end + $var wire 118 ;# BIQ[20] [117:0] $end + $var wire 118 ?# BIQ[21] [117:0] $end + $var wire 118 C# BIQ[22] [117:0] $end + $var wire 118 G# BIQ[23] [117:0] $end + $var wire 118 K# BIQ[24] [117:0] $end + $var wire 118 O# BIQ[25] [117:0] $end + $var wire 118 S# BIQ[26] [117:0] $end + $var wire 118 W# BIQ[27] [117:0] $end + $var wire 118 [# BIQ[28] [117:0] $end + $var wire 118 _# BIQ[29] [117:0] $end + $var wire 118 c# BIQ[30] [117:0] $end + $var wire 118 g# BIQ[31] [117:0] $end + $var wire 5 7 biq_read_address [4:0] $end + $var wire 6 k# biq_head_ptr [5:0] $end + $var wire 6 l# biq_tail_ptr [5:0] $end + $var wire 1 @! biq_full $end + $upscope $end + $scope module cu_instantiation1 $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 7 *" opcode [6:0] $end + $var wire 3 ," ALUOp [2:0] $end + $var wire 1 1" JumpReg $end + $var wire 1 3" Jump $end + $var wire 1 5" Branch $end + $var wire 1 7" RegSrc1 $end + $var wire 1 8" RegSrc2 $end + $var wire 1 <" UpperImm $end + $var wire 1 >" RegWrite $end + $var wire 1 @" MemWrite $end + $var wire 1 B" MemToReg $end + $var wire 1 ;" RetAddr $end + $var wire 1 E" imm $end + $upscope $end + $scope module cu_instantiation2 $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 7 +" opcode [6:0] $end + $var wire 3 -" ALUOp [2:0] $end + $var wire 1 2" JumpReg $end + $var wire 1 4" Jump $end + $var wire 1 6" Branch $end + $var wire 1 9" RegSrc1 $end + $var wire 1 :" RegSrc2 $end + $var wire 1 =" UpperImm $end + $var wire 1 ?" RegWrite $end + $var wire 1 A" MemWrite $end + $var wire 1 C" MemToReg $end + $var wire 1 D" RetAddr $end + $var wire 1 F" imm $end + $upscope $end + $scope module ig_instantiation1 $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 S! instruction [31:0] $end + $var wire 21 ." immediate_output [20:0] $end + $var wire 1 G" imm_type $end + $var wire 7 m# opcode [6:0] $end + $upscope $end + $scope module ig_instantiation2 $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 7% OPCODE_SIZE [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 T! instruction [31:0] $end + $var wire 21 /" immediate_output [20:0] $end + $var wire 1 H" imm_type $end + $var wire 7 n# opcode [6:0] $end + $upscope $end + $upscope $end + $scope module if_stage_inst $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 E! pd_valid1 $end + $var wire 1 F! pd_valid2 $end + $var wire 1 d stall_frontend $end + $var wire 1 I! pd_pred_taken $end + $var wire 1 J! pd_btb_hit $end + $var wire 32 G! pd_pc [31:0] $end + $var wire 32 H! pd_pred_target [31:0] $end + $var wire 9 K! pd_pht_index [8:0] $end + $var wire 3 L! pd_sp_snap [2:0] $end + $var wire 64 M! pd_ras_snap [63:0] $end + $var wire 9 O! pd_prev_ghr [8:0] $end + $var wire 1 V! if_pred_taken $end + $var wire 1 W! if_btb_hit $end + $var wire 1 P! if_valid1 $end + $var wire 1 Q! if_valid2 $end + $var wire 2 B! if_predecode_instr1 [1:0] $end + $var wire 2 C! if_predecode_instr2 [1:0] $end + $var wire 32 S! if_instr1 [31:0] $end + $var wire 32 T! if_instr2 [31:0] $end + $var wire 32 U! if_pred_target [31:0] $end + $var wire 30 R! if_pc [29:0] $end + $var wire 9 X! if_pht_index [8:0] $end + $var wire 3 Y! if_sp_snap [2:0] $end + $var wire 64 Z! if_ras_snap [63:0] $end + $var wire 9 \! if_prev_ghr [8:0] $end + $var wire 30 o# instr1_addr [29:0] $end + $var wire 30 p# instr2_addr [29:0] $end + $scope module im_instantiation $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 M% MEM_ROWS [31:0] $end + $var wire 1 0% CLK $end + $var wire 32 q# instr1_addr [31:0] $end + $var wire 32 r# instr2_addr [31:0] $end + $var wire 32 S! instr_1 [31:0] $end + $var wire 32 T! instr_2 [31:0] $end + $upscope $end + $scope module predecode_instantiation $end + $var wire 7 *" opcode1 [6:0] $end + $var wire 7 +" opcode2 [6:0] $end + $var wire 5 s# rd1 [4:0] $end + $var wire 5 t# rd2 [4:0] $end + $var wire 2 B! predecode_instr1 [1:0] $end + $var wire 2 C! predecode_instr2 [1:0] $end + $upscope $end + $upscope $end + $scope module pd_stage_inst $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 d stall_frontend $end + $var wire 1 % ex_actual_taken $end + $var wire 1 ' restore_ghr $end + $var wire 1 ( restore_ras $end + $var wire 1 ) update_pht $end + $var wire 1 . ex_is_jalr $end + $var wire 1 , ex_is_ret $end + $var wire 1 - ex_is_branch $end + $var wire 1 & flush $end + $var wire 2 B! if_predecode_instr1 [1:0] $end + $var wire 2 C! if_predecode_instr2 [1:0] $end + $var wire 32 / ex_actual_target_address [31:0] $end + $var wire 32 @% if_target_address [31:0] $end + $var wire 32 G! if_pc [31:0] $end + $var wire 32 0 ex_pc [31:0] $end + $var wire 9 1 ghr_snap [8:0] $end + $var wire 9 2 rb_pht_index [8:0] $end + $var wire 3 3 rb_sp_snap [2:0] $end + $var wire 64 4 rb_ras_snap [63:0] $end + $var wire 1 I! pd_pred_taken $end + $var wire 1 J! pd_btb_hit $end + $var wire 1 E! pd_valid1 $end + $var wire 1 F! pd_valid2 $end + $var wire 32 G! pd_pc [31:0] $end + $var wire 32 H! pd_pred_target [31:0] $end + $var wire 9 K! pd_pht_index [8:0] $end + $var wire 3 L! pd_sp_snap [2:0] $end + $var wire 64 M! pd_ras_snap [63:0] $end + $var wire 9 O! pd_prev_ghr [8:0] $end + $var wire 9 u# ghr_out [8:0] $end + $var wire 9 u# prev_ghr [8:0] $end + $var wire 9 v# pht_index [8:0] $end + $var wire 1 w# pred_taken $end + $var wire 1 x# btb_hit $end + $var wire 1 y# btb_is_branch $end + $var wire 1 z# is_return_instr $end + $var wire 1 {# squash_instruction $end + $var wire 32 |# pred_return_address [31:0] $end + $var wire 32 }# pred_target_address [31:0] $end + $var wire 3 ~# sp_snap [2:0] $end + $var wire 64 !$ ras_snap [63:0] $end + $var wire 32 #$ next_pc [31:0] $end + $scope module btb_instantiation $end + $var wire 32 N% BTB_ROWS [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 <% BTB_ADDRESS [31:0] $end + $var wire 32 O% TAG_SIZE [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $$ if_is_jal1 $end + $var wire 1 %$ if_is_jal2 $end + $var wire 1 % ex_is_taken_branch $end + $var wire 1 . ex_is_jalr $end + $var wire 1 C ex_is_not_ret $end + $var wire 32 G! pd_pc [31:0] $end + $var wire 32 G! if_pc [31:0] $end + $var wire 32 0 ex_pc [31:0] $end + $var wire 30 D ex_target_address [29:0] $end + $var wire 30 P% if_target_address [29:0] $end + $var wire 1 x# btb_hit $end + $var wire 1 {# squash_instruction $end + $var wire 1 y# btb_is_branch $end + $var wire 32 }# pred_target_address [31:0] $end + $var wire 23 &$ pd_tag [22:0] $end + $var wire 23 &$ if_tag [22:0] $end + $var wire 23 E ex_tag [22:0] $end + $var wire 6 '$ btb_read_address [5:0] $end + $var wire 6 F ex_btb_write_address [5:0] $end + $var wire 6 '$ if_btb_write_address [5:0] $end + $scope module unnamedblk1 $end + $var wire 32 ($ i [31:0] $end + $upscope $end + $upscope $end + $scope module ghr_instantiation $end + $var wire 32 8% GHR_SIZE [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 d stall_frontend $end + $var wire 1 ' restore_ghr $end + $var wire 1 % ex_actual_taken $end + $var wire 1 - ex_is_branch $end + $var wire 9 1 ghr_snap [8:0] $end + $var wire 9 u# ghr_out [8:0] $end + $var wire 9 u# prev_ghr [8:0] $end + $var wire 1 Q% pred_taken $end + $upscope $end + $scope module pc_instantiation $end + $var wire 32 6% XLEN [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 & flush $end + $var wire 1 d stall_frontend $end + $var wire 1 z# is_return_instr $end + $var wire 1 x# btb_hit $end + $var wire 1 w# pht_pred_taken $end + $var wire 1 y# btb_is_branch $end + $var wire 32 |# ras_target_address [31:0] $end + $var wire 32 }# btb_target_address [31:0] $end + $var wire 32 / ex_actual_target_address [31:0] $end + $var wire 32 #$ next_pc [31:0] $end + $upscope $end + $scope module pht_instantiation $end + $var wire 32 8% PHT_ADDRESS [31:0] $end + $var wire 32 >% COUNTER_SIZE [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 % ex_actual_taken $end + $var wire 1 ) update_pht $end + $var wire 9 v# pht_index [8:0] $end + $var wire 9 2 rb_pht_index [8:0] $end + $var wire 1 w# pred_taken $end + $upscope $end + $scope module ras_instantiation $end + $var wire 32 9% RAS_ADDRESS [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 R% RAS_LEN [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 d stall_frontend $end + $var wire 1 ( restore_ras $end + $var wire 2 B! if_predecode_instr1 [1:0] $end + $var wire 2 C! if_predecode_instr2 [1:0] $end + $var wire 32 @% if_actual_return_address [31:0] $end + $var wire 3 3 rb_sp_snap [2:0] $end + $var wire 64 4 rb_ras_snap [63:0] $end + $var wire 1 z# is_return_instr $end + $var wire 32 |# pred_return_address [31:0] $end + $var wire 3 ~# sp_snap [2:0] $end + $var wire 64 !$ ras_snap [63:0] $end + $var wire 32 )$ RAS[0] [31:0] $end + $var wire 32 *$ RAS[1] [31:0] $end + $var wire 32 +$ RAS[2] [31:0] $end + $var wire 32 ,$ RAS[3] [31:0] $end + $var wire 32 -$ RAS[4] [31:0] $end + $var wire 32 .$ RAS[5] [31:0] $end + $var wire 32 /$ RAS[6] [31:0] $end + $var wire 32 0$ RAS[7] [31:0] $end + $var wire 3 1$ sp [2:0] $end + $var wire 3 2$ next_sp [2:0] $end + $var wire 1 z# pop $end + $var wire 1 3$ push $end + $var wire 1 4$ if_is_call1 $end + $var wire 1 5$ if_is_call2 $end + $var wire 1 6$ if_is_ret1 $end + $var wire 1 7$ if_is_ret2 $end + $upscope $end + $upscope $end + $scope module rn_stage_inst $end + $var wire 32 <% PRF_ADDRESS [31:0] $end + $var wire 32 :% INIT_IMMEDIATE_SIZE [31:0] $end + $var wire 32 =% MAX_BRANCHES [31:0] $end + $var wire 32 >% BTAG_SIZE [31:0] $end + $var wire 32 ;% BIQ_ADDRESS [31:0] $end + $var wire 32 6% XLEN [31:0] $end + $var wire 32 N% NUM_PHY_REG [31:0] $end + $var wire 32 6% FL_ROWS [31:0] $end + $var wire 32 ;% FL_INDEX_WIDTH [31:0] $end + $var wire 32 <% FL_PTR_WIDTH [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 ]! id_take_snap $end + $var wire 1 ^! id_valid1 $end + $var wire 1 _! id_valid2 $end + $var wire 1 9 cdb_wakeup1 $end + $var wire 1 : cdb_wakeup2 $end + $var wire 1 ; comm_free_push1 $end + $var wire 1 < comm_free_push2 $end + $var wire 1 = ex_branch_resolved $end + $var wire 1 h! id_jump_reg1 $end + $var wire 1 {! id_jump_reg2 $end + $var wire 1 i! id_jump1 $end + $var wire 1 |! id_jump2 $end + $var wire 1 j! id_branch1 $end + $var wire 1 }! id_branch2 $end + $var wire 1 k! id_regsrc1_1 $end + $var wire 1 m! id_immtype1 $end + $var wire 1 n! id_memwrite1 $end + $var wire 1 "" id_immtype2 $end + $var wire 1 l! id_regsrc2_1 $end + $var wire 1 ~! id_regsrc1_2 $end + $var wire 1 !" id_regsrc2_2 $end + $var wire 1 s! id_upperimm1 $end + $var wire 1 (" id_upperimm2 $end + $var wire 1 o! id_regwrite1 $end + $var wire 1 $" id_regwrite2 $end + $var wire 1 #" id_memwrite2 $end + $var wire 1 p! id_memtoreg1 $end + $var wire 1 %" id_memtoreg2 $end + $var wire 1 q! id_retaddr1 $end + $var wire 1 &" id_retaddr2 $end + $var wire 1 r! id_isimm1 $end + $var wire 1 '" id_isimm2 $end + $var wire 6 > cdb_waked_reg1 [5:0] $end + $var wire 6 ? cdb_waked_reg2 [5:0] $end + $var wire 6 @ comm_free_reg1 [5:0] $end + $var wire 6 A comm_free_reg2 [5:0] $end + $var wire 2 B ex_btag [1:0] $end + $var wire 3 b! id_funct3_1 [2:0] $end + $var wire 3 u! id_funct3_2 [2:0] $end + $var wire 7 d! id_funct7_1 [6:0] $end + $var wire 7 w! id_funct7_2 [6:0] $end + $var wire 5 e! id_rs1_1 [4:0] $end + $var wire 5 f! id_rs2_1 [4:0] $end + $var wire 5 g! id_rd_1 [4:0] $end + $var wire 5 x! id_rs1_2 [4:0] $end + $var wire 5 y! id_rs2_2 [4:0] $end + $var wire 5 z! id_rd_2 [4:0] $end + $var wire 21 t! id_immout1 [20:0] $end + $var wire 21 )" id_immout2 [20:0] $end + $var wire 5 a! id_biq_address [4:0] $end + $var wire 30 `! id_pc [29:0] $end + $var wire 3 c! id_alu_op1 [2:0] $end + $var wire 3 v! id_alu_op2 [2:0] $end + $var wire 1 A! stall_frontend $end + $var wire 6 e rn_prd1 [5:0] $end + $var wire 6 f rn_prs1_1 [5:0] $end + $var wire 6 g rn_prs2_1 [5:0] $end + $var wire 6 h rn_old_prd1 [5:0] $end + $var wire 6 i rn_prd2 [5:0] $end + $var wire 6 j rn_prs1_2 [5:0] $end + $var wire 6 k rn_prs2_2 [5:0] $end + $var wire 6 l rn_old_prd2 [5:0] $end + $var wire 1 m rn_prs1_busy1 $end + $var wire 1 n rn_prs2_busy1 $end + $var wire 1 o rn_prs1_busy2 $end + $var wire 1 p rn_prs2_busy2 $end + $var wire 2 q rn_branch_tag [1:0] $end + $var wire 4 r rn_branch_mask [3:0] $end + $var wire 5 s rn_biq_address [4:0] $end + $var wire 30 t rn_pc [29:0] $end + $var wire 3 w rn_funct3_1 [2:0] $end + $var wire 3 y rn_funct3_2 [2:0] $end + $var wire 7 { rn_funct7_1 [6:0] $end + $var wire 7 | rn_funct7_2 [6:0] $end + $var wire 21 } rn_immout1 [20:0] $end + $var wire 21 ~ rn_immout2 [20:0] $end + $var wire 3 x rn_alu_op1 [2:0] $end + $var wire 3 z rn_alu_op2 [2:0] $end + $var wire 1 u rn_valid1 $end + $var wire 1 !! rn_jump_reg1 $end + $var wire 1 "! rn_jump1 $end + $var wire 1 #! rn_branch1 $end + $var wire 1 $! rn_regsrc1_1 $end + $var wire 1 %! rn_regsrc2_1 $end + $var wire 1 &! rn_immtype1 $end + $var wire 1 '! rn_isimm1 $end + $var wire 1 (! rn_retaddr1 $end + $var wire 1 )! rn_upperimm1 $end + $var wire 1 *! rn_regwrite1 $end + $var wire 1 +! rn_memwrite1 $end + $var wire 1 ,! rn_memtoreg1 $end + $var wire 1 v rn_valid2 $end + $var wire 1 -! rn_jump_reg2 $end + $var wire 1 .! rn_jump2 $end + $var wire 1 /! rn_branch2 $end + $var wire 1 0! rn_regsrc1_2 $end + $var wire 1 1! rn_regsrc2_2 $end + $var wire 1 2! rn_immtype2 $end + $var wire 1 3! rn_isimm2 $end + $var wire 1 4! rn_retaddr2 $end + $var wire 1 5! rn_upperimm2 $end + $var wire 1 6! rn_regwrite2 $end + $var wire 1 7! rn_memwrite2 $end + $var wire 1 8! rn_memtoreg2 $end + $var wire 6 8$ fl_freed_reg1 [5:0] $end + $var wire 6 9$ fl_freed_reg2 [5:0] $end + $var wire 192 G rmt_snap [191:0] $end + $var wire 192 M bs_rmt_snap [191:0] $end + $var wire 6 S fl_head_ptr [5:0] $end + $var wire 6 T bs_head_ptr_snap [5:0] $end + $var wire 6 8$ routed_freed_reg1 [5:0] $end + $var wire 6 :$ routed_freed_reg2 [5:0] $end + $var wire 1 ;$ pop1 $end + $var wire 1 <$ pop2 $end + $var wire 1 =$ bs_full $end + $var wire 1 >$ fl_empty $end + $scope module bs_instantiation $end + $var wire 32 <% PRF_ADDRESS [31:0] $end + $var wire 32 N% NUM_PHY_REG [31:0] $end + $var wire 32 =% MAX_BRANCHES [31:0] $end + $var wire 32 >% BTAG_SIZE [31:0] $end + $var wire 32 6% FL_ROWS [31:0] $end + $var wire 32 ;% FL_INDEX_WIDTH [31:0] $end + $var wire 32 <% FL_PTR_WIDTH [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 U id_take_snap $end + $var wire 1 = ex_branch_resolved $end + $var wire 1 ?$ pop1 $end + $var wire 1 @$ pop2 $end + $var wire 1 j! id_branch1 $end + $var wire 1 i! id_jump1 $end + $var wire 1 ^! id_valid1 $end + $var wire 2 B ex_btag [1:0] $end + $var wire 192 G rmt_snap [191:0] $end + $var wire 6 S freelist_head_snap [5:0] $end + $var wire 1 =$ bs_full $end + $var wire 192 M bs_rmt_snap [191:0] $end + $var wire 6 T bs_freelist_head_snap [5:0] $end + $var wire 2 q bs_branch_tag [1:0] $end + $var wire 4 r bs_branch_mask [3:0] $end + $var wire 202 A$ BS[0] [201:0] $end + $var wire 202 H$ BS[1] [201:0] $end + $var wire 202 O$ BS[2] [201:0] $end + $var wire 202 V$ BS[3] [201:0] $end + $var wire 4 r BMR [3:0] $end + $var wire 2 q current_btag [1:0] $end + $scope module unnamedblk1 $end + $var wire 32 ]$ i [31:0] $end + $upscope $end + $scope module unnamedblk2 $end + $var wire 32 ^$ i [31:0] $end + $upscope $end + $upscope $end + $scope module fl_instantiation $end + $var wire 32 <% PRF_ADDRESS [31:0] $end + $var wire 32 N% NUM_PHY_REG [31:0] $end + $var wire 32 6% FL_ROWS [31:0] $end + $var wire 32 ;% FL_INDEX_WIDTH [31:0] $end + $var wire 32 <% FL_PTR_WIDTH [31:0] $end + $var wire 1 0% CLK $end + $var wire 1 # reset $end + $var wire 1 $ flush $end + $var wire 1 A! stall_frontend $end + $var wire 1 ; push1 $end + $var wire 1 < push2 $end + $var wire 1 ;$ pop1 $end + $var wire 1 <$ pop2 $end + $var wire 1 j! id_branch1 $end + $var wire 1 i! id_jump1 $end + $var wire 1 ^! id_valid1 $end + $var wire 6 @ comm_free_reg1 [5:0] $end + $var wire 6 A comm_free_reg2 [5:0] $end + $var wire 6 T bs_head_ptr_snap [5:0] $end + $var wire 6 8$ fl_freed_reg1 [5:0] $end + $var wire 6 9$ fl_freed_reg2 [5:0] $end + $var wire 6 S fl_head_ptr [5:0] $end + $var wire 1 >$ fl_empty $end + $var wire 6 _$ FL[0] [5:0] $end + $var wire 6 `$ FL[1] [5:0] $end + $var wire 6 a$ FL[2] [5:0] $end + $var wire 6 b$ FL[3] [5:0] $end + $var wire 6 c$ FL[4] [5:0] $end + $var wire 6 d$ FL[5] [5:0] $end + $var wire 6 e$ FL[6] [5:0] $end + $var wire 6 f$ FL[7] [5:0] $end + $var wire 6 g$ FL[8] [5:0] $end + $var wire 6 h$ FL[9] [5:0] $end + $var wire 6 i$ FL[10] [5:0] $end + $var wire 6 j$ FL[11] [5:0] $end + $var wire 6 k$ FL[12] [5:0] $end + $var wire 6 l$ FL[13] [5:0] $end + $var wire 6 m$ FL[14] [5:0] $end + $var wire 6 n$ FL[15] [5:0] $end + $var wire 6 o$ FL[16] [5:0] $end + $var wire 6 p$ FL[17] [5:0] $end + $var wire 6 q$ FL[18] [5:0] $end + $var wire 6 r$ FL[19] [5:0] $end + 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