From 36c0b7ac3cabc9849f2ea41bb5ee21b9890faff7 Mon Sep 17 00:00:00 2001 From: Paveen383 Date: Wed, 27 Nov 2024 21:05:55 +0530 Subject: [PATCH 1/4] Update README.md --- README.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index fa3f430a..d8f51572 100644 --- a/README.md +++ b/README.md @@ -66,14 +66,16 @@ Y= A⊕B Program for logic gates and verify its truth table in quartus using Verilog programming - Developed by: RegisterNumber: + Developed by:Paveen Kumaran S.V RegisterNumber:(24000025) **Logic symbol & Truthtable** +![image](https://github.com/user-attachments/assets/c52010dd-fae1-4ff7-a880-7b36f859ced0) -**RTL realization Output:** -**RTL** +**RTL realization Output:RTL +![image](https://github.com/user-attachments/assets/0fef791e-cac5-4804-95dd-a12fdc0b743d) -**Result:** + +**Result:**Thus the truth table has been verified and implemented succcessfully using verilog HDL in Quartus II From bfe6315c5310f4936734daff0e6be14adf2bc691 Mon Sep 17 00:00:00 2001 From: Paveen383 Date: Thu, 2 Jan 2025 10:50:16 +0530 Subject: [PATCH 2/4] Update README.md --- README.md | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/README.md b/README.md index d8f51572..e98623ba 100644 --- a/README.md +++ b/README.md @@ -64,6 +64,21 @@ Y= A⊕B **PROGRAM** +``` +GATE LEVEL MODEL: +module log_gat(a,b,c1,c2,c3,c4,c5,c6,c7); +input a,b; +output c1,c2,c3,c4,c5,c6,c7; +not g1(c1,a); +and g2(c2,a,b); +or g3(c3,a,b); +nand g4(c4,a,b); +nor g5(c5,a,b); +xor g6(c6,a,b); +xnor g7(c7,a,b); +endmodule +``` + Program for logic gates and verify its truth table in quartus using Verilog programming Developed by:Paveen Kumaran S.V RegisterNumber:(24000025) From 35605dcca2331d6a10bece483830230075674778 Mon Sep 17 00:00:00 2001 From: Paveen383 Date: Thu, 2 Jan 2025 10:52:01 +0530 Subject: [PATCH 3/4] Rename README.md to README.md. --- README.md => README.md. | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename README.md => README.md. (100%) diff --git a/README.md b/README.md. similarity index 100% rename from README.md rename to README.md. From ac0c93833524190abe62023f26a663a930c851ac Mon Sep 17 00:00:00 2001 From: Paveen383 Date: Thu, 2 Jan 2025 11:06:02 +0530 Subject: [PATCH 4/4] Create README.md --- README.md | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 README.md diff --git a/README.md b/README.md new file mode 100644 index 00000000..c7d4a37b --- /dev/null +++ b/README.md @@ -0,0 +1,94 @@ +### study-of-basic-gates + +**AIM:** + +To study and verify the truth table of logic gates in Quartus II using Verilog programming. + +**Equipments Required:** + +Software – Quartus prime + +**Theory** + +Introduction Logic gates are the basic building blocks of any digital system. Logic gates are electronic circuits having one or more than one input and only one output. The relationship between the input and the output is based on a certain logic. Based on this, logic gates are named as + +AND gate OR gate NOT gate NAND gate NOR gate Ex-OR gate Ex-NOR gate + +**AND gate** + +The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B or can be written as AB +Y= A.B + +**OR gate** + +The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation. +Y= A+B + +**NOT gate** + +The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A' or A with a bar over the top, as shown at the outputs. +Y= A' + +**NAND gate** + +This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion. +Y= (AB)’ + +**NOR gate** + +This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output. The small circle represents inversion. +Y= (A+B)’ + +**Ex-OR gate** + +The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both of its two inputs are high. An encircled plus sign (⊕) is used to show the Ex-OR operation. +Y= A⊕B + +**Ex-NOR gate** + +The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the output. The small circle represents inversion. +Y= A⊕B + +**Procedure** + +1. Type the program in Quartus software. + +2. Compile and run the program. + +3. Generate the RTL schematic and save the logic diagram. + +4. Create nodes for inputs and outputs to generate the timing diagram. + +5. For different input combinations generate the timing diagram. + + +**PROGRAM** +``` +GATE LEVEL MODEL: +module log_gat(a,b,c1,c2,c3,c4,c5,c6,c7); +input a,b; +output c1,c2,c3,c4,c5,c6,c7; +not g1(c1,a); +and g2(c2,a,b); +or g3(c3,a,b); +nand g4(c4,a,b); +nor g5(c5,a,b); +xor g6(c6,a,b); +xnor g7(c7,a,b); +endmodule +``` + + +Program for logic gates and verify its truth table in quartus using Verilog programming + + Developed by:Paveen Kuamaran SV RegisterNumber:24000025 + +**Logic symbol & Truthtable** +![image](https://github.com/user-attachments/assets/c3cbec5f-84b6-4173-93cb-6a5af16363f4) + + +**RTL realization Output:RTL + +![image](https://github.com/user-attachments/assets/700e5975-d56a-47b5-9dba-b4ba8e60241e) + +