diff --git a/README.md b/README.md
index fa3f430a..3ac01657 100644
--- a/README.md
+++ b/README.md
@@ -63,14 +63,25 @@ Y= A⊕B
 
 
 **PROGRAM**
-
+module ex1(a,b,y1,y2,y3,y4,y5,y6);
+input a,b;
+output y1,y2,y3,y4,y5,y6;
+and g1(y1,a,b);
+or g2(y2,a,b);
+nand g3(y3,a,b);
+nor g4(y4,a,b);
+xor g5(y5,a,b);
+not g6(y6,a);
+endmodule
 Program for logic gates and verify its truth table in quartus using Verilog programming
 
  Developed by: RegisterNumber: 
  
 **Logic symbol & Truthtable**
+<img width="1486" height="828" alt="Screenshot (37)" src="https://github.com/user-attachments/assets/3b2991c1-4825-4ede-9087-5f8d27b63509" />
 
 **RTL realization Output:** 
+<img width="1483" height="838" alt="Screenshot (38)" src="https://github.com/user-attachments/assets/3e89b91c-3af3-4b98-afe5-12dce5d95946" />
 
 **RTL**