diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 6e8655faa..e19abe4b7 100755 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -12,18 +12,18 @@ # main repository, it's recommended to remove the image from the source # repository's container registry, so that the image from the main # repository's registry will be used there as well. -.templates_sha: &template_sha 567700e483aabed992d0a4fea84994a0472deff6 # see https://docs.gitlab.com/ee/ci/yaml/#includefile +.templates_sha: &template_sha c6aeb16f86e32525fa630fb99c66c4f3e62fc3cb # see https://docs.gitlab.com/ee/ci/yaml/#includefile include: - project: 'freedesktop/ci-templates' ref: *template_sha file: - - '/templates/debian.yml' - - '/templates/freebsd.yml' - - '/templates/ci-fairy.yml' + - '/templates/debian.yml' + - '/templates/freebsd.yml' + - '/templates/ci-fairy.yml' variables: - FDO_UPSTREAM_REPO: mesa/drm + FDO_UPSTREAM_REPO: mesa/libdrm FDO_REPO_SUFFIX: "$BUILD_OS/$BUILD_ARCH" stages: @@ -39,12 +39,11 @@ stages: .os-debian: variables: BUILD_OS: debian - FDO_DISTRIBUTION_VERSION: buster + FDO_DISTRIBUTION_VERSION: trixie-slim FDO_DISTRIBUTION_PACKAGES: 'build-essential docbook-xsl libatomic-ops-dev libcairo2-dev libcunit1-dev libpciaccess-dev meson ninja-build pkg-config python3 python3-pip python3-wheel python3-setuptools python3-docutils valgrind' - FDO_DISTRIBUTION_EXEC: 'pip3 install meson==0.59.0' # bump this tag every time you change something which requires rebuilding the # base image - FDO_DISTRIBUTION_TAG: "2023-09-01.0" + FDO_DISTRIBUTION_TAG: "2026-04-27.0" .debian-x86_64: extends: @@ -63,15 +62,16 @@ stages: - .os-debian variables: BUILD_ARCH: "armv7" + FDO_DISTRIBUTION_PLATFORM: linux/arm/v7 .os-freebsd: variables: BUILD_OS: freebsd - FDO_DISTRIBUTION_VERSION: "13.2" - FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess py39-docutils cairo' + FDO_DISTRIBUTION_VERSION: "14.2" + FDO_DISTRIBUTION_PACKAGES: 'meson ninja pkgconf libpciaccess textproc/py-docutils cairo' # bump this tag every time you change something which requires rebuilding the # base image - FDO_DISTRIBUTION_TAG: "2023-07-20.0" + FDO_DISTRIBUTION_TAG: "2025-05-22.0" .freebsd-x86_64: extends: @@ -190,8 +190,8 @@ x86_64-freebsd-container_prep: variables: GIT_DEPTH: 10 script: - - meson build - --auto-features=enabled + - meson setup build + --fatal-meson-warnings --auto-features=enabled -D udev=true - ninja -C build - ninja -C build test @@ -213,7 +213,7 @@ x86_64-freebsd-container_prep: # the workspace to see details about the failed tests. - | set +e - /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson build --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build" + /app/vmctl exec "pkg info; cd $CI_PROJECT_NAME ; meson setup build --fatal-meson-warnings --auto-features=enabled -D etnaviv=disabled -D nouveau=disabled -D valgrind=disabled && ninja -C build" set -ex scp -r vm:$CI_PROJECT_NAME/build/meson-logs . /app/vmctl exec "ninja -C $CI_PROJECT_NAME/build install" diff --git a/Android.bp b/Android.bp index ebaa23e26..b425f81d2 100644 --- a/Android.bp +++ b/Android.bp @@ -21,35 +21,6 @@ // IN THE SOFTWARE. // -package { - default_applicable_licenses: ["external_libdrm_license"], -} - -// Added automatically by a large-scale-change that took the approach of -// 'apply every license found to every target'. While this makes sure we respect -// every license restriction, it may not be entirely correct. -// -// e.g. GPL in an MIT project might only apply to the contrib/ directory. -// -// Please consider splitting the single license below into multiple licenses, -// taking care not to lose any license_kind information, and overriding the -// default license using the 'licenses: [...]' property on targets as needed. -// -// For unused files, consider creating a 'fileGroup' with "//visibility:private" -// to attach the license to, and including a comment whether the files may be -// used in the current project. -// See: http://go/android-license-faq -license { - name: "external_libdrm_license", - visibility: [":__subpackages__"], - license_kinds: [ - "SPDX-license-identifier-BSD", - "SPDX-license-identifier-MIT", - "legacy_unencumbered", - ], - // large-scale-change unable to identify any license_text files -} - subdirs = ["*"] build = ["Android.sources.bp"] @@ -83,6 +54,10 @@ cc_library_headers { host_supported: true, defaults: ["libdrm_defaults"], export_include_dirs: ["include/drm", "android"], + apex_available: [ + "//apex_available:platform", + "com.android.virt", + ], } genrule { @@ -90,7 +65,7 @@ genrule { out: ["generated_static_table_fourcc.h"], srcs: ["include/drm/drm_fourcc.h"], tool_files: ["gen_table_fourcc.py"], - cmd: "python3 $(location gen_table_fourcc.py) $(location include/drm/drm_fourcc.h) $(out)", + cmd: "python3 $(location gen_table_fourcc.py) $(in) $(out)", } // Library for the device diff --git a/CleanSpec.mk b/CleanSpec.mk index aa1d752b1..28a11db4e 100644 --- a/CleanSpec.mk +++ b/CleanSpec.mk @@ -2,7 +2,3 @@ $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/include/libdrm) $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/include/freedreno) $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/SHARED_LIBRARIES/libdrm_*intermediates) $(call add-clean-step, rm -rf $(PRODUCT_OUT)/obj/STATIC_LIBRARIES/libdrm_*intermediates) - -# libdrm is moved from /system to /vendor -$(call add-clean-step, rm -rf $(PRODUCT_OUT)/system/lib/libdrm.so) -$(call add-clean-step, rm -rf $(PRODUCT_OUT)/system/lib64/libdrm.so) diff --git a/METADATA b/METADATA deleted file mode 100644 index d97975ca3..000000000 --- a/METADATA +++ /dev/null @@ -1,3 +0,0 @@ -third_party { - license_type: NOTICE -} diff --git a/Makefile.sources b/Makefile.sources deleted file mode 100644 index 55290fe99..000000000 --- a/Makefile.sources +++ /dev/null @@ -1,45 +0,0 @@ -LIBDRM_FILES := \ - xf86drm.c \ - xf86drmHash.c \ - xf86drmHash.h \ - xf86drmRandom.c \ - xf86drmRandom.h \ - xf86drmSL.c \ - xf86drmMode.c \ - xf86atomic.h \ - libdrm_macros.h \ - libdrm_lists.h \ - util_double_list.h \ - util_math.h - -LIBDRM_H_FILES := \ - libsync.h \ - xf86drm.h \ - xf86drmMode.h - -LIBDRM_INCLUDE_H_FILES := \ - include/drm/drm.h \ - include/drm/drm_fourcc.h \ - include/drm/drm_mode.h \ - include/drm/drm_sarea.h \ - include/drm/i915_drm.h \ - include/drm/mach64_drm.h \ - include/drm/mga_drm.h \ - include/drm/msm_drm.h \ - include/drm/nouveau_drm.h \ - include/drm/qxl_drm.h \ - include/drm/r128_drm.h \ - include/drm/radeon_drm.h \ - include/drm/amdgpu_drm.h \ - include/drm/savage_drm.h \ - include/drm/sis_drm.h \ - include/drm/tegra_drm.h \ - include/drm/vc4_drm.h \ - include/drm/via_drm.h \ - include/drm/virtgpu_drm.h - -LIBDRM_INCLUDE_ANDROID_H_FILES := \ - android/gralloc_handle.h - -LIBDRM_INCLUDE_VMWGFX_H_FILES := \ - include/drm/vmwgfx_drm.h diff --git a/OWNERS b/OWNERS deleted file mode 100644 index 7b4c82dcf..000000000 --- a/OWNERS +++ /dev/null @@ -1,5 +0,0 @@ -# Default code reviewers picked from top 3 or more developers. -# Please update this list if you find better candidates. -adelva@google.com -john.stultz@linaro.org -seanpaul@google.com diff --git a/README.rst b/README.rst index 746080319..7d80181ff 100644 --- a/README.rst +++ b/README.rst @@ -49,3 +49,15 @@ Then use ninja to build and install: If you are installing into a system location you will need to run install separately, and as root. + +AMDGPU ASIC table file +---------------------- + +The AMDGPU driver requires the `amdgpu.ids` file. It is usually located at +`$PREFIX/share/libdrm`, but it is possible to specify a set of alternative +paths at runtime by setting the `AMDGPU_ASIC_ID_TABLE_PATHS` environment +variable with one or more colon-separated paths where to search for the +`amdgpu.ids` file. + +For this option to be available, the C library must support secure_getenv() +function. In systems without it (like NetBSD), this option won't be available. \ No newline at end of file diff --git a/amdgpu/Android.bp b/amdgpu/Android.bp old mode 100644 new mode 100755 index 94f5668d8..976f03e9d --- a/amdgpu/Android.bp +++ b/amdgpu/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/amdgpu/Android.sources.bp b/amdgpu/Android.sources.bp old mode 100644 new mode 100755 index be85283d6..e2a2888be --- a/amdgpu/Android.sources.bp +++ b/amdgpu/Android.sources.bp @@ -3,13 +3,13 @@ cc_defaults { name: "libdrm_amdgpu_sources", srcs: [ - "amdgpu_asic_id.c", + "amdgpu_asic_id.c", "amdgpu_bo.c", "amdgpu_cs.c", "amdgpu_device.c", "amdgpu_gpu_info.c", "amdgpu_vamgr.c", - "amdgpu_vm.c", + "amdgpu_vm.c", "handle_table.c", ], } diff --git a/amdgpu/Makefile.sources b/amdgpu/Makefile.sources deleted file mode 100644 index d6df324a3..000000000 --- a/amdgpu/Makefile.sources +++ /dev/null @@ -1,14 +0,0 @@ -LIBDRM_AMDGPU_FILES := \ - amdgpu_asic_id.c \ - amdgpu_bo.c \ - amdgpu_cs.c \ - amdgpu_device.c \ - amdgpu_gpu_info.c \ - amdgpu_internal.h \ - amdgpu_vamgr.c \ - amdgpu_vm.c \ - handle_table.c \ - handle_table.h - -LIBDRM_AMDGPU_H_FILES := \ - amdgpu.h diff --git a/amdgpu/amdgpu-symbols.txt b/amdgpu/amdgpu-symbols.txt old mode 100644 new mode 100755 index 530b343be..60c7d0650 --- a/amdgpu/amdgpu-symbols.txt +++ b/amdgpu/amdgpu-symbols.txt @@ -14,6 +14,7 @@ amdgpu_bo_query_info amdgpu_bo_set_metadata amdgpu_bo_va_op amdgpu_bo_va_op_raw +amdgpu_bo_va_op_raw2 amdgpu_bo_wait_for_idle amdgpu_create_bo_from_user_mem amdgpu_cs_chunk_fence_info_to_data @@ -56,6 +57,7 @@ amdgpu_cs_wait_semaphore amdgpu_device_deinitialize amdgpu_device_get_fd amdgpu_device_initialize +amdgpu_device_initialize2 amdgpu_find_bo_by_cpu_mapping amdgpu_get_marketing_name amdgpu_query_buffer_size_alignment @@ -69,11 +71,22 @@ amdgpu_query_hw_ip_count amdgpu_query_hw_ip_info amdgpu_query_info amdgpu_query_sensor_info +amdgpu_query_uq_fw_area_info amdgpu_query_video_caps_info amdgpu_read_mm_registers +amdgpu_va_manager_alloc +amdgpu_va_manager_init +amdgpu_va_manager_init2 +amdgpu_va_manager_deinit +amdgpu_va_manager_query_sw_info amdgpu_va_range_alloc +amdgpu_va_range_alloc2 amdgpu_va_range_free amdgpu_va_get_start_addr amdgpu_va_range_query amdgpu_vm_reserve_vmid amdgpu_vm_unreserve_vmid +amdgpu_create_userqueue +amdgpu_free_userqueue +amdgpu_userq_signal +amdgpu_userq_wait diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h old mode 100644 new mode 100755 index 9bdbf366a..6efb7a7de --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -42,7 +42,10 @@ extern "C" { #endif struct drm_amdgpu_info_hw_ip; +struct drm_amdgpu_info_uq_fw_areas; struct drm_amdgpu_bo_list_entry; +struct drm_amdgpu_userq_signal; +struct drm_amdgpu_userq_wait; /*--------------------------------------------------------------------------*/ /* --------------------------- Defines ------------------------------------ */ @@ -102,6 +105,19 @@ enum amdgpu_gpu_va_range enum amdgpu_sw_info { amdgpu_sw_info_address32_hi = 0, + /** Query the PRT control bit when the half VA range is reserved for + * PRT when the device is initialized. This depends on the GFX version. + * A return value of ~0 should be ignored. + */ + amdgpu_sw_info_address_prt_wa_control_bit = 1, +}; + +enum amdgpu_va_manager_sw_info { + /** Query the PRT control bit when the half VA range is reserved for + * PRT with AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT. The default value of + * ~0 shouldn't be considered a valid value. + */ + amdgpu_va_manager_sw_info_address_prt_wa_control_bit = 0, }; /*--------------------------------------------------------------------------*/ @@ -138,6 +154,12 @@ typedef struct amdgpu_bo_list *amdgpu_bo_list_handle; */ typedef struct amdgpu_va *amdgpu_va_handle; +/** + * Define handle dealing with VA allocation. An amdgpu_device + * owns one of these, but they can also be used without a device. + */ +typedef struct amdgpu_va_manager *amdgpu_va_manager_handle; + /** * Define handle for semaphore */ @@ -527,6 +549,20 @@ int amdgpu_device_initialize(int fd, uint32_t *minor_version, amdgpu_device_handle *device_handle); +/** + * Same as amdgpu_device_initialize() except when deduplicate_device + * is false *and* fd points to a device that was already initialized. + * In this case, amdgpu_device_initialize would return the same + * amdgpu_device_handle while here amdgpu_device_initialize2 would + * return a new handle. + * amdgpu_device_initialize() should be preferred in most situations; + * the only use-case where not-deduplicating devices make sense is + * when one wants to have isolated device handles in the same process. + */ +int amdgpu_device_initialize2(int fd, bool deduplicate_device, + uint32_t *major_version, + uint32_t *minor_version, + amdgpu_device_handle *device_handle); /** * * When access to such library does not needed any more the special @@ -1152,6 +1188,26 @@ int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type, unsigned ip_instance, struct drm_amdgpu_info_hw_ip *info); +/** + * Query FW area related information. + * + * The return size is query-specific and depends on the "type" parameter. + * No more than "size" bytes is returned. + * + * \param dev - \c [in] Device handle. See #amdgpu_device_initialize() + * \param type - \c [in] AMDGPU_HW_IP_* + * \param ip_instance - \c [in] HW IP index. + * \param info - \c [out] The pointer to return value + * + * \return 0 on success\n + * <0 - Negative POSIX error code + * +*/ +int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev, + unsigned type, + unsigned ip_instance, + struct drm_amdgpu_info_uq_fw_areas *info); + /** * Query heap information * @@ -1410,6 +1466,60 @@ int amdgpu_va_range_query(amdgpu_device_handle dev, uint64_t *start, uint64_t *end); +/** + * Allocate a amdgpu_va_manager object. + * The returned object has be initialized with the amdgpu_va_manager_init + * before use. + * On release, amdgpu_va_manager_deinit needs to be called, then the memory + * can be released using free(). + */ +amdgpu_va_manager_handle amdgpu_va_manager_alloc(void); + +void amdgpu_va_manager_init(amdgpu_va_manager_handle va_mgr, + uint64_t low_va_offset, uint64_t low_va_max, + uint64_t high_va_offset, uint64_t high_va_max, + uint32_t virtual_address_alignment); + +#define AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT 0x1 + +void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr, + uint64_t low_va_offset, uint64_t low_va_max, + uint64_t high_va_offset, uint64_t high_va_max, + uint32_t virtual_address_alignment, + uint32_t flags); + +void amdgpu_va_manager_deinit(amdgpu_va_manager_handle va_mgr); + +/** + * Similar to #amdgpu_va_range_alloc() but allocates VA + * directly from an amdgpu_va_manager_handle instead of using + * the manager from an amdgpu_device. + */ + +int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr, + enum amdgpu_gpu_va_range va_range_type, + uint64_t size, + uint64_t va_base_alignment, + uint64_t va_base_required, + uint64_t *va_base_allocated, + amdgpu_va_handle *va_range_handle, + uint64_t flags); + +/** + * Query VA manager information. + * + * \param va_mgr - \c [in] VA manager + * \param info - \c [in] amdgpu_va_manager_sw_info_* + * \param value - \c [out] Pointer to the return value. + * + * \return 0 on success\n + * <0 - Negative POSIX error code + * +*/ +int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr, + enum amdgpu_va_manager_sw_info info, + void *value); + /** * VA mapping/unmapping for the buffer object * @@ -1460,6 +1570,42 @@ int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, uint64_t flags, uint32_t ops); +/** + * VA mapping/unmapping of buffer object for usermode queue. + * + * This is not a simple drop-in extension for amdgpu_bo_va_op; instead, all + * parameters are treated "raw2", i.e. size is not automatically aligned, and + * all flags must be specified explicitly. + * + * \param dev - \c [in] device handle + * \param bo - \c [in] BO handle (may be NULL) + * \param offset - \c [in] Start offset to map + * \param size - \c [in] Size to map + * \param addr - \c [in] Start virtual address. + * \param flags - \c [in] Supported flags for mapping/unmapping + * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP + * \param vm_timeline_syncobj_out - \c [out] syncobj handle for PT update fence + * \param vm_timeline_point - \c [in] input timeline point + * \param input_fence_syncobj_handles - \c [in] Array of syncobj handles for bo unmap, + * clear and replace + * \param num_syncobj_handles - \c [in] Number of syncobj handles + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * +*/ +int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops, + uint32_t vm_timeline_syncobj_out, + uint64_t vm_timeline_point, + uint64_t input_fence_syncobj_array_in, + uint32_t num_syncobj_handles_in); + /** * create semaphore * @@ -1891,6 +2037,65 @@ int amdgpu_vm_reserve_vmid(amdgpu_device_handle dev, uint32_t flags); */ int amdgpu_vm_unreserve_vmid(amdgpu_device_handle dev, uint32_t flags); +/** + * Create USERQUEUE + * \param dev - \c [in] device handle + * \param ip_type - \c [in] ip type + * \param doorbell_handle - \c [in] doorbell handle + * \param doorbell_offset - \c [in] doorbell index + * \param mqd_in - \c [in] MQD data + * \param queue_va - \c [in] Virtual address of queue + * \param queue_size - \c [in] userqueue size + * \param wptr_va - \c [in] Virtual address of wptr + * \param rptr_va - \c [in] Virtual address of rptr + * \param queue_id - \c [out] queue id + * + * \return 0 on success otherwise POSIX Error code + */ + +int amdgpu_create_userqueue(amdgpu_device_handle dev, + uint32_t ip_type, + uint32_t doorbell_handle, + uint32_t doorbell_offset, + uint64_t queue_va, + uint64_t queue_size, + uint64_t wptr_va, + uint64_t rptr_va, + void *mqd_in, + uint32_t flags, + uint32_t *queue_id); + +/** + * Free USERQUEUE + * \param dev - \c [in] device handle + * \param queue_id - \c [in] queue id + * + * \return 0 on success otherwise POSIX Error code + */ +int amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id); + +/** + * Signal USERQUEUE + * \param dev - \c [in] device handle + * \param signal_data - \c [in] pointer to struct drm_amdgpu_userq_signal + * to be filled by the caller + * + * \return 0 on success otherwise POSIX Error code + */ +int amdgpu_userq_signal(amdgpu_device_handle dev, + struct drm_amdgpu_userq_signal *signal_data); + +/** + * Wait USERQUEUE + * \param dev - \c [in] device handle + * \param wait_data - \c [in/out] pointer to struct drm_amdgpu_userq_wait + * to be filled by the caller + * + * \return 0 on success otherwise POSIX Error code + */ +int amdgpu_userq_wait(amdgpu_device_handle dev, + struct drm_amdgpu_userq_wait *wait_data); + #ifdef __cplusplus } #endif diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c old mode 100644 new mode 100755 index a5007ffc8..fed3a5312 --- a/amdgpu/amdgpu_asic_id.c +++ b/amdgpu/amdgpu_asic_id.c @@ -22,6 +22,11 @@ * */ +// secure_getenv requires _GNU_SOURCE +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + #include #include #include @@ -104,6 +109,168 @@ static int parse_one_line(struct amdgpu_device *dev, const char *line) return r; } +static void amdgpu_parse_proc_cpuinfo(struct amdgpu_device *dev) +{ + const char *search_key = "model name"; + const char *radeon_key = "Radeon"; + char *line = NULL; + size_t len = 0; + FILE *fp; + + fp = fopen("/proc/cpuinfo", "r"); + if (fp == NULL) { + fprintf(stderr, "%s\n", strerror(errno)); + return; + } + + while (getline(&line, &len, fp) != -1) { + char *saveptr; + char *value; + + if (strncmp(line, search_key, strlen(search_key))) + continue; + + /* check for parts that have both CPU and GPU information */ + value = strstr(line, radeon_key); + + /* get content after the first colon */ + if (value == NULL) { + value = strstr(line, ":"); + if (value == NULL) + continue; + value++; + } + + /* strip whitespace */ + while (*value == ' ' || *value == '\t') + value++; + saveptr = strchr(value, '\n'); + if (saveptr) + *saveptr = '\0'; + + /* Add AMD to the new string if it's missing from slicing/dicing */ + if (strncmp(value, "AMD", 3) != 0) { + char *tmp = malloc(strlen(value) + 5); + + if (!tmp) + break; + sprintf(tmp, "AMD %s", value); + dev->marketing_name = tmp; + } else + dev->marketing_name = strdup(value); + break; + } + + free(line); + fclose(fp); +} + +#if HAVE_SECURE_GETENV +static char *join_path(const char *dir, const char *file) { + size_t dir_len = strlen(dir); + size_t file_len = strlen(file); + char *full_path = NULL; + + int need_slash = ((dir_len > 0) && (dir[dir_len - 1] != '/')); + size_t total_len = dir_len + (need_slash ? 1 : 0) + file_len + 1; // +1 for null terminator + + if (dir_len == 0) { + return strdup(file); + } + + full_path = malloc(total_len); + if (!full_path) { + return NULL; // Memory allocation failed + } + + strcpy(full_path, dir); + if (need_slash) { + full_path[dir_len] = '/'; + dir_len++; + } + strcpy(full_path + dir_len, file); + + return full_path; +} + +static char **split_env_var(const char *env_var_content) +{ + char **ret = NULL; + char *dup_env_val; + int elements = 1; + int index = 1; + + if (!env_var_content || env_var_content[0] == '\0') + return NULL; + + for(char *p = (char *)env_var_content; *p; p++) { + if (*p == ':') + elements++; + } + + dup_env_val = strdup(env_var_content); + if (!dup_env_val) { + return NULL; + } + ret = malloc(sizeof(char *) * (elements + 1)); + ret[0] = dup_env_val; + for(char *p = (char *)dup_env_val; *p; p++) { + if (*p == ':') { + *p = 0; + ret[index++] = p + 1; + } + } + ret[index] = NULL; // ensure that the last element in the array is NULL + return ret; +} + +static void split_env_var_free(char **split_var) +{ + if (split_var) { + // remember that the first element also points to the whole duplicated string, + // which was modified in place by replacing ':' with '\0' characters + free(split_var[0]); + free(split_var); + } +} + +static char *find_asic_id_table(void) +{ + // first check the paths in AMDGPU_ASIC_ID_TABLE_PATHS environment variable + const char *amdgpu_asic_id_table_paths = secure_getenv("AMDGPU_ASIC_ID_TABLE_PATHS"); + const char *file_name = NULL; + char *found_path = NULL; + char **paths = NULL; + + if (!amdgpu_asic_id_table_paths) + return NULL; + + // extract the file name from AMDGPU_ASIC_ID_TABLE + file_name = strrchr(AMDGPU_ASIC_ID_TABLE, '/'); + if (!file_name) + return NULL; + file_name++; // skip the '/' + + paths = split_env_var(amdgpu_asic_id_table_paths); + if (!paths) + return NULL; + + // for each path, join with file_name and check if it exists + for (int i = 0; paths[i] != NULL; i++) { + char *full_path = join_path(paths[i], file_name); + if (!full_path) { + continue; + } + if (access(full_path, R_OK) == 0) { + found_path = full_path; + break; + } + } + split_env_var_free(paths); + return found_path; +} +#endif + void amdgpu_parse_asic_ids(struct amdgpu_device *dev) { FILE *fp; @@ -113,11 +280,21 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev) int line_num = 1; int r = 0; - fp = fopen(AMDGPU_ASIC_ID_TABLE, "r"); + char *amdgpu_asic_id_table_path = NULL; +#if HAVE_SECURE_GETENV + // if this system lacks secure_getenv(), don't allow extra paths + // for security reasons. + amdgpu_asic_id_table_path = find_asic_id_table(); +#endif + // if not found, use the default AMDGPU_ASIC_ID_TABLE path + if (!amdgpu_asic_id_table_path) + amdgpu_asic_id_table_path = strdup(AMDGPU_ASIC_ID_TABLE); + + fp = fopen(amdgpu_asic_id_table_path, "r"); if (!fp) { - fprintf(stderr, "%s: %s\n", AMDGPU_ASIC_ID_TABLE, + fprintf(stderr, "%s: %s\n", amdgpu_asic_id_table_path, strerror(errno)); - return; + goto get_cpu; } /* 1st valid line is file version */ @@ -132,7 +309,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev) continue; } - drmMsg("%s version: %s\n", AMDGPU_ASIC_ID_TABLE, line); + drmMsg("%s version: %s\n", amdgpu_asic_id_table_path, line); break; } @@ -150,7 +327,7 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev) if (r == -EINVAL) { fprintf(stderr, "Invalid format: %s: line %d: %s\n", - AMDGPU_ASIC_ID_TABLE, line_num, line); + amdgpu_asic_id_table_path, line_num, line); } else if (r && r != -EAGAIN) { fprintf(stderr, "%s: Cannot parse ASIC IDs: %s\n", __func__, strerror(-r)); @@ -158,4 +335,11 @@ void amdgpu_parse_asic_ids(struct amdgpu_device *dev) free(line); fclose(fp); + +get_cpu: + free(amdgpu_asic_id_table_path); + if (dev->info.ids_flags & AMDGPU_IDS_FLAGS_FUSION && + dev->marketing_name == NULL) { + amdgpu_parse_proc_cpuinfo(dev); + } } diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c old mode 100644 new mode 100755 index 672f000d6..74e639849 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -74,6 +74,9 @@ drm_public int amdgpu_bo_alloc(amdgpu_device_handle dev, union drm_amdgpu_gem_create args; int r; + if (!alloc_buffer || !buf_handle) + return -EINVAL; + memset(&args, 0, sizeof(args)); args.in.bo_size = alloc_buffer->alloc_size; args.in.alignment = alloc_buffer->phys_alignment; @@ -105,6 +108,9 @@ drm_public int amdgpu_bo_set_metadata(amdgpu_bo_handle bo, { struct drm_amdgpu_gem_metadata args = {}; + if (!info) + return -EINVAL; + args.handle = bo->handle; args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA; args.data.flags = info->flags; @@ -132,7 +138,7 @@ drm_public int amdgpu_bo_query_info(amdgpu_bo_handle bo, int r; /* Validate the BO passed in */ - if (!bo->handle) + if (!bo->handle || !info) return -EINVAL; /* Query metadata. */ @@ -642,7 +648,7 @@ drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev, unsigned i; int r; - if (!number_of_resources) + if (!number_of_resources || !resources) return -EINVAL; /* overflow check for multiplication */ @@ -789,3 +795,39 @@ drm_public int amdgpu_bo_va_op_raw(amdgpu_device_handle dev, return r; } + +drm_public int amdgpu_bo_va_op_raw2(amdgpu_device_handle dev, + amdgpu_bo_handle bo, + uint64_t offset, + uint64_t size, + uint64_t addr, + uint64_t flags, + uint32_t ops, + uint32_t vm_timeline_syncobj_out, + uint64_t vm_timeline_point, + uint64_t input_fence_syncobj_handles, + uint32_t num_syncobj_handles) +{ + struct drm_amdgpu_gem_va va; + int r; + + if (ops != AMDGPU_VA_OP_MAP && ops != AMDGPU_VA_OP_UNMAP && + ops != AMDGPU_VA_OP_REPLACE && ops != AMDGPU_VA_OP_CLEAR) + return -EINVAL; + + memset(&va, 0, sizeof(va)); + va.handle = bo ? bo->handle : 0; + va.operation = ops; + va.flags = flags; + va.va_address = addr; + va.offset_in_bo = offset; + va.map_size = size; + va.vm_timeline_syncobj_out = vm_timeline_syncobj_out; + va.vm_timeline_point = vm_timeline_point; + va.input_fence_syncobj_handles = input_fence_syncobj_handles; + va.num_syncobj_handles = num_syncobj_handles; + + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_GEM_VA, &va, sizeof(va)); + + return r; +} diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c old mode 100644 new mode 100755 index 49fc16c3e..2db49675e --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -598,24 +598,31 @@ drm_public int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx, uint32_t ring, amdgpu_semaphore_handle sem) { + int ret; + if (!ctx || !sem) return -EINVAL; if (ip_type >= AMDGPU_HW_IP_NUM) return -EINVAL; if (ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; - /* sem has been signaled */ - if (sem->signal_fence.context) - return -EINVAL; + pthread_mutex_lock(&ctx->sequence_mutex); + /* sem has been signaled */ + if (sem->signal_fence.context) { + ret = -EINVAL; + goto unlock; + } sem->signal_fence.context = ctx; sem->signal_fence.ip_type = ip_type; sem->signal_fence.ip_instance = ip_instance; sem->signal_fence.ring = ring; sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring]; update_references(NULL, &sem->refcount); + ret = 0; +unlock: pthread_mutex_unlock(&ctx->sequence_mutex); - return 0; + return ret; } drm_public int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx, diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c old mode 100644 new mode 100755 index aeb5e3c54..b7d5589a9 --- a/amdgpu/amdgpu_device.c +++ b/amdgpu/amdgpu_device.c @@ -95,22 +95,26 @@ static int amdgpu_get_auth(int fd, int *auth) static void amdgpu_device_free_internal(amdgpu_device_handle dev) { - amdgpu_device_handle *node = &dev_list; - - pthread_mutex_lock(&dev_mutex); - while (*node != dev && (*node)->next) - node = &(*node)->next; - *node = (*node)->next; - pthread_mutex_unlock(&dev_mutex); + /* Remove dev from dev_list, if it was added there. */ + if (dev == dev_list) { + dev_list = dev->next; + } else { + for (amdgpu_device_handle node = dev_list; node; node = node->next) { + if (node->next == dev) { + node->next = dev->next; + break; + } + } + } close(dev->fd); if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd)) close(dev->flink_fd); - amdgpu_vamgr_deinit(&dev->vamgr_32); - amdgpu_vamgr_deinit(&dev->vamgr); - amdgpu_vamgr_deinit(&dev->vamgr_high_32); - amdgpu_vamgr_deinit(&dev->vamgr_high); + amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_32); + amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_low); + amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high_32); + amdgpu_vamgr_deinit(&dev->va_mgr.vamgr_high); handle_table_fini(&dev->bo_handles); handle_table_fini(&dev->bo_flink_names); pthread_mutex_destroy(&dev->bo_table_mutex); @@ -140,22 +144,58 @@ static void amdgpu_device_reference(struct amdgpu_device **dst, *dst = src; } -drm_public int amdgpu_device_initialize(int fd, - uint32_t *major_version, - uint32_t *minor_version, - amdgpu_device_handle *device_handle) +static int amdgpu_query_gfx_level_major(amdgpu_device_handle dev, + uint8_t *gfx_ip_version_major) +{ + struct drm_amdgpu_info_hw_ip ip_info; + uint32_t gfx_ip_count = 0; + int r; + + *gfx_ip_version_major = 0; + + r = amdgpu_query_hw_ip_count(dev, AMDGPU_HW_IP_GFX, &gfx_ip_count); + if (r) + return r; + + /* No graphics support. */ + if (gfx_ip_count == 0) + return 0; + + memset(&ip_info, 0, sizeof(ip_info)); + + r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &ip_info); + if (r) + return r; + + /* GFX6-8 don't set ip_discovery_version. */ + if (dev->minor_version >= 48 && ip_info.ip_discovery_version) { + *gfx_ip_version_major = (ip_info.ip_discovery_version >> 16) & 0xff; + } else { + *gfx_ip_version_major = ip_info.hw_ip_version_major; + } + + return r; +} + +static int _amdgpu_device_initialize(int fd, + uint32_t *major_version, + uint32_t *minor_version, + amdgpu_device_handle *device_handle, + bool deduplicate_device) { - struct amdgpu_device *dev; + struct amdgpu_device *dev = NULL; + uint8_t gfx_ip_version_major = 0; drmVersionPtr version; int r; int flag_auth = 0; int flag_authexist=0; uint32_t accel_working = 0; - uint64_t start, max; + uint32_t va_mgr_flags = 0; *device_handle = NULL; pthread_mutex_lock(&dev_mutex); + r = amdgpu_get_auth(fd, &flag_auth); if (r) { fprintf(stderr, "%s: amdgpu_get_auth (1) failed (%i)\n", @@ -164,9 +204,10 @@ drm_public int amdgpu_device_initialize(int fd, return r; } - for (dev = dev_list; dev; dev = dev->next) - if (fd_compare(dev->fd, fd) == 0) - break; + if (deduplicate_device) + for (dev = dev_list; dev; dev = dev->next) + if (fd_compare(dev->fd, fd) == 0) + break; if (dev) { r = amdgpu_get_auth(dev->fd, &flag_authexist); @@ -238,35 +279,35 @@ drm_public int amdgpu_device_initialize(int fd, goto cleanup; } - start = dev->dev_info.virtual_address_offset; - max = MIN2(dev->dev_info.virtual_address_max, 0x100000000ULL); - amdgpu_vamgr_init(&dev->vamgr_32, start, max, - dev->dev_info.virtual_address_alignment); - - start = max; - max = MAX2(dev->dev_info.virtual_address_max, 0x100000000ULL); - amdgpu_vamgr_init(&dev->vamgr, start, max, - dev->dev_info.virtual_address_alignment); - - start = dev->dev_info.high_va_offset; - max = MIN2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) + - 0x100000000ULL); - amdgpu_vamgr_init(&dev->vamgr_high_32, start, max, - dev->dev_info.virtual_address_alignment); + r = amdgpu_query_gfx_level_major(dev, &gfx_ip_version_major); + if (!r) { + /* Split the HIGH addr space for GFX6-GFX12, except GFX9 to + * implement a workaround for SMEM loads with NULL PRT pages. + * This is silently ignored if querying the GFX level failed. + */ + if (gfx_ip_version_major >= 6 && gfx_ip_version_major <= 12 && + gfx_ip_version_major != 9) { + va_mgr_flags |= AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT; + } + } - start = max; - max = MAX2(dev->dev_info.high_va_max, (start & ~0xffffffffULL) + - 0x100000000ULL); - amdgpu_vamgr_init(&dev->vamgr_high, start, max, - dev->dev_info.virtual_address_alignment); + amdgpu_va_manager_init2(&dev->va_mgr, + dev->dev_info.virtual_address_offset, + dev->dev_info.virtual_address_max, + dev->dev_info.high_va_offset, + dev->dev_info.high_va_max, + dev->dev_info.virtual_address_alignment, + va_mgr_flags); amdgpu_parse_asic_ids(dev); *major_version = dev->major_version; *minor_version = dev->minor_version; *device_handle = dev; - dev->next = dev_list; - dev_list = dev; + if (deduplicate_device) { + dev->next = dev_list; + dev_list = dev; + } pthread_mutex_unlock(&dev_mutex); return 0; @@ -279,9 +320,27 @@ drm_public int amdgpu_device_initialize(int fd, return r; } +drm_public int amdgpu_device_initialize(int fd, + uint32_t *major_version, + uint32_t *minor_version, + amdgpu_device_handle *device_handle) +{ + return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, true); +} + +drm_public int amdgpu_device_initialize2(int fd, bool deduplicate_device, + uint32_t *major_version, + uint32_t *minor_version, + amdgpu_device_handle *device_handle) +{ + return _amdgpu_device_initialize(fd, major_version, minor_version, device_handle, deduplicate_device); +} + drm_public int amdgpu_device_deinitialize(amdgpu_device_handle dev) { + pthread_mutex_lock(&dev_mutex); amdgpu_device_reference(&dev, NULL); + pthread_mutex_unlock(&dev_mutex); return 0; } @@ -306,10 +365,13 @@ drm_public int amdgpu_query_sw_info(amdgpu_device_handle dev, switch (info) { case amdgpu_sw_info_address32_hi: - if (dev->vamgr_high_32.va_max) - *val32 = (dev->vamgr_high_32.va_max - 1) >> 32; + if (dev->va_mgr.vamgr_high_32.va_max) + *val32 = (dev->va_mgr.vamgr_high_32.va_max - 1) >> 32; else - *val32 = (dev->vamgr_32.va_max - 1) >> 32; + *val32 = (dev->va_mgr.vamgr_32.va_max - 1) >> 32; + return 0; + case amdgpu_sw_info_address_prt_wa_control_bit: + *val32 = dev->va_mgr.address_prt_wa_control_bit; return 0; } return -EINVAL; diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c old mode 100644 new mode 100755 index 1a5143a60..62552a975 --- a/amdgpu/amdgpu_gpu_info.c +++ b/amdgpu/amdgpu_gpu_info.c @@ -137,6 +137,24 @@ drm_public int amdgpu_query_firmware_version(amdgpu_device_handle dev, return 0; } +drm_public int amdgpu_query_uq_fw_area_info(amdgpu_device_handle dev, + unsigned type, + unsigned ip_instance, + struct drm_amdgpu_info_uq_fw_areas *info) +{ + struct drm_amdgpu_info request; + + memset(&request, 0, sizeof(request)); + request.return_pointer = (uintptr_t)info; + request.return_size = sizeof(*info); + request.query = AMDGPU_INFO_UQ_FW_AREAS; + request.query_hw_ip.type = type; + request.query_hw_ip.ip_instance = ip_instance; + + return drmCommandWrite(dev->fd, DRM_AMDGPU_INFO, &request, + sizeof(struct drm_amdgpu_info)); +} + drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev) { int r, i; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h old mode 100644 new mode 100755 index 2834c9c6a..593b9f810 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -63,6 +63,22 @@ struct amdgpu_va { struct amdgpu_bo_va_mgr *vamgr; }; +struct amdgpu_va_manager { + /** The VA manager for the lower virtual address space */ + struct amdgpu_bo_va_mgr vamgr_low; + /** The VA manager for the 32bit address space */ + struct amdgpu_bo_va_mgr vamgr_32; + /** The VA manager for the high virtual address space */ + struct amdgpu_bo_va_mgr vamgr_high; + /** The VA manager for the 32bit high address space */ + struct amdgpu_bo_va_mgr vamgr_high_32; + + /** The bit to control whether it's the "LOW" or "HIGH" halves, when + * half of the address space is reserved for PRT to implement a SW + * workaround. */ + unsigned address_prt_wa_control_bit; +}; + struct amdgpu_device { atomic_t refcount; struct amdgpu_device *next; @@ -80,14 +96,8 @@ struct amdgpu_device { pthread_mutex_t bo_table_mutex; struct drm_amdgpu_info_device dev_info; struct amdgpu_gpu_info info; - /** The VA manager for the lower virtual address space */ - struct amdgpu_bo_va_mgr vamgr; - /** The VA manager for the 32bit address space */ - struct amdgpu_bo_va_mgr vamgr_32; - /** The VA manager for the high virtual address space */ - struct amdgpu_bo_va_mgr vamgr_high; - /** The VA manager for the 32bit high address space */ - struct amdgpu_bo_va_mgr vamgr_high_32; + + struct amdgpu_va_manager va_mgr; }; struct amdgpu_bo { diff --git a/amdgpu/amdgpu_userq.c b/amdgpu/amdgpu_userq.c new file mode 100755 index 000000000..123c979e0 --- /dev/null +++ b/amdgpu/amdgpu_userq.c @@ -0,0 +1,123 @@ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#include +#include +#include "xf86drm.h" +#include "amdgpu_drm.h" +#include "amdgpu_internal.h" + +drm_public int +amdgpu_create_userqueue(amdgpu_device_handle dev, + uint32_t ip_type, + uint32_t doorbell_handle, + uint32_t doorbell_offset, + uint64_t queue_va, + uint64_t queue_size, + uint64_t wptr_va, + uint64_t rptr_va, + void *mqd_in, + uint32_t flags, + uint32_t *queue_id) +{ + int ret; + union drm_amdgpu_userq userq; + uint64_t mqd_size; + + if (!dev) + return -EINVAL; + + switch (ip_type) { + case AMDGPU_HW_IP_GFX: + mqd_size = sizeof(struct drm_amdgpu_userq_mqd_gfx11); + break; + case AMDGPU_HW_IP_DMA: + mqd_size = sizeof(struct drm_amdgpu_userq_mqd_sdma_gfx11); + break; + case AMDGPU_HW_IP_COMPUTE: + mqd_size = sizeof(struct drm_amdgpu_userq_mqd_compute_gfx11); + break; + default: + return -EINVAL; + } + + memset(&userq, 0, sizeof(userq)); + + userq.in.op = AMDGPU_USERQ_OP_CREATE; + userq.in.ip_type = ip_type; + + userq.in.doorbell_handle = doorbell_handle; + userq.in.doorbell_offset = doorbell_offset; + + userq.in.queue_va = queue_va; + userq.in.queue_size = queue_size; + userq.in.wptr_va = wptr_va; + userq.in.rptr_va = rptr_va; + + userq.in.mqd = (uint64_t)mqd_in; + userq.in.mqd_size = mqd_size; + userq.in.flags = flags; + + ret = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ, + &userq, sizeof(userq)); + *queue_id = userq.out.queue_id; + + return ret; +} + +drm_public int +amdgpu_free_userqueue(amdgpu_device_handle dev, uint32_t queue_id) +{ + union drm_amdgpu_userq userq; + + memset(&userq, 0, sizeof(userq)); + userq.in.op = AMDGPU_USERQ_OP_FREE; + userq.in.queue_id = queue_id; + + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ, + &userq, sizeof(userq)); +} + +drm_public int +amdgpu_userq_signal(amdgpu_device_handle dev, + struct drm_amdgpu_userq_signal *signal_data) +{ + int r; + + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_SIGNAL, + signal_data, sizeof(struct drm_amdgpu_userq_signal)); + + return r; +} + +drm_public int +amdgpu_userq_wait(amdgpu_device_handle dev, + struct drm_amdgpu_userq_wait *wait_data) +{ + int r; + + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_USERQ_WAIT, + wait_data, sizeof(struct drm_amdgpu_userq_wait)); + + return r; +} diff --git a/amdgpu/amdgpu_vamgr.c b/amdgpu/amdgpu_vamgr.c old mode 100644 new mode 100755 index 2c4c9dbab..6e9cb654b --- a/amdgpu/amdgpu_vamgr.c +++ b/amdgpu/amdgpu_vamgr.c @@ -228,25 +228,40 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, uint64_t *va_base_allocated, amdgpu_va_handle *va_range_handle, uint64_t flags) +{ + return amdgpu_va_range_alloc2(&dev->va_mgr, va_range_type, size, + va_base_alignment, va_base_required, + va_base_allocated, va_range_handle, + flags); +} + +drm_public int amdgpu_va_range_alloc2(amdgpu_va_manager_handle va_mgr, + enum amdgpu_gpu_va_range va_range_type, + uint64_t size, + uint64_t va_base_alignment, + uint64_t va_base_required, + uint64_t *va_base_allocated, + amdgpu_va_handle *va_range_handle, + uint64_t flags) { struct amdgpu_bo_va_mgr *vamgr; bool search_from_top = !!(flags & AMDGPU_VA_RANGE_REPLAYABLE); int ret; /* Clear the flag when the high VA manager is not initialized */ - if (flags & AMDGPU_VA_RANGE_HIGH && !dev->vamgr_high_32.va_max) + if (flags & AMDGPU_VA_RANGE_HIGH && !va_mgr->vamgr_high_32.va_max) flags &= ~AMDGPU_VA_RANGE_HIGH; if (flags & AMDGPU_VA_RANGE_HIGH) { if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_high_32; + vamgr = &va_mgr->vamgr_high_32; else - vamgr = &dev->vamgr_high; + vamgr = &va_mgr->vamgr_high; } else { if (flags & AMDGPU_VA_RANGE_32_BIT) - vamgr = &dev->vamgr_32; + vamgr = &va_mgr->vamgr_32; else - vamgr = &dev->vamgr; + vamgr = &va_mgr->vamgr_low; } va_base_alignment = MAX2(va_base_alignment, vamgr->va_alignment); @@ -259,9 +274,9 @@ drm_public int amdgpu_va_range_alloc(amdgpu_device_handle dev, if (!(flags & AMDGPU_VA_RANGE_32_BIT) && ret) { /* fallback to 32bit address */ if (flags & AMDGPU_VA_RANGE_HIGH) - vamgr = &dev->vamgr_high_32; + vamgr = &va_mgr->vamgr_high_32; else - vamgr = &dev->vamgr_32; + vamgr = &va_mgr->vamgr_32; ret = amdgpu_vamgr_find_va(vamgr, size, va_base_alignment, va_base_required, search_from_top, va_base_allocated); @@ -300,3 +315,92 @@ drm_public uint64_t amdgpu_va_get_start_addr(amdgpu_va_handle va_handle) { return va_handle->address; } + +drm_public amdgpu_va_manager_handle amdgpu_va_manager_alloc(void) +{ + amdgpu_va_manager_handle r = calloc(1, sizeof(struct amdgpu_va_manager)); + return r; +} + +drm_public void amdgpu_va_manager_init(struct amdgpu_va_manager *va_mgr, + uint64_t low_va_offset, uint64_t low_va_max, + uint64_t high_va_offset, uint64_t high_va_max, + uint32_t virtual_address_alignment) +{ + amdgpu_va_manager_init2(va_mgr, low_va_offset, low_va_max, + high_va_offset, high_va_max, + virtual_address_alignment, 0); +} + +drm_public void amdgpu_va_manager_init2(struct amdgpu_va_manager *va_mgr, + uint64_t low_va_offset, uint64_t low_va_max, + uint64_t high_va_offset, uint64_t high_va_max, + uint32_t virtual_address_alignment, + uint32_t flags) +{ + uint64_t start, max; + + va_mgr->address_prt_wa_control_bit = ~0; + + start = low_va_offset; + max = MIN2(low_va_max, 0x100000000ULL); + amdgpu_vamgr_init(&va_mgr->vamgr_32, start, max, + virtual_address_alignment); + + start = max; + if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && !high_va_max) { + /* Reserve the half VA range for PRT by splitting it in two + * equal halves where one bit controls whether it's the LOW or + * HIGH half. + */ + va_mgr->address_prt_wa_control_bit = util_last_bit64(low_va_offset ^ low_va_max) - 1; + max = low_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit); + } else { + max = MAX2(low_va_max, 0x100000000ULL); + } + + amdgpu_vamgr_init(&va_mgr->vamgr_low, start, max, + virtual_address_alignment); + + start = high_va_offset; + max = MIN2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL); + amdgpu_vamgr_init(&va_mgr->vamgr_high_32, start, max, + virtual_address_alignment); + + start = max; + if ((flags & AMDGPU_VA_MGR_RESERVE_HALF_VA_FOR_PRT) && high_va_max) { + /* Reserve the half VA range for PRT by splitting it in two + * equal halves where one bit controls whether it's the LOW or + * HIGH half. + */ + va_mgr->address_prt_wa_control_bit = util_last_bit64(high_va_offset ^ high_va_max) - 1; + max = high_va_max ^ (1ull << va_mgr->address_prt_wa_control_bit); + } else { + max = MAX2(high_va_max, (start & ~0xffffffffULL) + 0x100000000ULL); + } + + amdgpu_vamgr_init(&va_mgr->vamgr_high, start, max, + virtual_address_alignment); +} + +drm_public void amdgpu_va_manager_deinit(struct amdgpu_va_manager *va_mgr) +{ + amdgpu_vamgr_deinit(&va_mgr->vamgr_32); + amdgpu_vamgr_deinit(&va_mgr->vamgr_low); + amdgpu_vamgr_deinit(&va_mgr->vamgr_high_32); + amdgpu_vamgr_deinit(&va_mgr->vamgr_high); +} + +drm_public int amdgpu_va_manager_query_sw_info(struct amdgpu_va_manager *va_mgr, + enum amdgpu_va_manager_sw_info info, + void *value) +{ + uint32_t *val32 = (uint32_t*)value; + + switch (info) { + case amdgpu_va_manager_sw_info_address_prt_wa_control_bit: + *val32 = va_mgr->address_prt_wa_control_bit; + return 0; + } + return -EINVAL; +} diff --git a/amdgpu/amdgpu_vm.c b/amdgpu/amdgpu_vm.c old mode 100644 new mode 100755 diff --git a/amdgpu/handle_table.c b/amdgpu/handle_table.c old mode 100644 new mode 100755 diff --git a/amdgpu/handle_table.h b/amdgpu/handle_table.h old mode 100644 new mode 100755 diff --git a/amdgpu/libdrm_amdgpu.pc.in b/amdgpu/libdrm_amdgpu.pc.in old mode 100644 new mode 100755 diff --git a/amdgpu/meson.build b/amdgpu/meson.build old mode 100644 new mode 100755 index 679de94d4..3962d32c2 --- a/amdgpu/meson.build +++ b/amdgpu/meson.build @@ -27,6 +27,7 @@ libdrm_amdgpu = library( files( 'amdgpu_asic_id.c', 'amdgpu_bo.c', 'amdgpu_cs.c', 'amdgpu_device.c', 'amdgpu_gpu_info.c', 'amdgpu_vamgr.c', 'amdgpu_vm.c', 'handle_table.c', + 'amdgpu_userq.c', ), config_file, ], @@ -37,7 +38,7 @@ libdrm_amdgpu = library( include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_threads, dep_atomic_ops, dep_rt], - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -55,9 +56,7 @@ ext_libdrm_amdgpu = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_amdgpu', ext_libdrm_amdgpu) -endif +meson.override_dependency('libdrm_amdgpu', ext_libdrm_amdgpu) test( 'amdgpu-symbols-check', diff --git a/data/Android.bp b/data/Android.bp index 8bb592110..47f64371a 100644 --- a/data/Android.bp +++ b/data/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - prebuilt_etc { name: "amdgpu.ids", proprietary: true, diff --git a/data/amdgpu.ids b/data/amdgpu.ids index 0e79a5832..978e5f746 100644 --- a/data/amdgpu.ids +++ b/data/amdgpu.ids @@ -4,6 +4,23 @@ # device_id, revision_id, product_name <-- single tab after comma 1.0.0 +1114, C2, AMD Radeon 860M Graphics +1114, C3, AMD Radeon 840M Graphics +1114, D2, AMD Radeon 860M Graphics +1114, D3, AMD Radeon 840M Graphics +1114, E2, AMD Radeon 860M Graphics +1114, E4, AMD Radeon 860M Graphics +1114, E5, AMD Radeon 840M Graphics +1114, E9, AMD Radeon 860M Graphics +1114, EA, AMD Radeon 840M Graphics +1114, ED, AMD Radeon 860M Graphics +1114, EE, AMD Radeon 840M Graphics +1114, F2, AMD Radeon 860M Graphics +1114, F3, AMD Radeon 840M Graphics +1114, F9, AMD Radeon 860M Graphics +1114, FA, AMD Radeon 840M Graphics +1114, FC, AMD Radeon 860M Graphics +1114, FD, AMD Radeon 840M Graphics 1309, 00, AMD Radeon R7 Graphics 130A, 00, AMD Radeon R6 Graphics 130B, 00, AMD Radeon R4 Graphics @@ -29,6 +46,89 @@ 131B, 00, AMD Radeon R4 Graphics 131C, 00, AMD Radeon R7 Graphics 131D, 00, AMD Radeon R6 Graphics +1435, AE, AMD Custom GPU 0932 +1506, C1, AMD Radeon 610M +1506, C2, AMD Radeon 610M +1506, C3, AMD Radeon 610M +1506, C4, AMD Radeon 610M +150E, C1, AMD Radeon 890M Graphics +150E, C4, AMD Radeon 880M Graphics +150E, C5, AMD Radeon 890M Graphics +150E, C6, AMD Radeon 890M Graphics +150E, C7, AMD Radeon 890M Graphics +150E, D1, AMD Radeon 890M Graphics +150E, D2, AMD Radeon 880M Graphics +150E, D3, AMD Radeon 890M Graphics +150E, E1, AMD Radeon 890M Graphics +150E, E3, AMD Radeon 890M Graphics +150E, E4, AMD Radeon 890M Graphics +150E, F1, AMD Radeon 890M Graphics +150E, F3, AMD Radeon 890M Graphics +1586, C1, AMD Radeon 8060S Graphics +1586, C2, AMD Radeon 8050S Graphics +1586, C3, AMD Radeon 8060S Graphics +1586, C4, AMD Radeon 8050S Graphics +1586, C6, AMD Radeon 8060S Graphics +1586, D1, AMD Radeon 8060S Graphics +1586, D2, AMD Radeon 8050S Graphics +1586, D4, AMD Radeon 8050S Graphics +1586, D5, AMD Radeon 8040S Graphics +15BF, 00, AMD Radeon 780M Graphics +15BF, 01, AMD Radeon 760M Graphics +15BF, 02, AMD Radeon 780M Graphics +15BF, 03, AMD Radeon 760M Graphics +15BF, 05, AMD Radeon 760M Graphics +15BF, 06, AMD Radeon 780M Graphics +15BF, 07, AMD Radeon 740M Graphics +15BF, 08, AMD Radeon 740M Graphics +15BF, C1, AMD Radeon 780M Graphics +15BF, C2, AMD Radeon 780M Graphics +15BF, C3, AMD Radeon 760M Graphics +15BF, C4, AMD Radeon 780M Graphics +15BF, C5, AMD Radeon 740M Graphics +15BF, C6, AMD Radeon 780M Graphics +15BF, C7, AMD Radeon 780M Graphics +15BF, C8, AMD Radeon 760M Graphics +15BF, C9, AMD Radeon 780M Graphics +15BF, CA, AMD Radeon 740M Graphics +15BF, CB, AMD Radeon 760M Graphics +15BF, CC, AMD Radeon 740M Graphics +15BF, CD, AMD Radeon 760M Graphics +15BF, CE, AMD Radeon 740M Graphics +15BF, CF, AMD Radeon 780M Graphics +15BF, D0, AMD Radeon 780M Graphics +15BF, D1, AMD Radeon 780M Graphics +15BF, D2, AMD Radeon 780M Graphics +15BF, D3, AMD Radeon 780M Graphics +15BF, D4, AMD Radeon 780M Graphics +15BF, D5, AMD Radeon 760M Graphics +15BF, D6, AMD Radeon 760M Graphics +15BF, D7, AMD Radeon 780M Graphics +15BF, D8, AMD Radeon 740M Graphics +15BF, D9, AMD Radeon 780M Graphics +15BF, DA, AMD Radeon 780M Graphics +15BF, DB, AMD Radeon 760M Graphics +15BF, DC, AMD Radeon 760M Graphics +15BF, DD, AMD Radeon 780M Graphics +15BF, DE, AMD Radeon 740M Graphics +15BF, DF, AMD Radeon 760M Graphics +15BF, F0, AMD Radeon 760M Graphics +15C8, C1, AMD Radeon 740M Graphics +15C8, C2, AMD Radeon 740M Graphics +15C8, C3, AMD Radeon 740M Graphics +15C8, C4, AMD Radeon 740M Graphics +15C8, C5, AMD Radeon 740M Graphics +15C8, C6, AMD Radeon 740M Graphics +15C8, C7, AMD Radeon 740M Graphics +15C8, C8, AMD Radeon 740M Graphics +15C8, D1, AMD Radeon 740M Graphics +15C8, D2, AMD Radeon 740M Graphics +15C8, D3, AMD Radeon 740M Graphics +15C8, D4, AMD Radeon 740M Graphics +15C8, D5, AMD Radeon 740M Graphics +15C8, D6, AMD Radeon 740M Graphics +15C8, D7, AMD Radeon 740M Graphics +15C8, D8, AMD Radeon 740M Graphics 15D8, 00, AMD Radeon RX Vega 8 Graphics WS 15D8, 91, AMD Radeon Vega 3 Graphics 15D8, 91, AMD Ryzen Embedded R1606G with Radeon Vega Gfx @@ -101,6 +201,102 @@ 15DD, E1, AMD Radeon Vega 3 Graphics 15DD, E2, AMD Radeon Vega 3 Graphics 163F, AE, AMD Custom GPU 0405 +163F, E1, AMD Custom GPU 0405 +164E, D8, AMD Radeon 610M +164E, D9, AMD Radeon 610M +164E, DA, AMD Radeon 610M +164E, DB, AMD Radeon 610M +164E, DC, AMD Radeon 610M +1681, 06, AMD Radeon 680M +1681, 07, AMD Radeon 660M +1681, 0A, AMD Radeon 680M +1681, 0B, AMD Radeon 660M +1681, C7, AMD Radeon 680M +1681, C8, AMD Radeon 680M +1681, C9, AMD Radeon 660M +1900, 01, AMD Radeon 780M Graphics +1900, 02, AMD Radeon 760M Graphics +1900, 03, AMD Radeon 780M Graphics +1900, 04, AMD Radeon 760M Graphics +1900, 05, AMD Radeon 780M Graphics +1900, 06, AMD Radeon 780M Graphics +1900, 07, AMD Radeon 760M Graphics +1900, B0, AMD Radeon 780M Graphics +1900, B1, AMD Radeon 780M Graphics +1900, B2, AMD Radeon 780M Graphics +1900, B3, AMD Radeon 780M Graphics +1900, B4, AMD Radeon 780M Graphics +1900, B5, AMD Radeon 780M Graphics +1900, B6, AMD Radeon 780M Graphics +1900, B7, AMD Radeon 760M Graphics +1900, B8, AMD Radeon 760M Graphics +1900, B9, AMD Radeon 780M Graphics +1900, BA, AMD Radeon 780M Graphics +1900, BB, AMD Radeon 780M Graphics +1900, C0, AMD Radeon 780M Graphics +1900, C1, AMD Radeon 760M Graphics +1900, C2, AMD Radeon 780M Graphics +1900, C3, AMD Radeon 760M Graphics +1900, C4, AMD Radeon 780M Graphics +1900, C5, AMD Radeon 780M Graphics +1900, C6, AMD Radeon 760M Graphics +1900, C7, AMD Radeon 780M Graphics +1900, C8, AMD Radeon 760M Graphics +1900, C9, AMD Radeon 780M Graphics +1900, CA, AMD Radeon 760M Graphics +1900, CB, AMD Radeon 780M Graphics +1900, CC, AMD Radeon 780M Graphics +1900, CD, AMD Radeon 760M Graphics +1900, CE, AMD Radeon 780M Graphics +1900, CF, AMD Radeon 760M Graphics +1900, D0, AMD Radeon 780M Graphics +1900, D1, AMD Radeon 760M Graphics +1900, D2, AMD Radeon 780M Graphics +1900, D3, AMD Radeon 760M Graphics +1900, D4, AMD Radeon 780M Graphics +1900, D5, AMD Radeon 780M Graphics +1900, D6, AMD Radeon 760M Graphics +1900, D7, AMD Radeon 780M Graphics +1900, D8, AMD Radeon 760M Graphics +1900, D9, AMD Radeon 780M Graphics +1900, DA, AMD Radeon 760M Graphics +1900, DB, AMD Radeon 780M Graphics +1900, DC, AMD Radeon 780M Graphics +1900, DD, AMD Radeon 760M Graphics +1900, DE, AMD Radeon 780M Graphics +1900, DF, AMD Radeon 760M Graphics +1900, F0, AMD Radeon 780M Graphics +1900, F1, AMD Radeon 780M Graphics +1900, F2, AMD Radeon 780M Graphics +1901, C1, AMD Radeon 740M Graphics +1901, C2, AMD Radeon 740M Graphics +1901, C3, AMD Radeon 740M Graphics +1901, C6, AMD Radeon 740M Graphics +1901, C7, AMD Radeon 740M Graphics +1901, C8, AMD Radeon 740M Graphics +1901, C9, AMD Radeon 740M Graphics +1901, CA, AMD Radeon 740M Graphics +1901, D1, AMD Radeon 740M Graphics +1901, D2, AMD Radeon 740M Graphics +1901, D3, AMD Radeon 740M Graphics +1901, D4, AMD Radeon 740M Graphics +1901, D5, AMD Radeon 740M Graphics +1901, D6, AMD Radeon 740M Graphics +1901, D7, AMD Radeon 740M Graphics +1901, D8, AMD Radeon 740M Graphics +1902, C0, AMD Radeon 840M Graphics +1902, C1, AMD Radeon 840M Graphics +1902, C2, AMD Radeon 820M Graphics +1902, C3, AMD Radeon 840M Graphics +1902, C6, AMD Radeon 820M Graphics +1902, C7, AMD Radeon 840M Graphics +1902, C8, AMD Radeon 840M Graphics +1902, C9, AMD Radeon 820M Graphics +1902, CA, AMD Radeon 840M Graphics +1902, D1, AMD Radeon 840M Graphics +1902, D3, AMD Radeon 840M Graphics +1902, D7, AMD Radeon 840M Graphics +1902, D8, AMD Radeon 840M Graphics 6600, 00, AMD Radeon HD 8600 / 8700M 6600, 81, AMD Radeon R7 M370 6601, 00, AMD Radeon HD 8500M / 8700M @@ -357,7 +553,7 @@ 73A1, 00, AMD Radeon Pro V620 73A3, 00, AMD Radeon Pro W6800 73A5, C0, AMD Radeon RX 6950 XT -73AE, 00, AMD Radeon Pro V620 +73AE, 00, AMD Radeon Pro V620 MxGPU 73AF, C0, AMD Radeon RX 6900 XT 73BF, C0, AMD Radeon RX 6900 XT 73BF, C1, AMD Radeon RX 6800 XT @@ -368,7 +564,12 @@ 73DF, C3, AMD Radeon RX 6800M 73DF, C5, AMD Radeon RX 6700 XT 73DF, CF, AMD Radeon RX 6700M +73DF, D5, AMD Radeon RX 6750 GRE 12GB 73DF, D7, AMD TDC-235 +73DF, DF, AMD Radeon RX 6700 +73DF, E5, AMD Radeon RX 6750 GRE 12GB +73DF, FF, AMD Radeon RX 6700 +73E0, 00, AMD Radeon RX 6600M 73E1, 00, AMD Radeon Pro W6600M 73E3, 00, AMD Radeon Pro W6600 73EF, C0, AMD Radeon RX 6800S @@ -380,6 +581,8 @@ 73FF, C3, AMD Radeon RX 6600M 73FF, C7, AMD Radeon RX 6600 73FF, CB, AMD Radeon RX 6600S +73FF, CF, AMD Radeon RX 6600 LE +73FF, DF, AMD Radeon RX 6750 GRE 10GB 7408, 00, AMD Instinct MI250X 740C, 01, AMD Instinct MI250X / MI250 740F, 02, AMD Instinct MI210 @@ -394,22 +597,60 @@ 743F, C7, AMD Radeon RX 6400 743F, C8, AMD Radeon RX 6500M 743F, CC, AMD Radeon 6550S +743F, CE, AMD Radeon RX 6450M 743F, CF, AMD Radeon RX 6300M +743F, D3, AMD Radeon RX 6550M 743F, D7, AMD Radeon RX 6400 7448, 00, AMD Radeon Pro W7900 +7449, 00, AMD Radeon Pro W7800 48GB +744A, 00, AMD Radeon Pro W7900 Dual Slot +744B, 00, AMD Radeon Pro W7900D 744C, C8, AMD Radeon RX 7900 XTX 744C, CC, AMD Radeon RX 7900 XT 744C, CE, AMD Radeon RX 7900 GRE +744C, CF, AMD Radeon RX 7900M 745E, CC, AMD Radeon Pro W7800 +7460, 00, AMD Radeon Pro V710 +7461, 00, AMD Radeon Pro V710 MxGPU +7470, 00, AMD Radeon Pro W7700 747E, C8, AMD Radeon RX 7800 XT +747E, D8, AMD Radeon RX 7800M +747E, DB, AMD Radeon RX 7700 747E, FF, AMD Radeon RX 7700 XT 7480, 00, AMD Radeon Pro W7600 +7480, C0, AMD Radeon RX 7600 XT 7480, C1, AMD Radeon RX 7700S +7480, C2, AMD Radeon RX 7650 GRE 7480, C3, AMD Radeon RX 7600S 7480, C7, AMD Radeon RX 7600M XT 7480, CF, AMD Radeon RX 7600 +7481, C7, AMD Steam Machine 7483, CF, AMD Radeon RX 7600M 7489, 00, AMD Radeon Pro W7500 +7499, 00, AMD Radeon Pro W7400 +7499, C0, AMD Radeon RX 7400 +7499, C1, AMD Radeon RX 7300 +74A0, 00, AMD Instinct MI300A +74A1, 00, AMD Instinct MI300X +74A2, 00, AMD Instinct MI308X +74A5, 00, AMD Instinct MI325X +74A8, 00, AMD Instinct MI308X HF +74A9, 00, AMD Instinct MI300X HF +74B5, 00, AMD Instinct MI300X VF +74B6, 00, AMD Instinct MI308X +74BD, 00, AMD Instinct MI300X HF +7550, C0, AMD Radeon RX 9070 XT +7550, C2, AMD Radeon RX 9070 GRE +7550, C3, AMD Radeon RX 9070 +7551, C0, AMD Radeon AI PRO R9700 +7551, C8, AMD Radeon AI PRO R9600D +7590, C0, AMD Radeon RX 9060 XT +7590, C1, AMD Radeon RX 9060 XT LP +7590, C7, AMD Radeon RX 9060 +75A0, 00, AMD Instinct MI350X +75A3, 00, AMD Instinct MI355X +75B0, 00, AMD Instinct MI350X VF +75B3, 00, AMD Instinct MI355X VF 9830, 00, AMD Radeon HD 8400 / R3 Series 9831, 00, AMD Radeon HD 8400E 9832, 00, AMD Radeon HD 8330 diff --git a/etnaviv/Android.bp b/etnaviv/Android.bp old mode 100644 new mode 100755 index d8d04af1d..21deda999 --- a/etnaviv/Android.bp +++ b/etnaviv/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/etnaviv/Android.sources.bp b/etnaviv/Android.sources.bp old mode 100644 new mode 100755 diff --git a/etnaviv/Makefile.sources b/etnaviv/Makefile.sources deleted file mode 100644 index 3ff2fbe5a..000000000 --- a/etnaviv/Makefile.sources +++ /dev/null @@ -1,12 +0,0 @@ -LIBDRM_ETNAVIV_FILES := \ - etnaviv_device.c \ - etnaviv_gpu.c \ - etnaviv_bo.c \ - etnaviv_bo_cache.c \ - etnaviv_perfmon.c \ - etnaviv_pipe.c \ - etnaviv_cmd_stream.c \ - etnaviv_priv.h - -LIBDRM_ETNAVIV_H_FILES := \ - etnaviv_drmif.h diff --git a/etnaviv/etnaviv-symbols.txt b/etnaviv/etnaviv-symbols.txt old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_bo.c b/etnaviv/etnaviv_bo.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_bo_cache.c b/etnaviv/etnaviv_bo_cache.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_cmd_stream.c b/etnaviv/etnaviv_cmd_stream.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_device.c b/etnaviv/etnaviv_device.c old mode 100644 new mode 100755 index 699df256f..052a2e206 --- a/etnaviv/etnaviv_device.c +++ b/etnaviv/etnaviv_device.c @@ -25,8 +25,7 @@ */ #include -#include -#include +#include #include #include #include diff --git a/etnaviv/etnaviv_drmif.h b/etnaviv/etnaviv_drmif.h old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_gpu.c b/etnaviv/etnaviv_gpu.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_perfmon.c b/etnaviv/etnaviv_perfmon.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_pipe.c b/etnaviv/etnaviv_pipe.c old mode 100644 new mode 100755 diff --git a/etnaviv/etnaviv_priv.h b/etnaviv/etnaviv_priv.h old mode 100644 new mode 100755 index fd49b959b..eef7f49c0 --- a/etnaviv/etnaviv_priv.h +++ b/etnaviv/etnaviv_priv.h @@ -45,7 +45,7 @@ #include "util_double_list.h" #include "etnaviv_drmif.h" -#include +#include "etnaviv_drm.h" struct etna_bo_bucket { uint32_t size; diff --git a/etnaviv/libdrm_etnaviv.pc.in b/etnaviv/libdrm_etnaviv.pc.in old mode 100644 new mode 100755 diff --git a/etnaviv/meson.build b/etnaviv/meson.build old mode 100644 new mode 100755 index 9ccf8696e..7d56bce2c --- a/etnaviv/meson.build +++ b/etnaviv/meson.build @@ -33,7 +33,7 @@ libdrm_etnaviv = library( c_args : libdrm_c_args, gnu_symbol_visibility : 'hidden', dependencies : [dep_threads, dep_rt, dep_atomic_ops], - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -51,9 +51,7 @@ ext_libdrm_etnaviv = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_etnaviv', ext_libdrm_etnaviv) -endif +meson.override_dependency('libdrm_etnaviv', ext_libdrm_etnaviv) test( 'etnaviv-symbols-check', @@ -61,6 +59,6 @@ test( args : [ '--lib', libdrm_etnaviv, '--symbols-file', files('etnaviv-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/exynos/exynos_drm.c b/exynos/exynos_drm.c index 3e322a17b..fb4cd8de0 100644 --- a/exynos/exynos_drm.c +++ b/exynos/exynos_drm.c @@ -31,7 +31,6 @@ #include #include -#include #include diff --git a/exynos/exynos_fimg2d.c b/exynos/exynos_fimg2d.c index ac6fa6872..f0aee9629 100644 --- a/exynos/exynos_fimg2d.c +++ b/exynos/exynos_fimg2d.c @@ -30,7 +30,6 @@ #include #include -#include #include diff --git a/exynos/meson.build b/exynos/meson.build index 6b4fe1e92..64f76eab3 100644 --- a/exynos/meson.build +++ b/exynos/meson.build @@ -26,7 +26,7 @@ libdrm_exynos = library( include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_threads], - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -38,9 +38,7 @@ ext_libdrm_exynos = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_exynos', ext_libdrm_exynos) -endif +meson.override_dependency('libdrm_exynos', ext_libdrm_exynos) pkg.generate( libdrm_exynos, @@ -56,6 +54,6 @@ test( args : [ '--lib', libdrm_exynos, '--symbols-file', files('exynos-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/freedreno/Android.bp b/freedreno/Android.bp deleted file mode 100644 index ca7f3e28e..000000000 --- a/freedreno/Android.bp +++ /dev/null @@ -1,20 +0,0 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - -build = ["Android.sources.bp"] - -cc_library_shared { - name: "libdrm_freedreno", - defaults: [ - "libdrm_defaults", - "libdrm_freedreno_sources", - ], - vendor: true, - shared_libs: ["libdrm"], -} diff --git a/freedreno/Android.sources.bp b/freedreno/Android.sources.bp deleted file mode 100644 index 3c1ca316a..000000000 --- a/freedreno/Android.sources.bp +++ /dev/null @@ -1,16 +0,0 @@ -// Autogenerated with Android.sources.bp.mk - -cc_defaults { - name: "libdrm_freedreno_sources", - srcs: [ - "freedreno_device.c", - "freedreno_pipe.c", - "freedreno_ringbuffer.c", - "freedreno_bo.c", - "freedreno_bo_cache.c", - "msm/msm_bo.c", - "msm/msm_device.c", - "msm/msm_pipe.c", - "msm/msm_ringbuffer.c", - ], -} diff --git a/freedreno/Makefile.sources b/freedreno/Makefile.sources deleted file mode 100644 index ca89511a0..000000000 --- a/freedreno/Makefile.sources +++ /dev/null @@ -1,25 +0,0 @@ -LIBDRM_FREEDRENO_FILES := \ - freedreno_device.c \ - freedreno_pipe.c \ - freedreno_priv.h \ - freedreno_ringbuffer.c \ - freedreno_bo.c \ - freedreno_bo_cache.c \ - msm/msm_bo.c \ - msm/msm_device.c \ - msm/msm_pipe.c \ - msm/msm_priv.h \ - msm/msm_ringbuffer.c - -LIBDRM_FREEDRENO_KGSL_FILES := \ - kgsl/kgsl_bo.c \ - kgsl/kgsl_device.c \ - kgsl/kgsl_drm.h \ - kgsl/kgsl_pipe.c \ - kgsl/kgsl_priv.h \ - kgsl/kgsl_ringbuffer.c \ - kgsl/msm_kgsl.h - -LIBDRM_FREEDRENO_H_FILES := \ - freedreno_drmif.h \ - freedreno_ringbuffer.h diff --git a/freedreno/freedreno-symbols.txt b/freedreno/freedreno-symbols.txt old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_bo.c b/freedreno/freedreno_bo.c old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_bo_cache.c b/freedreno/freedreno_bo_cache.c old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_device.c b/freedreno/freedreno_device.c old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_drmif.h b/freedreno/freedreno_drmif.h old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_pipe.c b/freedreno/freedreno_pipe.c old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_priv.h b/freedreno/freedreno_priv.h old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_ringbuffer.c b/freedreno/freedreno_ringbuffer.c old mode 100644 new mode 100755 diff --git a/freedreno/freedreno_ringbuffer.h b/freedreno/freedreno_ringbuffer.h old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/README b/freedreno/kgsl/README old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/kgsl_bo.c b/freedreno/kgsl/kgsl_bo.c old mode 100644 new mode 100755 index 7a6af2f08..55b6e5c0f --- a/freedreno/kgsl/kgsl_bo.c +++ b/freedreno/kgsl/kgsl_bo.c @@ -28,8 +28,6 @@ #include "kgsl_priv.h" -#include - static int set_memtype(struct fd_device *dev, uint32_t handle, uint32_t flags) { struct drm_kgsl_gem_memtype req = { diff --git a/freedreno/kgsl/kgsl_device.c b/freedreno/kgsl/kgsl_device.c old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/kgsl_drm.h b/freedreno/kgsl/kgsl_drm.h old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/kgsl_pipe.c b/freedreno/kgsl/kgsl_pipe.c old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/kgsl_priv.h b/freedreno/kgsl/kgsl_priv.h old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/kgsl_ringbuffer.c b/freedreno/kgsl/kgsl_ringbuffer.c old mode 100644 new mode 100755 diff --git a/freedreno/kgsl/msm_kgsl.h b/freedreno/kgsl/msm_kgsl.h old mode 100644 new mode 100755 diff --git a/freedreno/libdrm_freedreno.pc.in b/freedreno/libdrm_freedreno.pc.in old mode 100644 new mode 100755 diff --git a/freedreno/meson.build b/freedreno/meson.build old mode 100644 new mode 100755 index 5ba1a3f11..156362efc --- a/freedreno/meson.build +++ b/freedreno/meson.build @@ -46,7 +46,7 @@ libdrm_freedreno = library( include_directories : [inc_root, inc_drm], dependencies : [dep_valgrind, dep_threads, dep_rt, dep_atomic_ops], link_with : libdrm, - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -55,9 +55,7 @@ ext_libdrm_freedreno = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_freedreno', ext_libdrm_freedreno) -endif +meson.override_dependency('libdrm_freedreno', ext_libdrm_freedreno) install_headers( 'freedreno_drmif.h', 'freedreno_ringbuffer.h', @@ -77,6 +75,6 @@ test( args : [ '--lib', libdrm_freedreno, '--symbols-file', files('freedreno-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/freedreno/msm/msm_bo.c b/freedreno/msm/msm_bo.c old mode 100644 new mode 100755 diff --git a/freedreno/msm/msm_device.c b/freedreno/msm/msm_device.c old mode 100644 new mode 100755 diff --git a/freedreno/msm/msm_pipe.c b/freedreno/msm/msm_pipe.c old mode 100644 new mode 100755 diff --git a/freedreno/msm/msm_priv.h b/freedreno/msm/msm_priv.h old mode 100644 new mode 100755 diff --git a/freedreno/msm/msm_ringbuffer.c b/freedreno/msm/msm_ringbuffer.c old mode 100644 new mode 100755 diff --git a/gen_table_fourcc.py b/gen_table_fourcc.py index 1473d437a..cb8f1626c 100644 --- a/gen_table_fourcc.py +++ b/gen_table_fourcc.py @@ -34,7 +34,7 @@ fm_re = { 'intel': r'^#define I915_FORMAT_MOD_(\w+)', - 'others': r'^#define DRM_FORMAT_MOD_((?:ARM|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s', + 'others': r'^#define DRM_FORMAT_MOD_((?:ARM|APPLE|SAMSUNG|QCOM|VIVANTE|NVIDIA|BROADCOM|ALLWINNER)\w+)\s', 'vendors': r'^#define DRM_FORMAT_MOD_VENDOR_(\w+)' } diff --git a/include/drm/README b/include/drm/README index ea2320cc9..750a5a5a4 100644 --- a/include/drm/README +++ b/include/drm/README @@ -71,7 +71,7 @@ Note: One should not do _any_ changes to the files apart from the steps below. In order to update the files do the following: - Switch to a Linux kernel tree/branch which is not rebased. - For example: drm-next (https://cgit.freedesktop.org/drm/drm) + For example: drm-next (https://gitlab.freedesktop.org/drm/kernel/) - Install the headers via `make headers_install' to a separate location. - Copy the drm header[s] + git add + git commit. - Note: Your commit message must include: diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h index ad21c613f..8db4df395 100644 --- a/include/drm/amdgpu_drm.h +++ b/include/drm/amdgpu_drm.h @@ -54,6 +54,9 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 #define DRM_AMDGPU_SCHED 0x15 +#define DRM_AMDGPU_USERQ 0x16 +#define DRM_AMDGPU_USERQ_SIGNAL 0x17 +#define DRM_AMDGPU_USERQ_WAIT 0x18 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) @@ -71,6 +74,9 @@ extern "C" { #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq) +#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) +#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) /** * DOC: memory domains @@ -317,6 +323,261 @@ union drm_amdgpu_ctx { union drm_amdgpu_ctx_out out; }; +/* user queue IOCTL operations */ +#define AMDGPU_USERQ_OP_CREATE 1 +#define AMDGPU_USERQ_OP_FREE 2 + +/* queue priority levels */ +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3 +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0 +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0 +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1 +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2 +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */ +/* for queues that need access to protected content */ +#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2) + +/* + * This structure is a container to pass input configuration + * info for all supported userqueue related operations. + * For operation AMDGPU_USERQ_OP_CREATE: user is expected + * to set all fields, excep the parameter 'queue_id'. + * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected + * to be set is 'queue_id', eveything else is ignored. + */ +struct drm_amdgpu_userq_in { + /** AMDGPU_USERQ_OP_* */ + __u32 op; + /** Queue id passed for operation USERQ_OP_FREE */ + __u32 queue_id; + /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */ + __u32 ip_type; + /** + * @doorbell_handle: the handle of doorbell GEM object + * associated to this userqueue client. + */ + __u32 doorbell_handle; + /** + * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo. + * Kernel will generate absolute doorbell offset using doorbell_handle + * and doorbell_offset in the doorbell bo. + */ + __u32 doorbell_offset; + /** + * @flags: flags used for queue parameters + */ + __u32 flags; + + /** + * @queue_va: Virtual address of the GPU memory which holds the queue + * object. The queue holds the workload packets. + */ + __u64 queue_va; + /** + * @queue_size: Size of the queue in bytes, this needs to be 256-byte + * aligned. + */ + __u64 queue_size; + /** + * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR. + * This object must be at least 8 byte in size and aligned to 8-byte offset. + */ + __u64 rptr_va; + /** + * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR. + * This object must be at least 8 byte in size and aligned to 8-byte offset. + * + * Queue, RPTR and WPTR can come from the same object, as long as the size + * and alignment related requirements are met. + */ + __u64 wptr_va; + /** + * @mqd: MQD (memory queue descriptor) is a set of parameters which allow + * the GPU to uniquely define and identify a usermode queue. + * + * MQD data can be of different size for different GPU IP/engine and + * their respective versions/revisions, so this points to a __u64 * + * which holds IP specific MQD of this usermode queue. + */ + __u64 mqd; + /** + * @size: size of MQD data in bytes, it must match the MQD structure + * size of the respective engine/revision defined in UAPI for ex, for + * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11). + */ + __u64 mqd_size; +}; + +/* The structure to carry output of userqueue ops */ +struct drm_amdgpu_userq_out { + /** + * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique + * queue ID to represent the newly created userqueue in the system, otherwise + * it should be ignored. + */ + __u32 queue_id; + __u32 _pad; +}; + +union drm_amdgpu_userq { + struct drm_amdgpu_userq_in in; + struct drm_amdgpu_userq_out out; +}; + +/* GFX V11 IP specific MQD parameters */ +struct drm_amdgpu_userq_mqd_gfx11 { + /** + * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer. + * Use AMDGPU_INFO_IOCTL to find the exact size of the object. + */ + __u64 shadow_va; + /** + * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. + * Use AMDGPU_INFO_IOCTL to find the exact size of the object. + */ + __u64 csa_va; +}; + +/* GFX V11 SDMA IP specific MQD parameters */ +struct drm_amdgpu_userq_mqd_sdma_gfx11 { + /** + * @csa_va: Virtual address of the GPU memory to hold the CSA buffer. + * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL + * to get the size. + */ + __u64 csa_va; +}; + +/* GFX V11 Compute IP specific MQD parameters */ +struct drm_amdgpu_userq_mqd_compute_gfx11 { + /** + * @eop_va: Virtual address of the GPU memory to hold the EOP buffer. + * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL + * to get the size. + */ + __u64 eop_va; +}; + +/* userq signal/wait ioctl */ +struct drm_amdgpu_userq_signal { + /** + * @queue_id: Queue handle used by the userq fence creation function + * to retrieve the WPTR. + */ + __u32 queue_id; + __u32 pad; + /** + * @syncobj_handles: The list of syncobj handles submitted by the user queue + * job to be signaled. + */ + __u64 syncobj_handles; + /** + * @num_syncobj_handles: A count that represents the number of syncobj handles in + * @syncobj_handles. + */ + __u64 num_syncobj_handles; + /** + * @bo_read_handles: The list of BO handles that the submitted user queue job + * is using for read only. This will update BO fences in the kernel. + */ + __u64 bo_read_handles; + /** + * @bo_write_handles: The list of BO handles that the submitted user queue job + * is using for write only. This will update BO fences in the kernel. + */ + __u64 bo_write_handles; + /** + * @num_bo_read_handles: A count that represents the number of read BO handles in + * @bo_read_handles. + */ + __u32 num_bo_read_handles; + /** + * @num_bo_write_handles: A count that represents the number of write BO handles in + * @bo_write_handles. + */ + __u32 num_bo_write_handles; + +}; + +struct drm_amdgpu_userq_fence_info { + /** + * @va: A gpu address allocated for each queue which stores the + * read pointer (RPTR) value. + */ + __u64 va; + /** + * @value: A 64 bit value represents the write pointer (WPTR) of the + * queue commands which compared with the RPTR value to signal the + * fences. + */ + __u64 value; +}; + +struct drm_amdgpu_userq_wait { + /** + * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the + * wait queue and maintain the fence driver references in it. + */ + __u32 waitq_id; + __u32 pad; + /** + * @syncobj_handles: The list of syncobj handles submitted by the user queue + * job to get the va/value pairs. + */ + __u64 syncobj_handles; + /** + * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by + * the user queue job to get the va/value pairs at given @syncobj_timeline_points. + */ + __u64 syncobj_timeline_handles; + /** + * @syncobj_timeline_points: The list of timeline syncobj points submitted by the + * user queue job for the corresponding @syncobj_timeline_handles. + */ + __u64 syncobj_timeline_points; + /** + * @bo_read_handles: The list of read BO handles submitted by the user queue + * job to get the va/value pairs. + */ + __u64 bo_read_handles; + /** + * @bo_write_handles: The list of write BO handles submitted by the user queue + * job to get the va/value pairs. + */ + __u64 bo_write_handles; + /** + * @num_syncobj_timeline_handles: A count that represents the number of timeline + * syncobj handles in @syncobj_timeline_handles. + */ + __u16 num_syncobj_timeline_handles; + /** + * @num_fences: This field can be used both as input and output. As input it defines + * the maximum number of fences that can be returned and as output it will specify + * how many fences were actually returned from the ioctl. + */ + __u16 num_fences; + /** + * @num_syncobj_handles: A count that represents the number of syncobj handles in + * @syncobj_handles. + */ + __u32 num_syncobj_handles; + /** + * @num_bo_read_handles: A count that represents the number of read BO handles in + * @bo_read_handles. + */ + __u32 num_bo_read_handles; + /** + * @num_bo_write_handles: A count that represents the number of write BO handles in + * @bo_write_handles. + */ + __u32 num_bo_write_handles; + /** + * @out_fences: The field is a return value from the ioctl containing the list of + * address/value pairs to wait for. + */ + __u64 out_fences; +}; + /* vm ioctl */ #define AMDGPU_VM_OP_RESERVE_VMID 1 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 @@ -392,7 +653,7 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 -/* GFX9 and later: */ +/* GFX9 - GFX11: */ #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 @@ -406,6 +667,17 @@ struct drm_amdgpu_gem_userptr { #define AMDGPU_TILING_SCANOUT_SHIFT 63 #define AMDGPU_TILING_SCANOUT_MASK 0x1 +/* GFX12 and later: */ +#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0 +#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7 +/* These are DCC recompression setting for memory management: */ +#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3 +#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */ +#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5 +#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */ +#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8 +#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */ + /* Set/Get helpers for tiling flags. */ #define AMDGPU_TILING_SET(field, value) \ (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) @@ -579,6 +851,19 @@ struct drm_amdgpu_gem_va { __u64 offset_in_bo; /** Specify mapping size. Must be correctly aligned. */ __u64 map_size; + /** + * vm_timeline_point is a sequence number used to add new timeline point. + */ + __u64 vm_timeline_point; + /** + * The vm page table update fence is installed in given vm_timeline_syncobj_out + * at vm_timeline_point. + */ + __u32 vm_timeline_syncobj_out; + /** the number of syncobj handles in @input_fence_syncobj_handles */ + __u32 num_syncobj_handles; + /** Array of sync object handle to wait for given input fences */ + __u64 input_fence_syncobj_handles; }; #define AMDGPU_HW_IP_GFX 0 @@ -743,6 +1028,16 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_IDS_FLAGS_TMZ 0x4 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 +/* + * Query h/w info: Flag identifying VF/PF/PT mode + * + */ +#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 +#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 +#define AMDGPU_IDS_FLAGS_MODE_PF 0x0 +#define AMDGPU_IDS_FLAGS_MODE_VF 0x1 +#define AMDGPU_IDS_FLAGS_MODE_PT 0x2 + /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 /* get the crtc_id from the mode object id? */ @@ -865,6 +1160,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa /* Subquery id: Query GPU peak pstate memory clock */ #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb + /* Subquery id: Query input GPU power */ + #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc /* Number of VRAM page faults on CPU access. */ #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F @@ -908,6 +1205,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_MAX_IBS 0x22 /* query last page fault info */ #define AMDGPU_INFO_GPUVM_FAULT 0x23 +/* query FW object size and alignment */ +#define AMDGPU_INFO_UQ_FW_AREAS 0x24 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1166,6 +1465,9 @@ struct drm_amdgpu_info_device { __u32 csa_size; /* context save area base virtual alignment for gfx11 */ __u32 csa_alignment; + /* Userq IP mask (1 << AMDGPU_HW_IP_*) */ + __u32 userq_ip_mask; + __u32 pad; }; struct drm_amdgpu_info_hw_ip { @@ -1184,6 +1486,27 @@ struct drm_amdgpu_info_hw_ip { __u32 ip_discovery_version; }; +/* GFX metadata BO sizes and alignment info (in bytes) */ +struct drm_amdgpu_info_uq_fw_areas_gfx { + /* shadow area size */ + __u32 shadow_size; + /* shadow area base virtual mem alignment */ + __u32 shadow_alignment; + /* context save area size */ + __u32 csa_size; + /* context save area base virtual mem alignment */ + __u32 csa_alignment; +}; + +/* IP specific metadata related information used in the + * subquery AMDGPU_INFO_UQ_FW_AREAS + */ +struct drm_amdgpu_info_uq_fw_areas { + union { + struct drm_amdgpu_info_uq_fw_areas_gfx gfx; + }; +}; + struct drm_amdgpu_info_num_handles { /** Max handles as supported by firmware for UVD */ __u32 uvd_max_handles; @@ -1266,6 +1589,7 @@ struct drm_amdgpu_info_gpuvm_fault { #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ +#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ #if defined(__cplusplus) } diff --git a/include/drm/drm.h b/include/drm/drm.h index 4e4f7c2c3..1666e91b1 100644 --- a/include/drm/drm.h +++ b/include/drm/drm.h @@ -591,34 +591,65 @@ struct drm_set_version { int drm_dd_minor; }; -/* DRM_IOCTL_GEM_CLOSE ioctl argument type */ +/** + * struct drm_gem_close - Argument for &DRM_IOCTL_GEM_CLOSE ioctl. + * @handle: Handle of the object to be closed. + * @pad: Padding. + * + * Releases the handle to an mm object. + */ struct drm_gem_close { - /** Handle of the object to be closed. */ __u32 handle; __u32 pad; }; -/* DRM_IOCTL_GEM_FLINK ioctl argument type */ +/** + * struct drm_gem_flink - Argument for &DRM_IOCTL_GEM_FLINK ioctl. + * @handle: Handle for the object being named. + * @name: Returned global name. + * + * Create a global name for an object, returning the name. + * + * Note that the name does not hold a reference; when the object + * is freed, the name goes away. + */ struct drm_gem_flink { - /** Handle for the object being named */ __u32 handle; - - /** Returned global name */ __u32 name; }; -/* DRM_IOCTL_GEM_OPEN ioctl argument type */ +/** + * struct drm_gem_open - Argument for &DRM_IOCTL_GEM_OPEN ioctl. + * @name: Name of object being opened. + * @handle: Returned handle for the object. + * @size: Returned size of the object + * + * Open an object using the global name, returning a handle and the size. + * + * This handle (of course) holds a reference to the object, so the object + * will not go away until the handle is deleted. + */ struct drm_gem_open { - /** Name of object being opened */ __u32 name; - - /** Returned handle for the object */ __u32 handle; - - /** Returned size of the object */ __u64 size; }; +/** + * struct drm_gem_change_handle - Argument for &DRM_IOCTL_GEM_CHANGE_HANDLE ioctl. + * @handle: The handle of a gem object. + * @new_handle: An available gem handle. + * + * This ioctl changes the handle of a GEM object to the specified one. + * The new handle must be unused. On success the old handle is closed + * and all further IOCTL should refer to the new handle only. + * Calls to DRM_IOCTL_PRIME_FD_TO_HANDLE will return the new handle. + */ +struct drm_gem_change_handle { + __u32 handle; + __u32 new_handle; +}; + /** * DRM_CAP_DUMB_BUFFER * @@ -869,6 +900,21 @@ struct drm_get_cap { */ #define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6 +/** + * DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE + * + * If set to 1 the DRM core will allow setting the COLOR_PIPELINE + * property on a &drm_plane, as well as drm_colorop properties. + * + * Setting of these plane properties will be rejected when this client + * cap is set: + * - COLOR_ENCODING + * - COLOR_RANGE + * + * The client must enable &DRM_CLIENT_CAP_ATOMIC first. + */ +#define DRM_CLIENT_CAP_PLANE_COLOR_PIPELINE 7 + /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ struct drm_set_client_cap { __u64 capability; @@ -899,13 +945,17 @@ struct drm_syncobj_destroy { }; #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0) +#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_TIMELINE (1 << 1) #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0) +#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_TIMELINE (1 << 1) struct drm_syncobj_handle { __u32 handle; __u32 flags; __s32 fd; __u32 pad; + + __u64 point; }; struct drm_syncobj_transfer { @@ -1018,6 +1068,13 @@ struct drm_crtc_queue_sequence { __u64 user_data; /* user data passed to event */ }; +#define DRM_CLIENT_NAME_MAX_LEN 64 +struct drm_set_client_name { + __u64 name_len; + __u64 name; +}; + + #if defined(__cplusplus) } #endif @@ -1282,6 +1339,24 @@ extern "C" { */ #define DRM_IOCTL_MODE_CLOSEFB DRM_IOWR(0xD0, struct drm_mode_closefb) +/** + * DRM_IOCTL_SET_CLIENT_NAME - Attach a name to a drm_file + * + * Having a name allows for easier tracking and debugging. + * The length of the name (without null ending char) must be + * <= DRM_CLIENT_NAME_MAX_LEN. + * The call will fail if the name contains whitespaces or non-printable chars. + */ +#define DRM_IOCTL_SET_CLIENT_NAME DRM_IOWR(0xD1, struct drm_set_client_name) + +/** + * DRM_IOCTL_GEM_CHANGE_HANDLE - Move an object to a different handle + * + * Some applications (notably CRIU) need objects to have specific gem handles. + * This ioctl changes the object at one gem handle to use a new gem handle. + */ +#define DRM_IOCTL_GEM_CHANGE_HANDLE DRM_IOWR(0xD2, struct drm_gem_change_handle) + /* * Device specific ioctls should only be in their respective headers * The device specific ioctl range is from 0x40 to 0x9f. diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h index 9b2504802..d340ec204 100644 --- a/include/drm/drm_fourcc.h +++ b/include/drm/drm_fourcc.h @@ -1,24 +1,6 @@ +/* SPDX-License-Identifier: MIT */ /* * Copyright 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef DRM_FOURCC_H @@ -54,7 +36,7 @@ extern "C" { * Format modifiers may change any property of the buffer, including the number * of planes and/or the required allocation size. Format modifiers are * vendor-namespaced, and as such the relationship between a fourcc code and a - * modifier is specific to the modifer being used. For example, some modifiers + * modifier is specific to the modifier being used. For example, some modifiers * may preserve meaning - such as number of planes - from the fourcc code, * whereas others may not. * @@ -79,7 +61,7 @@ extern "C" { * format. * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users * see modifiers as opaque tokens they can check for equality and intersect. - * These users musn't need to know to reason about the modifier value + * These users mustn't need to know to reason about the modifier value * (i.e. they are not expected to extract information out of the modifier). * * Vendors should document their modifier usage in as much detail as @@ -210,6 +192,10 @@ extern "C" { #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */ #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */ +/* 48 bpp RGB */ +#define DRM_FORMAT_RGB161616 fourcc_code('R', 'G', '4', '8') /* [47:0] R:G:B 16:16:16 little endian */ +#define DRM_FORMAT_BGR161616 fourcc_code('B', 'G', '4', '8') /* [47:0] B:G:R 16:16:16 little endian */ + /* 64 bpp RGB */ #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ @@ -218,7 +204,7 @@ extern "C" { #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ /* - * Floating point 64bpp RGB + * Half-Floating point - 16b/component * IEEE 754-2008 binary16 half-precision float * [15:0] sign:exponent:mantissa 1:5:10 */ @@ -228,6 +214,20 @@ extern "C" { #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_R16F fourcc_code('R', ' ', ' ', 'H') /* [15:0] R 16 little endian */ +#define DRM_FORMAT_GR1616F fourcc_code('G', 'R', ' ', 'H') /* [31:0] G:R 16:16 little endian */ +#define DRM_FORMAT_BGR161616F fourcc_code('B', 'G', 'R', 'H') /* [47:0] B:G:R 16:16:16 little endian */ + +/* + * Floating point - 32b/component + * IEEE 754-2008 binary32 float + * [31:0] sign:exponent:mantissa 1:8:23 + */ +#define DRM_FORMAT_R32F fourcc_code('R', ' ', ' ', 'F') /* [31:0] R 32 little endian */ +#define DRM_FORMAT_GR3232F fourcc_code('G', 'R', ' ', 'F') /* [63:0] G:R 32:32 little endian */ +#define DRM_FORMAT_BGR323232F fourcc_code('B', 'G', 'R', 'F') /* [95:0] B:G:R 32:32:32 little endian */ +#define DRM_FORMAT_ABGR32323232F fourcc_code('A', 'B', '8', 'F') /* [127:0] A:B:G:R 32:32:32:32 little endian */ + /* * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits * of unused padding per component: @@ -246,6 +246,7 @@ extern "C" { #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */ #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */ #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */ +#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'Y', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */ /* * packed Y2xx indicate for each component, xx valid data occupy msb @@ -361,6 +362,14 @@ extern "C" { */ #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */ +/* + * 2 plane YCbCr422. + * 3 10 bit components and 2 padding bits packed into 4 bytes. + * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian + * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian + */ +#define DRM_FORMAT_P230 fourcc_code('P', '2', '3', '0') /* 2x1 subsampled Cr:Cb plane 10 bits per channel packed */ + /* 3 plane non-subsampled (444) YCbCr * 16 bits per component, but only 10 bits are used and 6 bits are padded * index 0: Y plane, [15:0] Y:x [10:6] little endian @@ -377,6 +386,51 @@ extern "C" { */ #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') +/* + * 3 plane non-subsampled (444) YCbCr LSB aligned + * 10 bpc, 30 bits per sample image data in a single contiguous buffer. + * index 0: Y plane, [31:0] x:Y2:Y1:Y0 [2:10:10:10] little endian + * index 1: Cb plane, [31:0] x:Cb2:Cb1:Cb0 [2:10:10:10] little endian + * index 2: Cr plane, [31:0] x:Cr2:Cr1:Cr0 [2:10:10:10] little endian + */ +#define DRM_FORMAT_T430 fourcc_code('T', '4', '3', '0') + +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^6=64. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [6:10] little endian + * index 1 = Cb plane, [15:0] z:Cb [6:10] little endian + * index 2 = Cr plane, [15:0] z:Cr [6:10] little endian + */ +#define DRM_FORMAT_S010 fourcc_code('S', '0', '1', '0') /* 2x2 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S210 fourcc_code('S', '2', '1', '0') /* 2x1 subsampled Cb (1) and Cr (2) planes 10 bits per channel */ +#define DRM_FORMAT_S410 fourcc_code('S', '4', '1', '0') /* non-subsampled Cb (1) and Cr (2) planes 10 bits per channel */ + +/* + * 3 plane YCbCr LSB aligned + * In order to use these formats in a similar fashion to MSB aligned ones + * implementation can multiply the values by 2^4=16. For that reason the padding + * must only contain zeros. + * index 0 = Y plane, [15:0] z:Y [4:12] little endian + * index 1 = Cb plane, [15:0] z:Cb [4:12] little endian + * index 2 = Cr plane, [15:0] z:Cr [4:12] little endian + */ +#define DRM_FORMAT_S012 fourcc_code('S', '0', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S212 fourcc_code('S', '2', '1', '2') /* 2x1 subsampled Cb (1) and Cr (2) planes 12 bits per channel */ +#define DRM_FORMAT_S412 fourcc_code('S', '4', '1', '2') /* non-subsampled Cb (1) and Cr (2) planes 12 bits per channel */ + +/* + * 3 plane YCbCr + * index 0 = Y plane, [15:0] Y little endian + * index 1 = Cb plane, [15:0] Cb little endian + * index 2 = Cr plane, [15:0] Cr little endian + */ +#define DRM_FORMAT_S016 fourcc_code('S', '0', '1', '6') /* 2x2 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S216 fourcc_code('S', '2', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes 16 bits per channel */ +#define DRM_FORMAT_S416 fourcc_code('S', '4', '1', '6') /* non-subsampled Cb (1) and Cr (2) planes 16 bits per channel */ + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -397,6 +451,16 @@ extern "C" { #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */ #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */ +/* + * Y-only (greyscale) formats + * + * The Y-only formats are handled similarly to the YCbCr formats in the display + * pipeline, with the Cb and Cr implicitly neutral (0.0 in nominal values). This + * also means that COLOR_RANGE property applies to the Y-only formats. + */ + +#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8-bit Y-only */ +#define DRM_FORMAT_XYYY2101010 fourcc_code('Y', 'P', 'A', '4') /* [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian */ /* * Format Modifiers: @@ -421,6 +485,8 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a +#define DRM_FORMAT_MOD_VENDOR_MTK 0x0b +#define DRM_FORMAT_MOD_VENDOR_APPLE 0x0c /* add more to the end as needed */ @@ -540,7 +606,7 @@ extern "C" { * This is a tiled layout using 4Kb tiles in row-major layout. * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which * are arranged in four groups (two wide, two high) with column-major layout. - * Each group therefore consits out of four 256 byte units, which are also laid + * Each group therefore consists out of four 256 byte units, which are also laid * out as 2x2 column-major. * 256 byte units are made out of four 64 byte blocks of pixels, producing * either a square block or a 2:1 unit. @@ -702,6 +768,31 @@ extern "C" { */ #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) +/* + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression + * on integrated graphics + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all compressible GEM objects. + */ +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) + +/* + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression + * on discrete graphics + * + * The main surface is Tile 4 and at plane index 0. For semi-planar formats + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices + * 0 and 1, respectively. The CCS for all planes are stored outside of the + * GEM object in a reserved memory area dedicated for the storage of the + * CCS data for all compressible GEM objects. The GEM object must be stored in + * contiguous memory with a size aligned to 64KB + */ +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) + /* * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks * @@ -898,14 +989,20 @@ extern "C" { * 2 = Gob Height 8, Turing+ Page Kind mapping * 3 = Reserved for future use. * - * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further - * bit remapping step that occurs at an even lower level than the - * page kind and block linear swizzles. This causes the layout of - * surfaces mapped in those SOC's GPUs to be incompatible with the - * equivalent mapping on other GPUs in the same system. - * - * 0 = Tegra K1 - Tegra Parker/TX2 Layout. - * 1 = Desktop GPU and Tegra Xavier+ Layout + * 22:22 s Sector layout. There is a further bit remapping step that occurs + * 26:27 at an even lower level than the page kind and block linear + * swizzles. This causes the bit arrangement of surfaces in memory + * to differ subtly, and prevents direct sharing of surfaces between + * GPUs with different layouts. + * + * 0 = Tegra K1 - Tegra Parker/TX2 Layout + * 1 = Pre-GB20x, GB20x 32+ bpp, GB10, Tegra Xavier-Orin Layout + * 2 = GB20x(Blackwell 2)+ 8 bpp surface layout + * 3 = GB20x(Blackwell 2)+ 16 bpp surface layout + * 4 = Reserved for future use. + * 5 = Reserved for future use. + * 6 = Reserved for future use. + * 7 = Reserved for future use. * * 25:23 c Lossless Framebuffer Compression type. * @@ -920,7 +1017,7 @@ extern "C" { * 6 = Reserved for future use * 7 = Reserved for future use * - * 55:25 - Reserved for future use. Must be zero. + * 55:28 - Reserved for future use. Must be zero. */ #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \ fourcc_mod_code(NVIDIA, (0x10 | \ @@ -928,6 +1025,7 @@ extern "C" { (((k) & 0xff) << 12) | \ (((g) & 0x3) << 20) | \ (((s) & 0x1) << 22) | \ + (((s) & 0x6) << 25) | \ (((c) & 0x7) << 23))) /* To grandfather in prior block linear format modifiers to the above layout, @@ -1103,7 +1201,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ /* - * The top 4 bits (out of the 56 bits alloted for specifying vendor specific + * The top 4 bits (out of the 56 bits allotted for specifying vendor specific * modifiers) denote the category for modifiers. Currently we have three * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of * sixteen different categories. @@ -1334,6 +1432,22 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) +/* + * ARM 64k interleaved modifier + * + * This is used by ARM Mali v10+ GPUs. With this modifier, the plane is divided + * into 64k byte 1:1 or 2:1 -sided tiles. The 64k tiles are laid out linearly. + * Each 64k tile is divided into blocks of 16x16 texel blocks, which are + * themselves laid out linearly within a 64k tile. Then within each 16x16 + * block, texel blocks are laid out according to U order, similar to + * 16X16_BLOCK_U_INTERLEAVED. + * + * Note that unlike 16X16_BLOCK_U_INTERLEAVED, the layout does not change + * depending on whether a format is compressed or not. + */ +#define DRM_FORMAT_MOD_ARM_INTERLEAVED_64K \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 2ULL) + /* * Allwinner tiled modifier * @@ -1419,7 +1533,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) * Amlogic FBC Memory Saving mode * * Indicates the storage is packed when pixel size is multiple of word - * boudaries, i.e. 8bit should be stored in this mode to save allocation + * boundaries, i.e. 8bit should be stored in this mode to save allocation * memory. * * This mode reduces body layout to 3072 bytes per 64x32 superblock with @@ -1428,6 +1542,90 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) */ #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) +/* MediaTek modifiers + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * 7: 0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_* + * 15: 8 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_* + * 23:16 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_* + * + */ + +#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags) + +/* + * MediaTek Tiled Modifier + * The lowest 8 bits of the modifier is used to specify the tiling + * layout. Only the 16L_32S tiling is used for now, but we define an + * "untiled" version and leave room for future expansion. + */ +#define MTK_FMT_MOD_TILE_MASK 0xf +#define MTK_FMT_MOD_TILE_NONE 0x0 +#define MTK_FMT_MOD_TILE_16L32S 0x1 + +/* + * Bits 8-15 specify compression options + */ +#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 8) +#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 8) +#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 8) + +/* + * Bits 16-23 specify how the bits of 10 bit formats are + * stored out in memory + */ +#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 16) +#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 16) + +/* alias for the most common tiling format */ +#define DRM_FORMAT_MOD_MTK_16L_32S_TILE DRM_FORMAT_MOD_MTK(MTK_FMT_MOD_TILE_16L32S) + +/* + * Apple GPU-tiled layouts. + * + * Apple GPUs support nonlinear tilings with optional lossless compression. + * + * GPU-tiled images are divided into 16KiB tiles: + * + * Bytes per pixel Tile size + * --------------- --------- + * 1 128x128 + * 2 128x64 + * 4 64x64 + * 8 64x32 + * 16 32x32 + * + * Tiles are raster-order. Pixels within a tile are interleaved (Morton order). + * + * Compressed images pad the body to 128-bytes and are immediately followed by a + * metadata section. The metadata section rounds the image dimensions to + * powers-of-two and contains 8 bytes for each 16x16 compression subtile. + * Subtiles are interleaved (Morton order). + * + * All images are 128-byte aligned. + * + * These layouts fundamentally do not have meaningful strides. No matter how we + * specify strides for these layouts, userspace unaware of Apple image layouts + * will be unable to use correctly the specified stride for any purpose. + * Userspace aware of the image layouts do not use strides. The most "correct" + * convention would be setting the image stride to 0. Unfortunately, some + * software assumes the stride is at least (width * bytes per pixel). We + * therefore require that stride equals (width * bytes per pixel). Since the + * stride is arbitrary here, we pick the simplest convention. + * + * Although containing two sections, compressed image layouts are treated in + * software as a single plane. This is modelled after AFBC, a similar + * scheme. Attempting to separate the sections to be "explicit" in DRM would + * only generate more confusion, as software does not treat the image this way. + * + * For detailed information on the hardware image layouts, see + * https://docs.mesa3d.org/drivers/asahi.html#image-layouts + */ +#define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1) +#define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2) + /* * AMD modifiers * @@ -1476,6 +1674,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_TILE_VER_GFX10 2 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 #define AMD_FMT_MOD_TILE_VER_GFX11 4 +#define AMD_FMT_MOD_TILE_VER_GFX12 5 /* * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical @@ -1486,13 +1685,31 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) /* * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has * GFX9 as canonical version. + * + * 64K_D_2D on GFX12 is identical to 64K_D on GFX11. */ #define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_4K_D_X 22 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 +/* Gfx12 swizzle modes: + * 0 - LINEAR + * 1 - 256B_2D - 2D block dimensions + * 2 - 4KB_2D + * 3 - 64KB_2D + * 4 - 256KB_2D + * 5 - 4KB_3D - 3D block dimensions + * 6 - 64KB_3D + * 7 - 256KB_3D + */ +#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 +#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 +#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 +#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 + #define AMD_FMT_MOD_DCC_BLOCK_64B 0 #define AMD_FMT_MOD_DCC_BLOCK_128B 1 #define AMD_FMT_MOD_DCC_BLOCK_256B 2 diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h index 95630f170..cbbbfc1df 100644 --- a/include/drm/drm_mode.h +++ b/include/drm/drm_mode.h @@ -36,10 +36,10 @@ extern "C" { /** * DOC: overview * - * DRM exposes many UAPI and structure definition to have a consistent - * and standardized interface with user. + * DRM exposes many UAPI and structure definitions to have a consistent + * and standardized interface with users. * Userspace can refer to these structure definitions and UAPI formats - * to communicate to driver + * to communicate to drivers. */ #define DRM_CONNECTOR_NAME_LEN 32 @@ -540,7 +540,7 @@ struct drm_mode_get_connector { /* the PROP_ATOMIC flag is used to hide properties from userspace that * is not aware of atomic properties. This is mostly to work around * older userspace (DDX drivers) that read/write each prop they find, - * witout being aware that this could be triggering a lengthy modeset. + * without being aware that this could be triggering a lengthy modeset. */ #define DRM_MODE_PROP_ATOMIC 0x80000000 @@ -629,6 +629,7 @@ struct drm_mode_connector_set_property { #define DRM_MODE_OBJECT_FB 0xfbfbfbfb #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb #define DRM_MODE_OBJECT_PLANE 0xeeeeeeee +#define DRM_MODE_OBJECT_COLOROP 0xfafafafa #define DRM_MODE_OBJECT_ANY 0 struct drm_mode_obj_get_properties { @@ -664,7 +665,7 @@ struct drm_mode_fb_cmd { }; #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ -#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */ +#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifier[] */ /** * struct drm_mode_fb_cmd2 - Frame-buffer metadata. @@ -846,6 +847,20 @@ struct drm_color_ctm { __u64 matrix[9]; }; +struct drm_color_ctm_3x4 { + /* + * Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude + * (not two's complement!) format. + * + * out matrix in + * |R| |0 1 2 3 | | R | + * |G| = |4 5 6 7 | x | G | + * |B| |8 9 10 11| | B | + * |1.0| + */ + __u64 matrix[12]; +}; + struct drm_color_lut { /* * Values are mapped linearly to 0.0 - 1.0 range, with 0x0 == 0.0 and @@ -857,6 +872,138 @@ struct drm_color_lut { __u16 reserved; }; +/* + * struct drm_color_lut32 + * + * 32-bit per channel color LUT entry, similar to drm_color_lut. + */ +struct drm_color_lut32 { + __u32 red; + __u32 green; + __u32 blue; + __u32 reserved; +}; + +/** + * enum drm_colorop_type - Type of color operation + * + * drm_colorops can be of many different types. Each type behaves differently + * and defines a different set of properties. This enum defines all types and + * gives a high-level description. + */ +enum drm_colorop_type { + /** + * @DRM_COLOROP_1D_CURVE: + * + * enum string "1D Curve" + * + * A 1D curve that is being applied to all color channels. The + * curve is specified via the CURVE_1D_TYPE colorop property. + */ + DRM_COLOROP_1D_CURVE, + + /** + * @DRM_COLOROP_1D_LUT: + * + * enum string "1D LUT" + * + * A simple 1D LUT of uniformly spaced &drm_color_lut32 entries, + * packed into a blob via the DATA property. The driver's + * expected LUT size is advertised via the SIZE property. + * + * The DATA blob is an array of struct drm_color_lut32 with size + * of "size". + */ + DRM_COLOROP_1D_LUT, + + /** + * @DRM_COLOROP_CTM_3X4: + * + * enum string "3x4 Matrix" + * + * A 3x4 matrix. Its values are specified via the + * &drm_color_ctm_3x4 struct provided via the DATA property. + * + * The DATA blob is a float[12]: + * out matrix in + * | R | | 0 1 2 3 | | R | + * | G | = | 4 5 6 7 | x | G | + * | B | | 8 9 10 12 | | B | + */ + DRM_COLOROP_CTM_3X4, + + /** + * @DRM_COLOROP_MULTIPLIER: + * + * enum string "Multiplier" + * + * A simple multiplier, applied to all color values. The + * multiplier is specified as a S31.32 via the MULTIPLIER + * property. + */ + DRM_COLOROP_MULTIPLIER, + + /** + * @DRM_COLOROP_3D_LUT: + * + * enum string "3D LUT" + * + * A 3D LUT of &drm_color_lut32 entries, + * packed into a blob via the DATA property. The driver's expected + * LUT size is advertised via the SIZE property, i.e., a 3D LUT with + * 17x17x17 entries will have SIZE set to 17. + * + * The DATA blob is a 3D array of struct drm_color_lut32 with dimension + * length of "size". + * The LUT elements are traversed like so: + * + * for B in range 0..n + * for G in range 0..n + * for R in range 0..n + * index = R + n * (G + n * B) + * color = lut3d[index] + */ + DRM_COLOROP_3D_LUT, +}; + +/** + * enum drm_colorop_lut3d_interpolation_type - type of 3DLUT interpolation + */ +enum drm_colorop_lut3d_interpolation_type { + /** + * @DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL: + * + * Tetrahedral 3DLUT interpolation + */ + DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL, +}; + +/** + * enum drm_colorop_lut1d_interpolation_type - type of interpolation for 1D LUTs + */ +enum drm_colorop_lut1d_interpolation_type { + /** + * @DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR: + * + * Linear interpolation. Values between points of the LUT will be + * linearly interpolated. + */ + DRM_COLOROP_LUT1D_INTERPOLATION_LINEAR, +}; + +/** + * struct drm_plane_size_hint - Plane size hints + * @width: The width of the plane in pixel + * @height: The height of the plane in pixel + * + * The plane SIZE_HINTS property blob contains an + * array of struct drm_plane_size_hint. + */ +struct drm_plane_size_hint { + __u16 width; + __u16 height; +}; + /** * struct hdr_metadata_infoframe - HDR Metadata Infoframe Data. * @@ -881,8 +1028,8 @@ struct hdr_metadata_infoframe { * These are coded as unsigned 16-bit values in units of * 0.00002, where 0x0000 represents zero and 0xC350 * represents 1.0000. - * @display_primaries.x: X cordinate of color primary. - * @display_primaries.y: Y cordinate of color primary. + * @display_primaries.x: X coordinate of color primary. + * @display_primaries.y: Y coordinate of color primary. */ struct { __u16 x, y; @@ -892,8 +1039,8 @@ struct hdr_metadata_infoframe { * These are coded as unsigned 16-bit values in units of * 0.00002, where 0x0000 represents zero and 0xC350 * represents 1.0000. - * @white_point.x: X cordinate of whitepoint of color primary. - * @white_point.y: Y cordinate of whitepoint of color primary. + * @white_point.x: X coordinate of whitepoint of color primary. + * @white_point.y: Y coordinate of whitepoint of color primary. */ struct { __u16 x, y; @@ -949,6 +1096,14 @@ struct hdr_output_metadata { * Request that the kernel sends back a vblank event (see * struct drm_event_vblank) with the &DRM_EVENT_FLIP_COMPLETE type when the * page-flip is done. + * + * When used with atomic uAPI, one event will be delivered per CRTC included in + * the atomic commit. A CRTC is included in an atomic commit if one of its + * properties is set, or if a property is set on a connector or plane linked + * via the CRTC_ID property to the CRTC. At least one CRTC must be included, + * and all pulled in CRTCs must be either previously or newly powered on (in + * other words, a powered off CRTC which stays off cannot be included in the + * atomic commit). */ #define DRM_MODE_PAGE_FLIP_EVENT 0x01 /** @@ -1045,7 +1200,7 @@ struct drm_mode_crtc_page_flip_target { * struct drm_mode_create_dumb - Create a KMS dumb buffer for scanout. * @height: buffer height in pixels * @width: buffer width in pixels - * @bpp: bits per pixel + * @bpp: color mode * @flags: must be zero * @handle: buffer object handle * @pitch: number of bytes between two consecutive lines @@ -1053,6 +1208,54 @@ struct drm_mode_crtc_page_flip_target { * * User-space fills @height, @width, @bpp and @flags. If the IOCTL succeeds, * the kernel fills @handle, @pitch and @size. + * + * The value of @bpp is a color-mode number describing a specific format + * or a variant thereof. The value often corresponds to the number of bits + * per pixel for most modes, although there are exceptions. Each color mode + * maps to a DRM format plus a number of modes with similar pixel layout. + * Framebuffer layout is always linear. + * + * Support for all modes and formats is optional. Even if dumb-buffer + * creation with a certain color mode succeeds, it is not guaranteed that + * the DRM driver supports any of the related formats. Most drivers support + * a color mode of 32 with a format of DRM_FORMAT_XRGB8888 on their primary + * plane. + * + * +------------+------------------------+------------------------+ + * | Color mode | Framebuffer format | Compatible formats | + * +============+========================+========================+ + * | 32 | * DRM_FORMAT_XRGB8888 | * DRM_FORMAT_BGRX8888 | + * | | | * DRM_FORMAT_RGBX8888 | + * | | | * DRM_FORMAT_XBGR8888 | + * +------------+------------------------+------------------------+ + * | 24 | * DRM_FORMAT_RGB888 | * DRM_FORMAT_BGR888 | + * +------------+------------------------+------------------------+ + * | 16 | * DRM_FORMAT_RGB565 | * DRM_FORMAT_BGR565 | + * +------------+------------------------+------------------------+ + * | 15 | * DRM_FORMAT_XRGB1555 | * DRM_FORMAT_BGRX1555 | + * | | | * DRM_FORMAT_RGBX1555 | + * | | | * DRM_FORMAT_XBGR1555 | + * +------------+------------------------+------------------------+ + * | 8 | * DRM_FORMAT_C8 | * DRM_FORMAT_D8 | + * | | | * DRM_FORMAT_R8 | + * +------------+------------------------+------------------------+ + * | 4 | * DRM_FORMAT_C4 | * DRM_FORMAT_D4 | + * | | | * DRM_FORMAT_R4 | + * +------------+------------------------+------------------------+ + * | 2 | * DRM_FORMAT_C2 | * DRM_FORMAT_D2 | + * | | | * DRM_FORMAT_R2 | + * +------------+------------------------+------------------------+ + * | 1 | * DRM_FORMAT_C1 | * DRM_FORMAT_D1 | + * | | | * DRM_FORMAT_R1 | + * +------------+------------------------+------------------------+ + * + * Color modes of 10, 12, 15, 30 and 64 are only supported for use by + * legacy user space. Please don't use them in new code. Other modes + * are not support. + * + * Do not attempt to allocate anything but linear framebuffer memory + * with single-plane RGB data. Allocation of other framebuffer + * layouts requires dedicated ioctls in the respective DRM driver. */ struct drm_mode_create_dumb { __u32 height; diff --git a/include/drm/virtgpu_drm.h b/include/drm/virtgpu_drm.h index f06a789f3..9debb320c 100644 --- a/include/drm/virtgpu_drm.h +++ b/include/drm/virtgpu_drm.h @@ -46,12 +46,16 @@ extern "C" { #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 #define DRM_VIRTGPU_WAIT 0x08 #define DRM_VIRTGPU_GET_CAPS 0x09 +#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a +#define DRM_VIRTGPU_CONTEXT_INIT 0x0b #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 +#define VIRTGPU_EXECBUF_RING_IDX 0x04 #define VIRTGPU_EXECBUF_FLAGS (\ VIRTGPU_EXECBUF_FENCE_FD_IN |\ VIRTGPU_EXECBUF_FENCE_FD_OUT |\ + VIRTGPU_EXECBUF_RING_IDX |\ 0) struct drm_virtgpu_map { @@ -60,6 +64,17 @@ struct drm_virtgpu_map { __u32 pad; }; +#define VIRTGPU_EXECBUF_SYNCOBJ_RESET 0x01 +#define VIRTGPU_EXECBUF_SYNCOBJ_FLAGS ( \ + VIRTGPU_EXECBUF_SYNCOBJ_RESET | \ + 0) +struct drm_virtgpu_execbuffer_syncobj { + __u32 handle; + __u32 flags; + __u64 point; +}; + +/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */ struct drm_virtgpu_execbuffer { __u32 flags; __u32 size; @@ -67,10 +82,22 @@ struct drm_virtgpu_execbuffer { __u64 bo_handles; __u32 num_bo_handles; __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ + __u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */ + __u32 syncobj_stride; /* size of @drm_virtgpu_execbuffer_syncobj */ + __u32 num_in_syncobjs; + __u32 num_out_syncobjs; + __u64 in_syncobjs; + __u64 out_syncobjs; }; #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ +#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */ +#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */ +#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */ +#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */ +#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */ +#define VIRTGPU_PARAM_EXPLICIT_DEBUG_NAME 8 /* Ability to set debug name from userspace */ struct drm_virtgpu_getparam { __u64 param; @@ -100,7 +127,7 @@ struct drm_virtgpu_resource_info { __u32 bo_handle; __u32 res_handle; __u32 size; - __u32 stride; + __u32 blob_mem; }; struct drm_virtgpu_3d_box { @@ -117,6 +144,8 @@ struct drm_virtgpu_3d_transfer_to_host { struct drm_virtgpu_3d_box box; __u32 level; __u32 offset; + __u32 stride; + __u32 layer_stride; }; struct drm_virtgpu_3d_transfer_from_host { @@ -124,6 +153,8 @@ struct drm_virtgpu_3d_transfer_from_host { struct drm_virtgpu_3d_box box; __u32 level; __u32 offset; + __u32 stride; + __u32 layer_stride; }; #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ @@ -132,6 +163,12 @@ struct drm_virtgpu_3d_wait { __u32 flags; }; +#define VIRTGPU_DRM_CAPSET_VIRGL 1 +#define VIRTGPU_DRM_CAPSET_VIRGL2 2 +#define VIRTGPU_DRM_CAPSET_GFXSTREAM_VULKAN 3 +#define VIRTGPU_DRM_CAPSET_VENUS 4 +#define VIRTGPU_DRM_CAPSET_CROSS_DOMAIN 5 +#define VIRTGPU_DRM_CAPSET_DRM 6 struct drm_virtgpu_get_caps { __u32 cap_set_id; __u32 cap_set_ver; @@ -140,6 +177,55 @@ struct drm_virtgpu_get_caps { __u32 pad; }; +struct drm_virtgpu_resource_create_blob { +#define VIRTGPU_BLOB_MEM_GUEST 0x0001 +#define VIRTGPU_BLOB_MEM_HOST3D 0x0002 +#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003 + +#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001 +#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002 +#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004 + /* zero is invalid blob_mem */ + __u32 blob_mem; + __u32 blob_flags; + __u32 bo_handle; + __u32 res_handle; + __u64 size; + + /* + * for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and + * VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero. + */ + __u32 pad; + __u32 cmd_size; + __u64 cmd; + __u64 blob_id; +}; + +#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001 +#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002 +#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003 +#define VIRTGPU_CONTEXT_PARAM_DEBUG_NAME 0x0004 +struct drm_virtgpu_context_set_param { + __u64 param; + __u64 value; +}; + +struct drm_virtgpu_context_init { + __u32 num_params; + __u32 pad; + + /* pointer to drm_virtgpu_context_set_param array */ + __u64 ctx_set_params; +}; + +/* + * Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in + * effect. The event size is sizeof(drm_event), since there is no additional + * payload. + */ +#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000 + #define DRM_IOCTL_VIRTGPU_MAP \ DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) @@ -175,6 +261,14 @@ struct drm_virtgpu_get_caps { DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ struct drm_virtgpu_get_caps) +#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \ + struct drm_virtgpu_resource_create_blob) + +#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \ + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \ + struct drm_virtgpu_context_init) + #if defined(__cplusplus) } #endif diff --git a/intel/.gitignore b/intel/.gitignore deleted file mode 100755 index 528b40869..000000000 --- a/intel/.gitignore +++ /dev/null @@ -1 +0,0 @@ -test_decode diff --git a/intel/Android.bp b/intel/Android.bp index 7c82f1e65..22713acc8 100755 --- a/intel/Android.bp +++ b/intel/Android.bp @@ -21,16 +21,6 @@ // IN THE SOFTWARE. // -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-BSD - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/intel/Makefile.sources b/intel/Makefile.sources deleted file mode 100644 index 6947ab742..000000000 --- a/intel/Makefile.sources +++ /dev/null @@ -1,15 +0,0 @@ -LIBDRM_INTEL_FILES := \ - intel_bufmgr.c \ - intel_bufmgr_priv.h \ - intel_bufmgr_fake.c \ - intel_bufmgr_gem.c \ - intel_decode.c \ - intel_chipset.h \ - mm.c \ - mm.h \ - uthash.h - -LIBDRM_INTEL_H_FILES := \ - intel_bufmgr.h \ - intel_aub.h \ - intel_debug.h diff --git a/intel/meson.build b/intel/meson.build index 4af2a3573..5622b5970 100644 --- a/intel/meson.build +++ b/intel/meson.build @@ -32,7 +32,7 @@ libdrm_intel = library( dependencies : [dep_pciaccess, dep_threads, dep_rt, dep_valgrind, dep_atomic_ops], c_args : libdrm_c_args, gnu_symbol_visibility : 'hidden', - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -41,9 +41,7 @@ ext_libdrm_intel = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_intel', ext_libdrm_intel) -endif +meson.override_dependency('libdrm_intel', ext_libdrm_intel) install_headers( 'intel_bufmgr.h', 'intel_aub.h', 'intel_debug.h', @@ -104,6 +102,6 @@ test( args : [ '--lib', libdrm_intel, '--symbols-file', files('intel-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/intel/tests/.gitignore b/intel/tests/.gitignore deleted file mode 100755 index e9d01ecb2..000000000 --- a/intel/tests/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*-new.txt diff --git a/intel/tests/gen4-3d.batch b/intel/tests/gen4-3d.batch deleted file mode 100755 index e6911a438..000000000 Binary files a/intel/tests/gen4-3d.batch and /dev/null differ diff --git a/intel/tests/gen4-3d.batch-ref.txt b/intel/tests/gen4-3d.batch-ref.txt deleted file mode 100755 index 20aa1d4eb..000000000 --- a/intel/tests/gen4-3d.batch-ref.txt +++ /dev/null @@ -1,488 +0,0 @@ -0x12300000: 0x61040000: 3DSTATE_PIPELINE_SELECT -0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP -0x12300008: 0x00000000: dword 1 -0x1230000c: 0x61020000: STATE_SIP -0x12300010: 0x00000000: dword 1 -0x12300014: 0x780b0000: 3DSTATE_VF_STATISTICS -0x12300018: 0x61010004: STATE_BASE_ADDRESS -0x1230001c: 0x00000001: general state base address 0x00000000 -0x12300020: 0x00000001: surface state base address 0x00000000 -0x12300024: 0x00000001: indirect state base address 0x00000000 -0x12300028: 0x00000001: general state upper bound disabled -0x1230002c: 0x00000001: indirect state upper bound disabled -0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x12300034: 0x00007e20: VS binding table -0x12300038: 0x00000000: GS binding table -0x1230003c: 0x00000000: Clip binding table -0x12300040: 0x00000000: SF binding table -0x12300044: 0x00007e20: WM binding table -0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR -0x1230004c: 0x00000000: dword 1 -0x12300050: 0x00000000: dword 2 -0x12300054: 0x00000000: dword 3 -0x12300058: 0x00000000: dword 4 -0x1230005c: 0x79050003: 3DSTATE_DEPTH_BUFFER -0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled -0x12300064: 0x00000000: depth offset -0x12300068: 0x09584ac0: 300x300 -0x1230006c: 0x00000000: volume depth -0x12300070: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300074: 0x00007d60: VS state -0x12300078: 0x00000000: GS state -0x1230007c: 0x00007d21: Clip state -0x12300080: 0x00007d80: SF state -0x12300084: 0x00007de0: WM state -0x12300088: 0x00007fc0: CC state -0x1230008c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300090: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300094: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300098: 0x60010000: CS_URB_STATE -0x1230009c: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 -0x123000a0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE -0x123000a4: 0x00000000: top left: 0,0 -0x123000a8: 0x012b012b: bottom right: 299,299 -0x123000ac: 0x00000000: origin: 0,0 -0x123000b0: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123000b4: 0x0000000c: buffer 0: sequential, pitch 12b -0x123000b8: 0x00000000: buffer address -0x123000bc: 0x00000000: max index -0x123000c0: 0x00000000: mbz -0x123000c4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123000c8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123000cc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123000d0: 0x60020100: CONSTANT_BUFFER: valid -0x123000d4: 0x00000001: offset: 0x00000000, length: 128 bytes -0x123000d8: 0x7b001804: 3DPRIMITIVE: tri fan sequential -0x123000dc: 0x00000004: vertex count -0x123000e0: 0x00000000: start vertex -0x123000e4: 0x00000001: instance count -0x123000e8: 0x00000000: start instance -0x123000ec: 0x00000000: index bias -0x123000f0: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x123000f4: 0x00007b40: VS binding table -0x123000f8: 0x00000000: GS binding table -0x123000fc: 0x00000000: Clip binding table -0x12300100: 0x00000000: SF binding table -0x12300104: 0x00007b40: WM binding table -0x12300108: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x1230010c: 0x00007aa0: VS state -0x12300110: 0x00007a41: GS state -0x12300114: 0x00007a61: Clip state -0x12300118: 0x00007ac0: SF state -0x1230011c: 0x00007b00: WM state -0x12300120: 0x00007cc0: CC state -0x12300124: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300128: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x1230012c: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300130: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300134: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300138: 0x00000000: buffer address -0x1230013c: 0x00000000: max index -0x12300140: 0x00000000: mbz -0x12300144: 0x60020100: CONSTANT_BUFFER: valid -0x12300148: 0x00000082: offset: 0x00000080, length: 192 bytes -0x1230014c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300150: 0x00000052: vertex count -0x12300154: 0x00000000: start vertex -0x12300158: 0x00000001: instance count -0x1230015c: 0x00000000: start instance -0x12300160: 0x00000000: index bias -0x12300164: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300168: 0x00007aa0: VS state -0x1230016c: 0x00007a21: GS state -0x12300170: 0x00007a61: Clip state -0x12300174: 0x00007ac0: SF state -0x12300178: 0x00007b00: WM state -0x1230017c: 0x00007cc0: CC state -0x12300180: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300184: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300188: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230018c: 0x60020100: CONSTANT_BUFFER: valid -0x12300190: 0x00000082: offset: 0x00000080, length: 192 bytes -0x12300194: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300198: 0x00000050: vertex count -0x1230019c: 0x00000052: start vertex -0x123001a0: 0x00000001: instance count -0x123001a4: 0x00000000: start instance -0x123001a8: 0x00000000: index bias -0x123001ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123001b0: 0x00007aa0: VS state -0x123001b4: 0x00007a01: GS state -0x123001b8: 0x00007a61: Clip state -0x123001bc: 0x00007ac0: SF state -0x123001c0: 0x00007b00: WM state -0x123001c4: 0x00007cc0: CC state -0x123001c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123001cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x123001d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x123001d4: 0x60020100: CONSTANT_BUFFER: valid -0x123001d8: 0x00000142: offset: 0x00000140, length: 192 bytes -0x123001dc: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123001e0: 0x00000052: vertex count -0x123001e4: 0x000000a2: start vertex -0x123001e8: 0x00000001: instance count -0x123001ec: 0x00000000: start instance -0x123001f0: 0x00000000: index bias -0x123001f4: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123001f8: 0x00007aa0: VS state -0x123001fc: 0x000079e1: GS state -0x12300200: 0x00007a61: Clip state -0x12300204: 0x00007ac0: SF state -0x12300208: 0x00007b00: WM state -0x1230020c: 0x00007cc0: CC state -0x12300210: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300214: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300218: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230021c: 0x60020100: CONSTANT_BUFFER: valid -0x12300220: 0x00000142: offset: 0x00000140, length: 192 bytes -0x12300224: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300228: 0x00000050: vertex count -0x1230022c: 0x000000f4: start vertex -0x12300230: 0x00000001: instance count -0x12300234: 0x00000000: start instance -0x12300238: 0x00000000: index bias -0x1230023c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300240: 0x00007aa0: VS state -0x12300244: 0x000079c1: GS state -0x12300248: 0x00007a61: Clip state -0x1230024c: 0x00007ac0: SF state -0x12300250: 0x00007b00: WM state -0x12300254: 0x00007cc0: CC state -0x12300258: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230025c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300260: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300264: 0x60020100: CONSTANT_BUFFER: valid -0x12300268: 0x00000142: offset: 0x00000140, length: 192 bytes -0x1230026c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300270: 0x000079a0: VS state -0x12300274: 0x000079c1: GS state -0x12300278: 0x00007a61: Clip state -0x1230027c: 0x00007ac0: SF state -0x12300280: 0x00007b00: WM state -0x12300284: 0x00007cc0: CC state -0x12300288: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230028c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300290: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300294: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300298: 0x00000018: buffer 0: sequential, pitch 24b -0x1230029c: 0x00000f48: buffer address -0x123002a0: 0x00000000: max index -0x123002a4: 0x00000000: mbz -0x123002a8: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123002ac: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123002b0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123002b4: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123002b8: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x123002bc: 0x60020100: CONSTANT_BUFFER: valid -0x123002c0: 0x00000202: offset: 0x00000200, length: 192 bytes -0x123002c4: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123002c8: 0x000000a2: vertex count -0x123002cc: 0x00000000: start vertex -0x123002d0: 0x00000001: instance count -0x123002d4: 0x00000000: start instance -0x123002d8: 0x00000000: index bias -0x123002dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123002e0: 0x000079a0: VS state -0x123002e4: 0x00000000: GS state -0x123002e8: 0x00007901: Clip state -0x123002ec: 0x00007940: SF state -0x123002f0: 0x00007960: WM state -0x123002f4: 0x00007cc0: CC state -0x123002f8: 0x00000000: MI_NOOP -0x123002fc: 0x00000000: MI_NOOP -0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300304: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300308: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230030c: 0x60020100: CONSTANT_BUFFER: valid -0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes -0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300318: 0x0000002a: vertex count -0x1230031c: 0x000000a2: start vertex -0x12300320: 0x00000001: instance count -0x12300324: 0x00000000: start instance -0x12300328: 0x00000000: index bias -0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300330: 0x00007860: VS state -0x12300334: 0x00007801: GS state -0x12300338: 0x00007821: Clip state -0x1230033c: 0x00007880: SF state -0x12300340: 0x000078a0: WM state -0x12300344: 0x00007cc0: CC state -0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230034c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300350: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b -0x1230035c: 0x00002268: buffer address -0x12300360: 0x00000000: max index -0x12300364: 0x00000000: mbz -0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300374: 0x60020100: CONSTANT_BUFFER: valid -0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300380: 0x0000002a: vertex count -0x12300384: 0x00000000: start vertex -0x12300388: 0x00000001: instance count -0x1230038c: 0x00000000: start instance -0x12300390: 0x00000000: index bias -0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300398: 0x00007860: VS state -0x1230039c: 0x000077e1: GS state -0x123003a0: 0x00007821: Clip state -0x123003a4: 0x00007880: SF state -0x123003a8: 0x000078a0: WM state -0x123003ac: 0x00007cc0: CC state -0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123003b4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x123003b8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x123003bc: 0x60020100: CONSTANT_BUFFER: valid -0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123003c8: 0x00000028: vertex count -0x123003cc: 0x0000002a: start vertex -0x123003d0: 0x00000001: instance count -0x123003d4: 0x00000000: start instance -0x123003d8: 0x00000000: index bias -0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123003e0: 0x00007860: VS state -0x123003e4: 0x000077c1: GS state -0x123003e8: 0x00007821: Clip state -0x123003ec: 0x00007880: SF state -0x123003f0: 0x000078a0: WM state -0x123003f4: 0x00007cc0: CC state -0x123003f8: 0x00000000: MI_NOOP -0x123003fc: 0x00000000: MI_NOOP -0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300404: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300408: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230040c: 0x60020100: CONSTANT_BUFFER: valid -0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes -0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300418: 0x0000002a: vertex count -0x1230041c: 0x00000052: start vertex -0x12300420: 0x00000001: instance count -0x12300424: 0x00000000: start instance -0x12300428: 0x00000000: index bias -0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300430: 0x00007860: VS state -0x12300434: 0x000077a1: GS state -0x12300438: 0x00007821: Clip state -0x1230043c: 0x00007880: SF state -0x12300440: 0x000078a0: WM state -0x12300444: 0x00007cc0: CC state -0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230044c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300450: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x12300454: 0x60020100: CONSTANT_BUFFER: valid -0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes -0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300460: 0x00000028: vertex count -0x12300464: 0x0000007c: start vertex -0x12300468: 0x00000001: instance count -0x1230046c: 0x00000000: start instance -0x12300470: 0x00000000: index bias -0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300478: 0x00007860: VS state -0x1230047c: 0x00007781: GS state -0x12300480: 0x00007821: Clip state -0x12300484: 0x00007880: SF state -0x12300488: 0x000078a0: WM state -0x1230048c: 0x00007cc0: CC state -0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300494: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300498: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230049c: 0x60020100: CONSTANT_BUFFER: valid -0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes -0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123004a8: 0x00007760: VS state -0x123004ac: 0x00007781: GS state -0x123004b0: 0x00007821: Clip state -0x123004b4: 0x00007880: SF state -0x123004b8: 0x000078a0: WM state -0x123004bc: 0x00007cc0: CC state -0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123004c4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x123004c8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b -0x123004d4: 0x00002a30: buffer address -0x123004d8: 0x00000000: max index -0x123004dc: 0x00000000: mbz -0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x123004f4: 0x60020100: CONSTANT_BUFFER: valid -0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes -0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300500: 0x00000052: vertex count -0x12300504: 0x00000000: start vertex -0x12300508: 0x00000001: instance count -0x1230050c: 0x00000000: start instance -0x12300510: 0x00000000: index bias -0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300518: 0x00007760: VS state -0x1230051c: 0x00000000: GS state -0x12300520: 0x000076c1: Clip state -0x12300524: 0x00007700: SF state -0x12300528: 0x00007720: WM state -0x1230052c: 0x00007cc0: CC state -0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300534: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300538: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230053c: 0x60020100: CONSTANT_BUFFER: valid -0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes -0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300548: 0x00000016: vertex count -0x1230054c: 0x00000052: start vertex -0x12300550: 0x00000001: instance count -0x12300554: 0x00000000: start instance -0x12300558: 0x00000000: index bias -0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300560: 0x00007620: VS state -0x12300564: 0x000075c1: GS state -0x12300568: 0x000075e1: Clip state -0x1230056c: 0x00007640: SF state -0x12300570: 0x00007660: WM state -0x12300574: 0x00007cc0: CC state -0x12300578: 0x00000000: MI_NOOP -0x1230057c: 0x00000000: MI_NOOP -0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300584: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300588: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300594: 0x000033f0: buffer address -0x12300598: 0x00000000: max index -0x1230059c: 0x00000000: mbz -0x123005a0: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123005a4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123005a8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123005ac: 0x60020100: CONSTANT_BUFFER: valid -0x123005b0: 0x00000502: offset: 0x00000500, length: 192 bytes -0x123005b4: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123005b8: 0x0000002a: vertex count -0x123005bc: 0x00000000: start vertex -0x123005c0: 0x00000001: instance count -0x123005c4: 0x00000000: start instance -0x123005c8: 0x00000000: index bias -0x123005cc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123005d0: 0x00007620: VS state -0x123005d4: 0x000075a1: GS state -0x123005d8: 0x000075e1: Clip state -0x123005dc: 0x00007640: SF state -0x123005e0: 0x00007660: WM state -0x123005e4: 0x00007cc0: CC state -0x123005e8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123005ec: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x123005f0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x123005f4: 0x60020100: CONSTANT_BUFFER: valid -0x123005f8: 0x00000502: offset: 0x00000500, length: 192 bytes -0x123005fc: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300600: 0x00000028: vertex count -0x12300604: 0x0000002a: start vertex -0x12300608: 0x00000001: instance count -0x1230060c: 0x00000000: start instance -0x12300610: 0x00000000: index bias -0x12300614: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300618: 0x00007620: VS state -0x1230061c: 0x00007581: GS state -0x12300620: 0x000075e1: Clip state -0x12300624: 0x00007640: SF state -0x12300628: 0x00007660: WM state -0x1230062c: 0x00007cc0: CC state -0x12300630: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300634: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300638: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230063c: 0x60020100: CONSTANT_BUFFER: valid -0x12300640: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x12300644: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300648: 0x0000002a: vertex count -0x1230064c: 0x00000052: start vertex -0x12300650: 0x00000001: instance count -0x12300654: 0x00000000: start instance -0x12300658: 0x00000000: index bias -0x1230065c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300660: 0x00007620: VS state -0x12300664: 0x00007561: GS state -0x12300668: 0x000075e1: Clip state -0x1230066c: 0x00007640: SF state -0x12300670: 0x00007660: WM state -0x12300674: 0x00007cc0: CC state -0x12300678: 0x00000000: MI_NOOP -0x1230067c: 0x00000000: MI_NOOP -0x12300680: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300684: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300688: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230068c: 0x60020100: CONSTANT_BUFFER: valid -0x12300690: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x12300694: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300698: 0x00000028: vertex count -0x1230069c: 0x0000007c: start vertex -0x123006a0: 0x00000001: instance count -0x123006a4: 0x00000000: start instance -0x123006a8: 0x00000000: index bias -0x123006ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123006b0: 0x00007620: VS state -0x123006b4: 0x00007541: GS state -0x123006b8: 0x000075e1: Clip state -0x123006bc: 0x00007640: SF state -0x123006c0: 0x00007660: WM state -0x123006c4: 0x00007cc0: CC state -0x123006c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123006cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x123006d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x123006d4: 0x60020100: CONSTANT_BUFFER: valid -0x123006d8: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x123006dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123006e0: 0x00007520: VS state -0x123006e4: 0x00007541: GS state -0x123006e8: 0x000075e1: Clip state -0x123006ec: 0x00007640: SF state -0x123006f0: 0x00007660: WM state -0x123006f4: 0x00007cc0: CC state -0x123006f8: 0x00000000: MI_NOOP -0x123006fc: 0x00000000: MI_NOOP -0x12300700: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300704: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300708: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230070c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300710: 0x00000018: buffer 0: sequential, pitch 24b -0x12300714: 0x00003bb8: buffer address -0x12300718: 0x00000000: max index -0x1230071c: 0x00000000: mbz -0x12300720: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300724: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300728: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x1230072c: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x12300730: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x12300734: 0x60020100: CONSTANT_BUFFER: valid -0x12300738: 0x00000682: offset: 0x00000680, length: 192 bytes -0x1230073c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300740: 0x00000052: vertex count -0x12300744: 0x00000000: start vertex -0x12300748: 0x00000001: instance count -0x1230074c: 0x00000000: start instance -0x12300750: 0x00000000: index bias -0x12300754: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300758: 0x00007520: VS state -0x1230075c: 0x00000000: GS state -0x12300760: 0x00007481: Clip state -0x12300764: 0x000074c0: SF state -0x12300768: 0x000074e0: WM state -0x1230076c: 0x00007cc0: CC state -0x12300770: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300774: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40 -0x12300778: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256 -0x1230077c: 0x60020100: CONSTANT_BUFFER: valid -0x12300780: 0x00000682: offset: 0x00000680, length: 192 bytes -0x12300784: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300788: 0x00000016: vertex count -0x1230078c: 0x00000052: start vertex -0x12300790: 0x00000001: instance count -0x12300794: 0x00000000: start instance -0x12300798: 0x00000000: index bias -0x1230079c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen5-3d.batch b/intel/tests/gen5-3d.batch deleted file mode 100755 index cf9d8d8e2..000000000 Binary files a/intel/tests/gen5-3d.batch and /dev/null differ diff --git a/intel/tests/gen5-3d.batch-ref.txt b/intel/tests/gen5-3d.batch-ref.txt deleted file mode 100755 index 51dd85f36..000000000 --- a/intel/tests/gen5-3d.batch-ref.txt +++ /dev/null @@ -1,512 +0,0 @@ -0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT -0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP -0x12300008: 0x00000000: dword 1 -0x1230000c: 0x61020000: STATE_SIP -0x12300010: 0x00000000: dword 1 -0x12300014: 0x680b0000: 3DSTATE_VF_STATISTICS -0x12300018: 0x61010006: STATE_BASE_ADDRESS -0x1230001c: 0x00000001: general state base address 0x00000000 -0x12300020: 0x00000001: surface state base address 0x00000000 -0x12300024: 0x00000001: indirect state base address 0x00000000 -0x12300028: 0x00000001: instruction state base address 0x00000000 -0x1230002c: 0x00000001: general state upper bound disabled -0x12300030: 0x00000001: indirect state upper bound disabled -0x12300034: 0x00000001: instruction state upper bound disabled -0x12300038: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x1230003c: 0x00007e20: VS binding table -0x12300040: 0x00000000: GS binding table -0x12300044: 0x00000000: Clip binding table -0x12300048: 0x00000000: SF binding table -0x1230004c: 0x00007e20: WM binding table -0x12300050: 0x79010003: 3DSTATE_CONSTANT_COLOR -0x12300054: 0x00000000: dword 1 -0x12300058: 0x00000000: dword 2 -0x1230005c: 0x00000000: dword 3 -0x12300060: 0x00000000: dword 4 -0x12300064: 0x79050004: 3DSTATE_DEPTH_BUFFER -0x12300068: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled, HiZ 0, Separate Stencil 0 -0x1230006c: 0x00000000: depth offset -0x12300070: 0x09584ac0: 300x300 -0x12300074: 0x00000000: volume depth -0x12300078: 0x00000000: -0x1230007c: 0x02000000: MI_FLUSH -0x12300080: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300084: 0x00007d60: VS state -0x12300088: 0x00000000: GS state -0x1230008c: 0x00007d21: Clip state -0x12300090: 0x00007d80: SF state -0x12300094: 0x00007de0: WM state -0x12300098: 0x00007fc0: CC state -0x1230009c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123000a0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123000a4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123000a8: 0x60010000: CS_URB_STATE -0x123000ac: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 -0x123000b0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE -0x123000b4: 0x00000000: top left: 0,0 -0x123000b8: 0x012b012b: bottom right: 299,299 -0x123000bc: 0x00000000: origin: 0,0 -0x123000c0: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123000c4: 0x0000000c: buffer 0: sequential, pitch 12b -0x123000c8: 0x00000000: buffer address -0x123000cc: 0x0000ffff: max index -0x123000d0: 0x00000000: mbz -0x123000d4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123000d8: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123000dc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123000e0: 0x60020100: CONSTANT_BUFFER: valid -0x123000e4: 0x00000001: offset: 0x00000000, length: 128 bytes -0x123000e8: 0x7b001804: 3DPRIMITIVE: tri fan sequential -0x123000ec: 0x00000004: vertex count -0x123000f0: 0x00000000: start vertex -0x123000f4: 0x00000001: instance count -0x123000f8: 0x00000000: start instance -0x123000fc: 0x00000000: index bias -0x12300100: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x12300104: 0x00007b40: VS binding table -0x12300108: 0x00000000: GS binding table -0x1230010c: 0x00000000: Clip binding table -0x12300110: 0x00000000: SF binding table -0x12300114: 0x00007b40: WM binding table -0x12300118: 0x02000000: MI_FLUSH -0x1230011c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300120: 0x00007aa0: VS state -0x12300124: 0x00007a41: GS state -0x12300128: 0x00007a61: Clip state -0x1230012c: 0x00007ac0: SF state -0x12300130: 0x00007b00: WM state -0x12300134: 0x00007cc0: CC state -0x12300138: 0x00000000: MI_NOOP -0x1230013c: 0x00000000: MI_NOOP -0x12300140: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300144: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300148: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x1230014c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300150: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300154: 0x00000000: buffer address -0x12300158: 0x00007fff: max index -0x1230015c: 0x00000000: mbz -0x12300160: 0x60020100: CONSTANT_BUFFER: valid -0x12300164: 0x00000082: offset: 0x00000080, length: 192 bytes -0x12300168: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x1230016c: 0x00000052: vertex count -0x12300170: 0x00000000: start vertex -0x12300174: 0x00000001: instance count -0x12300178: 0x00000000: start instance -0x1230017c: 0x00000000: index bias -0x12300180: 0x02000000: MI_FLUSH -0x12300184: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300188: 0x00007aa0: VS state -0x1230018c: 0x00007a21: GS state -0x12300190: 0x00007a61: Clip state -0x12300194: 0x00007ac0: SF state -0x12300198: 0x00007b00: WM state -0x1230019c: 0x00007cc0: CC state -0x123001a0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123001a4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123001a8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123001ac: 0x60020100: CONSTANT_BUFFER: valid -0x123001b0: 0x00000082: offset: 0x00000080, length: 192 bytes -0x123001b4: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123001b8: 0x00000050: vertex count -0x123001bc: 0x00000052: start vertex -0x123001c0: 0x00000001: instance count -0x123001c4: 0x00000000: start instance -0x123001c8: 0x00000000: index bias -0x123001cc: 0x02000000: MI_FLUSH -0x123001d0: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123001d4: 0x00007aa0: VS state -0x123001d8: 0x00007a01: GS state -0x123001dc: 0x00007a61: Clip state -0x123001e0: 0x00007ac0: SF state -0x123001e4: 0x00007b00: WM state -0x123001e8: 0x00007cc0: CC state -0x123001ec: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123001f0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123001f4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123001f8: 0x60020100: CONSTANT_BUFFER: valid -0x123001fc: 0x00000142: offset: 0x00000140, length: 192 bytes -0x12300200: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300204: 0x00000052: vertex count -0x12300208: 0x000000a2: start vertex -0x1230020c: 0x00000001: instance count -0x12300210: 0x00000000: start instance -0x12300214: 0x00000000: index bias -0x12300218: 0x02000000: MI_FLUSH -0x1230021c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300220: 0x00007aa0: VS state -0x12300224: 0x000079e1: GS state -0x12300228: 0x00007a61: Clip state -0x1230022c: 0x00007ac0: SF state -0x12300230: 0x00007b00: WM state -0x12300234: 0x00007cc0: CC state -0x12300238: 0x00000000: MI_NOOP -0x1230023c: 0x00000000: MI_NOOP -0x12300240: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300244: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300248: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x1230024c: 0x60020100: CONSTANT_BUFFER: valid -0x12300250: 0x00000142: offset: 0x00000140, length: 192 bytes -0x12300254: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300258: 0x00000050: vertex count -0x1230025c: 0x000000f4: start vertex -0x12300260: 0x00000001: instance count -0x12300264: 0x00000000: start instance -0x12300268: 0x00000000: index bias -0x1230026c: 0x02000000: MI_FLUSH -0x12300270: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300274: 0x00007aa0: VS state -0x12300278: 0x000079c1: GS state -0x1230027c: 0x00007a61: Clip state -0x12300280: 0x00007ac0: SF state -0x12300284: 0x00007b00: WM state -0x12300288: 0x00007cc0: CC state -0x1230028c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300290: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300294: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300298: 0x60020100: CONSTANT_BUFFER: valid -0x1230029c: 0x00000142: offset: 0x00000140, length: 192 bytes -0x123002a0: 0x02000000: MI_FLUSH -0x123002a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123002a8: 0x000079a0: VS state -0x123002ac: 0x000079c1: GS state -0x123002b0: 0x00007a61: Clip state -0x123002b4: 0x00007ac0: SF state -0x123002b8: 0x00007b00: WM state -0x123002bc: 0x00007cc0: CC state -0x123002c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123002c4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123002c8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123002cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123002d0: 0x00000018: buffer 0: sequential, pitch 24b -0x123002d4: 0x00000f48: buffer address -0x123002d8: 0x00007fff: max index -0x123002dc: 0x00000000: mbz -0x123002e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123002e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123002e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123002ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123002f0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123002f4: 0x60020100: CONSTANT_BUFFER: valid -0x123002f8: 0x00000202: offset: 0x00000200, length: 192 bytes -0x123002fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300300: 0x000000a2: vertex count -0x12300304: 0x00000000: start vertex -0x12300308: 0x00000001: instance count -0x1230030c: 0x00000000: start instance -0x12300310: 0x00000000: index bias -0x12300314: 0x02000000: MI_FLUSH -0x12300318: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x1230031c: 0x000079a0: VS state -0x12300320: 0x00000000: GS state -0x12300324: 0x00007901: Clip state -0x12300328: 0x00007940: SF state -0x1230032c: 0x00007960: WM state -0x12300330: 0x00007cc0: CC state -0x12300334: 0x00000000: MI_NOOP -0x12300338: 0x00000000: MI_NOOP -0x1230033c: 0x00000000: MI_NOOP -0x12300340: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300344: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300348: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x1230034c: 0x60020100: CONSTANT_BUFFER: valid -0x12300350: 0x00000202: offset: 0x00000200, length: 192 bytes -0x12300354: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300358: 0x0000002a: vertex count -0x1230035c: 0x000000a2: start vertex -0x12300360: 0x00000001: instance count -0x12300364: 0x00000000: start instance -0x12300368: 0x00000000: index bias -0x1230036c: 0x02000000: MI_FLUSH -0x12300370: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300374: 0x00007860: VS state -0x12300378: 0x00007801: GS state -0x1230037c: 0x00007821: Clip state -0x12300380: 0x00007880: SF state -0x12300384: 0x000078a0: WM state -0x12300388: 0x00007cc0: CC state -0x1230038c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300390: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300394: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300398: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x1230039c: 0x0000000c: buffer 0: sequential, pitch 12b -0x123003a0: 0x00002268: buffer address -0x123003a4: 0x00007fff: max index -0x123003a8: 0x00000000: mbz -0x123003ac: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123003b0: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123003b4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123003b8: 0x60020100: CONSTANT_BUFFER: valid -0x123003bc: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x123003c0: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123003c4: 0x0000002a: vertex count -0x123003c8: 0x00000000: start vertex -0x123003cc: 0x00000001: instance count -0x123003d0: 0x00000000: start instance -0x123003d4: 0x00000000: index bias -0x123003d8: 0x02000000: MI_FLUSH -0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123003e0: 0x00007860: VS state -0x123003e4: 0x000077e1: GS state -0x123003e8: 0x00007821: Clip state -0x123003ec: 0x00007880: SF state -0x123003f0: 0x000078a0: WM state -0x123003f4: 0x00007cc0: CC state -0x123003f8: 0x00000000: MI_NOOP -0x123003fc: 0x00000000: MI_NOOP -0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300404: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300408: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x1230040c: 0x60020100: CONSTANT_BUFFER: valid -0x12300410: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x12300414: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300418: 0x00000028: vertex count -0x1230041c: 0x0000002a: start vertex -0x12300420: 0x00000001: instance count -0x12300424: 0x00000000: start instance -0x12300428: 0x00000000: index bias -0x1230042c: 0x02000000: MI_FLUSH -0x12300430: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300434: 0x00007860: VS state -0x12300438: 0x000077c1: GS state -0x1230043c: 0x00007821: Clip state -0x12300440: 0x00007880: SF state -0x12300444: 0x000078a0: WM state -0x12300448: 0x00007cc0: CC state -0x1230044c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300450: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300454: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300458: 0x60020100: CONSTANT_BUFFER: valid -0x1230045c: 0x00000382: offset: 0x00000380, length: 192 bytes -0x12300460: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300464: 0x0000002a: vertex count -0x12300468: 0x00000052: start vertex -0x1230046c: 0x00000001: instance count -0x12300470: 0x00000000: start instance -0x12300474: 0x00000000: index bias -0x12300478: 0x02000000: MI_FLUSH -0x1230047c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300480: 0x00007860: VS state -0x12300484: 0x000077a1: GS state -0x12300488: 0x00007821: Clip state -0x1230048c: 0x00007880: SF state -0x12300490: 0x000078a0: WM state -0x12300494: 0x00007cc0: CC state -0x12300498: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230049c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123004a0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123004a4: 0x60020100: CONSTANT_BUFFER: valid -0x123004a8: 0x00000382: offset: 0x00000380, length: 192 bytes -0x123004ac: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123004b0: 0x00000028: vertex count -0x123004b4: 0x0000007c: start vertex -0x123004b8: 0x00000001: instance count -0x123004bc: 0x00000000: start instance -0x123004c0: 0x00000000: index bias -0x123004c4: 0x02000000: MI_FLUSH -0x123004c8: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123004cc: 0x00007860: VS state -0x123004d0: 0x00007781: GS state -0x123004d4: 0x00007821: Clip state -0x123004d8: 0x00007880: SF state -0x123004dc: 0x000078a0: WM state -0x123004e0: 0x00007cc0: CC state -0x123004e4: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123004e8: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123004ec: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123004f0: 0x60020100: CONSTANT_BUFFER: valid -0x123004f4: 0x00000382: offset: 0x00000380, length: 192 bytes -0x123004f8: 0x02000000: MI_FLUSH -0x123004fc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300500: 0x00007760: VS state -0x12300504: 0x00007781: GS state -0x12300508: 0x00007821: Clip state -0x1230050c: 0x00007880: SF state -0x12300510: 0x000078a0: WM state -0x12300514: 0x00007cc0: CC state -0x12300518: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230051c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300520: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300524: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300528: 0x00000018: buffer 0: sequential, pitch 24b -0x1230052c: 0x00002a30: buffer address -0x12300530: 0x00007fff: max index -0x12300534: 0x00000000: mbz -0x12300538: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x1230053c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300540: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300544: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x12300548: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x1230054c: 0x60020100: CONSTANT_BUFFER: valid -0x12300550: 0x00000442: offset: 0x00000440, length: 192 bytes -0x12300554: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300558: 0x00000052: vertex count -0x1230055c: 0x00000000: start vertex -0x12300560: 0x00000001: instance count -0x12300564: 0x00000000: start instance -0x12300568: 0x00000000: index bias -0x1230056c: 0x02000000: MI_FLUSH -0x12300570: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300574: 0x00007760: VS state -0x12300578: 0x00000000: GS state -0x1230057c: 0x000076c1: Clip state -0x12300580: 0x00007700: SF state -0x12300584: 0x00007720: WM state -0x12300588: 0x00007cc0: CC state -0x1230058c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300590: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300594: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300598: 0x60020100: CONSTANT_BUFFER: valid -0x1230059c: 0x00000442: offset: 0x00000440, length: 192 bytes -0x123005a0: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x123005a4: 0x00000016: vertex count -0x123005a8: 0x00000052: start vertex -0x123005ac: 0x00000001: instance count -0x123005b0: 0x00000000: start instance -0x123005b4: 0x00000000: index bias -0x123005b8: 0x02000000: MI_FLUSH -0x123005bc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123005c0: 0x00007620: VS state -0x123005c4: 0x000075c1: GS state -0x123005c8: 0x000075e1: Clip state -0x123005cc: 0x00007640: SF state -0x123005d0: 0x00007660: WM state -0x123005d4: 0x00007cc0: CC state -0x123005d8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123005dc: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123005e0: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123005e4: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123005e8: 0x0000000c: buffer 0: sequential, pitch 12b -0x123005ec: 0x000033f0: buffer address -0x123005f0: 0x00007fff: max index -0x123005f4: 0x00000000: mbz -0x123005f8: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123005fc: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300600: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300604: 0x60020100: CONSTANT_BUFFER: valid -0x12300608: 0x00000502: offset: 0x00000500, length: 192 bytes -0x1230060c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300610: 0x0000002a: vertex count -0x12300614: 0x00000000: start vertex -0x12300618: 0x00000001: instance count -0x1230061c: 0x00000000: start instance -0x12300620: 0x00000000: index bias -0x12300624: 0x02000000: MI_FLUSH -0x12300628: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x1230062c: 0x00007620: VS state -0x12300630: 0x000075a1: GS state -0x12300634: 0x000075e1: Clip state -0x12300638: 0x00007640: SF state -0x1230063c: 0x00007660: WM state -0x12300640: 0x00007cc0: CC state -0x12300644: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300648: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x1230064c: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300650: 0x60020100: CONSTANT_BUFFER: valid -0x12300654: 0x00000502: offset: 0x00000500, length: 192 bytes -0x12300658: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x1230065c: 0x00000028: vertex count -0x12300660: 0x0000002a: start vertex -0x12300664: 0x00000001: instance count -0x12300668: 0x00000000: start instance -0x1230066c: 0x00000000: index bias -0x12300670: 0x02000000: MI_FLUSH -0x12300674: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300678: 0x00007620: VS state -0x1230067c: 0x00007581: GS state -0x12300680: 0x000075e1: Clip state -0x12300684: 0x00007640: SF state -0x12300688: 0x00007660: WM state -0x1230068c: 0x00007cc0: CC state -0x12300690: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300694: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300698: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x1230069c: 0x60020100: CONSTANT_BUFFER: valid -0x123006a0: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x123006a4: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123006a8: 0x0000002a: vertex count -0x123006ac: 0x00000052: start vertex -0x123006b0: 0x00000001: instance count -0x123006b4: 0x00000000: start instance -0x123006b8: 0x00000000: index bias -0x123006bc: 0x02000000: MI_FLUSH -0x123006c0: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123006c4: 0x00007620: VS state -0x123006c8: 0x00007561: GS state -0x123006cc: 0x000075e1: Clip state -0x123006d0: 0x00007640: SF state -0x123006d4: 0x00007660: WM state -0x123006d8: 0x00007cc0: CC state -0x123006dc: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123006e0: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123006e4: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123006e8: 0x60020100: CONSTANT_BUFFER: valid -0x123006ec: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x123006f0: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123006f4: 0x00000028: vertex count -0x123006f8: 0x0000007c: start vertex -0x123006fc: 0x00000001: instance count -0x12300700: 0x00000000: start instance -0x12300704: 0x00000000: index bias -0x12300708: 0x02000000: MI_FLUSH -0x1230070c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300710: 0x00007620: VS state -0x12300714: 0x00007541: GS state -0x12300718: 0x000075e1: Clip state -0x1230071c: 0x00007640: SF state -0x12300720: 0x00007660: WM state -0x12300724: 0x00007cc0: CC state -0x12300728: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230072c: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300730: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300734: 0x60020100: CONSTANT_BUFFER: valid -0x12300738: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x1230073c: 0x02000000: MI_FLUSH -0x12300740: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300744: 0x00007520: VS state -0x12300748: 0x00007541: GS state -0x1230074c: 0x000075e1: Clip state -0x12300750: 0x00007640: SF state -0x12300754: 0x00007660: WM state -0x12300758: 0x00007cc0: CC state -0x1230075c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300760: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x12300764: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x12300768: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x1230076c: 0x00000018: buffer 0: sequential, pitch 24b -0x12300770: 0x00003bb8: buffer address -0x12300774: 0x00007fff: max index -0x12300778: 0x00000000: mbz -0x1230077c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300780: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300784: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300788: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x1230078c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300790: 0x60020100: CONSTANT_BUFFER: valid -0x12300794: 0x00000682: offset: 0x00000680, length: 192 bytes -0x12300798: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x1230079c: 0x00000052: vertex count -0x123007a0: 0x00000000: start vertex -0x123007a4: 0x00000001: instance count -0x123007a8: 0x00000000: start instance -0x123007ac: 0x00000000: index bias -0x123007b0: 0x02000000: MI_FLUSH -0x123007b4: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123007b8: 0x00007520: VS state -0x123007bc: 0x00000000: GS state -0x123007c0: 0x00007481: Clip state -0x123007c4: 0x000074c0: SF state -0x123007c8: 0x000074e0: WM state -0x123007cc: 0x00007cc0: CC state -0x123007d0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123007d4: 0x12444100: vs fence: 256, clip_fence: 292, gs_fence: 272 -0x123007d8: 0x40000184: sf fence: 388, vfe_fence: 0, cs_fence: 1024 -0x123007dc: 0x60020100: CONSTANT_BUFFER: valid -0x123007e0: 0x00000682: offset: 0x00000680, length: 192 bytes -0x123007e4: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x123007e8: 0x00000016: vertex count -0x123007ec: 0x00000052: start vertex -0x123007f0: 0x00000001: instance count -0x123007f4: 0x00000000: start instance -0x123007f8: 0x00000000: index bias -0x123007fc: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen6-3d.batch b/intel/tests/gen6-3d.batch deleted file mode 100755 index d57147e9a..000000000 Binary files a/intel/tests/gen6-3d.batch and /dev/null differ diff --git a/intel/tests/gen6-3d.batch-ref.txt b/intel/tests/gen6-3d.batch-ref.txt deleted file mode 100755 index 04cbddc73..000000000 --- a/intel/tests/gen6-3d.batch-ref.txt +++ /dev/null @@ -1,990 +0,0 @@ -0x12300000: 0x7a000002: PIPE_CONTROL -0x12300004: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300008: 0x00000000: -0x1230000c: 0x00000000: -0x12300010: 0x7a000002: PIPE_CONTROL -0x12300014: 0x00004000: qword write, -0x12300018: 0x00000000: -0x1230001c: 0x00000000: -0x12300020: 0x69040000: 3DSTATE_PIPELINE_SELECT -0x12300024: 0x790d0001: 3DSTATE_MULTISAMPLE -0x12300028: 0x00000000: dword 1 -0x1230002c: 0x00000000: dword 2 -0x12300030: 0x78180000: 3DSTATE_SAMPLE_MASK -0x12300034: 0x00000001: dword 1 -0x12300038: 0x790b0002: 3DSTATE_GS_SVB_INDEX -0x1230003c: 0x00000000: dword 1 -0x12300040: 0x00000000: dword 2 -0x12300044: 0xffffffff: dword 3 -0x12300048: 0x790b0002: 3DSTATE_GS_SVB_INDEX -0x1230004c: 0x20000000: dword 1 -0x12300050: 0x00000000: dword 2 -0x12300054: 0xffffffff: dword 3 -0x12300058: 0x790b0002: 3DSTATE_GS_SVB_INDEX -0x1230005c: 0x40000000: dword 1 -0x12300060: 0x00000000: dword 2 -0x12300064: 0xffffffff: dword 3 -0x12300068: 0x790b0002: 3DSTATE_GS_SVB_INDEX -0x1230006c: 0x60000000: dword 1 -0x12300070: 0x00000000: dword 2 -0x12300074: 0xffffffff: dword 3 -0x12300078: 0x61020000: STATE_SIP -0x1230007c: 0x00000000: dword 1 -0x12300080: 0x680b0000: 3DSTATE_VF_STATISTICS -0x12300084: 0x61010008: STATE_BASE_ADDRESS -0x12300088: 0x00000001: general state base address 0x00000000 -0x1230008c: 0x00000001: surface state base address 0x00000000 -0x12300090: 0x00000001: dynamic state base address 0x00000000 -0x12300094: 0x00000001: indirect state base address 0x00000000 -0x12300098: 0x00000001: instruction state base address 0x00000000 -0x1230009c: 0x00000001: general state upper bound disabled -0x123000a0: 0x00000001: dynamic state upper bound disabled -0x123000a4: 0x00000001: indirect state upper bound disabled -0x123000a8: 0x00000001: instruction state upper bound disabled -0x123000ac: 0x780d1c02: 3DSTATE_VIEWPORT_STATE_POINTERS -0x123000b0: 0x00007fe0: clip -0x123000b4: 0x00007fc0: sf -0x123000b8: 0x00007fa0: cc -0x123000bc: 0x78050001: 3DSTATE_URB -0x123000c0: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x123000c4: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x123000c8: 0x780e0002: 3DSTATE_CC_STATE_POINTERS -0x123000cc: 0x00007f81: blend change 1 -0x123000d0: 0x00007f01: depth stencil change 1 -0x123000d4: 0x00007f41: cc change 1 -0x123000d8: 0x78021302: 3DSTATE_SAMPLER_STATE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x123000dc: 0x00000000: VS sampler state -0x123000e0: 0x00000000: GS sampler state -0x123000e4: 0x00000000: WM sampler state -0x123000e8: 0x78150003: 3DSTATE_CONSTANT_VS_STATE -0x123000ec: 0x00000000: dword 1 -0x123000f0: 0x00000000: dword 2 -0x123000f4: 0x00000000: dword 3 -0x123000f8: 0x00000000: dword 4 -0x123000fc: 0x78100004: 3DSTATE_VS -0x12300100: 0x00000000: kernel pointer -0x12300104: 0x00000000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300108: 0x00000000: scratch offset -0x1230010c: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300110: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300114: 0x7a000002: PIPE_CONTROL -0x12300118: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x1230011c: 0x00000000: -0x12300120: 0x00000000: -0x12300124: 0x78160003: 3DSTATE_CONSTANT_GS_STATE -0x12300128: 0x00000000: dword 1 -0x1230012c: 0x00000000: dword 2 -0x12300130: 0x00000000: dword 3 -0x12300134: 0x00000000: dword 4 -0x12300138: 0x78110005: 3DSTATE_GS -0x1230013c: 0x00000000: kernel pointer -0x12300140: 0x00000000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300144: 0x00000000: scratch offset -0x12300148: 0x00000001: Dispatch GRF start 1, VUE read length 0, VUE read offset 0 -0x1230014c: 0x00000500: Max Threads 1, Rendering enable -0x12300150: 0x00000000: Reorder disable, Discard Adjaceny disable, GS disable -0x12300154: 0x78120002: 3DSTATE_CLIP -0x12300158: 0x00000400: UserClip distance cull test mask 0x0 -0x1230015c: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300160: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300164: 0x78130012: 3DSTATE_SF -0x12300168: 0x00200810: Attrib Out 0, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x1230016c: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300170: 0x22000000: AA disable, CullMode 1, Scissor disable, Multisample m ode 0 -0x12300174: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300178: 0x00000000: Global Depth Offset Constant 0.000000 -0x1230017c: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300180: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300184: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300188: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230018c: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300190: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300194: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300198: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230019c: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123001a0: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123001a4: 0x00000000: Point Sprite TexCoord Enable -0x123001a8: 0x00000000: Const Interp Enable -0x123001ac: 0x00000000: Attrib 7-0 WrapShortest Enable -0x123001b0: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123001b4: 0x78171003: 3DSTATE_CONSTANT_PS_STATE -0x123001b8: 0x00007ee0: dword 1 -0x123001bc: 0x00000000: dword 2 -0x123001c0: 0x00000000: dword 3 -0x123001c4: 0x00000000: dword 4 -0x123001c8: 0x78140007: 3DSTATE_WM -0x123001cc: 0x000000c0: kernel start pointer 0 -0x123001d0: 0x00000000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123001d4: 0x00000000: scratch offset -0x123001d8: 0x80020002: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 2 -0x123001dc: 0x4e084003: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 1 -0x123001e0: 0x00000000: Num SF output 0, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123001e4: 0x00000000: kernel start pointer 1 -0x123001e8: 0x00000140: kernel start pointer 2 -0x123001ec: 0x780f0000: 3DSTATE_SCISSOR_POINTERS -0x123001f0: 0x00007d20: scissor rect offset -0x123001f4: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x123001f8: 0x00007d40: VS binding table -0x123001fc: 0x00007d40: GS binding table -0x12300200: 0x00007d40: WM binding table -0x12300204: 0x7a000002: PIPE_CONTROL -0x12300208: 0x00002000: no write, depth stall, -0x1230020c: 0x00000000: -0x12300210: 0x00000000: -0x12300214: 0x7a000002: PIPE_CONTROL -0x12300218: 0x00000001: no write, depth cache flush, -0x1230021c: 0x00000000: -0x12300220: 0x00000000: -0x12300224: 0x7a000002: PIPE_CONTROL -0x12300228: 0x00002000: no write, depth stall, -0x1230022c: 0x00000000: -0x12300230: 0x00000000: -0x12300234: 0x79050005: 3DSTATE_DEPTH_BUFFER -0x12300238: 0x2c6c05ff: 2D, unknown, pitch = 1536 bytes, tiled, HiZ 1, Separate Stencil 1 -0x1230023c: 0x00000000: depth offset -0x12300240: 0x09584ac0: 300x300 -0x12300244: 0x00000000: volume depth -0x12300248: 0x00000000: -0x1230024c: 0x00000000: -0x12300250: 0x790f0001: 3DSTATE_HIER_DEPTH_BUFFER -0x12300254: 0x000005ff: dword 1 -0x12300258: 0x00000000: dword 2 -0x1230025c: 0x790e0001: 3D UNKNOWN: 3d_965 opcode = 0x790e -0x12300260: 0x0000027f: MI_NOOP -0x12300264: 0x00000000: MI_NOOP -0x12300268: 0x79100000: 3DSTATE_CLEAR_PARAMS -0x1230026c: 0x00000000: dword 1 -0x12300270: 0x79000002: 3DSTATE_DRAWING_RECTANGLE -0x12300274: 0x00000000: top left: 0,0 -0x12300278: 0x012b012b: bottom right: 299,299 -0x1230027c: 0x00000000: origin: 0,0 -0x12300280: 0x790b0002: 3DSTATE_GS_SVB_INDEX -0x12300284: 0x00000000: dword 1 -0x12300288: 0x00000000: dword 2 -0x1230028c: 0x00000000: dword 3 -0x12300290: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300294: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300298: 0x00000000: buffer address -0x1230029c: 0x0000ffff: max index -0x123002a0: 0x00000000: mbz -0x123002a4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123002a8: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123002ac: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123002b0: 0x7b001804: 3DPRIMITIVE: tri fan sequential -0x123002b4: 0x00000004: vertex count -0x123002b8: 0x00000000: start vertex -0x123002bc: 0x00000001: instance count -0x123002c0: 0x00000000: start instance -0x123002c4: 0x00000000: index bias -0x123002c8: 0x78050001: 3DSTATE_URB -0x123002cc: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x123002d0: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x123002d4: 0x780e0002: 3DSTATE_CC_STATE_POINTERS -0x123002d8: 0x00007f81: blend change 1 -0x123002dc: 0x00007cc1: depth stencil change 1 -0x123002e0: 0x00007d01: cc change 1 -0x123002e4: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x123002e8: 0x00007b85: dword 1 -0x123002ec: 0x00000000: dword 2 -0x123002f0: 0x00000000: dword 3 -0x123002f4: 0x00000000: dword 4 -0x123002f8: 0x78100004: 3DSTATE_VS -0x123002fc: 0x00000240: kernel pointer -0x12300300: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300304: 0x00000000: scratch offset -0x12300308: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x1230030c: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300310: 0x7a000002: PIPE_CONTROL -0x12300314: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300318: 0x00000000: -0x1230031c: 0x00000000: -0x12300320: 0x7a000002: PIPE_CONTROL -0x12300324: 0x00004000: qword write, -0x12300328: 0x00000000: -0x1230032c: 0x00000000: -0x12300330: 0x7a000002: PIPE_CONTROL -0x12300334: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300338: 0x00000000: -0x1230033c: 0x00000000: -0x12300340: 0x78120002: 3DSTATE_CLIP -0x12300344: 0x00000400: UserClip distance cull test mask 0x0 -0x12300348: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x1230034c: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300350: 0x78130012: 3DSTATE_SF -0x12300354: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300358: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x1230035c: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300360: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300364: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300368: 0x00000000: Global Depth Offset Scale 0.000000 -0x1230036c: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300370: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300374: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300378: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230037c: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300380: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300384: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300388: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230038c: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300390: 0x00000000: Point Sprite TexCoord Enable -0x12300394: 0x00000001: Const Interp Enable -0x12300398: 0x00000000: Attrib 7-0 WrapShortest Enable -0x1230039c: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123003a0: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x123003a4: 0x00000000: dword 1 -0x123003a8: 0x00000000: dword 2 -0x123003ac: 0x00000000: dword 3 -0x123003b0: 0x00000000: dword 4 -0x123003b4: 0x78140007: 3DSTATE_WM -0x123003b8: 0x00000500: kernel start pointer 0 -0x123003bc: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123003c0: 0x00000000: scratch offset -0x123003c4: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x123003c8: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x123003cc: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123003d0: 0x00000000: kernel start pointer 1 -0x123003d4: 0x00000500: kernel start pointer 2 -0x123003d8: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x123003dc: 0x00007a00: VS binding table -0x123003e0: 0x00007a00: GS binding table -0x123003e4: 0x00007a00: WM binding table -0x123003e8: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123003ec: 0x0000000c: buffer 0: sequential, pitch 12b -0x123003f0: 0x00000000: buffer address -0x123003f4: 0x00007fff: max index -0x123003f8: 0x00000000: mbz -0x123003fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300400: 0x00000052: vertex count -0x12300404: 0x00000000: start vertex -0x12300408: 0x00000001: instance count -0x1230040c: 0x00000000: start instance -0x12300410: 0x00000000: index bias -0x12300414: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300418: 0x00000050: vertex count -0x1230041c: 0x00000052: start vertex -0x12300420: 0x00000001: instance count -0x12300424: 0x00000000: start instance -0x12300428: 0x00000000: index bias -0x1230042c: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300430: 0x000078c5: dword 1 -0x12300434: 0x00000000: dword 2 -0x12300438: 0x00000000: dword 3 -0x1230043c: 0x00000000: dword 4 -0x12300440: 0x78100004: 3DSTATE_VS -0x12300444: 0x00000240: kernel pointer -0x12300448: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x1230044c: 0x00000000: scratch offset -0x12300450: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300454: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300458: 0x7a000002: PIPE_CONTROL -0x1230045c: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300460: 0x00000000: -0x12300464: 0x00000000: -0x12300468: 0x7a000002: PIPE_CONTROL -0x1230046c: 0x00004000: qword write, -0x12300470: 0x00000000: -0x12300474: 0x00000000: -0x12300478: 0x7a000002: PIPE_CONTROL -0x1230047c: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300480: 0x00000000: -0x12300484: 0x00000000: -0x12300488: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x1230048c: 0x00000000: dword 1 -0x12300490: 0x00000000: dword 2 -0x12300494: 0x00000000: dword 3 -0x12300498: 0x00000000: dword 4 -0x1230049c: 0x78140007: 3DSTATE_WM -0x123004a0: 0x00000500: kernel start pointer 0 -0x123004a4: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123004a8: 0x00000000: scratch offset -0x123004ac: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x123004b0: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x123004b4: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123004b8: 0x00000000: kernel start pointer 1 -0x123004bc: 0x00000500: kernel start pointer 2 -0x123004c0: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123004c4: 0x00000052: vertex count -0x123004c8: 0x000000a2: start vertex -0x123004cc: 0x00000001: instance count -0x123004d0: 0x00000000: start instance -0x123004d4: 0x00000000: index bias -0x123004d8: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123004dc: 0x00000050: vertex count -0x123004e0: 0x000000f4: start vertex -0x123004e4: 0x00000001: instance count -0x123004e8: 0x00000000: start instance -0x123004ec: 0x00000000: index bias -0x123004f0: 0x78050001: 3DSTATE_URB -0x123004f4: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x123004f8: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x123004fc: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300500: 0x00007785: dword 1 -0x12300504: 0x00000000: dword 2 -0x12300508: 0x00000000: dword 3 -0x1230050c: 0x00000000: dword 4 -0x12300510: 0x78100004: 3DSTATE_VS -0x12300514: 0x00000640: kernel pointer -0x12300518: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x1230051c: 0x00000000: scratch offset -0x12300520: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300524: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300528: 0x7a000002: PIPE_CONTROL -0x1230052c: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300530: 0x00000000: -0x12300534: 0x00000000: -0x12300538: 0x7a000002: PIPE_CONTROL -0x1230053c: 0x00004000: qword write, -0x12300540: 0x00000000: -0x12300544: 0x00000000: -0x12300548: 0x7a000002: PIPE_CONTROL -0x1230054c: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300550: 0x00000000: -0x12300554: 0x00000000: -0x12300558: 0x78130012: 3DSTATE_SF -0x1230055c: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300560: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300564: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300568: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x1230056c: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300570: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300574: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300578: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230057c: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300580: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300584: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300588: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230058c: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300590: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300594: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300598: 0x00000000: Point Sprite TexCoord Enable -0x1230059c: 0x00000001: Const Interp Enable -0x123005a0: 0x00000000: Attrib 7-0 WrapShortest Enable -0x123005a4: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123005a8: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x123005ac: 0x00007600: VS binding table -0x123005b0: 0x00007600: GS binding table -0x123005b4: 0x00007600: WM binding table -0x123005b8: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123005bc: 0x00000018: buffer 0: sequential, pitch 24b -0x123005c0: 0x00000f48: buffer address -0x123005c4: 0x00007fff: max index -0x123005c8: 0x00000000: mbz -0x123005cc: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123005d0: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123005d4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123005d8: 0x0240000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123005dc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123005e0: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123005e4: 0x000000a2: vertex count -0x123005e8: 0x00000000: start vertex -0x123005ec: 0x00000001: instance count -0x123005f0: 0x00000000: start instance -0x123005f4: 0x00000000: index bias -0x123005f8: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x123005fc: 0x000074c5: dword 1 -0x12300600: 0x00000000: dword 2 -0x12300604: 0x00000000: dword 3 -0x12300608: 0x00000000: dword 4 -0x1230060c: 0x78100004: 3DSTATE_VS -0x12300610: 0x00000640: kernel pointer -0x12300614: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300618: 0x00000000: scratch offset -0x1230061c: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300620: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300624: 0x7a000002: PIPE_CONTROL -0x12300628: 0x00100002: no write, cs stall, stall at scoreboard, -0x1230062c: 0x00000000: -0x12300630: 0x00000000: -0x12300634: 0x7a000002: PIPE_CONTROL -0x12300638: 0x00004000: qword write, -0x1230063c: 0x00000000: -0x12300640: 0x00000000: -0x12300644: 0x7a000002: PIPE_CONTROL -0x12300648: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x1230064c: 0x00000000: -0x12300650: 0x00000000: -0x12300654: 0x78120002: 3DSTATE_CLIP -0x12300658: 0x00000400: UserClip distance cull test mask 0x0 -0x1230065c: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300660: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300664: 0x78130012: 3DSTATE_SF -0x12300668: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x1230066c: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300670: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300674: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300678: 0x00000000: Global Depth Offset Constant 0.000000 -0x1230067c: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300680: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300684: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300688: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230068c: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300690: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300694: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300698: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x1230069c: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123006a0: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123006a4: 0x00000000: Point Sprite TexCoord Enable -0x123006a8: 0x00000000: Const Interp Enable -0x123006ac: 0x00000000: Attrib 7-0 WrapShortest Enable -0x123006b0: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123006b4: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x123006b8: 0x00000000: dword 1 -0x123006bc: 0x00000000: dword 2 -0x123006c0: 0x00000000: dword 3 -0x123006c4: 0x00000000: dword 4 -0x123006c8: 0x78140007: 3DSTATE_WM -0x123006cc: 0x00000900: kernel start pointer 0 -0x123006d0: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123006d4: 0x00000000: scratch offset -0x123006d8: 0x80060000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 6, start[1] 0, start[2] 0 -0x123006dc: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x123006e0: 0x00100400: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x1, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123006e4: 0x00000000: kernel start pointer 1 -0x123006e8: 0x00000900: kernel start pointer 2 -0x123006ec: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123006f0: 0x0000002a: vertex count -0x123006f4: 0x000000a2: start vertex -0x123006f8: 0x00000001: instance count -0x123006fc: 0x00000000: start instance -0x12300700: 0x00000000: index bias -0x12300704: 0x78050001: 3DSTATE_URB -0x12300708: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x1230070c: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x12300710: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300714: 0x00007385: dword 1 -0x12300718: 0x00000000: dword 2 -0x1230071c: 0x00000000: dword 3 -0x12300720: 0x00000000: dword 4 -0x12300724: 0x78100004: 3DSTATE_VS -0x12300728: 0x00000240: kernel pointer -0x1230072c: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300730: 0x00000000: scratch offset -0x12300734: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300738: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x1230073c: 0x7a000002: PIPE_CONTROL -0x12300740: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300744: 0x00000000: -0x12300748: 0x00000000: -0x1230074c: 0x7a000002: PIPE_CONTROL -0x12300750: 0x00004000: qword write, -0x12300754: 0x00000000: -0x12300758: 0x00000000: -0x1230075c: 0x7a000002: PIPE_CONTROL -0x12300760: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300764: 0x00000000: -0x12300768: 0x00000000: -0x1230076c: 0x78120002: 3DSTATE_CLIP -0x12300770: 0x00000400: UserClip distance cull test mask 0x0 -0x12300774: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300778: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x1230077c: 0x78130012: 3DSTATE_SF -0x12300780: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300784: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300788: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x1230078c: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300790: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300794: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300798: 0x00000000: Global Depth Offset Clamp 0.000000 -0x1230079c: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007a0: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007a4: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007a8: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007ac: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007b0: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007b4: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007b8: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123007bc: 0x00000000: Point Sprite TexCoord Enable -0x123007c0: 0x00000001: Const Interp Enable -0x123007c4: 0x00000000: Attrib 7-0 WrapShortest Enable -0x123007c8: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123007cc: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x123007d0: 0x00000000: dword 1 -0x123007d4: 0x00000000: dword 2 -0x123007d8: 0x00000000: dword 3 -0x123007dc: 0x00000000: dword 4 -0x123007e0: 0x78140007: 3DSTATE_WM -0x123007e4: 0x00000500: kernel start pointer 0 -0x123007e8: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123007ec: 0x00000000: scratch offset -0x123007f0: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x123007f4: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x123007f8: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123007fc: 0x00000000: kernel start pointer 1 -0x12300800: 0x00000500: kernel start pointer 2 -0x12300804: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x12300808: 0x00007200: VS binding table -0x1230080c: 0x00007200: GS binding table -0x12300810: 0x00007200: WM binding table -0x12300814: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300818: 0x0000000c: buffer 0: sequential, pitch 12b -0x1230081c: 0x00002268: buffer address -0x12300820: 0x00007fff: max index -0x12300824: 0x00000000: mbz -0x12300828: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x1230082c: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300830: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300834: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300838: 0x0000002a: vertex count -0x1230083c: 0x00000000: start vertex -0x12300840: 0x00000001: instance count -0x12300844: 0x00000000: start instance -0x12300848: 0x00000000: index bias -0x1230084c: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300850: 0x00000028: vertex count -0x12300854: 0x0000002a: start vertex -0x12300858: 0x00000001: instance count -0x1230085c: 0x00000000: start instance -0x12300860: 0x00000000: index bias -0x12300864: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300868: 0x000070c5: dword 1 -0x1230086c: 0x00000000: dword 2 -0x12300870: 0x00000000: dword 3 -0x12300874: 0x00000000: dword 4 -0x12300878: 0x78100004: 3DSTATE_VS -0x1230087c: 0x00000240: kernel pointer -0x12300880: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300884: 0x00000000: scratch offset -0x12300888: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x1230088c: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300890: 0x7a000002: PIPE_CONTROL -0x12300894: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300898: 0x00000000: -0x1230089c: 0x00000000: -0x123008a0: 0x7a000002: PIPE_CONTROL -0x123008a4: 0x00004000: qword write, -0x123008a8: 0x00000000: -0x123008ac: 0x00000000: -0x123008b0: 0x7a000002: PIPE_CONTROL -0x123008b4: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x123008b8: 0x00000000: -0x123008bc: 0x00000000: -0x123008c0: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x123008c4: 0x00000000: dword 1 -0x123008c8: 0x00000000: dword 2 -0x123008cc: 0x00000000: dword 3 -0x123008d0: 0x00000000: dword 4 -0x123008d4: 0x78140007: 3DSTATE_WM -0x123008d8: 0x00000500: kernel start pointer 0 -0x123008dc: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123008e0: 0x00000000: scratch offset -0x123008e4: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x123008e8: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x123008ec: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x123008f0: 0x00000000: kernel start pointer 1 -0x123008f4: 0x00000500: kernel start pointer 2 -0x123008f8: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123008fc: 0x0000002a: vertex count -0x12300900: 0x00000052: start vertex -0x12300904: 0x00000001: instance count -0x12300908: 0x00000000: start instance -0x1230090c: 0x00000000: index bias -0x12300910: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300914: 0x00000028: vertex count -0x12300918: 0x0000007c: start vertex -0x1230091c: 0x00000001: instance count -0x12300920: 0x00000000: start instance -0x12300924: 0x00000000: index bias -0x12300928: 0x78050001: 3DSTATE_URB -0x1230092c: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x12300930: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x12300934: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300938: 0x00006f85: dword 1 -0x1230093c: 0x00000000: dword 2 -0x12300940: 0x00000000: dword 3 -0x12300944: 0x00000000: dword 4 -0x12300948: 0x78100004: 3DSTATE_VS -0x1230094c: 0x00000640: kernel pointer -0x12300950: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300954: 0x00000000: scratch offset -0x12300958: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x1230095c: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300960: 0x7a000002: PIPE_CONTROL -0x12300964: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300968: 0x00000000: -0x1230096c: 0x00000000: -0x12300970: 0x7a000002: PIPE_CONTROL -0x12300974: 0x00004000: qword write, -0x12300978: 0x00000000: -0x1230097c: 0x00000000: -0x12300980: 0x7a000002: PIPE_CONTROL -0x12300984: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300988: 0x00000000: -0x1230098c: 0x00000000: -0x12300990: 0x78130012: 3DSTATE_SF -0x12300994: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300998: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x1230099c: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x123009a0: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x123009a4: 0x00000000: Global Depth Offset Constant 0.000000 -0x123009a8: 0x00000000: Global Depth Offset Scale 0.000000 -0x123009ac: 0x00000000: Global Depth Offset Clamp 0.000000 -0x123009b0: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009b4: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009b8: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009bc: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009c0: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009c4: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009c8: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009cc: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x123009d0: 0x00000000: Point Sprite TexCoord Enable -0x123009d4: 0x00000001: Const Interp Enable -0x123009d8: 0x00000000: Attrib 7-0 WrapShortest Enable -0x123009dc: 0x00000000: Attrib 15-8 WrapShortest Enable -0x123009e0: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x123009e4: 0x00006e00: VS binding table -0x123009e8: 0x00006e00: GS binding table -0x123009ec: 0x00006e00: WM binding table -0x123009f0: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123009f4: 0x00000018: buffer 0: sequential, pitch 24b -0x123009f8: 0x00002a30: buffer address -0x123009fc: 0x00007fff: max index -0x12300a00: 0x00000000: mbz -0x12300a04: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300a08: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300a0c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300a10: 0x0240000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x12300a14: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300a18: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300a1c: 0x00000052: vertex count -0x12300a20: 0x00000000: start vertex -0x12300a24: 0x00000001: instance count -0x12300a28: 0x00000000: start instance -0x12300a2c: 0x00000000: index bias -0x12300a30: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300a34: 0x00006cc5: dword 1 -0x12300a38: 0x00000000: dword 2 -0x12300a3c: 0x00000000: dword 3 -0x12300a40: 0x00000000: dword 4 -0x12300a44: 0x78100004: 3DSTATE_VS -0x12300a48: 0x00000640: kernel pointer -0x12300a4c: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300a50: 0x00000000: scratch offset -0x12300a54: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300a58: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300a5c: 0x7a000002: PIPE_CONTROL -0x12300a60: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300a64: 0x00000000: -0x12300a68: 0x00000000: -0x12300a6c: 0x7a000002: PIPE_CONTROL -0x12300a70: 0x00004000: qword write, -0x12300a74: 0x00000000: -0x12300a78: 0x00000000: -0x12300a7c: 0x7a000002: PIPE_CONTROL -0x12300a80: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300a84: 0x00000000: -0x12300a88: 0x00000000: -0x12300a8c: 0x78120002: 3DSTATE_CLIP -0x12300a90: 0x00000400: UserClip distance cull test mask 0x0 -0x12300a94: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300a98: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300a9c: 0x78130012: 3DSTATE_SF -0x12300aa0: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300aa4: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300aa8: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300aac: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300ab0: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300ab4: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300ab8: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300abc: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ac0: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ac4: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ac8: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300acc: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ad0: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ad4: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ad8: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300adc: 0x00000000: Point Sprite TexCoord Enable -0x12300ae0: 0x00000000: Const Interp Enable -0x12300ae4: 0x00000000: Attrib 7-0 WrapShortest Enable -0x12300ae8: 0x00000000: Attrib 15-8 WrapShortest Enable -0x12300aec: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x12300af0: 0x00000000: dword 1 -0x12300af4: 0x00000000: dword 2 -0x12300af8: 0x00000000: dword 3 -0x12300afc: 0x00000000: dword 4 -0x12300b00: 0x78140007: 3DSTATE_WM -0x12300b04: 0x00000900: kernel start pointer 0 -0x12300b08: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300b0c: 0x00000000: scratch offset -0x12300b10: 0x80060000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 6, start[1] 0, start[2] 0 -0x12300b14: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x12300b18: 0x00100400: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x1, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x12300b1c: 0x00000000: kernel start pointer 1 -0x12300b20: 0x00000900: kernel start pointer 2 -0x12300b24: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300b28: 0x00000016: vertex count -0x12300b2c: 0x00000052: start vertex -0x12300b30: 0x00000001: instance count -0x12300b34: 0x00000000: start instance -0x12300b38: 0x00000000: index bias -0x12300b3c: 0x78050001: 3DSTATE_URB -0x12300b40: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x12300b44: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x12300b48: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300b4c: 0x00006b85: dword 1 -0x12300b50: 0x00000000: dword 2 -0x12300b54: 0x00000000: dword 3 -0x12300b58: 0x00000000: dword 4 -0x12300b5c: 0x78100004: 3DSTATE_VS -0x12300b60: 0x00000240: kernel pointer -0x12300b64: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300b68: 0x00000000: scratch offset -0x12300b6c: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300b70: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300b74: 0x7a000002: PIPE_CONTROL -0x12300b78: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300b7c: 0x00000000: -0x12300b80: 0x00000000: -0x12300b84: 0x7a000002: PIPE_CONTROL -0x12300b88: 0x00004000: qword write, -0x12300b8c: 0x00000000: -0x12300b90: 0x00000000: -0x12300b94: 0x7a000002: PIPE_CONTROL -0x12300b98: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300b9c: 0x00000000: -0x12300ba0: 0x00000000: -0x12300ba4: 0x78120002: 3DSTATE_CLIP -0x12300ba8: 0x00000400: UserClip distance cull test mask 0x0 -0x12300bac: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300bb0: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300bb4: 0x78130012: 3DSTATE_SF -0x12300bb8: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300bbc: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300bc0: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300bc4: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300bc8: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300bcc: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300bd0: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300bd4: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300bd8: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300bdc: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300be0: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300be4: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300be8: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300bec: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300bf0: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300bf4: 0x00000000: Point Sprite TexCoord Enable -0x12300bf8: 0x00000001: Const Interp Enable -0x12300bfc: 0x00000000: Attrib 7-0 WrapShortest Enable -0x12300c00: 0x00000000: Attrib 15-8 WrapShortest Enable -0x12300c04: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x12300c08: 0x00000000: dword 1 -0x12300c0c: 0x00000000: dword 2 -0x12300c10: 0x00000000: dword 3 -0x12300c14: 0x00000000: dword 4 -0x12300c18: 0x78140007: 3DSTATE_WM -0x12300c1c: 0x00000500: kernel start pointer 0 -0x12300c20: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300c24: 0x00000000: scratch offset -0x12300c28: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x12300c2c: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x12300c30: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x12300c34: 0x00000000: kernel start pointer 1 -0x12300c38: 0x00000500: kernel start pointer 2 -0x12300c3c: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x12300c40: 0x00006a00: VS binding table -0x12300c44: 0x00006a00: GS binding table -0x12300c48: 0x00006a00: WM binding table -0x12300c4c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300c50: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300c54: 0x000033f0: buffer address -0x12300c58: 0x00007fff: max index -0x12300c5c: 0x00000000: mbz -0x12300c60: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x12300c64: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300c68: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300c6c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300c70: 0x0000002a: vertex count -0x12300c74: 0x00000000: start vertex -0x12300c78: 0x00000001: instance count -0x12300c7c: 0x00000000: start instance -0x12300c80: 0x00000000: index bias -0x12300c84: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300c88: 0x00000028: vertex count -0x12300c8c: 0x0000002a: start vertex -0x12300c90: 0x00000001: instance count -0x12300c94: 0x00000000: start instance -0x12300c98: 0x00000000: index bias -0x12300c9c: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300ca0: 0x000068c5: dword 1 -0x12300ca4: 0x00000000: dword 2 -0x12300ca8: 0x00000000: dword 3 -0x12300cac: 0x00000000: dword 4 -0x12300cb0: 0x78100004: 3DSTATE_VS -0x12300cb4: 0x00000240: kernel pointer -0x12300cb8: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300cbc: 0x00000000: scratch offset -0x12300cc0: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300cc4: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300cc8: 0x7a000002: PIPE_CONTROL -0x12300ccc: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300cd0: 0x00000000: -0x12300cd4: 0x00000000: -0x12300cd8: 0x7a000002: PIPE_CONTROL -0x12300cdc: 0x00004000: qword write, -0x12300ce0: 0x00000000: -0x12300ce4: 0x00000000: -0x12300ce8: 0x7a000002: PIPE_CONTROL -0x12300cec: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300cf0: 0x00000000: -0x12300cf4: 0x00000000: -0x12300cf8: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x12300cfc: 0x00000000: dword 1 -0x12300d00: 0x00000000: dword 2 -0x12300d04: 0x00000000: dword 3 -0x12300d08: 0x00000000: dword 4 -0x12300d0c: 0x78140007: 3DSTATE_WM -0x12300d10: 0x00000500: kernel start pointer 0 -0x12300d14: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300d18: 0x00000000: scratch offset -0x12300d1c: 0x80020000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 2, start[1] 0, start[2] 0 -0x12300d20: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x12300d24: 0x00100000: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x0, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x12300d28: 0x00000000: kernel start pointer 1 -0x12300d2c: 0x00000500: kernel start pointer 2 -0x12300d30: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300d34: 0x0000002a: vertex count -0x12300d38: 0x00000052: start vertex -0x12300d3c: 0x00000001: instance count -0x12300d40: 0x00000000: start instance -0x12300d44: 0x00000000: index bias -0x12300d48: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300d4c: 0x00000028: vertex count -0x12300d50: 0x0000007c: start vertex -0x12300d54: 0x00000001: instance count -0x12300d58: 0x00000000: start instance -0x12300d5c: 0x00000000: index bias -0x12300d60: 0x78050001: 3DSTATE_URB -0x12300d64: 0x00000100: VS entries 256, alloc size 1 (1024bit row) -0x12300d68: 0x00000000: GS entries 0, alloc size 1 (1024bit row) -0x12300d6c: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300d70: 0x00006785: dword 1 -0x12300d74: 0x00000000: dword 2 -0x12300d78: 0x00000000: dword 3 -0x12300d7c: 0x00000000: dword 4 -0x12300d80: 0x78100004: 3DSTATE_VS -0x12300d84: 0x00000640: kernel pointer -0x12300d88: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300d8c: 0x00000000: scratch offset -0x12300d90: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300d94: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300d98: 0x7a000002: PIPE_CONTROL -0x12300d9c: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300da0: 0x00000000: -0x12300da4: 0x00000000: -0x12300da8: 0x7a000002: PIPE_CONTROL -0x12300dac: 0x00004000: qword write, -0x12300db0: 0x00000000: -0x12300db4: 0x00000000: -0x12300db8: 0x7a000002: PIPE_CONTROL -0x12300dbc: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300dc0: 0x00000000: -0x12300dc4: 0x00000000: -0x12300dc8: 0x78130012: 3DSTATE_SF -0x12300dcc: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300dd0: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300dd4: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300dd8: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300ddc: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300de0: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300de4: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300de8: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300dec: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300df0: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300df4: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300df8: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300dfc: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300e00: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300e04: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300e08: 0x00000000: Point Sprite TexCoord Enable -0x12300e0c: 0x00000001: Const Interp Enable -0x12300e10: 0x00000000: Attrib 7-0 WrapShortest Enable -0x12300e14: 0x00000000: Attrib 15-8 WrapShortest Enable -0x12300e18: 0x78011302: 3DSTATE_BINDING_TABLE_POINTERS: VS mod 1, GS mod 1, PS mod 1 -0x12300e1c: 0x00006600: VS binding table -0x12300e20: 0x00006600: GS binding table -0x12300e24: 0x00006600: WM binding table -0x12300e28: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300e2c: 0x00000018: buffer 0: sequential, pitch 24b -0x12300e30: 0x00003bb8: buffer address -0x12300e34: 0x00007fff: max index -0x12300e38: 0x00000000: mbz -0x12300e3c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300e40: 0x02400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300e44: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300e48: 0x0240000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x12300e4c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300e50: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300e54: 0x00000052: vertex count -0x12300e58: 0x00000000: start vertex -0x12300e5c: 0x00000001: instance count -0x12300e60: 0x00000000: start instance -0x12300e64: 0x00000000: index bias -0x12300e68: 0x78151003: 3DSTATE_CONSTANT_VS_STATE -0x12300e6c: 0x000064c5: dword 1 -0x12300e70: 0x00000000: dword 2 -0x12300e74: 0x00000000: dword 3 -0x12300e78: 0x00000000: dword 4 -0x12300e7c: 0x78100004: 3DSTATE_VS -0x12300e80: 0x00000640: kernel pointer -0x12300e84: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300e88: 0x00000000: scratch offset -0x12300e8c: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x12300e90: 0x76000401: Max Threads 60, Vertex Cache enable, VS func enable -0x12300e94: 0x7a000002: PIPE_CONTROL -0x12300e98: 0x00100002: no write, cs stall, stall at scoreboard, -0x12300e9c: 0x00000000: -0x12300ea0: 0x00000000: -0x12300ea4: 0x7a000002: PIPE_CONTROL -0x12300ea8: 0x00004000: qword write, -0x12300eac: 0x00000000: -0x12300eb0: 0x00000000: -0x12300eb4: 0x7a000002: PIPE_CONTROL -0x12300eb8: 0x00002804: no write, depth stall, instruction cache invalidate, state cache invalidate, -0x12300ebc: 0x00000000: -0x12300ec0: 0x00000000: -0x12300ec4: 0x78120002: 3DSTATE_CLIP -0x12300ec8: 0x00000400: UserClip distance cull test mask 0x0 -0x12300ecc: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x12300ed0: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x12300ed4: 0x78130012: 3DSTATE_SF -0x12300ed8: 0x00600810: Attrib Out 1, Attrib Swizzle enable, VUE read length 1, VUE read offset 1 -0x12300edc: 0x00000403: Legacy Global DepthBias disable, FrontFace fill 0, BF fill 0, VP transform enable, FrontWinding_CCW -0x12300ee0: 0x62000000: AA disable, CullMode 3, Scissor disable, Multisample m ode 0 -0x12300ee4: 0x4c000808: Last Pixel disable, SubPixel Precision 8, Use PixelWidth 1 -0x12300ee8: 0x00000000: Global Depth Offset Constant 0.000000 -0x12300eec: 0x00000000: Global Depth Offset Scale 0.000000 -0x12300ef0: 0x00000000: Global Depth Offset Clamp 0.000000 -0x12300ef4: 0x00000000: Attrib 1 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 0 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300ef8: 0x00000000: Attrib 3 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 2 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300efc: 0x00000000: Attrib 5 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 4 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f00: 0x00000000: Attrib 7 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 6 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f04: 0x00000000: Attrib 9 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 8 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f08: 0x00000000: Attrib 11 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 10 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f0c: 0x00000000: Attrib 13 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 12 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f10: 0x00000000: Attrib 15 (Override , Const Source 0, Swizzle Select 0, Source 0); Attrib 14 (Override , Const Source 0, Swizzle Select 0, Source 0) -0x12300f14: 0x00000000: Point Sprite TexCoord Enable -0x12300f18: 0x00000000: Const Interp Enable -0x12300f1c: 0x00000000: Attrib 7-0 WrapShortest Enable -0x12300f20: 0x00000000: Attrib 15-8 WrapShortest Enable -0x12300f24: 0x78170003: 3DSTATE_CONSTANT_PS_STATE -0x12300f28: 0x00000000: dword 1 -0x12300f2c: 0x00000000: dword 2 -0x12300f30: 0x00000000: dword 3 -0x12300f34: 0x00000000: dword 4 -0x12300f38: 0x78140007: 3DSTATE_WM -0x12300f3c: 0x00000900: kernel start pointer 0 -0x12300f40: 0x00010000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x12300f44: 0x00000000: scratch offset -0x12300f48: 0x80060000: Depth Clear 0, Depth Resolve 0, HiZ Resolve 0, Dispatch GRF start[0] 6, start[1] 0, start[2] 0 -0x12300f4c: 0x4e084002: MaxThreads 40, PS KillPixel 0, PS computed Z 0, PS use sourceZ 0, Thread Dispatch 1, PS use sourceW 0, Dispatch32 0, Dispatch16 1, Dispatch8 0 -0x12300f50: 0x00100400: Num SF output 1, Pos XY offset 0, ZW interp mode 0 , Barycentric interp mode 0x1, Point raster rule 0, Multisample mode 0, Multisample Dispatch mode 0 -0x12300f54: 0x00000000: kernel start pointer 1 -0x12300f58: 0x00000900: kernel start pointer 2 -0x12300f5c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300f60: 0x00000016: vertex count -0x12300f64: 0x00000052: start vertex -0x12300f68: 0x00000001: instance count -0x12300f6c: 0x00000000: start instance -0x12300f70: 0x00000000: index bias -0x12300f74: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gen7-2d-copy.batch b/intel/tests/gen7-2d-copy.batch deleted file mode 100755 index ce7fc292b..000000000 Binary files a/intel/tests/gen7-2d-copy.batch and /dev/null differ diff --git a/intel/tests/gen7-2d-copy.batch-ref.txt b/intel/tests/gen7-2d-copy.batch-ref.txt deleted file mode 100755 index 0d621d37e..000000000 --- a/intel/tests/gen7-2d-copy.batch-ref.txt +++ /dev/null @@ -1,14 +0,0 @@ -0x12300000: 0x54f08006: XY_SRC_COPY_BLT (rgb enabled, alpha enabled, src tile 1, dst tile 0) -0x12300004: 0x03cc0190: format 8888, pitch 400, rop 0xcc, clipping disabled, -0x12300008: 0x00000000: dst (0,0) -0x1230000c: 0x00640064: dst (100,100) -0x12300010: 0x122e9000: dst offset 0x122e9000 -0x12300014: 0x00000000: src (0,0) -0x12300018: 0x00000080: src pitch 128 -0x1230001c: 0x02ff1000: src offset 0x02ff1000 -0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write' -0x12300024: 0x00000000: address -0x12300028: 0x00000000: dword -0x1230002c: 0x00000000: upper dword -0x12300030: 0x05000000: MI_BATCH_BUFFER_END -0x12300034: 0x00000000: diff --git a/intel/tests/gen7-3d.batch b/intel/tests/gen7-3d.batch deleted file mode 100755 index 328ec8817..000000000 Binary files a/intel/tests/gen7-3d.batch and /dev/null differ diff --git a/intel/tests/gen7-3d.batch-ref.txt b/intel/tests/gen7-3d.batch-ref.txt deleted file mode 100755 index cd2dfc4c3..000000000 --- a/intel/tests/gen7-3d.batch-ref.txt +++ /dev/null @@ -1,212 +0,0 @@ -0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT -0x12300004: 0x790d0002: 3DSTATE_MULTISAMPLE -0x12300008: 0x00000000: dword 1 -0x1230000c: 0x00000000: dword 2 -0x12300010: 0x00000000: dword 3 -0x12300014: 0x78180000: 3DSTATE_SAMPLE_MASK -0x12300018: 0x00000001: dword 1 -0x1230001c: 0x61020000: STATE_SIP -0x12300020: 0x00000000: dword 1 -0x12300024: 0x680b0000: 3DSTATE_VF_STATISTICS -0x12300028: 0x61010008: STATE_BASE_ADDRESS -0x1230002c: 0x00000001: general state base address 0x00000000 -0x12300030: 0x091ba001: surface state base address 0x091ba000 -0x12300034: 0x091ba001: dynamic state base address 0x091ba000 -0x12300038: 0x00000001: indirect state base address 0x00000000 -0x1230003c: 0x091c2001: instruction state base address 0x091c2000 -0x12300040: 0x00000001: general state upper bound disabled -0x12300044: 0x091c2001: dynamic state upper bound 0x091c2000 -0x12300048: 0x00000001: indirect state upper bound disabled -0x1230004c: 0x00000001: instruction state upper bound disabled -0x12300050: 0x78230000: 3DSTATE_VIEWPORT_STATE_POINTERS_CC -0x12300054: 0x00007fe0: pointer to CC viewport -0x12300058: 0x78210000: 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP -0x1230005c: 0x00007f80: pointer to SF_CLIP viewport -0x12300060: 0x78300000: 3DSTATE_URB_VS -0x12300064: 0x040002c0: 16KB start, size=1 64B rows, nr_entries=704, total size 45056B -0x12300068: 0x78330000: 3DSTATE_URB_GS -0x1230006c: 0x04000000: 16KB start, size=1 64B rows, nr_entries=0, total size 0B -0x12300070: 0x78310000: 3DSTATE_URB_HS -0x12300074: 0x04000000: 16KB start, size=1 64B rows, nr_entries=0, total size 0B -0x12300078: 0x78320000: 3DSTATE_URB_DS -0x1230007c: 0x04000000: 16KB start, size=1 64B rows, nr_entries=0, total size 0B -0x12300080: 0x78240000: 3DSTATE_BLEND_STATE_POINTERS -0x12300084: 0x00007f41: pointer to BLEND_STATE at 0x00007f40 (changed) -0x12300088: 0x780e0000: 3DSTATE_CC_STATE_POINTERS -0x1230008c: 0x00007f01: pointer to COLOR_CALC_STATE at 0x00007f00 (changed) -0x12300090: 0x78250000: 3DSTATE_DEPTH_STENCIL_STATE_POINTERS -0x12300094: 0x00007ec1: pointer to DEPTH_STENCIL_STATE at 0x00007ec0 (changed) -0x12300098: 0x78160005: 3DSTATE_CONSTANT_GS -0x1230009c: 0x00000000: len 0 = 0, len 1 = 0 -0x123000a0: 0x00000000: len 2 = 0, len 3 = 0 -0x123000a4: 0x00000000: pointer to constbuf 0 -0x123000a8: 0x00000000: pointer to constbuf 1 -0x123000ac: 0x00000000: pointer to constbuf 2 -0x123000b0: 0x00000000: pointer to constbuf 3 -0x123000b4: 0x78110005: 3DSTATE_GS -0x123000b8: 0x00000000: kernel pointer -0x123000bc: 0x00000000: SPF=0, VME=0, Sampler Count 0, Binding table count 0 -0x123000c0: 0x00000000: scratch offset -0x123000c4: 0x00000401: Dispatch GRF start 1, VUE read length 0, VUE read offset 0 -0x123000c8: 0x00000400: Max Threads 1, Rendering disable -0x123000cc: 0x00000000: Reorder disable, Discard Adjaceny disable, GS disable -0x123000d0: 0x78290000: 3DSTATE_BINDING_TABLE_POINTERS_GS -0x123000d4: 0x00000000: dword 1 -0x123000d8: 0x78190005: 3DSTATE_CONSTANT_HS -0x123000dc: 0x00000000: len 0 = 0, len 1 = 0 -0x123000e0: 0x00000000: len 2 = 0, len 3 = 0 -0x123000e4: 0x00000000: pointer to constbuf 0 -0x123000e8: 0x00000000: pointer to constbuf 1 -0x123000ec: 0x00000000: pointer to constbuf 2 -0x123000f0: 0x00000000: pointer to constbuf 3 -0x123000f4: 0x781b0005: 3DSTATE_HS -0x123000f8: 0x00000000: dword 1 -0x123000fc: 0x00000000: dword 2 -0x12300100: 0x00000000: dword 3 -0x12300104: 0x00000000: dword 4 -0x12300108: 0x00000000: dword 5 -0x1230010c: 0x00000000: dword 6 -0x12300110: 0x78270000: 3DSTATE_BINDING_TABLE_POINTERS_HS -0x12300114: 0x00000000: dword 1 -0x12300118: 0x781c0002: 3DSTATE_TE -0x1230011c: 0x00000000: dword 1 -0x12300120: 0x00000000: dword 2 -0x12300124: 0x00000000: dword 3 -0x12300128: 0x781a0005: 3DSTATE_CONSTANT_DS -0x1230012c: 0x00000000: len 0 = 0, len 1 = 0 -0x12300130: 0x00000000: len 2 = 0, len 3 = 0 -0x12300134: 0x00000000: pointer to constbuf 0 -0x12300138: 0x00000000: pointer to constbuf 1 -0x1230013c: 0x00000000: pointer to constbuf 2 -0x12300140: 0x00000000: pointer to constbuf 3 -0x12300144: 0x781d0004: 3DSTATE_DS -0x12300148: 0x00000000: dword 1 -0x1230014c: 0x00000000: dword 2 -0x12300150: 0x00000000: dword 3 -0x12300154: 0x00000000: dword 4 -0x12300158: 0x00000000: dword 5 -0x1230015c: 0x78280000: 3DSTATE_BINDING_TABLE_POINTERS_DS -0x12300160: 0x00000000: dword 1 -0x12300164: 0x78260000: 3DSTATE_BINDING_TABLE_POINTERS_VS -0x12300168: 0x00007c40: dword 1 -0x1230016c: 0x782b0000: 3DSTATE_SAMPLER_STATE_POINTERS_VS -0x12300170: 0x00007c20: dword 1 -0x12300174: 0x79120000: 3DSTATE_PUSH_CONSTANT_ALLOC_VS -0x12300178: 0x00000008: dword 1 -0x1230017c: 0x78150005: 3DSTATE_CONSTANT_VS -0x12300180: 0x00000002: len 0 = 2, len 1 = 0 -0x12300184: 0x00000000: len 2 = 0, len 3 = 0 -0x12300188: 0x00007e00: pointer to constbuf 0 -0x1230018c: 0x00000000: pointer to constbuf 1 -0x12300190: 0x00000000: pointer to constbuf 2 -0x12300194: 0x00000000: pointer to constbuf 3 -0x12300198: 0x78100004: 3DSTATE_VS -0x1230019c: 0x00000000: kernel pointer -0x123001a0: 0x08000000: SPF=0, VME=0, Sampler Count 1, Binding table count 0 -0x123001a4: 0x00000000: scratch offset -0x123001a8: 0x00100800: Dispatch GRF start 1, VUE read length 1, VUE read offset 0 -0x123001ac: 0xfe000401: Max Threads 128, Vertex Cache enable, VS func enable -0x123001b0: 0x781e0001: 3DSTATE_STREAMOUT -0x123001b4: 0x00000000: dword 1 -0x123001b8: 0x00000000: dword 2 -0x123001bc: 0x78120002: 3DSTATE_CLIP -0x123001c0: 0x00150400: UserClip distance cull test mask 0x0 -0x123001c4: 0x98000026: Clip enable, API mode OGL, Viewport XY test enable, Viewport Z test enable, Guardband test disable, Clip mode 0, Perspective Divide enable, Non-Perspective Barycentric disable, Tri Provoking 2, Line Provoking 1, Trifan Provoking 2 -0x123001c8: 0x0003ffe0: Min PointWidth 1, Max PointWidth 2047, Force Zero RTAIndex enable, Max VPIndex 0 -0x123001cc: 0x781f000c: 3DSTATE_SBE -0x123001d0: 0x00600810: dword 1 -0x123001d4: 0x00000000: dword 2 -0x123001d8: 0x00000000: dword 3 -0x123001dc: 0x00000000: dword 4 -0x123001e0: 0x00000000: dword 5 -0x123001e4: 0x00000000: dword 6 -0x123001e8: 0x00000000: dword 7 -0x123001ec: 0x00000000: dword 8 -0x123001f0: 0x00000000: dword 9 -0x123001f4: 0x00000000: dword 10 -0x123001f8: 0x00000000: dword 11 -0x123001fc: 0x00000000: dword 12 -0x12300200: 0x00000000: dword 13 -0x12300204: 0x78130005: 3DSTATE_SF -0x12300208: 0x00001403: dword 1 -0x1230020c: 0x22000000: dword 2 -0x12300210: 0x4c000808: dword 3 -0x12300214: 0x00000000: dword 4 -0x12300218: 0x00000000: dword 5 -0x1230021c: 0x00000000: dword 6 -0x12300220: 0x78140001: 3DSTATE_WM -0x12300224: 0xa0000840: (PP ), point UR -0x12300228: 0x00000000: MS -0x1230022c: 0x782a0000: 3DSTATE_BINDING_TABLE_POINTERS_PS -0x12300230: 0x00007c40: dword 1 -0x12300234: 0x782f0000: 3DSTATE_SAMPLER_STATE_POINTERS_PS -0x12300238: 0x00007c20: dword 1 -0x1230023c: 0x79160000: 3DSTATE_PUSH_CONSTANT_ALLOC_PS -0x12300240: 0x00080008: dword 1 -0x12300244: 0x78170005: 3DSTATE_CONSTANT_PS -0x12300248: 0x00000000: len 0 = 0, len 1 = 0 -0x1230024c: 0x00000000: len 2 = 0, len 3 = 0 -0x12300250: 0x00000000: pointer to constbuf 0 -0x12300254: 0x00000000: pointer to constbuf 1 -0x12300258: 0x00000000: pointer to constbuf 2 -0x1230025c: 0x00000000: pointer to constbuf 3 -0x12300260: 0x78200006: 3DSTATE_PS -0x12300264: 0x00000140: dword 1 -0x12300268: 0x08000000: dword 2 -0x1230026c: 0x00000000: dword 3 -0x12300270: 0x55000403: dword 4 -0x12300274: 0x00040006: dword 5 -0x12300278: 0x00000000: dword 6 -0x1230027c: 0x00000240: dword 7 -0x12300280: 0x780f0000: 3DSTATE_SCISSOR_POINTERS -0x12300284: 0x00007be0: scissor rect offset -0x12300288: 0x7a000002: PIPE_CONTROL -0x1230028c: 0x00002000: no write, depth stall, -0x12300290: 0x00000000: -0x12300294: 0x00000000: -0x12300298: 0x7a000002: PIPE_CONTROL -0x1230029c: 0x00000001: no write, depth cache flush, -0x123002a0: 0x00000000: -0x123002a4: 0x00000000: -0x123002a8: 0x7a000002: PIPE_CONTROL -0x123002ac: 0x00002000: no write, depth stall, -0x123002b0: 0x00000000: -0x123002b4: 0x00000000: -0x123002b8: 0x78050005: 3DSTATE_DEPTH_BUFFER -0x123002bc: 0xe0040000: dword 1 -0x123002c0: 0x00000000: dword 2 -0x123002c4: 0x00000000: dword 3 -0x123002c8: 0x00000000: dword 4 -0x123002cc: 0x00000000: dword 5 -0x123002d0: 0x00000000: dword 6 -0x123002d4: 0x78070001: 3DSTATE_HIER_DEPTH_BUFFER -0x123002d8: 0x00000000: pitch 1b -0x123002dc: 0x00000000: pointer to HiZ buffer -0x123002e0: 0x78060001: 3DSTATE_STENCIL_BUFFER -0x123002e4: 0x00000000: dword 1 -0x123002e8: 0x00000000: dword 2 -0x123002ec: 0x78040001: 3DSTATE_CLEAR_PARAMS -0x123002f0: 0x00000000: dword 1 -0x123002f4: 0x00000000: dword 2 -0x123002f8: 0x79000002: 3DSTATE_DRAWING_RECTANGLE -0x123002fc: 0x00000000: top left: 0,0 -0x12300300: 0x00130077: bottom right: 119,19 -0x12300304: 0x00000000: origin: 0,0 -0x12300308: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x1230030c: 0x00004014: buffer 0: sequential, pitch 20b -0x12300310: 0x158b3000: buffer address -0x12300314: 0x158c2fff: max index -0x12300318: 0x00000000: mbz -0x1230031c: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300320: 0x02850000: buffer 0: valid, type 0x0085, src offset 0x0000 bytes -0x12300324: 0x11230000: (X, Y, 0.0, 1.0), dst offset 0x00 bytes -0x12300328: 0x02400008: buffer 0: valid, type 0x0040, src offset 0x0008 bytes -0x1230032c: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300330: 0x7b000005: 3DPRIMITIVE: -0x12300334: 0x00000007: quad list sequential -0x12300338: 0x00000004: vertex count -0x1230033c: 0x00000000: start vertex -0x12300340: 0x00000001: instance count -0x12300344: 0x00000000: start instance -0x12300348: 0x00000000: index bias -0x1230034c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/gm45-3d.batch b/intel/tests/gm45-3d.batch deleted file mode 100755 index 549608bb2..000000000 Binary files a/intel/tests/gm45-3d.batch and /dev/null differ diff --git a/intel/tests/gm45-3d.batch-ref.txt b/intel/tests/gm45-3d.batch-ref.txt deleted file mode 100755 index 5a47d77ca..000000000 --- a/intel/tests/gm45-3d.batch-ref.txt +++ /dev/null @@ -1,488 +0,0 @@ -0x12300000: 0x69040000: 3DSTATE_PIPELINE_SELECT -0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP -0x12300008: 0x00000000: dword 1 -0x1230000c: 0x61020000: STATE_SIP -0x12300010: 0x00000000: dword 1 -0x12300014: 0x680b0000: 3DSTATE_VF_STATISTICS -0x12300018: 0x61010004: STATE_BASE_ADDRESS -0x1230001c: 0x00000001: general state base address 0x00000000 -0x12300020: 0x00000001: surface state base address 0x00000000 -0x12300024: 0x00000001: indirect state base address 0x00000000 -0x12300028: 0x00000001: general state upper bound disabled -0x1230002c: 0x00000001: indirect state upper bound disabled -0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x12300034: 0x00007e20: VS binding table -0x12300038: 0x00000000: GS binding table -0x1230003c: 0x00000000: Clip binding table -0x12300040: 0x00000000: SF binding table -0x12300044: 0x00007e20: WM binding table -0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR -0x1230004c: 0x00000000: dword 1 -0x12300050: 0x00000000: dword 2 -0x12300054: 0x00000000: dword 3 -0x12300058: 0x00000000: dword 4 -0x1230005c: 0x79050004: 3DSTATE_DEPTH_BUFFER -0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled -0x12300064: 0x00000000: depth offset -0x12300068: 0x09584ac0: 300x300 -0x1230006c: 0x00000000: volume depth -0x12300070: 0x00000000: -0x12300074: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300078: 0x00007d60: VS state -0x1230007c: 0x00000000: GS state -0x12300080: 0x00007d21: Clip state -0x12300084: 0x00007d80: SF state -0x12300088: 0x00007de0: WM state -0x1230008c: 0x00007fc0: CC state -0x12300090: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300094: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300098: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230009c: 0x60010000: CS_URB_STATE -0x123000a0: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4 -0x123000a4: 0x79000002: 3DSTATE_DRAWING_RECTANGLE -0x123000a8: 0x00000000: top left: 0,0 -0x123000ac: 0x012b012b: bottom right: 299,299 -0x123000b0: 0x00000000: origin: 0,0 -0x123000b4: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123000b8: 0x0000000c: buffer 0: sequential, pitch 12b -0x123000bc: 0x00000000: buffer address -0x123000c0: 0x00000000: max index -0x123000c4: 0x00000000: mbz -0x123000c8: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123000cc: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123000d0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123000d4: 0x60020100: CONSTANT_BUFFER: valid -0x123000d8: 0x00000001: offset: 0x00000000, length: 128 bytes -0x123000dc: 0x7b001804: 3DPRIMITIVE: tri fan sequential -0x123000e0: 0x00000004: vertex count -0x123000e4: 0x00000000: start vertex -0x123000e8: 0x00000001: instance count -0x123000ec: 0x00000000: start instance -0x123000f0: 0x00000000: index bias -0x123000f4: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS -0x123000f8: 0x00007b40: VS binding table -0x123000fc: 0x00000000: GS binding table -0x12300100: 0x00000000: Clip binding table -0x12300104: 0x00000000: SF binding table -0x12300108: 0x00007b40: WM binding table -0x1230010c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300110: 0x00007aa0: VS state -0x12300114: 0x00007a41: GS state -0x12300118: 0x00007a61: Clip state -0x1230011c: 0x00007ac0: SF state -0x12300120: 0x00007b00: WM state -0x12300124: 0x00007cc0: CC state -0x12300128: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230012c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300130: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300134: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300138: 0x0000000c: buffer 0: sequential, pitch 12b -0x1230013c: 0x00000000: buffer address -0x12300140: 0x00000000: max index -0x12300144: 0x00000000: mbz -0x12300148: 0x60020100: CONSTANT_BUFFER: valid -0x1230014c: 0x00000082: offset: 0x00000080, length: 192 bytes -0x12300150: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300154: 0x00000052: vertex count -0x12300158: 0x00000000: start vertex -0x1230015c: 0x00000001: instance count -0x12300160: 0x00000000: start instance -0x12300164: 0x00000000: index bias -0x12300168: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x1230016c: 0x00007aa0: VS state -0x12300170: 0x00007a21: GS state -0x12300174: 0x00007a61: Clip state -0x12300178: 0x00007ac0: SF state -0x1230017c: 0x00007b00: WM state -0x12300180: 0x00007cc0: CC state -0x12300184: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300188: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x1230018c: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300190: 0x60020100: CONSTANT_BUFFER: valid -0x12300194: 0x00000082: offset: 0x00000080, length: 192 bytes -0x12300198: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x1230019c: 0x00000050: vertex count -0x123001a0: 0x00000052: start vertex -0x123001a4: 0x00000001: instance count -0x123001a8: 0x00000000: start instance -0x123001ac: 0x00000000: index bias -0x123001b0: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123001b4: 0x00007aa0: VS state -0x123001b8: 0x00007a01: GS state -0x123001bc: 0x00007a61: Clip state -0x123001c0: 0x00007ac0: SF state -0x123001c4: 0x00007b00: WM state -0x123001c8: 0x00007cc0: CC state -0x123001cc: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123001d0: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x123001d4: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x123001d8: 0x60020100: CONSTANT_BUFFER: valid -0x123001dc: 0x00000142: offset: 0x00000140, length: 192 bytes -0x123001e0: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123001e4: 0x00000052: vertex count -0x123001e8: 0x000000a2: start vertex -0x123001ec: 0x00000001: instance count -0x123001f0: 0x00000000: start instance -0x123001f4: 0x00000000: index bias -0x123001f8: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123001fc: 0x00007aa0: VS state -0x12300200: 0x000079e1: GS state -0x12300204: 0x00007a61: Clip state -0x12300208: 0x00007ac0: SF state -0x1230020c: 0x00007b00: WM state -0x12300210: 0x00007cc0: CC state -0x12300214: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300218: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x1230021c: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300220: 0x60020100: CONSTANT_BUFFER: valid -0x12300224: 0x00000142: offset: 0x00000140, length: 192 bytes -0x12300228: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x1230022c: 0x00000050: vertex count -0x12300230: 0x000000f4: start vertex -0x12300234: 0x00000001: instance count -0x12300238: 0x00000000: start instance -0x1230023c: 0x00000000: index bias -0x12300240: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300244: 0x00007aa0: VS state -0x12300248: 0x000079c1: GS state -0x1230024c: 0x00007a61: Clip state -0x12300250: 0x00007ac0: SF state -0x12300254: 0x00007b00: WM state -0x12300258: 0x00007cc0: CC state -0x1230025c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300260: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300264: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300268: 0x60020100: CONSTANT_BUFFER: valid -0x1230026c: 0x00000142: offset: 0x00000140, length: 192 bytes -0x12300270: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300274: 0x000079a0: VS state -0x12300278: 0x000079c1: GS state -0x1230027c: 0x00007a61: Clip state -0x12300280: 0x00007ac0: SF state -0x12300284: 0x00007b00: WM state -0x12300288: 0x00007cc0: CC state -0x1230028c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300290: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300294: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300298: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x1230029c: 0x00000018: buffer 0: sequential, pitch 24b -0x123002a0: 0x00000f48: buffer address -0x123002a4: 0x00000000: max index -0x123002a8: 0x00000000: mbz -0x123002ac: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123002b0: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123002b4: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123002b8: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123002bc: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x123002c0: 0x60020100: CONSTANT_BUFFER: valid -0x123002c4: 0x00000202: offset: 0x00000200, length: 192 bytes -0x123002c8: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123002cc: 0x000000a2: vertex count -0x123002d0: 0x00000000: start vertex -0x123002d4: 0x00000001: instance count -0x123002d8: 0x00000000: start instance -0x123002dc: 0x00000000: index bias -0x123002e0: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123002e4: 0x000079a0: VS state -0x123002e8: 0x00000000: GS state -0x123002ec: 0x00007901: Clip state -0x123002f0: 0x00007940: SF state -0x123002f4: 0x00007960: WM state -0x123002f8: 0x00007cc0: CC state -0x123002fc: 0x00000000: MI_NOOP -0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300304: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300308: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230030c: 0x60020100: CONSTANT_BUFFER: valid -0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes -0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300318: 0x0000002a: vertex count -0x1230031c: 0x000000a2: start vertex -0x12300320: 0x00000001: instance count -0x12300324: 0x00000000: start instance -0x12300328: 0x00000000: index bias -0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300330: 0x00007860: VS state -0x12300334: 0x00007801: GS state -0x12300338: 0x00007821: Clip state -0x1230033c: 0x00007880: SF state -0x12300340: 0x000078a0: WM state -0x12300344: 0x00007cc0: CC state -0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230034c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300350: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b -0x1230035c: 0x00002268: buffer address -0x12300360: 0x00000000: max index -0x12300364: 0x00000000: mbz -0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x12300374: 0x60020100: CONSTANT_BUFFER: valid -0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300380: 0x0000002a: vertex count -0x12300384: 0x00000000: start vertex -0x12300388: 0x00000001: instance count -0x1230038c: 0x00000000: start instance -0x12300390: 0x00000000: index bias -0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300398: 0x00007860: VS state -0x1230039c: 0x000077e1: GS state -0x123003a0: 0x00007821: Clip state -0x123003a4: 0x00007880: SF state -0x123003a8: 0x000078a0: WM state -0x123003ac: 0x00007cc0: CC state -0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123003b4: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x123003b8: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x123003bc: 0x60020100: CONSTANT_BUFFER: valid -0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes -0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x123003c8: 0x00000028: vertex count -0x123003cc: 0x0000002a: start vertex -0x123003d0: 0x00000001: instance count -0x123003d4: 0x00000000: start instance -0x123003d8: 0x00000000: index bias -0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123003e0: 0x00007860: VS state -0x123003e4: 0x000077c1: GS state -0x123003e8: 0x00007821: Clip state -0x123003ec: 0x00007880: SF state -0x123003f0: 0x000078a0: WM state -0x123003f4: 0x00007cc0: CC state -0x123003f8: 0x00000000: MI_NOOP -0x123003fc: 0x00000000: MI_NOOP -0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300404: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300408: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230040c: 0x60020100: CONSTANT_BUFFER: valid -0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes -0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300418: 0x0000002a: vertex count -0x1230041c: 0x00000052: start vertex -0x12300420: 0x00000001: instance count -0x12300424: 0x00000000: start instance -0x12300428: 0x00000000: index bias -0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300430: 0x00007860: VS state -0x12300434: 0x000077a1: GS state -0x12300438: 0x00007821: Clip state -0x1230043c: 0x00007880: SF state -0x12300440: 0x000078a0: WM state -0x12300444: 0x00007cc0: CC state -0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x1230044c: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300450: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x12300454: 0x60020100: CONSTANT_BUFFER: valid -0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes -0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300460: 0x00000028: vertex count -0x12300464: 0x0000007c: start vertex -0x12300468: 0x00000001: instance count -0x1230046c: 0x00000000: start instance -0x12300470: 0x00000000: index bias -0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300478: 0x00007860: VS state -0x1230047c: 0x00007781: GS state -0x12300480: 0x00007821: Clip state -0x12300484: 0x00007880: SF state -0x12300488: 0x000078a0: WM state -0x1230048c: 0x00007cc0: CC state -0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300494: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300498: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230049c: 0x60020100: CONSTANT_BUFFER: valid -0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes -0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123004a8: 0x00007760: VS state -0x123004ac: 0x00007781: GS state -0x123004b0: 0x00007821: Clip state -0x123004b4: 0x00007880: SF state -0x123004b8: 0x000078a0: WM state -0x123004bc: 0x00007cc0: CC state -0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123004c4: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x123004c8: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b -0x123004d4: 0x00002a30: buffer address -0x123004d8: 0x00000000: max index -0x123004dc: 0x00000000: mbz -0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x123004f4: 0x60020100: CONSTANT_BUFFER: valid -0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes -0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300500: 0x00000052: vertex count -0x12300504: 0x00000000: start vertex -0x12300508: 0x00000001: instance count -0x1230050c: 0x00000000: start instance -0x12300510: 0x00000000: index bias -0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300518: 0x00007760: VS state -0x1230051c: 0x00000000: GS state -0x12300520: 0x000076c1: Clip state -0x12300524: 0x00007700: SF state -0x12300528: 0x00007720: WM state -0x1230052c: 0x00007cc0: CC state -0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300534: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300538: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230053c: 0x60020100: CONSTANT_BUFFER: valid -0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes -0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300548: 0x00000016: vertex count -0x1230054c: 0x00000052: start vertex -0x12300550: 0x00000001: instance count -0x12300554: 0x00000000: start instance -0x12300558: 0x00000000: index bias -0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300560: 0x00007620: VS state -0x12300564: 0x000075c1: GS state -0x12300568: 0x000075e1: Clip state -0x1230056c: 0x00007640: SF state -0x12300570: 0x00007660: WM state -0x12300574: 0x00007cc0: CC state -0x12300578: 0x00000000: MI_NOOP -0x1230057c: 0x00000000: MI_NOOP -0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300584: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300588: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b -0x12300594: 0x000033f0: buffer address -0x12300598: 0x00000000: max index -0x1230059c: 0x00000000: mbz -0x123005a0: 0x78090001: 3DSTATE_VERTEX_ELEMENTS -0x123005a4: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x123005a8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x123005ac: 0x60020100: CONSTANT_BUFFER: valid -0x123005b0: 0x00000502: offset: 0x00000500, length: 192 bytes -0x123005b4: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x123005b8: 0x0000002a: vertex count -0x123005bc: 0x00000000: start vertex -0x123005c0: 0x00000001: instance count -0x123005c4: 0x00000000: start instance -0x123005c8: 0x00000000: index bias -0x123005cc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123005d0: 0x00007620: VS state -0x123005d4: 0x000075a1: GS state -0x123005d8: 0x000075e1: Clip state -0x123005dc: 0x00007640: SF state -0x123005e0: 0x00007660: WM state -0x123005e4: 0x00007cc0: CC state -0x123005e8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123005ec: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x123005f0: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x123005f4: 0x60020100: CONSTANT_BUFFER: valid -0x123005f8: 0x00000502: offset: 0x00000500, length: 192 bytes -0x123005fc: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300600: 0x00000028: vertex count -0x12300604: 0x0000002a: start vertex -0x12300608: 0x00000001: instance count -0x1230060c: 0x00000000: start instance -0x12300610: 0x00000000: index bias -0x12300614: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300618: 0x00007620: VS state -0x1230061c: 0x00007581: GS state -0x12300620: 0x000075e1: Clip state -0x12300624: 0x00007640: SF state -0x12300628: 0x00007660: WM state -0x1230062c: 0x00007cc0: CC state -0x12300630: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300634: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300638: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230063c: 0x60020100: CONSTANT_BUFFER: valid -0x12300640: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x12300644: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300648: 0x0000002a: vertex count -0x1230064c: 0x00000052: start vertex -0x12300650: 0x00000001: instance count -0x12300654: 0x00000000: start instance -0x12300658: 0x00000000: index bias -0x1230065c: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300660: 0x00007620: VS state -0x12300664: 0x00007561: GS state -0x12300668: 0x000075e1: Clip state -0x1230066c: 0x00007640: SF state -0x12300670: 0x00007660: WM state -0x12300674: 0x00007cc0: CC state -0x12300678: 0x00000000: MI_NOOP -0x1230067c: 0x00000000: MI_NOOP -0x12300680: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300684: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300688: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230068c: 0x60020100: CONSTANT_BUFFER: valid -0x12300690: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x12300694: 0x7b001c04: 3DPRIMITIVE: quad list sequential -0x12300698: 0x00000028: vertex count -0x1230069c: 0x0000007c: start vertex -0x123006a0: 0x00000001: instance count -0x123006a4: 0x00000000: start instance -0x123006a8: 0x00000000: index bias -0x123006ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123006b0: 0x00007620: VS state -0x123006b4: 0x00007541: GS state -0x123006b8: 0x000075e1: Clip state -0x123006bc: 0x00007640: SF state -0x123006c0: 0x00007660: WM state -0x123006c4: 0x00007cc0: CC state -0x123006c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x123006cc: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x123006d0: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x123006d4: 0x60020100: CONSTANT_BUFFER: valid -0x123006d8: 0x000005c2: offset: 0x000005c0, length: 192 bytes -0x123006dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x123006e0: 0x00007520: VS state -0x123006e4: 0x00007541: GS state -0x123006e8: 0x000075e1: Clip state -0x123006ec: 0x00007640: SF state -0x123006f0: 0x00007660: WM state -0x123006f4: 0x00007cc0: CC state -0x123006f8: 0x00000000: MI_NOOP -0x123006fc: 0x00000000: MI_NOOP -0x12300700: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300704: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300708: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230070c: 0x78080003: 3DSTATE_VERTEX_BUFFERS -0x12300710: 0x00000018: buffer 0: sequential, pitch 24b -0x12300714: 0x00003bb8: buffer address -0x12300718: 0x00000000: max index -0x1230071c: 0x00000000: mbz -0x12300720: 0x78090003: 3DSTATE_VERTEX_ELEMENTS -0x12300724: 0x04400000: buffer 0: valid, type 0x0040, src offset 0x0000 bytes -0x12300728: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes -0x1230072c: 0x0440000c: buffer 0: valid, type 0x0040, src offset 0x000c bytes -0x12300730: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes -0x12300734: 0x60020100: CONSTANT_BUFFER: valid -0x12300738: 0x00000682: offset: 0x00000680, length: 192 bytes -0x1230073c: 0x7b002004: 3DPRIMITIVE: quad strip sequential -0x12300740: 0x00000052: vertex count -0x12300744: 0x00000000: start vertex -0x12300748: 0x00000001: instance count -0x1230074c: 0x00000000: start instance -0x12300750: 0x00000000: index bias -0x12300754: 0x78000005: 3DSTATE_PIPELINED_POINTERS -0x12300758: 0x00007520: VS state -0x1230075c: 0x00000000: GS state -0x12300760: 0x00007481: Clip state -0x12300764: 0x000074c0: SF state -0x12300768: 0x000074e0: WM state -0x1230076c: 0x00007cc0: CC state -0x12300770: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs -0x12300774: 0x05212040: vs fence: 64, clip_fence: 82, gs_fence: 72 -0x12300778: 0x18000062: sf fence: 98, vfe_fence: 0, cs_fence: 384 -0x1230077c: 0x60020100: CONSTANT_BUFFER: valid -0x12300780: 0x00000682: offset: 0x00000680, length: 192 bytes -0x12300784: 0x7b001404: 3DPRIMITIVE: tri strip sequential -0x12300788: 0x00000016: vertex count -0x1230078c: 0x00000052: start vertex -0x12300790: 0x00000001: instance count -0x12300794: 0x00000000: start instance -0x12300798: 0x00000000: index bias -0x1230079c: 0x05000000: MI_BATCH_BUFFER_END diff --git a/intel/tests/test-batch.sh b/intel/tests/test-batch.sh deleted file mode 100755 index b85f639a1..000000000 --- a/intel/tests/test-batch.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/bin/sh - -TEST_FILENAME=`echo "$0" | sed 's|\.sh$||'` -./test_decode $TEST_FILENAME - -ret=$? - -# pretty-print a diff showing what happened, and leave the dumped -# around for possibly moving over the ref. -if test $ret = 1; then - REF_FILENAME="$TEST_FILENAME-ref.txt" - NEW_FILENAME="$TEST_FILENAME-new.txt" - ./test_decode $TEST_FILENAME -dump > $NEW_FILENAME - if test $? = 0; then - echo "Differences:" - diff -u $REF_FILENAME $NEW_FILENAME - fi -fi - -exit $ret diff --git a/libsync.h b/libsync.h index f1a2f96d3..c6b64ed33 100644 --- a/libsync.h +++ b/libsync.h @@ -33,7 +33,7 @@ #include #include #include -#include +#include #include #if defined(__cplusplus) diff --git a/man/drm-kms.7.rst b/man/drm-kms.7.rst index 587d7eb79..715e703db 100644 --- a/man/drm-kms.7.rst +++ b/man/drm-kms.7.rst @@ -214,7 +214,7 @@ Reporting Bugs ============== Bugs in this manual should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues +https://gitlab.freedesktop.org/mesa/libdrm/-/issues See Also ======== diff --git a/man/drm-memory.7.rst b/man/drm-memory.7.rst index 7d09eeb14..9aa75e01d 100644 --- a/man/drm-memory.7.rst +++ b/man/drm-memory.7.rst @@ -304,7 +304,7 @@ Reporting Bugs ============== Bugs in this manual should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues +https://gitlab.freedesktop.org/mesa/libdrm/-/issues See Also ======== diff --git a/man/drm.7.rst b/man/drm.7.rst index df2c1c740..3d8766a29 100644 --- a/man/drm.7.rst +++ b/man/drm.7.rst @@ -82,7 +82,7 @@ Reporting Bugs ============== Bugs in this manual should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues. +https://gitlab.freedesktop.org/mesa/libdrm/-/issues. See Also ======== diff --git a/man/drmAvailable.3.rst b/man/drmAvailable.3.rst index 5da77bebf..03d9ace86 100644 --- a/man/drmAvailable.3.rst +++ b/man/drmAvailable.3.rst @@ -33,7 +33,7 @@ Reporting Bugs ============== Bugs in this function should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues +https://gitlab.freedesktop.org/mesa/libdrm/-/issues See Also ======== diff --git a/man/drmHandleEvent.3.rst b/man/drmHandleEvent.3.rst index ecc63ed09..f0de6921a 100644 --- a/man/drmHandleEvent.3.rst +++ b/man/drmHandleEvent.3.rst @@ -53,7 +53,7 @@ Reporting Bugs ============== Bugs in this function should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues +https://gitlab.freedesktop.org/mesa/libdrm/-/issues See Also ======== diff --git a/man/drmModeGetResources.3.rst b/man/drmModeGetResources.3.rst index d1358d224..c1d95d649 100644 --- a/man/drmModeGetResources.3.rst +++ b/man/drmModeGetResources.3.rst @@ -81,7 +81,7 @@ Reporting Bugs ============== Bugs in this function should be reported to -https://gitlab.freedesktop.org/mesa/drm/-/issues +https://gitlab.freedesktop.org/mesa/libdrm/-/issues See Also ======== diff --git a/meson.build b/meson.build index 1a7dbbe42..1796b2131 100644 --- a/meson.build +++ b/meson.build @@ -18,15 +18,22 @@ # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE # SOFTWARE. +# The versioning should always stay at 2.4.x. If bumping away from this, +# you must ensure that all users of patch_ver are changed such that DSO versions +# continuously increment (e.g. blindly bumping from 2.4.122 to 2.5.0 would +# roll the libdrm DSO versioning from libdrm.so.2.122.0 back to libdrm.so.2.0.0 +# which would be bad) project( 'libdrm', ['c'], - version : '2.4.120', + version : '2.4.134', license : 'MIT', meson_version : '>= 0.59', default_options : ['buildtype=debugoptimized', 'c_std=c11'], ) +patch_ver = meson.project_version().split('.')[2] + if ['windows', 'darwin'].contains(host_machine.system()) error('unsupported OS: @0@'.format(host_machine.system())) endif @@ -44,8 +51,16 @@ dep_threads = dependency('threads') cc = meson.get_compiler('c') +config.set10('HAVE_SECURE_GETENV', cc.has_function('secure_getenv')) + android = cc.compiles('''int func() { return __ANDROID__; }''') +# Solaris / Illumos +if host_machine.system() == 'sunos' + add_global_arguments('-D__EXTENSIONS__', language : 'c') + add_global_arguments('-D_POSIX_C_SOURCE=3', language : 'c') +endif + symbols_check = find_program('symbols-check.py') prog_nm = find_program('nm') @@ -154,10 +169,9 @@ if not cc.has_function('clock_gettime', prefix : '#define _GNU_SOURCE\n#include else dep_rt = [] endif -dep_m = cc.find_library('m', required : false) # The header is not required on Linux, and is in fact deprecated in glibc 2.30+ -if ['linux'].contains(host_machine.system()) +if host_machine.system() == 'linux' config.set10('HAVE_SYS_SYSCTL_H', false) else # From Niclas Zeising: @@ -193,7 +207,6 @@ libdrm_c_args = cc.get_supported_arguments([ '-Wno-unused-parameter', '-Wno-attributes', '-Wno-long-long', '-Wno-missing-field-initializers']) -dep_cunit = dependency('cunit', version : '>= 2.1', required : false) dep_cairo = dependency('cairo', required : get_option('cairo-tests')) with_cairo_tests = dep_cairo.found() @@ -231,11 +244,15 @@ if target_machine.endian() == 'big' config.set('HAVE_BIG_ENDIAN', 1) endif +if android + config.set('BIONIC_IOCTL_NO_SIGNEDNESS_OVERLOAD', 1) +endif + config_file = configure_file( configuration : config, output : 'config.h', ) -add_project_arguments('-include', '@0@'.format(config_file), language : 'c') +add_project_arguments('-include', meson.current_build_dir() / 'config.h', language : 'c') inc_root = include_directories('.') inc_drm = include_directories('include/drm') @@ -251,14 +268,14 @@ libdrm_files = [files( if android libdrm_kw = {} else - libdrm_kw = {'version' : '2.4.0'} + libdrm_kw = { 'version' : '2.@0@.0'.format(patch_ver) } endif libdrm = library( 'drm', libdrm_files, c_args : libdrm_c_args, - dependencies : [dep_valgrind, dep_rt, dep_m], + dependencies : [dep_valgrind, dep_rt], include_directories : inc_drm, install : true, kwargs : libdrm_kw, @@ -280,9 +297,7 @@ ext_libdrm = declare_dependency( include_directories : [inc_root, inc_drm], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm', ext_libdrm) -endif +meson.override_dependency('libdrm', ext_libdrm) install_headers('libsync.h', 'xf86drm.h', 'xf86drmMode.h') install_headers( diff --git a/meson_options.txt b/meson_options.txt index e80d79e2c..922145afc 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -46,13 +46,11 @@ option( option( 'omap', type : 'feature', - value : 'disabled', description : '''Enable support for OMAP's experimental KMS API.''', ) option( 'exynos', type : 'feature', - value : 'disabled', description : '''Enable support for EXYNOS's experimental KMS API.''', ) option( @@ -63,7 +61,6 @@ option( option( 'tegra', type : 'feature', - value : 'disabled', description : '''Enable support for Tegra's experimental KMS API.''', ) option( diff --git a/nouveau/Android.bp b/nouveau/Android.bp index b844fdde2..12c37e3dc 100644 --- a/nouveau/Android.bp +++ b/nouveau/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/nouveau/Makefile.sources b/nouveau/Makefile.sources deleted file mode 100644 index 89f2a2b5c..000000000 --- a/nouveau/Makefile.sources +++ /dev/null @@ -1,9 +0,0 @@ -LIBDRM_NOUVEAU_FILES := \ - nouveau.c \ - pushbuf.c \ - bufctx.c \ - abi16.c \ - private.h - -LIBDRM_NOUVEAU_H_FILES := \ - nouveau.h diff --git a/nouveau/meson.build b/nouveau/meson.build index 71c8f5522..1b541f4d1 100644 --- a/nouveau/meson.build +++ b/nouveau/meson.build @@ -27,7 +27,7 @@ libdrm_nouveau = library( include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_threads, dep_atomic_ops], - version : '2.0.0', + version : '2.@0@.0'.format(patch_ver), install : true, ) @@ -36,9 +36,7 @@ ext_libdrm_nouveau = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_nouveau', ext_libdrm_nouveau) -endif +meson.override_dependency('libdrm_nouveau', ext_libdrm_nouveau) install_headers('nouveau.h', subdir : 'libdrm/nouveau') install_headers( diff --git a/omap/Android.bp b/omap/Android.bp index a3a5a9e3e..05ca7d2db 100644 --- a/omap/Android.bp +++ b/omap/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/omap/meson.build b/omap/meson.build index eebd1420f..145fc3ddd 100644 --- a/omap/meson.build +++ b/omap/meson.build @@ -26,7 +26,7 @@ libdrm_omap = library( gnu_symbol_visibility : 'hidden', link_with : libdrm, dependencies : [dep_threads, dep_atomic_ops], - version : '1.0.0', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -35,9 +35,7 @@ ext_libdrm_omap = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_omap', ext_libdrm_omap) -endif +meson.override_dependency('libdrm_omap', ext_libdrm_omap) install_headers('omap_drmif.h', subdir : 'libdrm') install_headers('omap_drm.h', subdir : 'omap') @@ -56,6 +54,6 @@ test( args : [ '--lib', libdrm_omap, '--symbols-file', files('omap-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/omap/omap_drm.c b/omap/omap_drm.c index aa2736604..273e449ff 100644 --- a/omap/omap_drm.c +++ b/omap/omap_drm.c @@ -27,8 +27,6 @@ */ #include -#include -#include #include #include #include @@ -42,10 +40,6 @@ #include "omap_drm.h" #include "omap_drmif.h" -#define __round_mask(x, y) ((__typeof__(x))((y)-1)) -#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) -#define PAGE_SIZE 4096 - static pthread_mutex_t table_lock = PTHREAD_MUTEX_INITIALIZER; static void * dev_table; @@ -208,12 +202,6 @@ static struct omap_bo * omap_bo_new_impl(struct omap_device *dev, bo = bo_from_handle(dev, req.handle); pthread_mutex_unlock(&table_lock); - if (flags & OMAP_BO_TILED) { - bo->size = round_up(size.tiled.width, PAGE_SIZE) * size.tiled.height; - } else { - bo->size = size.bytes; - } - return bo; fail: @@ -433,7 +421,7 @@ drm_public uint32_t omap_bo_size(struct omap_bo *bo) drm_public void *omap_bo_map(struct omap_bo *bo) { if (!bo->map) { - if (!bo->offset) { + if (!bo->size || !bo->offset) { get_buffer_info(bo); } diff --git a/radeon/Android.bp b/radeon/Android.bp old mode 100644 new mode 100755 index 6c52084f6..9d0a09ec7 --- a/radeon/Android.bp +++ b/radeon/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_shared { diff --git a/radeon/Android.sources.bp b/radeon/Android.sources.bp old mode 100644 new mode 100755 diff --git a/radeon/Makefile.sources b/radeon/Makefile.sources deleted file mode 100644 index 1cf482a4e..000000000 --- a/radeon/Makefile.sources +++ /dev/null @@ -1,21 +0,0 @@ -LIBDRM_RADEON_FILES := \ - radeon_bo_gem.c \ - radeon_cs_gem.c \ - radeon_cs_space.c \ - radeon_bo.c \ - radeon_cs.c \ - radeon_surface.c - -LIBDRM_RADEON_H_FILES := \ - radeon_bo.h \ - radeon_cs.h \ - radeon_surface.h \ - radeon_bo_gem.h \ - radeon_cs_gem.h \ - radeon_bo_int.h \ - radeon_cs_int.h \ - r600_pci_ids.h - -LIBDRM_RADEON_BOF_FILES := \ - bof.c \ - bof.h diff --git a/radeon/bof.c b/radeon/bof.c old mode 100644 new mode 100755 diff --git a/radeon/bof.h b/radeon/bof.h old mode 100644 new mode 100755 diff --git a/radeon/libdrm_radeon.pc.in b/radeon/libdrm_radeon.pc.in old mode 100644 new mode 100755 diff --git a/radeon/meson.build b/radeon/meson.build old mode 100644 new mode 100755 index 7aa9b705c..2d2e88541 --- a/radeon/meson.build +++ b/radeon/meson.build @@ -33,7 +33,7 @@ libdrm_radeon = library( include_directories : [inc_root, inc_drm], link_with : libdrm, dependencies : [dep_threads, dep_atomic_ops], - version : '1.0.1', + version : '1.@0@.0'.format(patch_ver), install : true, ) @@ -42,9 +42,7 @@ ext_libdrm_radeon = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_radeon', ext_libdrm_radeon) -endif +meson.override_dependency('libdrm_radeon', ext_libdrm_radeon) install_headers( 'radeon_bo.h', 'radeon_cs.h', 'radeon_surface.h', 'radeon_bo_gem.h', diff --git a/radeon/r600_pci_ids.h b/radeon/r600_pci_ids.h old mode 100644 new mode 100755 diff --git a/radeon/radeon-symbols.txt b/radeon/radeon-symbols.txt old mode 100644 new mode 100755 diff --git a/radeon/radeon_bo.c b/radeon/radeon_bo.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_bo.h b/radeon/radeon_bo.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_bo_gem.c b/radeon/radeon_bo_gem.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_bo_gem.h b/radeon/radeon_bo_gem.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_bo_int.h b/radeon/radeon_bo_int.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs.c b/radeon/radeon_cs.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs.h b/radeon/radeon_cs.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs_gem.h b/radeon/radeon_cs_gem.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs_int.h b/radeon/radeon_cs_int.h old mode 100644 new mode 100755 diff --git a/radeon/radeon_cs_space.c b/radeon/radeon_cs_space.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c old mode 100644 new mode 100755 diff --git a/radeon/radeon_surface.h b/radeon/radeon_surface.h old mode 100644 new mode 100755 diff --git a/symbols-check.py b/symbols-check.py index 2e7ba68d1..c63c0d112 100644 --- a/symbols-check.py +++ b/symbols-check.py @@ -7,6 +7,7 @@ # This list contains symbols that _might_ be exported for some platforms PLATFORM_SYMBOLS = [ + '_GLOBAL_OFFSET_TABLE_', '__bss_end__', '__bss_start__', '__bss_start', @@ -16,6 +17,9 @@ '_end', '_fini', '_init', + '_fbss', + '_fdata', + '_ftext', ] diff --git a/tegra/Android.bp b/tegra/Android.bp index 297c01932..33eaf6c50 100644 --- a/tegra/Android.bp +++ b/tegra/Android.bp @@ -1,12 +1,3 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - cc_library_shared { name: "libdrm_tegra", vendor: true, diff --git a/tegra/job.c b/tegra/job.c index 75a344f1d..b9af49876 100755 --- a/tegra/job.c +++ b/tegra/job.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include "private.h" diff --git a/tegra/meson.build b/tegra/meson.build index 5325ed747..bd1e08f86 100644 --- a/tegra/meson.build +++ b/tegra/meson.build @@ -31,7 +31,7 @@ libdrm_tegra = library( dependencies : [dep_threads, dep_atomic_ops], c_args : libdrm_c_args, gnu_symbol_visibility : 'hidden', - version : '0.0.0', + version : '0.@0@.0'.format(patch_ver), install : true, ) @@ -40,9 +40,7 @@ ext_libdrm_tegra = declare_dependency( include_directories : [inc_drm, include_directories('.')], ) -if meson.version().version_compare('>= 0.54.0') - meson.override_dependency('libdrm_tegra', ext_libdrm_tegra) -endif +meson.override_dependency('libdrm_tegra', ext_libdrm_tegra) install_headers('tegra.h', subdir : 'libdrm') @@ -59,6 +57,6 @@ test( args : [ '--lib', libdrm_tegra, '--symbols-file', files('tegra-symbols.txt'), - '--nm', prog_nm.path(), + '--nm', prog_nm.full_path(), ], ) diff --git a/tests/Android.bp b/tests/Android.bp index bff7f9913..7eb3e3a9a 100644 --- a/tests/Android.bp +++ b/tests/Android.bp @@ -1,15 +1,7 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - subdirs = ["*"] cc_library_headers { name: "libdrm_test_headers", export_include_dirs: ["."], + vendor_available: true, } diff --git a/tests/amdgpu/amdgpu_stress.c b/tests/amdgpu/amdgpu_stress.c deleted file mode 100644 index f919351e1..000000000 --- a/tests/amdgpu/amdgpu_stress.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "drm.h" -#include "xf86drmMode.h" -#include "xf86drm.h" -#include "amdgpu.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#define MAX_CARDS_SUPPORTED 4 -#define NUM_BUFFER_OBJECTS 1024 - -#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ - (((sub_op) & 0xFF) << 8) | \ - (((op) & 0xFF) << 0)) - -#define SDMA_OPCODE_COPY 1 -# define SDMA_COPY_SUB_OPCODE_LINEAR 0 - - -#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \ - (((b) & 0x1) << 26) | \ - (((t) & 0x1) << 23) | \ - (((s) & 0x1) << 22) | \ - (((cnt) & 0xFFFFF) << 0)) -#define SDMA_OPCODE_COPY_SI 3 - - -/** Help string for command line parameters */ -static const char usage[] = - "Usage: %s [-?h] [-b v|g|vg size] " - "[-c from to size count]\n" - "where:\n" - " b - Allocate a BO in VRAM, GTT or VRAM|GTT of size bytes.\n" - " This flag can be used multiple times. The first bo will\n" - " have id `1`, then second id `2`, ...\n" - " c - Copy size bytes from BO (bo_id1) to BO (bo_id2), count times\n" - " h - Display this help\n" - "\n" - "Sizes can be postfixes with k, m or g for kilo, mega and gigabyte scaling\n"; - -/** Specified options strings for getopt */ -static const char options[] = "?hb:c:"; - -/* Open AMD devices. - * Returns the fd of the first device it could open. - */ -static int amdgpu_open_device(void) -{ - drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - unsigned int i; - int drm_count; - - drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); - if (drm_count < 0) { - fprintf(stderr, "drmGetDevices2() returned an error %d\n", - drm_count); - return drm_count; - } - - for (i = 0; i < drm_count; i++) { - drmVersionPtr version; - int fd; - - /* If this is not PCI device, skip*/ - if (devices[i]->bustype != DRM_BUS_PCI) - continue; - - /* If this is not AMD GPU vender ID, skip*/ - if (devices[i]->deviceinfo.pci->vendor_id != 0x1002) - continue; - - if (!(devices[i]->available_nodes & 1 << DRM_NODE_RENDER)) - continue; - - fd = open(devices[i]->nodes[DRM_NODE_RENDER], O_RDWR | O_CLOEXEC); - - /* This node is not available. */ - if (fd < 0) continue; - - version = drmGetVersion(fd); - if (!version) { - fprintf(stderr, - "Warning: Cannot get version for %s." - "Error is %s\n", - devices[i]->nodes[DRM_NODE_RENDER], - strerror(errno)); - close(fd); - continue; - } - - if (strcmp(version->name, "amdgpu")) { - /* This is not AMDGPU driver, skip.*/ - drmFreeVersion(version); - close(fd); - continue; - } - - drmFreeVersion(version); - drmFreeDevices(devices, drm_count); - return fd; - } - - return -1; -} - -amdgpu_device_handle device_handle; -amdgpu_context_handle context_handle; - -amdgpu_bo_handle resources[NUM_BUFFER_OBJECTS]; -uint64_t virtual[NUM_BUFFER_OBJECTS]; -unsigned int num_buffers; -uint32_t *pm4; - -int alloc_bo(uint32_t domain, uint64_t size) -{ - struct amdgpu_bo_alloc_request request = {}; - amdgpu_bo_handle bo; - amdgpu_va_handle va; - uint64_t addr; - int r; - - if (num_buffers >= NUM_BUFFER_OBJECTS) - return -ENOSPC; - - request.alloc_size = size; - request.phys_alignment = 0; - request.preferred_heap = domain; - request.flags = 0; - r = amdgpu_bo_alloc(device_handle, &request, &bo); - if (r) - return r; - - r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, - size, 0, 0, &addr, &va, 0); - if (r) - return r; - - r = amdgpu_bo_va_op_raw(device_handle, bo, 0, size, addr, - AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_WRITEABLE | - AMDGPU_VM_PAGE_EXECUTABLE, AMDGPU_VA_OP_MAP); - if (r) - return r; - - resources[num_buffers] = bo; - virtual[num_buffers] = addr; - fprintf(stdout, "Allocated BO number %u at 0x%" PRIx64 ", domain 0x%x, size %" PRIu64 "\n", - num_buffers++, addr, domain, size); - return 0; -} - -int submit_ib(uint32_t from, uint32_t to, uint64_t size, uint32_t count) -{ - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_fence fence_status; - struct amdgpu_cs_ib_info ib_info; - uint64_t copied = size, delta; - struct timespec start, stop; - - uint64_t src = virtual[from]; - uint64_t dst = virtual[to]; - uint32_t expired; - int i, r; - - i = 0; - while (size) { - uint64_t bytes = size < 0x40000 ? size : 0x40000; - - if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, - bytes); - pm4[i++] = 0xffffffff & dst; - pm4[i++] = 0xffffffff & src; - pm4[i++] = (0xffffffff00000000 & dst) >> 32; - pm4[i++] = (0xffffffff00000000 & src) >> 32; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, - SDMA_COPY_SUB_OPCODE_LINEAR, - 0); - if ( device_handle->info.family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = bytes - 1; - else - pm4[i++] = bytes; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & src; - pm4[i++] = (0xffffffff00000000 & src) >> 32; - pm4[i++] = 0xffffffff & dst; - pm4[i++] = (0xffffffff00000000 & dst) >> 32; - } - - size -= bytes; - src += bytes; - dst += bytes; - } - - memset(&ib_info, 0, sizeof(ib_info)); - ib_info.ib_mc_address = virtual[0]; - ib_info.size = i; - - memset(&ibs_request, 0, sizeof(ibs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_DMA; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = clock_gettime(CLOCK_MONOTONIC, &start); - if (r) - return errno; - - r = amdgpu_bo_list_create(device_handle, num_buffers, resources, NULL, - &ibs_request.resources); - if (r) - return r; - - for (i = 0; i < count; ++i) { - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - } - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - memset(&fence_status, 0, sizeof(fence_status)); - fence_status.ip_type = ibs_request.ip_type; - fence_status.ip_instance = 0; - fence_status.ring = ibs_request.ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request.seq_no; - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - r = clock_gettime(CLOCK_MONOTONIC, &stop); - if (r) - return errno; - - delta = stop.tv_nsec + stop.tv_sec * 1000000000UL; - delta -= start.tv_nsec + start.tv_sec * 1000000000UL; - - fprintf(stdout, "Submitted %u IBs to copy from %u(%" PRIx64 ") to %u(%" PRIx64 ") %" PRIu64 " bytes took %" PRIu64 " usec\n", - count, from, virtual[from], to, virtual[to], copied, delta / 1000); - return 0; -} - -void next_arg(int argc, char **argv, const char *msg) -{ - optarg = argv[optind++]; - if (optind > argc || optarg[0] == '-') { - fprintf(stderr, "%s\n", msg); - exit(EXIT_FAILURE); - } -} - -uint64_t parse_size(void) -{ - uint64_t size; - char ext[2]; - - ext[0] = 0; - if (sscanf(optarg, "%" PRIi64 "%1[kmgKMG]", &size, ext) < 1) { - fprintf(stderr, "Can't parse size arg: %s\n", optarg); - exit(EXIT_FAILURE); - } - switch (ext[0]) { - case 'k': - case 'K': - size *= 1024; - break; - case 'm': - case 'M': - size *= 1024 * 1024; - break; - case 'g': - case 'G': - size *= 1024 * 1024 * 1024; - break; - default: - break; - } - return size; -} - -int main(int argc, char **argv) -{ - uint32_t major_version, minor_version; - uint32_t domain, from, to, count; - uint64_t size; - int fd, r, c; - - fd = amdgpu_open_device(); - if (fd < 0) { - perror("Cannot open AMDGPU device"); - exit(EXIT_FAILURE); - } - - r = amdgpu_device_initialize(fd, &major_version, &minor_version, &device_handle); - if (r) { - fprintf(stderr, "amdgpu_device_initialize returned %d\n", r); - exit(EXIT_FAILURE); - } - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) { - fprintf(stderr, "amdgpu_cs_ctx_create returned %d\n", r); - exit(EXIT_FAILURE); - } - - if (argc == 1) { - fprintf(stderr, usage, argv[0]); - exit(EXIT_FAILURE); - } - - r = alloc_bo(AMDGPU_GEM_DOMAIN_GTT, 2ULL * 1024 * 1024); - if (r) { - fprintf(stderr, "Buffer allocation failed with %d\n", r); - exit(EXIT_FAILURE); - } - - r = amdgpu_bo_cpu_map(resources[0], (void **)&pm4); - if (r) { - fprintf(stderr, "Buffer mapping failed with %d\n", r); - exit(EXIT_FAILURE); - } - - opterr = 0; - while ((c = getopt(argc, argv, options)) != -1) { - switch (c) { - case 'b': - if (!strcmp(optarg, "v")) - domain = AMDGPU_GEM_DOMAIN_VRAM; - else if (!strcmp(optarg, "g")) - domain = AMDGPU_GEM_DOMAIN_GTT; - else if (!strcmp(optarg, "vg")) - domain = AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT; - else { - fprintf(stderr, "Invalid domain: %s\n", optarg); - exit(EXIT_FAILURE); - } - next_arg(argc, argv, "Missing buffer size"); - size = parse_size(); - if (size < getpagesize()) { - fprintf(stderr, "Buffer size to small %" PRIu64 "\n", size); - exit(EXIT_FAILURE); - } - r = alloc_bo(domain, size); - if (r) { - fprintf(stderr, "Buffer allocation failed with %d\n", r); - exit(EXIT_FAILURE); - } - break; - case 'c': - if (sscanf(optarg, "%u", &from) != 1) { - fprintf(stderr, "Can't parse from buffer: %s\n", optarg); - exit(EXIT_FAILURE); - } - next_arg(argc, argv, "Missing to buffer"); - if (sscanf(optarg, "%u", &to) != 1) { - fprintf(stderr, "Can't parse to buffer: %s\n", optarg); - exit(EXIT_FAILURE); - } - next_arg(argc, argv, "Missing size"); - size = parse_size(); - next_arg(argc, argv, "Missing count"); - count = parse_size(); - r = submit_ib(from, to, size, count); - if (r) { - fprintf(stderr, "IB submission failed with %d\n", r); - exit(EXIT_FAILURE); - } - break; - case '?': - case 'h': - fprintf(stderr, usage, argv[0]); - exit(EXIT_SUCCESS); - default: - fprintf(stderr, usage, argv[0]); - exit(EXIT_FAILURE); - } - } - - return EXIT_SUCCESS; -} diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c deleted file mode 100644 index ec787889a..000000000 --- a/tests/amdgpu/amdgpu_test.c +++ /dev/null @@ -1,949 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef __linux__ -#include -#elif __FreeBSD__ -/* SPECNAMELEN in FreeBSD is defined here: */ -#include -#endif -#ifdef MAJOR_IN_MKDEV -#include -#endif -#ifdef MAJOR_IN_SYSMACROS -#include -#endif - -#include "drm.h" -#include "xf86drmMode.h" -#include "xf86drm.h" - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_internal.h" - -/* Test suite names */ -#define BASIC_TESTS_STR "Basic Tests" -#define BO_TESTS_STR "BO Tests" -#define CS_TESTS_STR "CS Tests" -#define VCE_TESTS_STR "VCE Tests" -#define VCN_TESTS_STR "VCN Tests" -#define JPEG_TESTS_STR "JPEG Tests" -#define UVD_ENC_TESTS_STR "UVD ENC Tests" -#define DEADLOCK_TESTS_STR "Deadlock Tests" -#define VM_TESTS_STR "VM Tests" -#define RAS_TESTS_STR "RAS Tests" -#define SYNCOBJ_TIMELINE_TESTS_STR "SYNCOBJ TIMELINE Tests" -#define SECURITY_TESTS_STR "Security Tests" -#define HOTUNPLUG_TESTS_STR "Hotunplug Tests" -#define CP_DMA_TESTS_STR "CP DMA Tests" - -/** - * Open handles for amdgpu devices - * - */ -int drm_amdgpu[MAX_CARDS_SUPPORTED]; - -/** Open render node to test */ -int open_render_node = 0; /* By default run most tests on primary node */ - -/** The table of all known test suites to run */ -static CU_SuiteInfo suites[] = { - { - .pName = BASIC_TESTS_STR, - .pInitFunc = suite_basic_tests_init, - .pCleanupFunc = suite_basic_tests_clean, - .pTests = basic_tests, - }, - { - .pName = BO_TESTS_STR, - .pInitFunc = suite_bo_tests_init, - .pCleanupFunc = suite_bo_tests_clean, - .pTests = bo_tests, - }, - { - .pName = CS_TESTS_STR, - .pInitFunc = suite_cs_tests_init, - .pCleanupFunc = suite_cs_tests_clean, - .pTests = cs_tests, - }, - { - .pName = VCE_TESTS_STR, - .pInitFunc = suite_vce_tests_init, - .pCleanupFunc = suite_vce_tests_clean, - .pTests = vce_tests, - }, - { - .pName = VCN_TESTS_STR, - .pInitFunc = suite_vcn_tests_init, - .pCleanupFunc = suite_vcn_tests_clean, - .pTests = vcn_tests, - }, - { - .pName = JPEG_TESTS_STR, - .pInitFunc = suite_jpeg_tests_init, - .pCleanupFunc = suite_jpeg_tests_clean, - .pTests = jpeg_tests, - }, - { - .pName = UVD_ENC_TESTS_STR, - .pInitFunc = suite_uvd_enc_tests_init, - .pCleanupFunc = suite_uvd_enc_tests_clean, - .pTests = uvd_enc_tests, - }, - { - .pName = DEADLOCK_TESTS_STR, - .pInitFunc = suite_deadlock_tests_init, - .pCleanupFunc = suite_deadlock_tests_clean, - .pTests = deadlock_tests, - }, - { - .pName = VM_TESTS_STR, - .pInitFunc = suite_vm_tests_init, - .pCleanupFunc = suite_vm_tests_clean, - .pTests = vm_tests, - }, - { - .pName = RAS_TESTS_STR, - .pInitFunc = suite_ras_tests_init, - .pCleanupFunc = suite_ras_tests_clean, - .pTests = ras_tests, - }, - { - .pName = SYNCOBJ_TIMELINE_TESTS_STR, - .pInitFunc = suite_syncobj_timeline_tests_init, - .pCleanupFunc = suite_syncobj_timeline_tests_clean, - .pTests = syncobj_timeline_tests, - }, - { - .pName = SECURITY_TESTS_STR, - .pInitFunc = suite_security_tests_init, - .pCleanupFunc = suite_security_tests_clean, - .pTests = security_tests, - }, - { - .pName = HOTUNPLUG_TESTS_STR, - .pInitFunc = suite_hotunplug_tests_init, - .pCleanupFunc = suite_hotunplug_tests_clean, - .pTests = hotunplug_tests, - }, - { - .pName = CP_DMA_TESTS_STR, - .pInitFunc = suite_cp_dma_tests_init, - .pCleanupFunc = suite_cp_dma_tests_clean, - .pTests = cp_dma_tests, - }, - - CU_SUITE_INFO_NULL, -}; - -typedef CU_BOOL (*active__stat_func)(void); - -typedef struct Suites_Active_Status { - char* pName; - active__stat_func pActive; -}Suites_Active_Status; - -static CU_BOOL always_active() -{ - return CU_TRUE; -} - -static Suites_Active_Status suites_active_stat[] = { - { - .pName = BASIC_TESTS_STR, - .pActive = suite_basic_tests_enable, - }, - { - .pName = BO_TESTS_STR, - .pActive = always_active, - }, - { - .pName = CS_TESTS_STR, - .pActive = suite_cs_tests_enable, - }, - { - .pName = VCE_TESTS_STR, - .pActive = suite_vce_tests_enable, - }, - { - .pName = VCN_TESTS_STR, - .pActive = suite_vcn_tests_enable, - }, - { - .pName = JPEG_TESTS_STR, - .pActive = suite_jpeg_tests_enable, - }, - { - .pName = UVD_ENC_TESTS_STR, - .pActive = suite_uvd_enc_tests_enable, - }, - { - .pName = DEADLOCK_TESTS_STR, - .pActive = suite_deadlock_tests_enable, - }, - { - .pName = VM_TESTS_STR, - .pActive = suite_vm_tests_enable, - }, - { - .pName = RAS_TESTS_STR, - .pActive = suite_ras_tests_enable, - }, - { - .pName = SYNCOBJ_TIMELINE_TESTS_STR, - .pActive = suite_syncobj_timeline_tests_enable, - }, - { - .pName = SECURITY_TESTS_STR, - .pActive = suite_security_tests_enable, - }, - { - .pName = HOTUNPLUG_TESTS_STR, - .pActive = suite_hotunplug_tests_enable, - }, - { - .pName = CP_DMA_TESTS_STR, - .pActive = suite_cp_dma_tests_enable, - }, -}; - - -/* - * Display information about all suites and their tests - * - * NOTE: Must be run after registry is initialized and suites registered. - */ -static void display_test_suites(void) -{ - int iSuite; - int iTest; - CU_pSuite pSuite = NULL; - CU_pTest pTest = NULL; - - printf("%5s: %2s: %8s: %s\n", "What", "ID", "Status", "Name"); - - for (iSuite = 0; suites[iSuite].pName != NULL; iSuite++) { - - pSuite = CU_get_suite_by_index((unsigned int) iSuite + 1, - CU_get_registry()); - - if (!pSuite) { - fprintf(stderr, "Invalid suite id : %d\n", iSuite + 1); - continue; - } - - printf("Suite: %2d: %8s: %s\n", - iSuite + 1, - pSuite->fActive ? "ENABLED" : "DISABLED", - suites[iSuite].pName); - - if (!pSuite->fActive) - continue; - - for (iTest = 0; suites[iSuite].pTests[iTest].pName != NULL; - iTest++) { - pTest = CU_get_test_by_index((unsigned int) iTest + 1, - pSuite); - if (!pTest) { - fprintf(stderr, "Invalid test id : %d\n", iTest + 1); - continue; - } - printf(" Test: %2d: %8s: %s\n", - iTest + 1, - pSuite->fActive && pTest->fActive ? "ENABLED" : "DISABLED", - suites[iSuite].pTests[iTest].pName); - } - } -} - -/** Help string for command line parameters */ -static const char usage[] = - "Usage: %s [-hlpr] [-s ] [-e [.] [-e ...]] [-t ] [-f] " - "[-b ] [-d ]\n" - "Where,\n" - " -b Specify device's PCI bus id to run tests\n" - " -d Specify device's PCI device id to run tests (optional)\n" - " -e [.] Disable test of suite . If only is given, then disable\n" - " the whole suite. Can be specified more than once on the command line\n" - " to disable multiple tests or suites.\n" - " -f Force executing inactive suite or test\n" - " -h Display this help\n" - " -l Display all test suites and their tests\n" - " -p Display information of AMDGPU devices in system\n" - " -r Run the tests on render node\n" - " -s Enable only test suite \n" - " -t Enable only test of test suite \n"; -/** Specified options strings for getopt */ -static const char options[] = "hlrps:t:e:b:d:f"; - -/* Open AMD devices. - * Return the number of AMD device opened. - */ -static int amdgpu_open_devices(int open_render_node) -{ - drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - int i; - int drm_node; - int amd_index = 0; - int drm_count; - int fd; - drmVersionPtr version; - - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) { - drm_amdgpu[i] = -1; - } - - drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); - - if (drm_count < 0) { - fprintf(stderr, - "drmGetDevices2() returned an error %d\n", - drm_count); - return 0; - } - - for (i = 0; i < drm_count; i++) { - /* If this is not PCI device, skip*/ - if (devices[i]->bustype != DRM_BUS_PCI) - continue; - - /* If this is not AMD GPU vender ID, skip*/ - if (devices[i]->deviceinfo.pci->vendor_id != 0x1002) - continue; - - if (open_render_node) - drm_node = DRM_NODE_RENDER; - else - drm_node = DRM_NODE_PRIMARY; - - fd = -1; - if (devices[i]->available_nodes & 1 << drm_node) - fd = open( - devices[i]->nodes[drm_node], - O_RDWR | O_CLOEXEC); - - /* This node is not available. */ - if (fd < 0) continue; - - version = drmGetVersion(fd); - if (!version) { - fprintf(stderr, - "Warning: Cannot get version for %s." - "Error is %s\n", - devices[i]->nodes[drm_node], - strerror(errno)); - close(fd); - continue; - } - - if (strcmp(version->name, "amdgpu")) { - /* This is not AMDGPU driver, skip.*/ - drmFreeVersion(version); - close(fd); - continue; - } - - drmFreeVersion(version); - - drm_amdgpu[amd_index] = fd; - amd_index++; - } - - drmFreeDevices(devices, drm_count); - return amd_index; -} - -/* Close AMD devices. - */ -void amdgpu_close_devices() -{ - int i; - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) - if (drm_amdgpu[i] >=0) { - close(drm_amdgpu[i]); - } -} - -/* Print AMD devices information */ -static void amdgpu_print_devices() -{ - int i; - drmDevicePtr device; - - /* Open the first AMD device to print driver information. */ - if (drm_amdgpu[0] >=0) { - /* Display AMD driver version information.*/ - drmVersionPtr retval = drmGetVersion(drm_amdgpu[0]); - - if (retval == NULL) { - perror("Cannot get version for AMDGPU device"); - return; - } - - printf("Driver name: %s, Date: %s, Description: %s.\n", - retval->name, retval->date, retval->desc); - drmFreeVersion(retval); - } - - /* Display information of AMD devices */ - printf("Devices:\n"); - for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >=0; i++) - if (drmGetDevice2(drm_amdgpu[i], - DRM_DEVICE_GET_PCI_REVISION, - &device) == 0) { - if (device->bustype == DRM_BUS_PCI) { - printf("PCI "); - printf(" domain:%04x", - device->businfo.pci->domain); - printf(" bus:%02x", - device->businfo.pci->bus); - printf(" device:%02x", - device->businfo.pci->dev); - printf(" function:%01x", - device->businfo.pci->func); - printf(" vendor_id:%04x", - device->deviceinfo.pci->vendor_id); - printf(" device_id:%04x", - device->deviceinfo.pci->device_id); - printf(" subvendor_id:%04x", - device->deviceinfo.pci->subvendor_id); - printf(" subdevice_id:%04x", - device->deviceinfo.pci->subdevice_id); - printf(" revision_id:%02x", - device->deviceinfo.pci->revision_id); - printf("\n"); - } - drmFreeDevice(&device); - } -} - -/* Find a match AMD device in PCI bus - * Return the index of the device or -1 if not found - */ -static int amdgpu_find_device(uint8_t bus, uint16_t dev) -{ - int i; - drmDevicePtr device; - - for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) { - if (drmGetDevice2(drm_amdgpu[i], - DRM_DEVICE_GET_PCI_REVISION, - &device) == 0) { - if (device->bustype == DRM_BUS_PCI) - if ((bus == 0xFF || device->businfo.pci->bus == bus) && - device->deviceinfo.pci->device_id == dev) { - drmFreeDevice(&device); - return i; - } - - drmFreeDevice(&device); - } - } - - return -1; -} - -static void amdgpu_disable_suites() -{ - amdgpu_device_handle device_handle; - uint32_t major_version, minor_version, family_id; - drmDevicePtr devices[MAX_CARDS_SUPPORTED]; - int i, drm_count; - int size = sizeof(suites_active_stat) / sizeof(suites_active_stat[0]); - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return; - - family_id = device_handle->info.family_id; - - if (amdgpu_device_deinitialize(device_handle)) - return; - - drm_count = drmGetDevices2(0, devices, MAX_CARDS_SUPPORTED); - - /* Set active status for suites based on their policies */ - for (i = 0; i < size; ++i) - if (amdgpu_set_suite_active(suites_active_stat[i].pName, - suites_active_stat[i].pActive())) - fprintf(stderr, "suite deactivation failed - %s\n", CU_get_error_msg()); - - /* Explicitly disable specific tests due to known bugs or preferences */ - /* - * BUG: Compute ring stalls and never recovers when the address is - * written after the command already submitted - */ - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "compute ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "sdma ring block test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(DEADLOCK_TESTS_STR, - "sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - if (amdgpu_set_test_active(BASIC_TESTS_STR, "bo eviction Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX8 and GFX9 only */ - if (family_id < AMDGPU_FAMILY_VI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(BASIC_TESTS_STR, "Sync dependency Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) { - if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test (GFX)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - if (amdgpu_set_test_active(BASIC_TESTS_STR, "Dispatch Test (Compute)", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - } - - /* This test was ran on GFX9 only */ - if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(BASIC_TESTS_STR, "Draw Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* This test was ran on GFX9 only */ - //if (family_id < AMDGPU_FAMILY_AI || family_id > AMDGPU_FAMILY_RV) - if (amdgpu_set_test_active(BASIC_TESTS_STR, "GPU reset Test", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); - - /* You need at least 2 devices for this */ - if (drm_count < 2) - if (amdgpu_set_test_active(HOTUNPLUG_TESTS_STR, "Unplug with exported fence", CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", CU_get_error_msg()); -} - -int test_device_index; - -int amdgpu_open_device_on_test_index(int render_node) -{ - int i; - - if (amdgpu_open_devices(open_render_node) <= 0) { - perror("Cannot open AMDGPU device"); - return -1; - } - - if (test_device_index >= 0) { - /* Most tests run on device of drm_amdgpu[0]. - * Swap the chosen device to drm_amdgpu[0]. - */ - i = drm_amdgpu[0]; - drm_amdgpu[0] = drm_amdgpu[test_device_index]; - drm_amdgpu[test_device_index] = i; - } - - return 0; - - -} - - -static bool amdgpu_node_is_drm(int maj, int min) -{ -#ifdef __linux__ - char path[64]; - struct stat sbuf; - - snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device/drm", - maj, min); - return stat(path, &sbuf) == 0; -#elif defined(__FreeBSD__) - char name[SPECNAMELEN]; - - if (!devname_r(makedev(maj, min), S_IFCHR, name, sizeof(name))) - return 0; - /* Handle drm/ and dri/ as both are present in different FreeBSD version - * FreeBSD on amd64/i386/powerpc external kernel modules create node in - * in /dev/drm/ and links in /dev/dri while a WIP in kernel driver creates - * only device nodes in /dev/dri/ */ - return (!strncmp(name, "drm/", 4) || !strncmp(name, "dri/", 4)); -#else - return maj == DRM_MAJOR; -#endif -} - -char *amdgpu_get_device_from_fd(int fd) -{ -#ifdef __linux__ - struct stat sbuf; - char path[PATH_MAX + 1]; - unsigned int maj, min; - - if (fstat(fd, &sbuf)) - return NULL; - - maj = major(sbuf.st_rdev); - min = minor(sbuf.st_rdev); - - if (!amdgpu_node_is_drm(maj, min) || !S_ISCHR(sbuf.st_mode)) - return NULL; - - snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min); - return strdup(path); -#else - return NULL; -#endif -} - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(_A) (sizeof(_A)/sizeof(_A[0])) -#endif - -static void amdgpu_test_disable(long suite, long test) -{ - const char *suite_name; - - if (suite < 1) - return; - - /* The array is 0-based, so subract 1. */ - suite--; - if (suite >= ARRAY_SIZE(suites) - 1) - return; - - suite_name = suites[suite].pName; - if (test < 1) { - fprintf(stderr, "Deactivating suite %s\n", suite_name); - amdgpu_set_suite_active(suite_name, CU_FALSE); - } else { - int ii; - - /* The array is 0-based so subtract 1. */ - test--; - for (ii = 0; suites[suite].pTests[ii].pName; ii++) { - if (ii == test) { - fprintf(stderr, "Deactivating %s:%s\n", - suite_name, - suites[suite].pTests[ii].pName); - amdgpu_set_test_active(suite_name, - suites[suite].pTests[ii].pName, - CU_FALSE); - break; - } - } - - if (suites[suite].pTests[ii].pName == NULL) - fprintf(stderr, "No such suite.test %ld.%ld\n", suite, test); - } -} - -/* The main() function for setting up and running the tests. - * Returns a CUE_SUCCESS on successful running, another - * CUnit error code on failure. - */ -int main(int argc, char **argv) -{ - int c; /* Character received from getopt */ - int i = 0; - int suite_id = -1; /* By default run everything */ - int test_id = -1; /* By default run all tests in the suite */ - int pci_bus_id = -1; /* By default PC bus ID is not specified */ - int pci_device_id = 0; /* By default PC device ID is zero */ - int display_devices = 0;/* By default not to display devices' info */ - CU_pSuite pSuite = NULL; - CU_pTest pTest = NULL; - int display_list = 0; - int force_run = 0; - - /* Parse command line string. - * Process various command line options as early as possible. - */ - opterr = 0; /* Do not print error messages from getopt */ - while ((c = getopt(argc, argv, options)) != -1) { - switch (c) { - case 'h': - fprintf(stderr, usage, argv[0]); - exit(EXIT_SUCCESS); - } - } - - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) - drm_amdgpu[i] = -1; - - if (amdgpu_open_devices(open_render_node) <= 0) { - perror("Cannot open AMDGPU device"); - exit(EXIT_FAILURE); - } - - if (drm_amdgpu[0] < 0) { - perror("Cannot open AMDGPU device"); - exit(EXIT_FAILURE); - } - - /* Parse command line string */ - opterr = 0; /* Do not print error messages from getopt */ - optind = 1; - while ((c = getopt(argc, argv, options)) != -1) { - switch (c) { - case 'p': - display_devices = 1; - break; - } - } - - if (display_devices) { - amdgpu_print_devices(); - amdgpu_close_devices(); - exit(EXIT_SUCCESS); - } - - /* Parse command line string */ - opterr = 0; /* Do not print error messages from getopt */ - optind = 1; - while ((c = getopt(argc, argv, options)) != -1) { - switch (c) { - case 'b': - pci_bus_id = atoi(optarg); - break; - case 'd': - sscanf(optarg, "%x", &pci_device_id); - break; - } - } - - if (pci_bus_id > 0 || pci_device_id) { - /* A device was specified to run the test */ - test_device_index = amdgpu_find_device(pci_bus_id, - pci_device_id); - - if (test_device_index >= 0) { - /* Most tests run on device of drm_amdgpu[0]. - * Swap the chosen device to drm_amdgpu[0]. - */ - i = drm_amdgpu[0]; - drm_amdgpu[0] = drm_amdgpu[test_device_index]; - drm_amdgpu[test_device_index] = i; - } else { - fprintf(stderr, - "The specified GPU device does not exist.\n"); - exit(EXIT_FAILURE); - } - } - - /* Initialize test suites to run */ - - /* initialize the CUnit test registry */ - if (CUE_SUCCESS != CU_initialize_registry()) { - amdgpu_close_devices(); - return CU_get_error(); - } - - /* Register suites. */ - if (CU_register_suites(suites) != CUE_SUCCESS) { - fprintf(stderr, "suite registration failed - %s\n", - CU_get_error_msg()); - CU_cleanup_registry(); - amdgpu_close_devices(); - exit(EXIT_FAILURE); - } - - /* Run tests using the CUnit Basic interface */ - CU_basic_set_mode(CU_BRM_VERBOSE); - - /* Disable suites and individual tests based on misc. conditions */ - amdgpu_disable_suites(); - - /* Parse command line string */ - opterr = 0; /* Do not print error messages from getopt */ - optind = 1; - while ((c = getopt(argc, argv, options)) != -1) { - switch (c) { - case 'l': - display_list = 1; - break; - } - } - - if (display_list) { - display_test_suites(); - goto end; - } - - /* Parse command line string */ - opterr = 0; /* Do not print error messages from getopt */ - optind = 1; - while ((c = getopt(argc, argv, options)) != -1) { - long esuite = -1; - long etest = -1; - char *endp; - switch (c) { - case 's': - suite_id = atoi(optarg); - break; - case 't': - test_id = atoi(optarg); - break; - case 'r': - open_render_node = 1; - break; - case 'f': - force_run = 1; - break; - case 'e': - esuite = strtol(optarg, &endp, 0); - if (endp == optarg) { - fprintf(stderr, "No digits given for -e argument\n"); - goto end; - } else if (endp && *endp == '.' && esuite > 0) { - char *tt = endp + 1; - etest = strtol(tt, &endp, 0); - if (endp == tt) { - fprintf(stderr, "No digits given for test in -e s.t argument\n"); - goto end; - } else if (endp && *endp != '\0') { - fprintf(stderr, "Bad input given for test in -e s.t argument\n"); - goto end; - } else if (etest < 1) { - fprintf(stderr, "Test in -e s.t argument cannot be smaller than 1\n"); - goto end; - } - } else if (endp && *endp != '\0') { - fprintf(stderr, "Bad input given for suite for -e s argument\n"); - goto end; - } else if (esuite < 1) { - fprintf(stderr, "Suite in -e s argument cannot be smaller than 1\n"); - goto end; - } - amdgpu_test_disable(esuite, etest); - break; - case 'h': - case 'p': - case 'b': - case 'd': - case 'l': - /* Those have been processed earlier. - */ - break; - case '?': - default: - fprintf(stderr, "Unknown command line option '%c'. Try -h.\n", - c == '?' ? optopt : c); - goto end; - } - } - - if (suite_id != -1) { /* If user specify particular suite? */ - pSuite = CU_get_suite_by_index((unsigned int) suite_id, - CU_get_registry()); - - if (pSuite) { - - if (force_run) - CU_set_suite_active(pSuite, CU_TRUE); - - if (test_id != -1) { /* If user specify test id */ - pTest = CU_get_test_by_index( - (unsigned int) test_id, - pSuite); - if (pTest) { - if (force_run) - CU_set_test_active(pTest, CU_TRUE); - - CU_basic_run_test(pSuite, pTest); - } - else { - fprintf(stderr, "Invalid test id: %d\n", - test_id); - CU_cleanup_registry(); - amdgpu_close_devices(); - exit(EXIT_FAILURE); - } - } else - CU_basic_run_suite(pSuite); - } else { - fprintf(stderr, "Invalid suite id : %d\n", - suite_id); - CU_cleanup_registry(); - amdgpu_close_devices(); - exit(EXIT_FAILURE); - } - } else - CU_basic_run_tests(); - -end: - CU_cleanup_registry(); - amdgpu_close_devices(); - return CU_get_error(); -} diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h deleted file mode 100644 index e2ba043bb..000000000 --- a/tests/amdgpu/amdgpu_test.h +++ /dev/null @@ -1,546 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _AMDGPU_TEST_H_ -#define _AMDGPU_TEST_H_ - -#include "amdgpu.h" -#include "amdgpu_drm.h" - -/** - * Define max. number of card in system which we are able to handle - */ -#define MAX_CARDS_SUPPORTED 128 - -/* Forward reference for array to keep "drm" handles */ -extern int drm_amdgpu[MAX_CARDS_SUPPORTED]; - -/* Global variables */ -extern int open_render_node; - -/************************* Basic test suite ********************************/ - -/* - * Define basic test suite to serve as the starting point for future testing -*/ - -/** - * Initialize basic test suite - */ -int suite_basic_tests_init(); - -/** - * Deinitialize basic test suite - */ -int suite_basic_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_basic_tests_enable(void); - -/** - * Tests in basic test suite - */ -extern CU_TestInfo basic_tests[]; - -/** - * Initialize bo test suite - */ -int suite_bo_tests_init(); - -/** - * Deinitialize bo test suite - */ -int suite_bo_tests_clean(); - -/** - * Tests in bo test suite - */ -extern CU_TestInfo bo_tests[]; - -/** - * Initialize cs test suite - */ -int suite_cs_tests_init(); - -/** - * Deinitialize cs test suite - */ -int suite_cs_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_cs_tests_enable(void); - -/** - * Tests in cs test suite - */ -extern CU_TestInfo cs_tests[]; - -/** - * Initialize vce test suite - */ -int suite_vce_tests_init(); - -/** - * Deinitialize vce test suite - */ -int suite_vce_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_vce_tests_enable(void); - -/** - * Tests in vce test suite - */ -extern CU_TestInfo vce_tests[]; - -/** -+ * Initialize vcn test suite -+ */ -int suite_vcn_tests_init(); - -/** -+ * Deinitialize vcn test suite -+ */ -int suite_vcn_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_vcn_tests_enable(void); - -/** -+ * Tests in vcn test suite -+ */ -extern CU_TestInfo vcn_tests[]; - -/** -+ * Initialize jpeg test suite -+ */ -int suite_jpeg_tests_init(); - -/** -+ * Deinitialize jpeg test suite -+ */ -int suite_jpeg_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_jpeg_tests_enable(void); - -/** -+ * Tests in vcn test suite -+ */ -extern CU_TestInfo jpeg_tests[]; - -/** - * Initialize uvd enc test suite - */ -int suite_uvd_enc_tests_init(); - -/** - * Deinitialize uvd enc test suite - */ -int suite_uvd_enc_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_uvd_enc_tests_enable(void); - -/** - * Tests in uvd enc test suite - */ -extern CU_TestInfo uvd_enc_tests[]; - -/** - * Initialize deadlock test suite - */ -int suite_deadlock_tests_init(); - -/** - * Deinitialize deadlock test suite - */ -int suite_deadlock_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_deadlock_tests_enable(void); - -/** - * Tests in uvd enc test suite - */ -extern CU_TestInfo deadlock_tests[]; - -/** - * Initialize vm test suite - */ -int suite_vm_tests_init(); - -/** - * Deinitialize deadlock test suite - */ -int suite_vm_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_vm_tests_enable(void); - -/** - * Tests in vm test suite - */ -extern CU_TestInfo vm_tests[]; - - -/** - * Initialize ras test suite - */ -int suite_ras_tests_init(); - -/** - * Deinitialize deadlock test suite - */ -int suite_ras_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_ras_tests_enable(void); - -/** - * Tests in ras test suite - */ -extern CU_TestInfo ras_tests[]; - - -/** - * Initialize syncobj timeline test suite - */ -int suite_syncobj_timeline_tests_init(); - -/** - * Deinitialize syncobj timeline test suite - */ -int suite_syncobj_timeline_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_syncobj_timeline_tests_enable(void); - -/** - * Tests in syncobj timeline test suite - */ -extern CU_TestInfo syncobj_timeline_tests[]; - - -/** - * Initialize cp dma test suite - */ -int suite_cp_dma_tests_init(); - -/** - * Deinitialize cp dma test suite - */ -int suite_cp_dma_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_cp_dma_tests_enable(void); - -/** - * Tests in cp dma test suite - */ -extern CU_TestInfo cp_dma_tests[]; - -/** - * Initialize security test suite - */ -int suite_security_tests_init(); - -/** - * Deinitialize security test suite - */ -int suite_security_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_security_tests_enable(void); - -/** - * Tests in security test suite - */ -extern CU_TestInfo security_tests[]; - -extern void -amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle - device, - unsigned ip_type, - bool secure); - -extern void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip); -extern void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip); -extern void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip); -extern void amdgpu_test_draw_helper(amdgpu_device_handle device_handle); -extern void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle); -extern void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle); - -/** - * Initialize hotunplug test suite - */ -int suite_hotunplug_tests_init(); - -/** - * Deinitialize hotunplug test suite - */ -int suite_hotunplug_tests_clean(); - -/** - * Decide if the suite is enabled by default or not. - */ -CU_BOOL suite_hotunplug_tests_enable(void); - -/** - * Tests in uvd enc test suite - */ -extern CU_TestInfo hotunplug_tests[]; - - -/** - * Helper functions - */ -static inline amdgpu_bo_handle gpu_mem_alloc( - amdgpu_device_handle device_handle, - uint64_t size, - uint64_t alignment, - uint32_t type, - uint64_t flags, - uint64_t *vmc_addr, - amdgpu_va_handle *va_handle) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle = NULL; - int r; - - req.alloc_size = size; - req.phys_alignment = alignment; - req.preferred_heap = type; - req.flags = flags; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - if (r) - return NULL; - - if (vmc_addr && va_handle) { - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - size, alignment, 0, vmc_addr, - va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - if (r) - goto error_free_bo; - - r = amdgpu_bo_va_op(buf_handle, 0, size, *vmc_addr, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - if (r) - goto error_free_va; - } - - return buf_handle; - -error_free_va: - r = amdgpu_va_range_free(*va_handle); - CU_ASSERT_EQUAL(r, 0); - -error_free_bo: - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); - - return NULL; -} - -static inline int gpu_mem_free(amdgpu_bo_handle bo, - amdgpu_va_handle va_handle, - uint64_t vmc_addr, - uint64_t size) -{ - int r; - - if (!bo) - return 0; - - if (va_handle) { - r = amdgpu_bo_va_op(bo, 0, size, vmc_addr, 0, - AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - if (r) - return r; - - r = amdgpu_va_range_free(va_handle); - CU_ASSERT_EQUAL(r, 0); - if (r) - return r; - } - - r = amdgpu_bo_free(bo); - CU_ASSERT_EQUAL(r, 0); - - return r; -} - -static inline int -amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size, - unsigned alignment, unsigned heap, uint64_t flags, - amdgpu_bo_handle *bo) -{ - struct amdgpu_bo_alloc_request request = {}; - amdgpu_bo_handle buf_handle; - int r; - - request.alloc_size = size; - request.phys_alignment = alignment; - request.preferred_heap = heap; - request.flags = flags; - - r = amdgpu_bo_alloc(dev, &request, &buf_handle); - if (r) - return r; - - *bo = buf_handle; - - return 0; -} - -int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, - unsigned alignment, unsigned heap, uint64_t alloc_flags, - uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, - uint64_t *mc_address, - amdgpu_va_handle *va_handle); - -static inline int -amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size, - unsigned alignment, unsigned heap, uint64_t alloc_flags, - amdgpu_bo_handle *bo, void **cpu, uint64_t *mc_address, - amdgpu_va_handle *va_handle) -{ - return amdgpu_bo_alloc_and_map_raw(dev, size, alignment, heap, - alloc_flags, 0, bo, cpu, mc_address, va_handle); -} - -static inline int -amdgpu_bo_unmap_and_free(amdgpu_bo_handle bo, amdgpu_va_handle va_handle, - uint64_t mc_addr, uint64_t size) -{ - amdgpu_bo_cpu_unmap(bo); - amdgpu_bo_va_op(bo, 0, size, mc_addr, 0, AMDGPU_VA_OP_UNMAP); - amdgpu_va_range_free(va_handle); - amdgpu_bo_free(bo); - - return 0; - -} - -static inline int -amdgpu_get_bo_list(amdgpu_device_handle dev, amdgpu_bo_handle bo1, - amdgpu_bo_handle bo2, amdgpu_bo_list_handle *list) -{ - amdgpu_bo_handle resources[] = {bo1, bo2}; - - return amdgpu_bo_list_create(dev, bo2 ? 2 : 1, resources, NULL, list); -} - - -static inline CU_ErrorCode amdgpu_set_suite_active(const char *suite_name, - CU_BOOL active) -{ - CU_ErrorCode r = CU_set_suite_active(CU_get_suite(suite_name), active); - - if (r != CUE_SUCCESS) - fprintf(stderr, "Failed to obtain suite %s\n", suite_name); - - return r; -} - -static inline CU_ErrorCode amdgpu_set_test_active(const char *suite_name, - const char *test_name, CU_BOOL active) -{ - CU_ErrorCode r; - CU_pSuite pSuite = CU_get_suite(suite_name); - - if (!pSuite) { - fprintf(stderr, "Failed to obtain suite %s\n", - suite_name); - return CUE_NOSUITE; - } - - r = CU_set_test_active(CU_get_test(pSuite, test_name), active); - if (r != CUE_SUCCESS) - fprintf(stderr, "Failed to obtain test %s\n", test_name); - - return r; -} - - -static inline bool asic_is_gfx_pipe_removed(uint32_t family_id, uint32_t chip_id, uint32_t chip_rev) -{ - - if (family_id != AMDGPU_FAMILY_AI) - return false; - - switch (chip_id - chip_rev) { - /* Arcturus */ - case 0x32: - /* Aldebaran */ - case 0x3c: - return true; - default: - return false; - } -} - -void amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle, - amdgpu_context_handle context_handle, - unsigned ip_type, int instance, int pm4_dw, - uint32_t *pm4_src, int res_cnt, - amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request, - bool secure); - -void amdgpu_close_devices(); -int amdgpu_open_device_on_test_index(int render_node); -char *amdgpu_get_device_from_fd(int fd); - -#endif /* #ifdef _AMDGPU_TEST_H_ */ diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c deleted file mode 100644 index 0e4a357bb..000000000 --- a/tests/amdgpu/basic_tests.c +++ /dev/null @@ -1,2556 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include -#ifdef MAJOR_IN_SYSMACROS -#include -#endif -#include -#include -#if HAVE_ALLOCA_H -# include -#endif -#include - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include "util_math.h" - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t chip_id; -static uint32_t chip_rev; - -static void amdgpu_query_info_test(void); -static void amdgpu_command_submission_gfx(void); -static void amdgpu_command_submission_compute(void); -static void amdgpu_command_submission_multi_fence(void); -static void amdgpu_command_submission_sdma(void); -static void amdgpu_userptr_test(void); -static void amdgpu_semaphore_test(void); -static void amdgpu_sync_dependency_test(void); -static void amdgpu_bo_eviction_test(void); -static void amdgpu_compute_dispatch_test(void); -static void amdgpu_gfx_dispatch_test(void); -static void amdgpu_draw_test(void); -static void amdgpu_gpu_reset_test(void); -static void amdgpu_stable_pstate_test(void); - -static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); -static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); -static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, - unsigned ip_type, - int instance, int pm4_dw, uint32_t *pm4_src, - int res_cnt, amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request); - -CU_TestInfo basic_tests[] = { - { "Query Info Test", amdgpu_query_info_test }, - { "Userptr Test", amdgpu_userptr_test }, - { "bo eviction Test", amdgpu_bo_eviction_test }, - { "Command submission Test (GFX)", amdgpu_command_submission_gfx }, - { "Command submission Test (Compute)", amdgpu_command_submission_compute }, - { "Command submission Test (Multi-Fence)", amdgpu_command_submission_multi_fence }, - { "Command submission Test (SDMA)", amdgpu_command_submission_sdma }, - { "SW semaphore Test", amdgpu_semaphore_test }, - { "Sync dependency Test", amdgpu_sync_dependency_test }, - { "Dispatch Test (Compute)", amdgpu_compute_dispatch_test }, - { "Dispatch Test (GFX)", amdgpu_gfx_dispatch_test }, - { "Draw Test", amdgpu_draw_test }, - { "GPU reset Test", amdgpu_gpu_reset_test }, - { "Stable pstate Test", amdgpu_stable_pstate_test }, - CU_TEST_INFO_NULL, -}; -#define BUFFER_SIZE (MAX2(8 * 1024, getpagesize())) -#define SDMA_PKT_HEADER_op_offset 0 -#define SDMA_PKT_HEADER_op_mask 0x000000FF -#define SDMA_PKT_HEADER_op_shift 0 -#define SDMA_PKT_HEADER_OP(x) (((x) & SDMA_PKT_HEADER_op_mask) << SDMA_PKT_HEADER_op_shift) -#define SDMA_OPCODE_CONSTANT_FILL 11 -# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) - /* 0 = byte fill - * 2 = DW fill - */ -#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ - (((sub_op) & 0xFF) << 8) | \ - (((op) & 0xFF) << 0)) -#define SDMA_OPCODE_WRITE 2 -# define SDMA_WRITE_SUB_OPCODE_LINEAR 0 -# define SDMA_WRTIE_SUB_OPCODE_TILED 1 - -#define SDMA_OPCODE_COPY 1 -# define SDMA_COPY_SUB_OPCODE_LINEAR 0 - -#define SDMA_OPCODE_ATOMIC 10 -# define SDMA_ATOMIC_LOOP(x) ((x) << 0) - /* 0 - single_pass_atomic. - * 1 - loop_until_compare_satisfied. - */ -# define SDMA_ATOMIC_TMZ(x) ((x) << 2) - /* 0 - non-TMZ. - * 1 - TMZ. - */ -# define SDMA_ATOMIC_OPCODE(x) ((x) << 9) - /* TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008 - * same as Packet 3 - */ - -#define GFX_COMPUTE_NOP 0xffff1000 -#define SDMA_NOP 0x0 - -/* PM4 */ -#define PACKET_TYPE0 0 -#define PACKET_TYPE1 1 -#define PACKET_TYPE2 2 -#define PACKET_TYPE3 3 - -#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) -#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) -#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) -#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) -#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ - ((reg) & 0xFFFF) | \ - ((n) & 0x3FFF) << 16) -#define CP_PACKET2 0x80000000 -#define PACKET2_PAD_SHIFT 0 -#define PACKET2_PAD_MASK (0x3fffffff << 0) - -#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) - -#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ - (((op) & 0xFF) << 8) | \ - ((n) & 0x3FFF) << 16) -#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1) - -/* Packet 3 types */ -#define PACKET3_NOP 0x10 - -#define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) ((x) << 8) - /* 0 - register - * 1 - memory (sync - via GRBM) - * 2 - gl2 - * 3 - gds - * 4 - reserved - * 5 - memory (async - direct) - */ -#define WR_ONE_ADDR (1 << 16) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) - /* 0 - me - * 1 - pfp - * 2 - ce - */ - -#define PACKET3_ATOMIC_MEM 0x1E -#define TC_OP_ATOMIC_CMPSWAP_RTN_32 0x00000008 -#define ATOMIC_MEM_COMMAND(x) ((x) << 8) - /* 0 - single_pass_atomic. - * 1 - loop_until_compare_satisfied. - */ -#define ATOMIC_MEM_CACHEPOLICAY(x) ((x) << 25) - /* 0 - lru. - * 1 - stream. - */ -#define ATOMIC_MEM_ENGINESEL(x) ((x) << 30) - /* 0 - micro_engine. - */ - -#define PACKET3_DMA_DATA 0x50 -/* 1. header - * 2. CONTROL - * 3. SRC_ADDR_LO or DATA [31:0] - * 4. SRC_ADDR_HI [31:0] - * 5. DST_ADDR_LO [31:0] - * 6. DST_ADDR_HI [7:0] - * 7. COMMAND [30:21] | BYTE_COUNT [20:0] - */ -/* CONTROL */ -# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) - /* 0 - ME - * 1 - PFP - */ -# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) - /* 0 - LRU - * 1 - Stream - * 2 - Bypass - */ -# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) -# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) - /* 0 - DST_ADDR using DAS - * 1 - GDS - * 3 - DST_ADDR using L2 - */ -# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - * 2 - Bypass - */ -# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) -# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) - /* 0 - SRC_ADDR using SAS - * 1 - GDS - * 2 - DATA - * 3 - SRC_ADDR using L2 - */ -# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) -/* COMMAND */ -# define PACKET3_DMA_DATA_DIS_WC (1 << 21) -# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) - /* 0 - none - * 1 - 8 in 16 - * 2 - 8 in 32 - * 3 - 8 in 64 - */ -# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) - /* 0 - none - * 1 - 8 in 16 - * 2 - 8 in 32 - * 3 - 8 in 64 - */ -# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) - /* 0 - memory - * 1 - register - */ -# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) -# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) -# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) - -#define SDMA_PACKET_SI(op, b, t, s, cnt) ((((op) & 0xF) << 28) | \ - (((b) & 0x1) << 26) | \ - (((t) & 0x1) << 23) | \ - (((s) & 0x1) << 22) | \ - (((cnt) & 0xFFFFF) << 0)) -#define SDMA_OPCODE_COPY_SI 3 -#define SDMA_OPCODE_CONSTANT_FILL_SI 13 -#define SDMA_NOP_SI 0xf -#define GFX_COMPUTE_NOP_SI 0x80000000 -#define PACKET3_DMA_DATA_SI 0x41 -# define PACKET3_DMA_DATA_SI_ENGINE(x) ((x) << 27) - /* 0 - ME - * 1 - PFP - */ -# define PACKET3_DMA_DATA_SI_DST_SEL(x) ((x) << 20) - /* 0 - DST_ADDR using DAS - * 1 - GDS - * 3 - DST_ADDR using L2 - */ -# define PACKET3_DMA_DATA_SI_SRC_SEL(x) ((x) << 29) - /* 0 - SRC_ADDR using SAS - * 1 - GDS - * 2 - DATA - * 3 - SRC_ADDR using L2 - */ -# define PACKET3_DMA_DATA_SI_CP_SYNC (1 << 31) - - -#define PKT3_CONTEXT_CONTROL 0x28 -#define CONTEXT_CONTROL_LOAD_ENABLE(x) (((unsigned)(x) & 0x1) << 31) -#define CONTEXT_CONTROL_LOAD_CE_RAM(x) (((unsigned)(x) & 0x1) << 28) -#define CONTEXT_CONTROL_SHADOW_ENABLE(x) (((unsigned)(x) & 0x1) << 31) - -#define PKT3_CLEAR_STATE 0x12 - -#define PKT3_SET_SH_REG 0x76 -#define PACKET3_SET_SH_REG_START 0x00002c00 - -#define PKT3_SET_SH_REG_INDEX 0x9B - -#define PACKET3_DISPATCH_DIRECT 0x15 -#define PACKET3_EVENT_WRITE 0x46 -#define PACKET3_ACQUIRE_MEM 0x58 -#define PACKET3_SET_CONTEXT_REG 0x69 -#define PACKET3_SET_UCONFIG_REG 0x79 -#define PACKET3_DRAW_INDEX_AUTO 0x2D -/* gfx 8 */ -#define mmCOMPUTE_PGM_LO 0x2e0c -#define mmCOMPUTE_PGM_RSRC1 0x2e12 -#define mmCOMPUTE_TMPRING_SIZE 0x2e18 -#define mmCOMPUTE_USER_DATA_0 0x2e40 -#define mmCOMPUTE_USER_DATA_1 0x2e41 -#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 -#define mmCOMPUTE_NUM_THREAD_X 0x2e07 - - - -#define SWAP_32(num) (((num & 0xff000000) >> 24) | \ - ((num & 0x0000ff00) << 8) | \ - ((num & 0x00ff0000) >> 8) | \ - ((num & 0x000000ff) << 24)) - - -/* Shader code - * void main() -{ - - float x = some_input; - for (unsigned i = 0; i < 1000000; i++) - x = sin(x); - - u[0] = 42u; -} -*/ - -static uint32_t shader_bin[] = { - SWAP_32(0x800082be), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0x040085bf), - SWAP_32(0x02810281), SWAP_32(0x02ff08bf), SWAP_32(0x7f969800), SWAP_32(0xfcff84bf), - SWAP_32(0xff0083be), SWAP_32(0x00f00000), SWAP_32(0xc10082be), SWAP_32(0xaa02007e), - SWAP_32(0x000070e0), SWAP_32(0x00000080), SWAP_32(0x000081bf) -}; - -#define CODE_OFFSET 512 -#define DATA_OFFSET 1024 - -enum cs_type { - CS_BUFFERCLEAR, - CS_BUFFERCOPY, - CS_HANG, - CS_HANG_SLOW -}; - -static const uint32_t bufferclear_cs_shader_gfx9[] = { - 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, - 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206, - 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000, - 0xbf810000 -}; - -static const uint32_t bufferclear_cs_shader_gfx10[] = { - 0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205, - 0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004, - 0xBF810000 -}; - -static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = { - {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 }, - {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 }, - {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 }, - {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 }, - {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 } -}; - -static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5; - -static const uint32_t buffercopy_cs_shader_gfx9[] = { - 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, - 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70, - 0xe01c2000, 0x80010200, 0xbf810000 -}; - -static const uint32_t buffercopy_cs_shader_gfx10[] = { - 0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201, - 0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000 -}; - -static const uint32_t preamblecache_gfx9[] = { - 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, - 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, - 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, - 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0, - 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0, - 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0, - 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0, - 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20, - 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, - 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0, - 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0, - 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, - 0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0, - 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, - 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0, - 0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, - 0xc0017900, 0x24b, 0x0 -}; - -static const uint32_t preamblecache_gfx10[] = { - 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, - 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, - 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, - 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0, - 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0, - 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0, - 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0, - 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20, - 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, - 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0, - 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0, - 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, - 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0, - 0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2, - 0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0, - 0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff, - 0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0, - 0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0, - 0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 -}; - -enum ps_type { - PS_CONST, - PS_TEX, - PS_HANG, - PS_HANG_SLOW -}; - -static const uint32_t ps_const_shader_gfx9[] = { - 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203, - 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, - 0xC4001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6; - -static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 }, - { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 } - } -}; - -static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = { - 0x00000004 -}; - -static const uint32_t ps_num_sh_registers_gfx9 = 2; - -static const uint32_t ps_const_sh_registers_gfx9[][2] = { - {0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 }, - {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } -}; - -static const uint32_t ps_num_context_registers_gfx9 = 7; - -static const uint32_t ps_const_context_reg_gfx9[][2] = { - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 } -}; - -static const uint32_t ps_const_shader_gfx10[] = { - 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203, - 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, - 0xF8001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6; - -static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 }, - { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, - { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 } - } -}; - -static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = { - 0x00000004 -}; - -static const uint32_t ps_num_sh_registers_gfx10 = 2; - -static const uint32_t ps_const_sh_registers_gfx10[][2] = { - {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 }, - {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } -}; - -static const uint32_t ps_tex_shader_gfx9[] = { - 0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000, - 0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00, - 0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000, - 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, - 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = { - 0x0000000B -}; - -static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6; - -static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 }, - { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 } - } -}; - -static const uint32_t ps_tex_sh_registers_gfx9[][2] = { - {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 }, - {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } -}; - -static const uint32_t ps_tex_context_reg_gfx9[][2] = { - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 } -}; - -static const uint32_t ps_tex_shader_gfx10[] = { - 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, - 0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A, - 0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70, - 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, - 0xF8001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = { - 0x0000000C -}; - -static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6; - -static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 }, - { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, - { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 } - } -}; - -static const uint32_t vs_RectPosTexFast_shader_gfx9[] = { - 0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100, - 0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206, - 0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080, - 0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003, - 0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101, - 0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903, - 0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100, - 0xC400020F, 0x05060403, 0xBF810000 -}; - -static const uint32_t vs_RectPosTexFast_shader_gfx10[] = { - 0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206, - 0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200, - 0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207, - 0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001, - 0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002, - 0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209, - 0xF80008CF, 0x05030100, 0xF800020F, 0x05060402, - 0xBF810000 -}; - -static const uint32_t cached_cmd_gfx9[] = { - 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, - 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, - 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12, - 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, - 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, - 0xc0026900, 0x292, 0x20, 0x60201b8, - 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 -}; - -static const uint32_t cached_cmd_gfx10[] = { - 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, - 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, - 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18, - 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, - 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, - 0xc0026900, 0x292, 0x20, 0x6020000, - 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 -}; - -unsigned int memcpy_ps_hang[] = { - 0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100, - 0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001, - 0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002, - 0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000, - 0xF800180F, 0x03020100, 0xBF810000 -}; - -struct amdgpu_test_shader { - uint32_t *shader; - uint32_t header_length; - uint32_t body_length; - uint32_t foot_length; -}; - -unsigned int memcpy_cs_hang_slow_ai_codes[] = { - 0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100, - 0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000 -}; - -struct amdgpu_test_shader memcpy_cs_hang_slow_ai = { - memcpy_cs_hang_slow_ai_codes, - 4, - 3, - 1 -}; - -unsigned int memcpy_cs_hang_slow_rv_codes[] = { - 0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100, - 0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000 -}; - -struct amdgpu_test_shader memcpy_cs_hang_slow_rv = { - memcpy_cs_hang_slow_rv_codes, - 4, - 3, - 1 -}; - -unsigned int memcpy_cs_hang_slow_nv_codes[] = { - 0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100, - 0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000 -}; - -struct amdgpu_test_shader memcpy_cs_hang_slow_nv = { - memcpy_cs_hang_slow_nv_codes, - 4, - 3, - 1 -}; - -unsigned int memcpy_ps_hang_slow_ai_codes[] = { - 0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000, - 0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00, - 0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000, - 0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f, - 0x03020100, 0xbf810000 -}; - -struct amdgpu_test_shader memcpy_ps_hang_slow_ai = { - memcpy_ps_hang_slow_ai_codes, - 7, - 2, - 9 -}; - -int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size, - unsigned alignment, unsigned heap, uint64_t alloc_flags, - uint64_t mapping_flags, amdgpu_bo_handle *bo, void **cpu, - uint64_t *mc_address, - amdgpu_va_handle *va_handle) -{ - struct amdgpu_bo_alloc_request request = {}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle handle; - uint64_t vmc_addr; - int r; - - request.alloc_size = size; - request.phys_alignment = alignment; - request.preferred_heap = heap; - request.flags = alloc_flags; - - r = amdgpu_bo_alloc(dev, &request, &buf_handle); - if (r) - return r; - - r = amdgpu_va_range_alloc(dev, - amdgpu_gpu_va_range_general, - size, alignment, 0, &vmc_addr, - &handle, 0); - if (r) - goto error_va_alloc; - - r = amdgpu_bo_va_op_raw(dev, buf_handle, 0, ALIGN(size, getpagesize()), vmc_addr, - AMDGPU_VM_PAGE_READABLE | - AMDGPU_VM_PAGE_WRITEABLE | - AMDGPU_VM_PAGE_EXECUTABLE | - mapping_flags, - AMDGPU_VA_OP_MAP); - if (r) - goto error_va_map; - - r = amdgpu_bo_cpu_map(buf_handle, cpu); - if (r) - goto error_cpu_map; - - *bo = buf_handle; - *mc_address = vmc_addr; - *va_handle = handle; - - return 0; - - error_cpu_map: - amdgpu_bo_cpu_unmap(buf_handle); - - error_va_map: - amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); - - error_va_alloc: - amdgpu_bo_free(buf_handle); - return r; -} - - - -CU_BOOL suite_basic_tests_enable(void) -{ - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - - family_id = device_handle->info.family_id; - chip_id = device_handle->info.chip_external_rev; - chip_rev = device_handle->info.chip_rev; - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - /* disable gfx engine basic test cases for some asics have no CPG */ - if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { - if (amdgpu_set_test_active("Basic Tests", - "Command submission Test (GFX)", - CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", - CU_get_error_msg()); - - if (amdgpu_set_test_active("Basic Tests", - "Command submission Test (Multi-Fence)", - CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", - CU_get_error_msg()); - - if (amdgpu_set_test_active("Basic Tests", - "Sync dependency Test", - CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", - CU_get_error_msg()); - } - - return CU_TRUE; -} - -int suite_basic_tests_init(void) -{ - struct amdgpu_gpu_info gpu_info = {0}; - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - if (r) - return CUE_SINIT_FAILED; - - family_id = gpu_info.family_id; - - return CUE_SUCCESS; -} - -int suite_basic_tests_clean(void) -{ - int r = amdgpu_device_deinitialize(device_handle); - - if (r == 0) - return CUE_SUCCESS; - else - return CUE_SCLEAN_FAILED; -} - -static void amdgpu_query_info_test(void) -{ - struct amdgpu_gpu_info gpu_info = {0}; - uint32_t version, feature; - int r; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, - 0, &version, &feature); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_gfx_separate_ibs(void) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; - void *ib_result_cpu, *ib_result_ce_cpu; - uint64_t ib_result_mc_address, ib_result_ce_mc_address; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info[2]; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t *ptr; - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; - int r, i = 0; - struct drm_amdgpu_info_hw_ip info; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); - CU_ASSERT_EQUAL(r, 0); - - if (info.hw_ip_version_major >= 11) - return; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_ce_handle, &ib_result_ce_cpu, - &ib_result_ce_mc_address, &va_handle_ce); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, - ib_result_ce_handle, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; - if (family_id != AMDGPU_FAMILY_SI) { - ptr[i++] = 0xc0008900; - ptr[i++] = 0; - } - ptr[i++] = 0xc0008400; - ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; - ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ - ptr = ib_result_cpu; - ptr[0] = 0xc0008600; - ptr[1] = 0x00000001; - ib_info[1].ib_mc_address = ib_result_mc_address; - ib_info[1].size = 2; - - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.number_of_ibs = 2; - ibs_request.ibs = ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - - CU_ASSERT_EQUAL(r, 0); - - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_GFX; - fence_status.ip_instance = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, - ib_result_ce_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - -} - -static void amdgpu_command_submission_gfx_shared_ib(void) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info[2]; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t *ptr; - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - int r, i = 0; - struct drm_amdgpu_info_hw_ip info; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); - CU_ASSERT_EQUAL(r, 0); - - if (info.hw_ip_version_major >= 11) - return; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_cpu; - if (family_id != AMDGPU_FAMILY_SI) { - ptr[i++] = 0xc0008900; - ptr[i++] = 0; - } - ptr[i++] = 0xc0008400; - ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_mc_address; - ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - ptr = (uint32_t *)ib_result_cpu + 4; - ptr[0] = 0xc0008600; - ptr[1] = 0x00000001; - ib_info[1].ib_mc_address = ib_result_mc_address + 16; - ib_info[1].size = 2; - - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.number_of_ibs = 2; - ibs_request.ibs = ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - - CU_ASSERT_EQUAL(r, 0); - - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_GFX; - fence_status.ip_instance = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_gfx_cp_write_data(void) -{ - amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_GFX); -} - -static void amdgpu_command_submission_gfx_cp_const_fill(void) -{ - amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_GFX); -} - -static void amdgpu_command_submission_gfx_cp_copy_data(void) -{ - amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX); -} - -static void amdgpu_bo_eviction_test(void) -{ - const int sdma_write_length = 1024; - const int pm4_dw = 256; - amdgpu_context_handle context_handle; - amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2]; - amdgpu_bo_handle *resources; - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; - uint64_t bo1_mc, bo2_mc; - volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle bo1_va_handle, bo2_va_handle; - struct amdgpu_heap_info vram_info, gtt_info; - - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - - ib_info = calloc(1, sizeof(*ib_info)); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - - ibs_request = calloc(1, sizeof(*ibs_request)); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - /* prepare resource */ - resources = calloc(4, sizeof(amdgpu_bo_handle)); - CU_ASSERT_NOT_EQUAL(resources, NULL); - - r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM, - 0, &vram_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, - AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_alloc_wrap(device_handle, vram_info.max_allocation, 4096, - AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT, - 0, >t_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[0]); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_alloc_wrap(device_handle, gtt_info.max_allocation, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, >t_max[1]); - CU_ASSERT_EQUAL(r, 0); - - - - loop1 = loop2 = 0; - /* run 9 circle to test all mapping combination */ - while(loop1 < 2) { - while(loop2 < 2) { - /* allocate UC bo1for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop1], &bo1, - (void**)&bo1_cpu, &bo1_mc, - &bo1_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); - - /* allocate UC bo2 for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop2], &bo2, - (void**)&bo2_cpu, &bo2_mc, - &bo2_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); - - resources[0] = bo1; - resources[1] = bo2; - resources[2] = vram_max[loop2]; - resources[3] = gtt_max[loop2]; - - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, - sdma_write_length); - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else - pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } - - amdgpu_test_exec_cs_helper(context_handle, - AMDGPU_HW_IP_DMA, 0, - i, pm4, - 4, resources, - ib_info, ibs_request); - - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); - } - r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop2++; - } - loop2 = 0; - loop1++; - } - amdgpu_bo_free(vram_max[0]); - amdgpu_bo_free(vram_max[1]); - amdgpu_bo_free(gtt_max[0]); - amdgpu_bo_free(gtt_max[1]); - /* clean resources */ - free(resources); - free(ibs_request); - free(ib_info); - free(pm4); - - /* end of test */ - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - - -static void amdgpu_command_submission_gfx(void) -{ - /* write data using the CP */ - amdgpu_command_submission_gfx_cp_write_data(); - /* const fill using the CP */ - amdgpu_command_submission_gfx_cp_const_fill(); - /* copy data using the CP */ - amdgpu_command_submission_gfx_cp_copy_data(); - /* separate IB buffers for multi-IB submission */ - amdgpu_command_submission_gfx_separate_ibs(); - /* shared IB buffer for multi-IB submission */ - amdgpu_command_submission_gfx_shared_ib(); -} - -static void amdgpu_semaphore_test(void) -{ - amdgpu_context_handle context_handle[2]; - amdgpu_semaphore_handle sem; - amdgpu_bo_handle ib_result_handle[2]; - void *ib_result_cpu[2]; - uint64_t ib_result_mc_address[2]; - struct amdgpu_cs_request ibs_request[2] = {0}; - struct amdgpu_cs_ib_info ib_info[2] = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t *ptr; - uint32_t expired; - uint32_t sdma_nop, gfx_nop; - amdgpu_bo_list_handle bo_list[2]; - amdgpu_va_handle va_handle[2]; - int r, i; - struct amdgpu_gpu_info gpu_info = {0}; - unsigned gc_ip_type; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? - AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; - - if (family_id == AMDGPU_FAMILY_SI) { - sdma_nop = SDMA_PACKET_SI(SDMA_NOP_SI, 0, 0, 0, 0); - gfx_nop = GFX_COMPUTE_NOP_SI; - } else { - sdma_nop = SDMA_PKT_HEADER_OP(SDMA_NOP); - gfx_nop = GFX_COMPUTE_NOP; - } - - r = amdgpu_cs_create_semaphore(&sem); - CU_ASSERT_EQUAL(r, 0); - for (i = 0; i < 2; i++) { - r = amdgpu_cs_ctx_create(device_handle, &context_handle[i]); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle[i], &ib_result_cpu[i], - &ib_result_mc_address[i], &va_handle[i]); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle[i], - NULL, &bo_list[i]); - CU_ASSERT_EQUAL(r, 0); - } - - /* 1. same context different engine */ - ptr = ib_result_cpu[0]; - ptr[0] = sdma_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - - ibs_request[0].ip_type = AMDGPU_HW_IP_DMA; - ibs_request[0].number_of_ibs = 1; - ibs_request[0].ibs = &ib_info[0]; - ibs_request[0].resources = bo_list[0]; - ibs_request[0].fence_info.handle = NULL; - r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_signal_semaphore(context_handle[0], AMDGPU_HW_IP_DMA, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_wait_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; - ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - - ibs_request[1].ip_type = gc_ip_type; - ibs_request[1].number_of_ibs = 1; - ibs_request[1].ibs = &ib_info[1]; - ibs_request[1].resources = bo_list[1]; - ibs_request[1].fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[1], 1); - CU_ASSERT_EQUAL(r, 0); - - fence_status.context = context_handle[0]; - fence_status.ip_type = gc_ip_type; - fence_status.ip_instance = 0; - fence_status.fence = ibs_request[1].seq_no; - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - /* 2. same engine different context */ - ptr = ib_result_cpu[0]; - ptr[0] = gfx_nop; - ib_info[0].ib_mc_address = ib_result_mc_address[0]; - ib_info[0].size = 1; - - ibs_request[0].ip_type = gc_ip_type; - ibs_request[0].number_of_ibs = 1; - ibs_request[0].ibs = &ib_info[0]; - ibs_request[0].resources = bo_list[0]; - ibs_request[0].fence_info.handle = NULL; - r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request[0], 1); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_signal_semaphore(context_handle[0], gc_ip_type, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_wait_semaphore(context_handle[1], gc_ip_type, 0, 0, sem); - CU_ASSERT_EQUAL(r, 0); - ptr = ib_result_cpu[1]; - ptr[0] = gfx_nop; - ib_info[1].ib_mc_address = ib_result_mc_address[1]; - ib_info[1].size = 1; - - ibs_request[1].ip_type = gc_ip_type; - ibs_request[1].number_of_ibs = 1; - ibs_request[1].ibs = &ib_info[1]; - ibs_request[1].resources = bo_list[1]; - ibs_request[1].fence_info.handle = NULL; - r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request[1], 1); - - CU_ASSERT_EQUAL(r, 0); - - fence_status.context = context_handle[1]; - fence_status.ip_type = gc_ip_type; - fence_status.ip_instance = 0; - fence_status.fence = ibs_request[1].seq_no; - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - for (i = 0; i < 2; i++) { - r = amdgpu_bo_unmap_and_free(ib_result_handle[i], va_handle[i], - ib_result_mc_address[i], 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list[i]); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle[i]); - CU_ASSERT_EQUAL(r, 0); - } - - r = amdgpu_cs_destroy_semaphore(sem); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_compute_nop(void) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t *ptr; - uint32_t expired; - int r, instance; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - struct drm_amdgpu_info_hw_ip info; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_COMPUTE, 0, &info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - for (instance = 0; (1 << instance) & info.available_rings; instance++) { - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - memset(ptr, 0, 16); - ptr[0]=PACKET3(PACKET3_NOP, 14); - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_COMPUTE; - ibs_request.ring = instance; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_COMPUTE; - fence_status.ip_instance = 0; - fence_status.ring = instance; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - } - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_compute_cp_write_data(void) -{ - amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_COMPUTE); -} - -static void amdgpu_command_submission_compute_cp_const_fill(void) -{ - amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_COMPUTE); -} - -static void amdgpu_command_submission_compute_cp_copy_data(void) -{ - amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_COMPUTE); -} - -static void amdgpu_command_submission_compute(void) -{ - /* write data using the CP */ - amdgpu_command_submission_compute_cp_write_data(); - /* const fill using the CP */ - amdgpu_command_submission_compute_cp_const_fill(); - /* copy data using the CP */ - amdgpu_command_submission_compute_cp_copy_data(); - /* nop test */ - amdgpu_command_submission_compute_nop(); -} - -/* - * caller need create/release: - * pm4_src, resources, ib_info, and ibs_request - * submit command stream described in ibs_request and wait for this IB accomplished - */ -void -amdgpu_test_exec_cs_helper_raw(amdgpu_device_handle device_handle, - amdgpu_context_handle context_handle, - unsigned ip_type, int instance, int pm4_dw, - uint32_t *pm4_src, int res_cnt, - amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request, - bool secure) -{ - int r; - uint32_t expired; - uint32_t *ring_ptr; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_fence fence_status = {0}; - amdgpu_bo_handle *all_res = alloca(sizeof(resources[0]) * (res_cnt + 1)); - amdgpu_va_handle va_handle; - - /* prepare CS */ - CU_ASSERT_NOT_EQUAL(pm4_src, NULL); - CU_ASSERT_NOT_EQUAL(resources, NULL); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - CU_ASSERT_TRUE(pm4_dw <= 1024); - - /* allocate IB */ - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* copy PM4 packet to ring from caller */ - ring_ptr = ib_result_cpu; - memcpy(ring_ptr, pm4_src, pm4_dw * sizeof(*pm4_src)); - - ib_info->ib_mc_address = ib_result_mc_address; - ib_info->size = pm4_dw; - if (secure) - ib_info->flags |= AMDGPU_IB_FLAGS_SECURE; - - ibs_request->ip_type = ip_type; - ibs_request->ring = instance; - ibs_request->number_of_ibs = 1; - ibs_request->ibs = ib_info; - ibs_request->fence_info.handle = NULL; - - memcpy(all_res, resources, sizeof(resources[0]) * res_cnt); - all_res[res_cnt] = ib_result_handle; - - r = amdgpu_bo_list_create(device_handle, res_cnt+1, all_res, - NULL, &ibs_request->resources); - CU_ASSERT_EQUAL(r, 0); - - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - /* submit CS */ - r = amdgpu_cs_submit(context_handle, 0, ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(ibs_request->resources); - CU_ASSERT_EQUAL(r, 0); - - fence_status.ip_type = ip_type; - fence_status.ip_instance = 0; - fence_status.ring = ibs_request->ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request->seq_no; - - /* wait for IB accomplished */ - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); -} - -static void -amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, - unsigned ip_type, int instance, int pm4_dw, - uint32_t *pm4_src, int res_cnt, - amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request) -{ - amdgpu_test_exec_cs_helper_raw(device_handle, context_handle, - ip_type, instance, pm4_dw, pm4_src, - res_cnt, resources, ib_info, - ibs_request, false); -} - -void -amdgpu_command_submission_write_linear_helper_with_secure(amdgpu_device_handle - device, unsigned - ip_type, bool secure) -{ - const int sdma_write_length = 128; - const int pm4_dw = 256; - amdgpu_context_handle context_handle; - amdgpu_bo_handle bo; - amdgpu_bo_handle *resources; - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - uint32_t bo_cpu_origin; - int i, j, r, loop, ring_id; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - struct drm_amdgpu_info_hw_ip hw_ip_info; - - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - - ib_info = calloc(1, sizeof(*ib_info)); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - - ibs_request = calloc(1, sizeof(*ibs_request)); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - r = amdgpu_query_hw_ip_info(device, ip_type, 0, &hw_ip_info); - CU_ASSERT_EQUAL(r, 0); - - for (i = 0; secure && (i < 2); i++) - gtt_flags[i] |= AMDGPU_GEM_CREATE_ENCRYPTED; - - r = amdgpu_cs_ctx_create(device, &context_handle); - - CU_ASSERT_EQUAL(r, 0); - - /* prepare resource */ - resources = calloc(1, sizeof(amdgpu_bo_handle)); - CU_ASSERT_NOT_EQUAL(resources, NULL); - - for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device, - sdma_write_length * sizeof(uint32_t), - 4096, AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); - - resources[0] = bo; - - /* fulfill PM4: test DMA write-linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, - sdma_write_length); - else - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, - secure ? SDMA_ATOMIC_TMZ(1) : 0); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); - pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } - - amdgpu_test_exec_cs_helper_raw(device, context_handle, - ip_type, ring_id, i, pm4, - 1, resources, ib_info, - ibs_request, secure); - - /* verify if SDMA test result meets with expected */ - i = 0; - if (!secure) { - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); - } - } else if (ip_type == AMDGPU_HW_IP_GFX) { - memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); - pm4[i++] = PACKET3(PACKET3_ATOMIC_MEM, 7); - /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN - * command, 1-loop_until_compare_satisfied. - * single_pass_atomic, 0-lru - * engine_sel, 0-micro_engine - */ - pm4[i++] = (TC_OP_ATOMIC_CMPSWAP_RTN_32 | - ATOMIC_MEM_COMMAND(1) | - ATOMIC_MEM_CACHEPOLICAY(0) | - ATOMIC_MEM_ENGINESEL(0)); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0x12345678; - pm4[i++] = 0x0; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0x0; - pm4[i++] = 0x100; - amdgpu_test_exec_cs_helper_raw(device, context_handle, - ip_type, ring_id, i, pm4, - 1, resources, ib_info, - ibs_request, true); - } else if (ip_type == AMDGPU_HW_IP_DMA) { - /* restore the bo_cpu to compare */ - bo_cpu_origin = bo_cpu[0]; - memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); - /* atomic opcode for 32b w/ RTN and ATOMIC_SWAPCMP_RTN - * loop, 1-loop_until_compare_satisfied. - * single_pass_atomic, 0-lru - */ - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC, - 0, - SDMA_ATOMIC_LOOP(1) | - SDMA_ATOMIC_TMZ(1) | - SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32)); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0x12345678; - pm4[i++] = 0x0; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0x0; - pm4[i++] = 0x100; - amdgpu_test_exec_cs_helper_raw(device, context_handle, - ip_type, ring_id, i, pm4, - 1, resources, ib_info, - ibs_request, true); - /* DMA's atomic behavir is unlike GFX - * If the comparing data is not equal to destination data, - * For GFX, loop again till gfx timeout(system hang). - * For DMA, loop again till timer expired and then send interrupt. - * So testcase can't use interrupt mechanism. - * We take another way to verify. When the comparing data is not - * equal to destination data, overwrite the source data to the destination - * buffer. Otherwise, original destination data unchanged. - * So if the bo_cpu data is overwritten, the result is passed. - */ - CU_ASSERT_NOT_EQUAL(bo_cpu[0], bo_cpu_origin); - - /* compare again for the case of dest_data != cmp_data */ - i = 0; - /* restore again, here dest_data should be */ - bo_cpu_origin = bo_cpu[0]; - memset((void*)pm4, 0, pm4_dw * sizeof(uint32_t)); - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_ATOMIC, - 0, - SDMA_ATOMIC_LOOP(1) | - SDMA_ATOMIC_TMZ(1) | - SDMA_ATOMIC_OPCODE(TC_OP_ATOMIC_CMPSWAP_RTN_32)); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0x87654321; - pm4[i++] = 0x0; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0x0; - pm4[i++] = 0x100; - amdgpu_test_exec_cs_helper_raw(device, context_handle, - ip_type, ring_id, i, pm4, - 1, resources, ib_info, - ibs_request, true); - /* here bo_cpu[0] should be unchanged, still is 0x12345678, otherwise failed*/ - CU_ASSERT_EQUAL(bo_cpu[0], bo_cpu_origin); - } - - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length * sizeof(uint32_t)); - CU_ASSERT_EQUAL(r, 0); - loop++; - } - } - /* clean resources */ - free(resources); - free(ibs_request); - free(ib_info); - free(pm4); - - /* end of test */ - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) -{ - amdgpu_command_submission_write_linear_helper_with_secure(device_handle, - ip_type, - false); -} - -static void amdgpu_command_submission_sdma_write_linear(void) -{ - amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA); -} - -static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) -{ - const int sdma_write_length = 1024 * 1024; - const int pm4_dw = 256; - amdgpu_context_handle context_handle; - amdgpu_bo_handle bo; - amdgpu_bo_handle *resources; - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; - uint64_t bo_mc; - volatile uint32_t *bo_cpu; - int i, j, r, loop, ring_id; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle va_handle; - struct drm_amdgpu_info_hw_ip hw_ip_info; - - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - - ib_info = calloc(1, sizeof(*ib_info)); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - - ibs_request = calloc(1, sizeof(*ibs_request)); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - /* prepare resource */ - resources = calloc(1, sizeof(amdgpu_bo_handle)); - CU_ASSERT_NOT_EQUAL(resources, NULL); - - for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length); - - resources[0] = bo; - - /* fulfill PM4: test DMA const fill */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, - 0, 0, 0, - sdma_write_length / 4); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, - SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0xdeadbeaf; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else - pm4[i++] = sdma_write_length; - } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xdeadbeaf; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(2) | - PACKET3_DMA_DATA_SI_CP_SYNC; - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(2) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } - } - - amdgpu_test_exec_cs_helper(context_handle, - ip_type, ring_id, - i, pm4, - 1, resources, - ib_info, ibs_request); - - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < (sdma_write_length / 4)) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); - } - - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop++; - } - } - /* clean resources */ - free(resources); - free(ibs_request); - free(ib_info); - free(pm4); - - /* end of test */ - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_sdma_const_fill(void) -{ - amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_DMA); -} - -static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) -{ - const int sdma_write_length = 1024; - const int pm4_dw = 256; - amdgpu_context_handle context_handle; - amdgpu_bo_handle bo1, bo2; - amdgpu_bo_handle *resources; - uint32_t *pm4; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; - uint64_t bo1_mc, bo2_mc; - volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2, ring_id; - uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; - amdgpu_va_handle bo1_va_handle, bo2_va_handle; - struct drm_amdgpu_info_hw_ip hw_ip_info; - - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - - ib_info = calloc(1, sizeof(*ib_info)); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - - ibs_request = calloc(1, sizeof(*ibs_request)); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - /* prepare resource */ - resources = calloc(2, sizeof(amdgpu_bo_handle)); - CU_ASSERT_NOT_EQUAL(resources, NULL); - - for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { - loop1 = loop2 = 0; - /* run 9 circle to test all mapping combination */ - while(loop1 < 2) { - while(loop2 < 2) { - /* allocate UC bo1for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop1], &bo1, - (void**)&bo1_cpu, &bo1_mc, - &bo1_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); - - /* allocate UC bo2 for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop2], &bo2, - (void**)&bo2_cpu, &bo2_mc, - &bo2_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); - - resources[0] = bo1; - resources[1] = bo2; - - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, - 0, 0, 0, - sdma_write_length); - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, - SDMA_COPY_SUB_OPCODE_LINEAR, - 0); - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else - pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(0) | - PACKET3_DMA_DATA_SI_CP_SYNC | - (0xffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(0) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; - } - } - - amdgpu_test_exec_cs_helper(context_handle, - ip_type, ring_id, - i, pm4, - 2, resources, - ib_info, ibs_request); - - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); - } - r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop2++; - } - loop1++; - } - } - /* clean resources */ - free(resources); - free(ibs_request); - free(ib_info); - free(pm4); - - /* end of test */ - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_sdma_copy_linear(void) -{ - amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_DMA); -} - -static void amdgpu_command_submission_sdma(void) -{ - amdgpu_command_submission_sdma_write_linear(); - amdgpu_command_submission_sdma_const_fill(); - amdgpu_command_submission_sdma_copy_linear(); -} - -static void amdgpu_command_submission_multi_fence_wait_all(bool wait_all) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle, ib_result_ce_handle; - void *ib_result_cpu, *ib_result_ce_cpu; - uint64_t ib_result_mc_address, ib_result_ce_mc_address; - struct amdgpu_cs_request ibs_request[2] = {0}; - struct amdgpu_cs_ib_info ib_info[2]; - struct amdgpu_cs_fence fence_status[2] = {0}; - uint32_t *ptr; - uint32_t expired; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle, va_handle_ce; - int r; - int i = 0, ib_cs_num = 2; - struct drm_amdgpu_info_hw_ip info; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_GFX, 0, &info); - CU_ASSERT_EQUAL(r, 0); - - if (info.hw_ip_version_major >= 11) - return; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_ce_handle, &ib_result_ce_cpu, - &ib_result_ce_mc_address, &va_handle_ce); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, - ib_result_ce_handle, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - memset(ib_info, 0, 2 * sizeof(struct amdgpu_cs_ib_info)); - - /* IT_SET_CE_DE_COUNTERS */ - ptr = ib_result_ce_cpu; - if (family_id != AMDGPU_FAMILY_SI) { - ptr[i++] = 0xc0008900; - ptr[i++] = 0; - } - ptr[i++] = 0xc0008400; - ptr[i++] = 1; - ib_info[0].ib_mc_address = ib_result_ce_mc_address; - ib_info[0].size = i; - ib_info[0].flags = AMDGPU_IB_FLAG_CE; - - /* IT_WAIT_ON_CE_COUNTER */ - ptr = ib_result_cpu; - ptr[0] = 0xc0008600; - ptr[1] = 0x00000001; - ib_info[1].ib_mc_address = ib_result_mc_address; - ib_info[1].size = 2; - - for (i = 0; i < ib_cs_num; i++) { - ibs_request[i].ip_type = AMDGPU_HW_IP_GFX; - ibs_request[i].number_of_ibs = 2; - ibs_request[i].ibs = ib_info; - ibs_request[i].resources = bo_list; - ibs_request[i].fence_info.handle = NULL; - } - - r = amdgpu_cs_submit(context_handle, 0,ibs_request, ib_cs_num); - - CU_ASSERT_EQUAL(r, 0); - - for (i = 0; i < ib_cs_num; i++) { - fence_status[i].context = context_handle; - fence_status[i].ip_type = AMDGPU_HW_IP_GFX; - fence_status[i].fence = ibs_request[i].seq_no; - } - - r = amdgpu_cs_wait_fences(fence_status, ib_cs_num, wait_all, - AMDGPU_TIMEOUT_INFINITE, - &expired, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_ce_handle, va_handle_ce, - ib_result_ce_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_command_submission_multi_fence(void) -{ - amdgpu_command_submission_multi_fence_wait_all(true); - amdgpu_command_submission_multi_fence_wait_all(false); -} - -static void amdgpu_userptr_test(void) -{ - int i, r, j; - uint32_t *pm4 = NULL; - uint64_t bo_mc; - void *ptr = NULL; - int pm4_dw = 256; - int sdma_write_length = 4; - amdgpu_bo_handle handle; - amdgpu_context_handle context_handle; - struct amdgpu_cs_ib_info *ib_info; - struct amdgpu_cs_request *ibs_request; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - - pm4 = calloc(pm4_dw, sizeof(*pm4)); - CU_ASSERT_NOT_EQUAL(pm4, NULL); - - ib_info = calloc(1, sizeof(*ib_info)); - CU_ASSERT_NOT_EQUAL(ib_info, NULL); - - ibs_request = calloc(1, sizeof(*ibs_request)); - CU_ASSERT_NOT_EQUAL(ibs_request, NULL); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - posix_memalign(&ptr, sysconf(_SC_PAGE_SIZE), BUFFER_SIZE); - CU_ASSERT_NOT_EQUAL(ptr, NULL); - memset(ptr, 0, BUFFER_SIZE); - - r = amdgpu_create_bo_from_user_mem(device_handle, - ptr, BUFFER_SIZE, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - BUFFER_SIZE, 1, 0, &bo_mc, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, BUFFER_SIZE, bo_mc, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - handle = buf_handle; - - j = i = 0; - - if (family_id == AMDGPU_FAMILY_SI) - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, - sdma_write_length); - else - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - - while (j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - - if (!fork()) { - pm4[0] = 0x0; - exit(0); - } - - amdgpu_test_exec_cs_helper(context_handle, - AMDGPU_HW_IP_DMA, 0, - i, pm4, - 1, &handle, - ib_info, ibs_request); - i = 0; - while (i < sdma_write_length) { - CU_ASSERT_EQUAL(((int*)ptr)[i++], 0xdeadbeaf); - } - free(ibs_request); - free(ib_info); - free(pm4); - - r = amdgpu_bo_va_op(buf_handle, 0, BUFFER_SIZE, bo_mc, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_va_range_free(va_handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); - free(ptr); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - - wait(NULL); -} - -static void amdgpu_sync_dependency_test(void) -{ - amdgpu_context_handle context_handle[2]; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t expired; - int i, j, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - static uint32_t *ptr; - uint64_t seq_no; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle[0]); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_ctx_create(device_handle, &context_handle[1]); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 8192, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - i = 0; - - memcpy(ptr + CODE_OFFSET , shader_bin, sizeof(shader_bin)); - - /* Dispatch minimal init config and verify it's executed */ - ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1); - ptr[i++] = 0x80000000; - ptr[i++] = 0x80000000; - - ptr[i++] = PACKET3(PKT3_CLEAR_STATE, 0); - ptr[i++] = 0x80000000; - - - /* Program compute regs */ - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); - ptr[i++] = mmCOMPUTE_PGM_LO - PACKET3_SET_SH_REG_START; - ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 8; - ptr[i++] = (ib_result_mc_address + CODE_OFFSET * 4) >> 40; - - - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); - ptr[i++] = mmCOMPUTE_PGM_RSRC1 - PACKET3_SET_SH_REG_START; - /* - * 002c0040 COMPUTE_PGM_RSRC1 <- VGPRS = 0 - SGPRS = 1 - PRIORITY = 0 - FLOAT_MODE = 192 (0xc0) - PRIV = 0 - DX10_CLAMP = 1 - DEBUG_MODE = 0 - IEEE_MODE = 0 - BULKY = 0 - CDBG_USER = 0 - * - */ - ptr[i++] = 0x002c0040; - - - /* - * 00000010 COMPUTE_PGM_RSRC2 <- SCRATCH_EN = 0 - USER_SGPR = 8 - TRAP_PRESENT = 0 - TGID_X_EN = 0 - TGID_Y_EN = 0 - TGID_Z_EN = 0 - TG_SIZE_EN = 0 - TIDIG_COMP_CNT = 0 - EXCP_EN_MSB = 0 - LDS_SIZE = 0 - EXCP_EN = 0 - * - */ - ptr[i++] = 0x00000010; - - -/* - * 00000100 COMPUTE_TMPRING_SIZE <- WAVES = 256 (0x100) - WAVESIZE = 0 - * - */ - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); - ptr[i++] = mmCOMPUTE_TMPRING_SIZE - PACKET3_SET_SH_REG_START; - ptr[i++] = 0x00000100; - - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 2); - ptr[i++] = mmCOMPUTE_USER_DATA_0 - PACKET3_SET_SH_REG_START; - ptr[i++] = 0xffffffff & (ib_result_mc_address + DATA_OFFSET * 4); - ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32; - - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 1); - ptr[i++] = mmCOMPUTE_RESOURCE_LIMITS - PACKET3_SET_SH_REG_START; - ptr[i++] = 0; - - ptr[i++] = PACKET3(PKT3_SET_SH_REG, 3); - ptr[i++] = mmCOMPUTE_NUM_THREAD_X - PACKET3_SET_SH_REG_START; - ptr[i++] = 1; - ptr[i++] = 1; - ptr[i++] = 1; - - - /* Dispatch */ - ptr[i++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); - ptr[i++] = 1; - ptr[i++] = 1; - ptr[i++] = 1; - ptr[i++] = 0x00000045; /* DISPATCH DIRECT field */ - - - while (i & 7) - ptr[i++] = 0xffff1000; /* type3 nop packet */ - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = i; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle[1], 0,&ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - seq_no = ibs_request.seq_no; - - - - /* Prepare second command with dependency on the first */ - j = i; - ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); - ptr[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - ptr[i++] = 0xfffffffc & (ib_result_mc_address + DATA_OFFSET * 4); - ptr[i++] = (0xffffffff00000000 & (ib_result_mc_address + DATA_OFFSET * 4)) >> 32; - ptr[i++] = 99; - - while (i & 7) - ptr[i++] = 0xffff1000; /* type3 nop packet */ - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address + j * 4; - ib_info.size = i - j; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - ibs_request.number_of_dependencies = 1; - - ibs_request.dependencies = calloc(1, sizeof(*ibs_request.dependencies)); - ibs_request.dependencies[0].context = context_handle[1]; - ibs_request.dependencies[0].ip_instance = 0; - ibs_request.dependencies[0].ring = 0; - ibs_request.dependencies[0].fence = seq_no; - - - r = amdgpu_cs_submit(context_handle[0], 0,&ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle[0]; - fence_status.ip_type = AMDGPU_HW_IP_GFX; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL(r, 0); - - /* Expect the second command to wait for shader to complete */ - CU_ASSERT_EQUAL(ptr[DATA_OFFSET], 99); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle[0]); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_ctx_free(context_handle[1]); - CU_ASSERT_EQUAL(r, 0); - - free(ibs_request.dependencies); -} - -static void amdgpu_compute_dispatch_test(void) -{ - amdgpu_test_dispatch_helper(device_handle, AMDGPU_HW_IP_COMPUTE); -} -static void amdgpu_gfx_dispatch_test(void) -{ - amdgpu_test_dispatch_helper(device_handle, AMDGPU_HW_IP_GFX); -} - -static void amdgpu_draw_test(void) -{ - amdgpu_test_draw_helper(device_handle); -} -static void amdgpu_gpu_reset_test(void) -{ - int r; - char debugfs_path[256], tmp[10]; - int fd; - struct stat sbuf; - amdgpu_context_handle context_handle; - uint32_t hang_state, hangs; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = fstat(drm_amdgpu[0], &sbuf); - CU_ASSERT_EQUAL(r, 0); - - sprintf(debugfs_path, "/sys/kernel/debug/dri/%d/amdgpu_gpu_recover", minor(sbuf.st_rdev)); - fd = open(debugfs_path, O_RDONLY); - CU_ASSERT(fd >= 0); - - r = read(fd, tmp, sizeof(tmp)/sizeof(char)); - CU_ASSERT(r > 0); - - r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); - - close(fd); - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - - amdgpu_compute_dispatch_test(); - amdgpu_gfx_dispatch_test(); -} - -static void amdgpu_stable_pstate_test(void) -{ - int r; - amdgpu_context_handle context_handle; - uint32_t current_pstate = 0, new_pstate = 0; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_stable_pstate(context_handle, - AMDGPU_CTX_OP_GET_STABLE_PSTATE, - 0, ¤t_pstate); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_NONE); - - r = amdgpu_cs_ctx_stable_pstate(context_handle, - AMDGPU_CTX_OP_SET_STABLE_PSTATE, - AMDGPU_CTX_STABLE_PSTATE_PEAK, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_stable_pstate(context_handle, - AMDGPU_CTX_OP_GET_STABLE_PSTATE, - 0, &new_pstate); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(new_pstate, AMDGPU_CTX_STABLE_PSTATE_PEAK); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} diff --git a/tests/amdgpu/bo_tests.c b/tests/amdgpu/bo_tests.c deleted file mode 100644 index 8fc7fe26c..000000000 --- a/tests/amdgpu/bo_tests.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#define BUFFER_SIZE (4*1024) -#define BUFFER_ALIGN (4*1024) - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; - -static amdgpu_bo_handle buffer_handle; -static uint64_t virtual_mc_base_address; -static amdgpu_va_handle va_handle; - -static void amdgpu_bo_export_import(void); -static void amdgpu_bo_metadata(void); -static void amdgpu_bo_map_unmap(void); -static void amdgpu_memory_alloc(void); -static void amdgpu_mem_fail_alloc(void); -static void amdgpu_bo_find_by_cpu_mapping(void); - -CU_TestInfo bo_tests[] = { - { "Export/Import", amdgpu_bo_export_import }, - { "Metadata", amdgpu_bo_metadata }, - { "CPU map/unmap", amdgpu_bo_map_unmap }, - { "Memory alloc Test", amdgpu_memory_alloc }, - { "Memory fail alloc Test", amdgpu_mem_fail_alloc }, - { "Find bo by CPU mapping", amdgpu_bo_find_by_cpu_mapping }, - CU_TEST_INFO_NULL, -}; - -int suite_bo_tests_init(void) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - uint64_t va; - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - - return CUE_SINIT_FAILED; - } - - req.alloc_size = BUFFER_SIZE; - req.phys_alignment = BUFFER_ALIGN; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - BUFFER_SIZE, BUFFER_ALIGN, 0, - &va, &va_handle, 0); - if (r) - goto error_va_alloc; - - r = amdgpu_bo_va_op(buf_handle, 0, BUFFER_SIZE, va, 0, AMDGPU_VA_OP_MAP); - if (r) - goto error_va_map; - - buffer_handle = buf_handle; - virtual_mc_base_address = va; - - return CUE_SUCCESS; - -error_va_map: - amdgpu_va_range_free(va_handle); - -error_va_alloc: - amdgpu_bo_free(buf_handle); - return CUE_SINIT_FAILED; -} - -int suite_bo_tests_clean(void) -{ - int r; - - r = amdgpu_bo_va_op(buffer_handle, 0, BUFFER_SIZE, - virtual_mc_base_address, 0, - AMDGPU_VA_OP_UNMAP); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_va_range_free(va_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_bo_free(buffer_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static void amdgpu_bo_export_import_do_type(enum amdgpu_bo_handle_type type) -{ - struct amdgpu_bo_import_result res = {0}; - uint32_t shared_handle; - int r; - - r = amdgpu_bo_export(buffer_handle, type, &shared_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_import(device_handle, type, shared_handle, &res); - CU_ASSERT_EQUAL(r, 0); - - CU_ASSERT_EQUAL(res.buf_handle, buffer_handle); - CU_ASSERT_EQUAL(res.alloc_size, BUFFER_SIZE); - - r = amdgpu_bo_free(res.buf_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_bo_export_import(void) -{ - if (open_render_node) { - printf("(DRM render node is used. Skip export/Import test) "); - return; - } - - amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_gem_flink_name); - amdgpu_bo_export_import_do_type(amdgpu_bo_handle_type_dma_buf_fd); -} - -static void amdgpu_bo_metadata(void) -{ - struct amdgpu_bo_metadata meta = {0}; - struct amdgpu_bo_info info = {0}; - int r; - - meta.size_metadata = 4; - meta.umd_metadata[0] = 0xdeadbeef; - - r = amdgpu_bo_set_metadata(buffer_handle, &meta); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_query_info(buffer_handle, &info); - CU_ASSERT_EQUAL(r, 0); - - CU_ASSERT_EQUAL(info.metadata.size_metadata, 4); - CU_ASSERT_EQUAL(info.metadata.umd_metadata[0], 0xdeadbeef); -} - -static void amdgpu_bo_map_unmap(void) -{ - uint32_t *ptr; - int i, r; - - r = amdgpu_bo_cpu_map(buffer_handle, (void **)&ptr); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_NOT_EQUAL(ptr, NULL); - - for (i = 0; i < (BUFFER_SIZE / 4); ++i) - ptr[i] = 0xdeadbeef; - - r = amdgpu_bo_cpu_unmap(buffer_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_memory_alloc(void) -{ - amdgpu_bo_handle bo; - amdgpu_va_handle va_handle; - uint64_t bo_mc; - int r; - - /* Test visible VRAM */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test invisible VRAM */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_NO_CPU_ACCESS, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GART Cacheable */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - 0, &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GART USWC */ - bo = gpu_mem_alloc(device_handle, - 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_CPU_GTT_USWC, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GDS */ - bo = gpu_mem_alloc(device_handle, 1024, 0, - AMDGPU_GEM_DOMAIN_GDS, 0, - NULL, NULL); - r = gpu_mem_free(bo, NULL, 0, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test GWS */ - bo = gpu_mem_alloc(device_handle, 1, 0, - AMDGPU_GEM_DOMAIN_GWS, 0, - NULL, NULL); - r = gpu_mem_free(bo, NULL, 0, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test OA */ - bo = gpu_mem_alloc(device_handle, 1, 0, - AMDGPU_GEM_DOMAIN_OA, 0, - NULL, NULL); - r = gpu_mem_free(bo, NULL, 0, 4096); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_mem_fail_alloc(void) -{ - int r; - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - - /* Test impossible mem allocation, 1TB */ - req.alloc_size = 0xE8D4A51000; - req.phys_alignment = 4096; - req.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; - req.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, -ENOMEM); - - if (!r) { - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); - } -} - -static void amdgpu_bo_find_by_cpu_mapping(void) -{ - amdgpu_bo_handle bo_handle, find_bo_handle; - amdgpu_va_handle va_handle; - void *bo_cpu; - uint64_t bo_mc_address; - uint64_t offset; - int r; - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &bo_handle, &bo_cpu, - &bo_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_find_bo_by_cpu_mapping(device_handle, - bo_cpu, - 4096, - &find_bo_handle, - &offset); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(offset, 0); - CU_ASSERT_EQUAL(bo_handle->handle, find_bo_handle->handle); - - atomic_dec(&find_bo_handle->refcount, 1); - r = amdgpu_bo_unmap_and_free(bo_handle, va_handle, - bo_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); -} diff --git a/tests/amdgpu/cp_dma_tests.c b/tests/amdgpu/cp_dma_tests.c deleted file mode 100755 index e82214fed..000000000 --- a/tests/amdgpu/cp_dma_tests.c +++ /dev/null @@ -1,533 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#define IB_SIZE 4096 -#define MAX_RESOURCES 8 - -#define DMA_SIZE 4097 -#define DMA_DATA_BYTE 0xea - -static bool do_p2p; - -static amdgpu_device_handle executing_device_handle; -static uint32_t executing_device_major_version; -static uint32_t executing_device_minor_version; - -static amdgpu_device_handle peer_exporting_device_handle; -static uint32_t peer_exporting_device_major_version; -static uint32_t peer_exporting_device_minor_version; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static uint32_t *ib_cpu; -static uint64_t ib_mc_address; -static amdgpu_va_handle ib_va_handle; -static uint32_t num_dword; - -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; - -static uint8_t* reference_data; - -static void amdgpu_cp_dma_host_to_vram(void); -static void amdgpu_cp_dma_vram_to_host(void); -static void amdgpu_cp_dma_p2p_vram_to_vram(void); -static void amdgpu_cp_dma_p2p_host_to_vram(void); -static void amdgpu_cp_dma_p2p_vram_to_host(void); - -/** - * Tests in cp dma test suite - */ -CU_TestInfo cp_dma_tests[] = { - { "CP DMA write Host to VRAM", amdgpu_cp_dma_host_to_vram }, - { "CP DMA write VRAM to Host", amdgpu_cp_dma_vram_to_host }, - - { "Peer to Peer CP DMA write VRAM to VRAM", amdgpu_cp_dma_p2p_vram_to_vram }, - { "Peer to Peer CP DMA write Host to VRAM", amdgpu_cp_dma_p2p_host_to_vram }, - { "Peer to Peer CP DMA write VRAM to Host", amdgpu_cp_dma_p2p_vram_to_host }, - CU_TEST_INFO_NULL, -}; - -struct amdgpu_cp_dma_bo{ - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t gpu_va; - uint64_t size; -}; - -static int allocate_bo_and_va(amdgpu_device_handle dev, - uint64_t size, uint64_t alignment, - uint32_t heap, uint64_t alloc_flags, - struct amdgpu_cp_dma_bo *bo) { - struct amdgpu_bo_alloc_request request = {}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t vmc_addr; - int r; - - request.alloc_size = size; - request.phys_alignment = alignment; - request.preferred_heap = heap; - request.flags = alloc_flags; - - r = amdgpu_bo_alloc(dev, &request, &buf_handle); - if (r) - goto error_bo_alloc; - - r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general, - size, alignment, 0, - &vmc_addr, &va_handle, 0); - if (r) - goto error_va_alloc; - - r = amdgpu_bo_va_op(buf_handle, 0, size, vmc_addr, - AMDGPU_VM_PAGE_READABLE | - AMDGPU_VM_PAGE_WRITEABLE | - AMDGPU_VM_PAGE_EXECUTABLE, - AMDGPU_VA_OP_MAP); - if (r) - goto error_va_map; - - bo->buf_handle = buf_handle; - bo->va_handle = va_handle; - bo->gpu_va = vmc_addr; - bo->size = size; - - return 0; - -error_va_map: - amdgpu_bo_va_op(buf_handle, 0, - size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); - -error_va_alloc: - amdgpu_va_range_free(va_handle); - -error_bo_alloc: - amdgpu_bo_free(buf_handle); - - return r; -} - -static int import_dma_buf_to_bo(amdgpu_device_handle dev, - int dmabuf_fd, struct amdgpu_cp_dma_bo *bo) { - amdgpu_va_handle va_handle; - uint64_t vmc_addr; - int r; - struct amdgpu_bo_import_result bo_import_result = {}; - - r = amdgpu_bo_import(dev, amdgpu_bo_handle_type_dma_buf_fd, - dmabuf_fd, &bo_import_result); - if (r) - goto error_bo_import; - - r = amdgpu_va_range_alloc(dev, amdgpu_gpu_va_range_general, - bo_import_result.alloc_size, 0, 0, - &vmc_addr, &va_handle, 0); - if (r) - goto error_va_alloc; - - r = amdgpu_bo_va_op(bo_import_result.buf_handle, 0, - bo_import_result.alloc_size, vmc_addr, - AMDGPU_VM_PAGE_READABLE | - AMDGPU_VM_PAGE_WRITEABLE | - AMDGPU_VM_PAGE_EXECUTABLE, - AMDGPU_VA_OP_MAP); - if (r) - goto error_va_map; - - bo->buf_handle = bo_import_result.buf_handle; - bo->va_handle = va_handle; - bo->gpu_va = vmc_addr; - bo->size = bo_import_result.alloc_size; - - return 0; - -error_va_map: - amdgpu_bo_va_op(bo_import_result.buf_handle, 0, - bo_import_result.alloc_size, vmc_addr, 0, AMDGPU_VA_OP_UNMAP); - -error_va_alloc: - amdgpu_va_range_free(va_handle); - -error_bo_import: - amdgpu_bo_free(bo_import_result.buf_handle); - - return r; -} - -static int free_bo(struct amdgpu_cp_dma_bo bo) { - int r; - r = amdgpu_bo_va_op(bo.buf_handle, 0, - bo.size, bo.gpu_va, 0, AMDGPU_VA_OP_UNMAP); - if(r) - return r; - - r = amdgpu_va_range_free(bo.va_handle); - if(r) - return r; - - r = amdgpu_bo_free(bo.buf_handle); - if(r) - return r; - - return 0; -} - -static int submit_and_sync() { - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - uint32_t family_id, chip_id, chip_rev; - unsigned gc_ip_type; - int r; - - r = amdgpu_bo_list_create(executing_device_handle, - num_resources, resources, - NULL, &ibs_request.resources); - if (r) - return r; - - family_id = executing_device_handle->info.family_id; - chip_id = executing_device_handle->info.chip_external_rev; - chip_rev = executing_device_handle->info.chip_rev; - - gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? - AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = num_dword; - - ibs_request.ip_type = gc_ip_type; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = gc_ip_type; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - return 0; -} - -static void cp_dma_cmd(struct amdgpu_cp_dma_bo src_bo, - struct amdgpu_cp_dma_bo dst_bo) { - _Static_assert(DMA_SIZE < (1 << 26), "DMA size exceeds CP DMA maximium!"); - - ib_cpu[0] = 0xc0055000; - ib_cpu[1] = 0x80000000; - ib_cpu[2] = src_bo.gpu_va & 0x00000000ffffffff; - ib_cpu[3] = (src_bo.gpu_va & 0xffffffff00000000) >> 32; - ib_cpu[4] = dst_bo.gpu_va & 0x00000000ffffffff; - ib_cpu[5] = (dst_bo.gpu_va & 0xffffffff00000000) >> 32; - // size is read from the lower 26bits. - ib_cpu[6] = ((1 << 26) - 1) & DMA_SIZE; - ib_cpu[7] = 0xffff1000; - - num_dword = 8; - - resources[0] = src_bo.buf_handle; - resources[1] = dst_bo.buf_handle; - resources[2] = ib_handle; - num_resources = 3; -} - -static void amdgpu_cp_dma(uint32_t src_heap, uint32_t dst_heap) { - int r; - struct amdgpu_cp_dma_bo src_bo = {0}; - struct amdgpu_cp_dma_bo dst_bo = {0}; - void *src_bo_cpu; - void *dst_bo_cpu; - - /* allocate the src bo, set its data to DMA_DATA_BYTE */ - r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096, - src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu); - CU_ASSERT_EQUAL(r, 0); - memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE); - - r = amdgpu_bo_cpu_unmap(src_bo.buf_handle); - CU_ASSERT_EQUAL(r, 0); - - /* allocate the dst bo and clear its content to all 0 */ - r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096, - dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &dst_bo); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(dst_bo.buf_handle, (void **)&dst_bo_cpu); - CU_ASSERT_EQUAL(r, 0); - - _Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!"); - memset(dst_bo_cpu, 0, DMA_SIZE); - - /* record CP DMA command and dispatch the command */ - cp_dma_cmd(src_bo, dst_bo); - - r = submit_and_sync(); - CU_ASSERT_EQUAL(r, 0); - - /* verify the dst bo is filled with DMA_DATA_BYTE */ - CU_ASSERT_EQUAL(memcmp(dst_bo_cpu, reference_data, DMA_SIZE) == 0, true); - - r = amdgpu_bo_cpu_unmap(dst_bo.buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = free_bo(src_bo); - CU_ASSERT_EQUAL(r, 0); - - r = free_bo(dst_bo); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cp_dma_p2p(uint32_t src_heap, uint32_t dst_heap) { - int r; - struct amdgpu_cp_dma_bo exported_bo = {0}; - int dma_buf_fd; - int dma_buf_fd_dup; - struct amdgpu_cp_dma_bo src_bo = {0}; - struct amdgpu_cp_dma_bo imported_dst_bo = {0}; - void *exported_bo_cpu; - void *src_bo_cpu; - - /* allocate a bo on the peer device and export it to dma-buf */ - r = allocate_bo_and_va(peer_exporting_device_handle, DMA_SIZE, 4096, - src_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &exported_bo); - CU_ASSERT_EQUAL(r, 0); - - /* map the exported bo and clear its content to 0 */ - _Static_assert(DMA_DATA_BYTE != 0, "Initialization data should be different from DMA data!"); - r = amdgpu_bo_cpu_map(exported_bo.buf_handle, (void **)&exported_bo_cpu); - CU_ASSERT_EQUAL(r, 0); - memset(exported_bo_cpu, 0, DMA_SIZE); - - r = amdgpu_bo_export(exported_bo.buf_handle, - amdgpu_bo_handle_type_dma_buf_fd, (uint32_t*)&dma_buf_fd); - CU_ASSERT_EQUAL(r, 0); - - // According to amdgpu_drm: - // "Buffer must be "imported" only using new "fd" - // (different from one used by "exporter")" - dma_buf_fd_dup = dup(dma_buf_fd); - r = close(dma_buf_fd); - CU_ASSERT_EQUAL(r, 0); - - /* import the dma-buf to the executing device, imported bo is the DMA destination */ - r = import_dma_buf_to_bo( - executing_device_handle, dma_buf_fd_dup, &imported_dst_bo); - CU_ASSERT_EQUAL(r, 0); - - r = close(dma_buf_fd_dup); - CU_ASSERT_EQUAL(r, 0); - - /* allocate the src bo and set its content to DMA_DATA_BYTE */ - r = allocate_bo_and_va(executing_device_handle, DMA_SIZE, 4096, - dst_heap, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, &src_bo); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(src_bo.buf_handle, (void **)&src_bo_cpu); - CU_ASSERT_EQUAL(r, 0); - - memset(src_bo_cpu, DMA_DATA_BYTE, DMA_SIZE); - - r = amdgpu_bo_cpu_unmap(src_bo.buf_handle); - CU_ASSERT_EQUAL(r, 0); - - /* record CP DMA command and dispatch the command */ - cp_dma_cmd(src_bo, imported_dst_bo); - - r = submit_and_sync(); - CU_ASSERT_EQUAL(r, 0); - - /* verify the bo from the peer device is filled with DMA_DATA_BYTE */ - CU_ASSERT_EQUAL(memcmp(exported_bo_cpu, reference_data, DMA_SIZE) == 0, true); - - r = amdgpu_bo_cpu_unmap(exported_bo.buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = free_bo(exported_bo); - CU_ASSERT_EQUAL(r, 0); - - r = free_bo(imported_dst_bo); - CU_ASSERT_EQUAL(r, 0); - - r = free_bo(src_bo); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cp_dma_host_to_vram(void) { - amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM); -} - -static void amdgpu_cp_dma_vram_to_host(void) { - amdgpu_cp_dma(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT); -} - -static void amdgpu_cp_dma_p2p_vram_to_vram(void) { - amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_VRAM); -} - -static void amdgpu_cp_dma_p2p_host_to_vram(void) { - amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_GTT, AMDGPU_GEM_DOMAIN_VRAM); -} - -static void amdgpu_cp_dma_p2p_vram_to_host(void) { - amdgpu_cp_dma_p2p(AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_DOMAIN_GTT); -} - -int suite_cp_dma_tests_init() { - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], - &executing_device_major_version, - &executing_device_minor_version, - &executing_device_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_cs_ctx_create(executing_device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(executing_device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_handle, (void**)&ib_cpu, - &ib_mc_address, &ib_va_handle); - if (r) - return CUE_SINIT_FAILED; - - if (do_p2p) { - r = amdgpu_device_initialize(drm_amdgpu[1], - &peer_exporting_device_major_version, - &peer_exporting_device_minor_version, - &peer_exporting_device_handle); - - if (r) - return CUE_SINIT_FAILED; - } - - reference_data = (uint8_t*)malloc(DMA_SIZE); - if (!reference_data) - return CUE_SINIT_FAILED; - memset(reference_data, DMA_DATA_BYTE, DMA_SIZE); - - return CUE_SUCCESS; -} - -int suite_cp_dma_tests_clean() { - int r; - - free(reference_data); - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(executing_device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - if (do_p2p) { - r = amdgpu_device_deinitialize(peer_exporting_device_handle); - if (r) - return CUE_SCLEAN_FAILED; - } - - return CUE_SUCCESS; -} - -CU_BOOL suite_cp_dma_tests_enable(void) { - int r = 0; - - if (amdgpu_device_initialize(drm_amdgpu[0], - &executing_device_major_version, - &executing_device_minor_version, - &executing_device_handle)) - return CU_FALSE; - - if (!(executing_device_handle->info.family_id >= AMDGPU_FAMILY_AI && - executing_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) { - printf("Testing device has ASIC that is not supported by CP-DMA test suite!\n"); - return CU_FALSE; - } - - if (amdgpu_device_deinitialize(executing_device_handle)) - return CU_FALSE; - - if (drm_amdgpu[1] >= 0) { - r = amdgpu_device_initialize(drm_amdgpu[1], - &peer_exporting_device_major_version, - &peer_exporting_device_minor_version, - &peer_exporting_device_handle); - - if (r == 0 && (peer_exporting_device_handle->info.family_id >= AMDGPU_FAMILY_AI && - peer_exporting_device_handle->info.family_id <= AMDGPU_FAMILY_NV)) { - do_p2p = true; - } - - if (r == 0 && amdgpu_device_deinitialize(peer_exporting_device_handle) != 0) { - printf("Deinitialize peer_exporting_device_handle failed!\n"); - return CU_FALSE; - } - } - - if (!do_p2p) { - amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to VRAM", CU_FALSE); - amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write Host to VRAM", CU_FALSE); - amdgpu_set_test_active("CP DMA Tests", "Peer to Peer CP DMA write VRAM to Host", CU_FALSE); - printf("Peer device is not opened or has ASIC not supported by the suite, skip all Peer to Peer tests.\n"); - } - - return CU_TRUE; -} diff --git a/tests/amdgpu/cs_tests.c b/tests/amdgpu/cs_tests.c deleted file mode 100644 index f5096781e..000000000 --- a/tests/amdgpu/cs_tests.c +++ /dev/null @@ -1,471 +0,0 @@ -/* - * Copyright 2014 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include - -#include "CUnit/Basic.h" - -#include "util_math.h" - -#include "amdgpu_test.h" -#include "decode_messages.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#define IB_SIZE 4096 -#define MAX_RESOURCES 16 - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t chip_rev; -static uint32_t chip_id; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static uint64_t ib_mc_address; -static uint32_t *ib_cpu; -static amdgpu_va_handle ib_va_handle; - -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; - -static void amdgpu_cs_uvd_create(void); -static void amdgpu_cs_uvd_decode(void); -static void amdgpu_cs_uvd_destroy(void); - -CU_TestInfo cs_tests[] = { - { "UVD create", amdgpu_cs_uvd_create }, - { "UVD decode", amdgpu_cs_uvd_decode }, - { "UVD destroy", amdgpu_cs_uvd_destroy }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_cs_tests_enable(void) -{ - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - family_id = device_handle->info.family_id; - chip_id = device_handle->info.chip_external_rev; - chip_rev = device_handle->info.chip_rev; - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { - printf("\n\nThe ASIC NOT support UVD, suite disabled\n"); - return CU_FALSE; - } - - return CU_TRUE; -} - -int suite_cs_tests_init(void) -{ - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - amdgpu_va_handle ib_result_va_handle; - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - - return CUE_SINIT_FAILED; - } - - family_id = device_handle->info.family_id; - /* VI asic POLARIS10/11 have specific external_rev_id */ - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, - &ib_result_va_handle); - if (r) - return CUE_SINIT_FAILED; - - ib_handle = ib_result_handle; - ib_mc_address = ib_result_mc_address; - ib_cpu = ib_result_cpu; - ib_va_handle = ib_result_va_handle; - - return CUE_SUCCESS; -} - -int suite_cs_tests_clean(void) -{ - int r; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static int submit(unsigned ndw, unsigned ip) -{ - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - int r; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = ndw; - - ibs_request.ip_type = ip; - - r = amdgpu_bo_list_create(device_handle, num_resources, resources, - NULL, &ibs_request.resources); - if (r) - return r; - - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = ip; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - return 0; -} - -static void uvd_cmd(uint64_t addr, unsigned cmd, int *idx) -{ - ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC4 : 0x81C4; - ib_cpu[(*idx)++] = addr; - ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC5 : 0x81C5; - ib_cpu[(*idx)++] = addr >> 32; - ib_cpu[(*idx)++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC3 : 0x81C3; - ib_cpu[(*idx)++] = cmd << 1; -} - -static void amdgpu_cs_uvd_create(void) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - uint64_t va = 0; - amdgpu_va_handle va_handle; - void *msg; - int i, r; - - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - 4096, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(buf_handle, &msg); - CU_ASSERT_EQUAL(r, 0); - - memcpy(msg, uvd_create_msg, sizeof(uvd_create_msg)); - - if (family_id >= AMDGPU_FAMILY_VI) { - ((uint8_t*)msg)[0x10] = 7; - /* chip beyond polaris 10/11 */ - if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || - chip_id == chip_rev+0x64)) { - /* dpb size */ - ((uint8_t*)msg)[0x28] = 0x00; - ((uint8_t*)msg)[0x29] = 0x94; - ((uint8_t*)msg)[0x2A] = 0x6B; - ((uint8_t*)msg)[0x2B] = 0x00; - } - } - - r = amdgpu_bo_cpu_unmap(buf_handle); - CU_ASSERT_EQUAL(r, 0); - - num_resources = 0; - resources[num_resources++] = buf_handle; - resources[num_resources++] = ib_handle; - - i = 0; - uvd_cmd(va, 0x0, &i); - for (; i % 16; ++i) - ib_cpu[i] = 0x80000000; - - r = submit(i, AMDGPU_HW_IP_UVD); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, 4096, va, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_uvd_decode(void) -{ - const unsigned dpb_size = 15923584, dt_size = 737280; - uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr; - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - uint64_t sum; - uint8_t *ptr; - int i, r; - - req.alloc_size = 4*1024; /* msg */ - req.alloc_size += 4*1024; /* fb */ - if (family_id >= AMDGPU_FAMILY_VI) - req.alloc_size += 4096; /*it_scaling_table*/ - req.alloc_size += ALIGN(sizeof(uvd_bitstream), 4*1024); - req.alloc_size += ALIGN(dpb_size, 4*1024); - req.alloc_size += ALIGN(dt_size, 4*1024); - - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(buf_handle, (void **)&ptr); - CU_ASSERT_EQUAL(r, 0); - - memcpy(ptr, uvd_decode_msg, sizeof(uvd_decode_msg)); - memcpy(ptr + sizeof(uvd_decode_msg), avc_decode_msg, sizeof(avc_decode_msg)); - - if (family_id >= AMDGPU_FAMILY_VI) { - ptr[0x10] = 7; - ptr[0x98] = 0x00; - ptr[0x99] = 0x02; - /* chip beyond polaris10/11 */ - if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || - chip_id == chip_rev+0x64)) { - /* dpb size */ - ptr[0x24] = 0x00; - ptr[0x25] = 0x94; - ptr[0x26] = 0x6B; - ptr[0x27] = 0x00; - /*ctx size */ - ptr[0x2C] = 0x00; - ptr[0x2D] = 0xAF; - ptr[0x2E] = 0x50; - ptr[0x2F] = 0x00; - } - } - - ptr += 4*1024; - memset(ptr, 0, 4*1024); - if (family_id >= AMDGPU_FAMILY_VI) { - ptr += 4*1024; - memcpy(ptr, uvd_it_scaling_table, sizeof(uvd_it_scaling_table)); - } - - ptr += 4*1024; - memcpy(ptr, uvd_bitstream, sizeof(uvd_bitstream)); - - ptr += ALIGN(sizeof(uvd_bitstream), 4*1024); - memset(ptr, 0, dpb_size); - - ptr += ALIGN(dpb_size, 4*1024); - memset(ptr, 0, dt_size); - - num_resources = 0; - resources[num_resources++] = buf_handle; - resources[num_resources++] = ib_handle; - - msg_addr = va; - fb_addr = msg_addr + 4*1024; - if (family_id >= AMDGPU_FAMILY_VI) { - it_addr = fb_addr + 4*1024; - bs_addr = it_addr + 4*1024; - } else - bs_addr = fb_addr + 4*1024; - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); - - ctx_addr = 0; - if (family_id >= AMDGPU_FAMILY_VI) { - if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || - chip_id == chip_rev+0x64)) { - ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); - } - } - - dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); - - i = 0; - uvd_cmd(msg_addr, 0x0, &i); - uvd_cmd(dpb_addr, 0x1, &i); - uvd_cmd(dt_addr, 0x2, &i); - uvd_cmd(fb_addr, 0x3, &i); - uvd_cmd(bs_addr, 0x100, &i); - - if (family_id >= AMDGPU_FAMILY_VI) { - uvd_cmd(it_addr, 0x204, &i); - if ((family_id == AMDGPU_FAMILY_AI) || - (chip_id == chip_rev+0x50 || chip_id == chip_rev+0x5A || - chip_id == chip_rev+0x64)) - uvd_cmd(ctx_addr, 0x206, &i); - } - - ib_cpu[i++] = (family_id < AMDGPU_FAMILY_AI) ? 0x3BC6 : 0x81C6; - ib_cpu[i++] = 0x1; - for (; i % 16; ++i) - ib_cpu[i] = 0x80000000; - - r = submit(i, AMDGPU_HW_IP_UVD); - CU_ASSERT_EQUAL(r, 0); - - /* TODO: use a real CRC32 */ - for (i = 0, sum = 0; i < dt_size; ++i) - sum += ptr[i]; - CU_ASSERT_EQUAL(sum, SUM_DECODE); - - r = amdgpu_bo_cpu_unmap(buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_uvd_destroy(void) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - void *msg; - int i, r; - - req.alloc_size = 4*1024; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(buf_handle, &msg); - CU_ASSERT_EQUAL(r, 0); - - memcpy(msg, uvd_destroy_msg, sizeof(uvd_destroy_msg)); - if (family_id >= AMDGPU_FAMILY_VI) - ((uint8_t*)msg)[0x10] = 7; - - r = amdgpu_bo_cpu_unmap(buf_handle); - CU_ASSERT_EQUAL(r, 0); - - num_resources = 0; - resources[num_resources++] = buf_handle; - resources[num_resources++] = ib_handle; - - i = 0; - uvd_cmd(va, 0x0, &i); - for (; i % 16; ++i) - ib_cpu[i] = 0x80000000; - - r = submit(i, AMDGPU_HW_IP_UVD); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(buf_handle); - CU_ASSERT_EQUAL(r, 0); -} diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c deleted file mode 100644 index 2928233df..000000000 --- a/tests/amdgpu/deadlock_tests.c +++ /dev/null @@ -1,696 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#if HAVE_ALLOCA_H -# include -#endif - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#include - - -/* - * This defines the delay in MS after which memory location designated for - * compression against reference value is written to, unblocking command - * processor - */ -#define WRITE_MEM_ADDRESS_DELAY_MS 100 - -#define PACKET_TYPE3 3 - -#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ - (((op) & 0xFF) << 8) | \ - ((n) & 0x3FFF) << 16) - -#define PACKET3_WAIT_REG_MEM 0x3C -#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) - /* 0 - always - * 1 - < - * 2 - <= - * 3 - == - * 4 - != - * 5 - >= - * 6 - > - */ -#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) - /* 0 - reg - * 1 - mem - */ -#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) - /* 0 - wait_reg_mem - * 1 - wr_wait_wr_reg - */ -#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) - /* 0 - me - * 1 - pfp - */ - -#define PACKET3_WRITE_DATA 0x37 -#define WRITE_DATA_DST_SEL(x) ((x) << 8) - /* 0 - register - * 1 - memory (sync - via GRBM) - * 2 - gl2 - * 3 - gds - * 4 - reserved - * 5 - memory (async - direct) - */ -#define WR_ONE_ADDR (1 << 16) -#define WR_CONFIRM (1 << 20) -#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) - /* 0 - LRU - * 1 - Stream - */ -#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) - /* 0 - me - * 1 - pfp - * 2 - ce - */ - -#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f - -#define SDMA_PKT_HEADER_OP(x) (x & 0xff) -#define SDMA_OP_POLL_REGMEM 8 - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; - -static pthread_t stress_thread; -static uint32_t *ptr; - -static uint32_t family_id; -static uint32_t chip_rev; -static uint32_t chip_id; - -int use_uc_mtype = 0; - -static void amdgpu_deadlock_helper(unsigned ip_type); -static void amdgpu_deadlock_gfx(void); -static void amdgpu_deadlock_compute(void); -static void amdgpu_illegal_reg_access(); -static void amdgpu_illegal_mem_access(); -static void amdgpu_deadlock_sdma(void); -static void amdgpu_dispatch_hang_gfx(void); -static void amdgpu_dispatch_hang_compute(void); -static void amdgpu_dispatch_hang_slow_gfx(void); -static void amdgpu_dispatch_hang_slow_compute(void); -static void amdgpu_draw_hang_gfx(void); -static void amdgpu_draw_hang_slow_gfx(void); -static void amdgpu_hang_sdma(void); -static void amdgpu_hang_slow_sdma(void); - -CU_BOOL suite_deadlock_tests_enable(void) -{ - CU_BOOL enable = CU_TRUE; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - family_id = device_handle->info.family_id; - chip_id = device_handle->info.chip_external_rev; - chip_rev = device_handle->info.chip_rev; - - /* - * Only enable for ASICs supporting GPU reset and for which it's enabled - * by default (currently GFX8+ dGPUS and gfx9+ APUs). Note that Raven1 - * did not support GPU reset, but newer variants do. - */ - if (family_id == AMDGPU_FAMILY_SI || - family_id == AMDGPU_FAMILY_KV || - family_id == AMDGPU_FAMILY_CZ || - family_id == AMDGPU_FAMILY_RV) { - printf("\n\nGPU reset is not enabled for the ASIC, deadlock suite disabled\n"); - enable = CU_FALSE; - } - - if (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { - if (amdgpu_set_test_active("Deadlock Tests", - "gfx ring block test (set amdgpu.lockup_timeout=50)", - CU_FALSE)) - fprintf(stderr, "test deactivation failed - %s\n", - CU_get_error_msg()); - } - - if (device_handle->info.family_id >= AMDGPU_FAMILY_AI) - use_uc_mtype = 1; - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - return enable; -} - -int suite_deadlock_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } - - return CUE_SUCCESS; -} - -int suite_deadlock_tests_clean(void) -{ - int r = amdgpu_device_deinitialize(device_handle); - - if (r == 0) - return CUE_SUCCESS; - else - return CUE_SCLEAN_FAILED; -} - - -CU_TestInfo deadlock_tests[] = { - { "gfx ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_gfx }, - { "compute ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_compute }, - { "sdma ring block test (set amdgpu.lockup_timeout=50)", amdgpu_deadlock_sdma }, - { "illegal reg access test", amdgpu_illegal_reg_access }, - { "illegal mem access test (set amdgpu.vm_fault_stop=2)", amdgpu_illegal_mem_access }, - { "gfx ring bad dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_gfx }, - { "compute ring bad dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_compute }, - { "gfx ring bad slow dispatch test (set amdgpu.lockup_timeout=50)", amdgpu_dispatch_hang_slow_gfx }, - { "compute ring bad slow dispatch test (set amdgpu.lockup_timeout=50,50)", amdgpu_dispatch_hang_slow_compute }, - { "gfx ring bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_gfx }, - { "gfx ring slow bad draw test (set amdgpu.lockup_timeout=50)", amdgpu_draw_hang_slow_gfx }, - { "sdma ring corrupted header test (set amdgpu.lockup_timeout=50)", amdgpu_hang_sdma }, - { "sdma ring slow linear copy test (set amdgpu.lockup_timeout=50)", amdgpu_hang_slow_sdma }, - CU_TEST_INFO_NULL, -}; - -static void *write_mem_address(void *data) -{ - int i; - - /* useconds_t range is [0, 1,000,000] so use loop for waits > 1s */ - for (i = 0; i < WRITE_MEM_ADDRESS_DELAY_MS; i++) - usleep(1000); - - ptr[256] = 0x1; - - return 0; -} - -static void amdgpu_deadlock_gfx(void) -{ - amdgpu_deadlock_helper(AMDGPU_HW_IP_GFX); -} - -static void amdgpu_deadlock_compute(void) -{ - amdgpu_deadlock_helper(AMDGPU_HW_IP_COMPUTE); -} - -static void amdgpu_deadlock_helper(unsigned ip_type) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t expired; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - - r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - - ptr[0] = PACKET3(PACKET3_WAIT_REG_MEM, 5); - ptr[1] = (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */ - WAIT_REG_MEM_FUNCTION(4) | /* != */ - WAIT_REG_MEM_ENGINE(0)); /* me */ - ptr[2] = (ib_result_mc_address + 256*4) & 0xfffffffc; - ptr[3] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; - ptr[4] = 0x00000000; /* reference value */ - ptr[5] = 0xffffffff; /* and mask */ - ptr[6] = 0x00000004; /* poll interval */ - - for (i = 7; i < 16; ++i) - ptr[i] = 0xffff1000; - - - ptr[256] = 0x0; /* the memory we wait on to change */ - - - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = ip_type; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - for (i = 0; i < 200; i++) { - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - } - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = ip_type; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - pthread_join(stress_thread, NULL); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_deadlock_sdma(void) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t expired; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - struct drm_amdgpu_info_hw_ip info; - uint32_t ring_id; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { - r = pthread_create(&stress_thread, NULL, write_mem_address, NULL); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, use_uc_mtype ? AMDGPU_VM_MTYPE_UC : 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - i = 0; - - ptr[i++] = SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) | - (0 << 26) | /* WAIT_REG_MEM */ - (4 << 28) | /* != */ - (1 << 31); /* memory */ - ptr[i++] = (ib_result_mc_address + 256*4) & 0xfffffffc; - ptr[i++] = ((ib_result_mc_address + 256*4) >> 32) & 0xffffffff; - ptr[i++] = 0x00000000; /* reference value */ - ptr[i++] = 0xffffffff; /* and mask */ - ptr[i++] = 4 | /* poll interval */ - (0xfff << 16); /* retry count */ - - for (; i < 16; i++) - ptr[i] = 0; - - ptr[256] = 0x0; /* the memory we wait on to change */ - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_DMA; - ibs_request.ring = ring_id; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - for (i = 0; i < 200; i++) { - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - } - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_DMA; - fence_status.ip_instance = 0; - fence_status.ring = ring_id; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - pthread_join(stress_thread, NULL); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - } - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void bad_access_helper(int reg_access) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t expired; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map_raw(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - i = 0; - - ptr[i++] = PACKET3(PACKET3_WRITE_DATA, 3); - ptr[i++] = (reg_access ? WRITE_DATA_DST_SEL(0) : WRITE_DATA_DST_SEL(5))| WR_CONFIRM; - ptr[i++] = reg_access ? mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR : 0xdeadbee0; - ptr[i++] = 0; - ptr[i++] = 0xdeadbeef; - - for (; i < 16; ++i) - ptr[i] = 0xffff1000; - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_GFX; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_illegal_reg_access() -{ - bad_access_helper(1); -} - -static void amdgpu_illegal_mem_access() -{ - bad_access_helper(0); -} - -static void amdgpu_dispatch_hang_gfx(void) -{ - amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_GFX); -} -static void amdgpu_dispatch_hang_compute(void) -{ - amdgpu_test_dispatch_hang_helper(device_handle, AMDGPU_HW_IP_COMPUTE); -} -static void amdgpu_dispatch_hang_slow_gfx(void) -{ - amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_GFX); -} -static void amdgpu_dispatch_hang_slow_compute(void) -{ - amdgpu_test_dispatch_hang_slow_helper(device_handle, AMDGPU_HW_IP_COMPUTE); -} -static void amdgpu_draw_hang_gfx(void) -{ - amdgpu_test_draw_hang_helper(device_handle); -} -static void amdgpu_draw_hang_slow_gfx(void) -{ - amdgpu_test_draw_hang_slow_helper(device_handle); -} - -#define DMA_CORRUPTED_HEADER_HANG 1 -#define DMA_SLOW_LINEARCOPY_HANG 2 - -static void amdgpu_hang_sdma_helper(unsigned hang_type) -{ - const int sdma_write_length = 1024; - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - amdgpu_bo_handle bo1, bo2; - amdgpu_bo_handle resources[3]; - amdgpu_bo_list_handle bo_list; - void *ib_result_cpu; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_fence fence_status; - uint64_t bo1_mc, bo2_mc; - uint64_t ib_result_mc_address; - volatile unsigned char *bo1_cpu, *bo2_cpu; - amdgpu_va_handle bo1_va_handle, bo2_va_handle; - amdgpu_va_handle va_handle; - struct drm_amdgpu_info_hw_ip hw_ip_info; - int i, j, r; - uint32_t expired, ib_size; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_DMA, 0, &hw_ip_info); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - if (hang_type == DMA_CORRUPTED_HEADER_HANG) - ib_size = 4096; - else - ib_size = 4096 * 0x20000; - - r = amdgpu_bo_alloc_and_map(device_handle, ib_size, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - 0, &bo1, - (void**)&bo1_cpu, &bo1_mc, - &bo1_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); - - /* allocate UC bo2 for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - 0, &bo2, - (void**)&bo2_cpu, &bo2_mc, - &bo2_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); - - resources[0] = bo1; - resources[1] = bo2; - resources[2] = ib_result_handle; - r = amdgpu_bo_list_create(device_handle, 3, - resources, NULL, &bo_list); - - /* fulfill PM4: with bad copy linear header */ - ptr = ib_result_cpu; - i = 0; - if (hang_type == DMA_CORRUPTED_HEADER_HANG) { - ptr[i++] = 0x23decd3d; - ptr[i++] = sdma_write_length - 1; - ptr[i++] = 0; - ptr[i++] = 0xffffffff & bo1_mc; - ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - ptr[i++] = 0xffffffff & bo2_mc; - ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } else { - for (j = 1; j < 0x20000; j++) { - ptr[i++] = 0x1; - ptr[i++] = sdma_write_length - 1; - ptr[i++] = 0; - ptr[i++] = 0xffffffff & bo1_mc; - ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - ptr[i++] = 0xffffffff & bo2_mc; - ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - ptr[i++] = 0x1; - ptr[i++] = sdma_write_length - 1; - ptr[i++] = 0; - ptr[i++] = 0xffffffff & bo2_mc; - ptr[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - ptr[i++] = 0xffffffff & bo1_mc; - ptr[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - } - } - - /* exec command */ - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = i; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_DMA; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = AMDGPU_HW_IP_DMA; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL((r == 0 || r == -ECANCELED), 1); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - - /* end of test */ - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_hang_sdma(void) -{ - amdgpu_hang_sdma_helper(DMA_CORRUPTED_HEADER_HANG); -} -static void amdgpu_hang_slow_sdma(void) -{ - amdgpu_hang_sdma_helper(DMA_SLOW_LINEARCOPY_HANG); -} diff --git a/tests/amdgpu/decode_messages.h b/tests/amdgpu/decode_messages.h deleted file mode 100644 index 218cd779f..000000000 --- a/tests/amdgpu/decode_messages.h +++ /dev/null @@ -1,881 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef _DECODE_MESSAGES_H_ -#define _DECODE_MESSAGES_H_ - -#define SUM_DECODE 0x20345d8 - -static const uint8_t uvd_create_msg[] = { - 0xe4,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x03,0x00,0x00, - 0xe0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0xf9,0xf2,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 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-static const uint8_t uvd_it_scaling_table[] = { - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, - 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10, -}; - -static const uint8_t vcn_dec_create_msg[] = { - 0x28,0x00,0x00,0x00,0x38,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x28,0x00,0x00,0x00, - 0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00, -}; - -static const uint8_t vcn_dec_decode_msg[] = { - 0x28,0x00,0x00,0x00,0x90,0x06,0x00,0x00,0x02,0x00,0x00,0x00,0x01,0x00,0x00,0x00, - 0x03,0x00,0x44,0x40,0x01,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x38,0x00,0x00,0x00, - 0xb4,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x00,0xec,0x00,0x00,0x00, - 0x5c,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x60,0x03,0x00,0x00,0xe0,0x01,0x00,0x00,0x80,0x05,0x00,0x00,0x00,0x94,0x6b,0x00, - 0x96,0x4e,0x0b,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xaf,0x50,0x00, - 0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00, - 0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0xc0,0x03,0x00,0x00,0x80,0x07,0x00,0x00,0x60,0x09,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -}; - -static const uint8_t vcn_dec_destroy_msg[] = { - 0x28,0x00,0x00,0x00,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00, - 0x03,0x00,0x44,0x40,0x00,0x00,0x00,0x00, -}; - -static const uint8_t feedback_msg[] = { - 0x2c,0x00,0x00,0x00,0x2c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, -}; - -static const uint8_t jpeg_bitstream[] = { - 0xFF, 0xD8, 0xFF, 0xDB, 0x01, 0x06, 0x00, 0x08, 0x04, 0x04, 0x04, 0x04, 0x04, 0x05, 0x05, 0x05, - 0x05, 0x05, 0x05, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, - 0x07, 0x07, 0x07, 0x08, 0x08, 0x08, 0x07, 0x07, 0x07, 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x08, - 0x08, 0x09, 0x09, 0x09, 0x08, 0x08, 0x08, 0x08, 0x09, 0x09, 0x0A, 0x0A, 0x0A, 0x0C, 0x0C, 0x0B, - 0x0B, 0x0E, 0x0E, 0x0E, 0x11, 0x11, 0x14, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC4, 0x00, 0x4B, 0x00, 0x01, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x10, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0x08, 0x00, 0x08, - 0x03, 0x00, 0x22, 0x00, 0x01, 0x11, 0x00, 0x02, 0x11, 0x00, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x00, - 0x00, 0x01, 0x11, 0x02, 0x11, 0x00, 0x3F, 0x00, 0x9F, 0xC0, 0x07, 0xFF, 0xD9, 0xFF, 0xD9, -}; - -#endif /* _DECODE_MESSAGES_H_ */ diff --git a/tests/amdgpu/frame.h b/tests/amdgpu/frame.h deleted file mode 100644 index 335401c1d..000000000 --- a/tests/amdgpu/frame.h +++ /dev/null @@ -1,1949 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _frame_h_ -#define _frame_h_ - -static const uint8_t frame[] = { - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, - 0xaa, 0xaa, 0xaa, 0xaa, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, - 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x91, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, 0x6a, - 0x6a, 0x6a, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, - 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, 0x29, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, - 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xeb, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, - 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xd2, 0xaa, 0xaa, 0xaa, - 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* Copyright 2021 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include -#include -#if HAVE_ALLOCA_H -# include -#endif - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include "xf86drm.h" -#include - -#define GFX_COMPUTE_NOP 0xffff1000 - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static char *sysfs_remove = NULL; -static bool do_cs; - -CU_BOOL suite_hotunplug_tests_enable(void) -{ - CU_BOOL enable = CU_TRUE; - drmDevicePtr device; - - if (drmGetDevice2(drm_amdgpu[0], DRM_DEVICE_GET_PCI_REVISION, &device)) { - printf("\n\nGPU Failed to get DRM device PCI info!\n"); - return CU_FALSE; - } - - if (device->bustype != DRM_BUS_PCI) { - printf("\n\nGPU device is not on PCI bus!\n"); - amdgpu_device_deinitialize(device_handle); - return CU_FALSE; - } - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - /* Latest tested amdgpu version to work with all the tests */ - if (minor_version < 46) - enable = false; - - /* skip hotplug test on APUs */ - if(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_FUSION) - enable = false; - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - return enable; -} - -int suite_hotunplug_tests_init(void) -{ - /* We need to open/close device at each test manually */ - amdgpu_close_devices(); - - return CUE_SUCCESS; -} - -int suite_hotunplug_tests_clean(void) -{ - - - return CUE_SUCCESS; -} - -static int amdgpu_hotunplug_trigger(const char *pathname) -{ - int fd, len; - - fd = open(pathname, O_WRONLY); - if (fd < 0) - return -errno; - - len = write(fd, "1", 1); - close(fd); - - return len; -} - -static int amdgpu_hotunplug_setup_test() -{ - int r; - char *tmp_str; - - if (amdgpu_open_device_on_test_index(open_render_node) < 0) { - printf("\n\n Failed to reopen device file!\n"); - return CUE_SINIT_FAILED; - - - - } - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } - - tmp_str = amdgpu_get_device_from_fd(drm_amdgpu[0]); - if (!tmp_str){ - printf("\n\n Device path not found!\n"); - return CUE_SINIT_FAILED; - } - - sysfs_remove = realloc(tmp_str, strlen(tmp_str) * 2); - strcat(sysfs_remove, "/remove"); - - return 0; -} - -static int amdgpu_hotunplug_teardown_test() -{ - if (amdgpu_device_deinitialize(device_handle)) - return CUE_SCLEAN_FAILED; - - amdgpu_close_devices(); - - if (sysfs_remove) - free(sysfs_remove); - - return 0; -} - -static inline int amdgpu_hotunplug_remove() -{ - return amdgpu_hotunplug_trigger(sysfs_remove); -} - -static inline int amdgpu_hotunplug_rescan() -{ - return amdgpu_hotunplug_trigger("/sys/bus/pci/rescan"); -} - -static int amdgpu_cs_sync(amdgpu_context_handle context, - unsigned int ip_type, - int ring, - unsigned int seqno) -{ - struct amdgpu_cs_fence fence = { - .context = context, - .ip_type = ip_type, - .ring = ring, - .fence = seqno, - }; - uint32_t expired; - - return amdgpu_cs_query_fence_status(&fence, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); -} - -static void *amdgpu_nop_cs() -{ - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - uint32_t *ptr; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - amdgpu_context_handle context; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - - r = amdgpu_cs_ctx_create(device_handle, &context); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - for (i = 0; i < 16; ++i) - ptr[i] = GFX_COMPUTE_NOP; - - r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - - while (do_cs) - amdgpu_cs_submit(context, 0, &ibs_request, 1); - - amdgpu_cs_sync(context, AMDGPU_HW_IP_GFX, 0, ibs_request.seq_no); - amdgpu_bo_list_destroy(bo_list); - amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - - amdgpu_cs_ctx_free(context); - - return (void *)0; -} - -static pthread_t* amdgpu_create_cs_thread() -{ - int r; - pthread_t *thread = malloc(sizeof(*thread)); - if (!thread) - return NULL; - - do_cs = true; - - r = pthread_create(thread, NULL, amdgpu_nop_cs, NULL); - CU_ASSERT_EQUAL(r, 0); - - /* Give thread enough time to start*/ - usleep(100000); - return thread; -} - -static void amdgpu_destroy_cs_thread(pthread_t *thread) -{ - void *status; - - do_cs = false; - - pthread_join(*thread, &status); - CU_ASSERT_EQUAL(status, 0); - - free(thread); -} - - -static void amdgpu_hotunplug_test(bool with_cs) -{ - int r; - pthread_t *thread = NULL; - - r = amdgpu_hotunplug_setup_test(); - CU_ASSERT_EQUAL(r , 0); - - if (with_cs) { - thread = amdgpu_create_cs_thread(); - CU_ASSERT_NOT_EQUAL(thread, NULL); - } - - r = amdgpu_hotunplug_remove(); - CU_ASSERT_EQUAL(r > 0, 1); - - if (with_cs) - amdgpu_destroy_cs_thread(thread); - - r = amdgpu_hotunplug_teardown_test(); - CU_ASSERT_EQUAL(r , 0); - - r = amdgpu_hotunplug_rescan(); - CU_ASSERT_EQUAL(r > 0, 1); -} - -static void amdgpu_hotunplug_simple(void) -{ - amdgpu_hotunplug_test(false); -} - -static void amdgpu_hotunplug_with_cs(void) -{ - amdgpu_hotunplug_test(true); -} - -static void amdgpu_hotunplug_with_exported_bo(void) -{ - int r; - uint32_t dma_buf_fd; - unsigned int *ptr; - amdgpu_bo_handle bo_handle; - - struct amdgpu_bo_alloc_request request = { - .alloc_size = 4096, - .phys_alignment = 4096, - .preferred_heap = AMDGPU_GEM_DOMAIN_GTT, - .flags = 0, - }; - - r = amdgpu_hotunplug_setup_test(); - CU_ASSERT_EQUAL(r , 0); - - amdgpu_bo_alloc(device_handle, &request, &bo_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_export(bo_handle, amdgpu_bo_handle_type_dma_buf_fd, &dma_buf_fd); - CU_ASSERT_EQUAL(r, 0); - - ptr = mmap(NULL, 4096, PROT_READ | PROT_WRITE, MAP_SHARED, dma_buf_fd, 0); - CU_ASSERT_NOT_EQUAL(ptr, MAP_FAILED); - - r = amdgpu_hotunplug_remove(); - CU_ASSERT_EQUAL(r > 0, 1); - - amdgpu_bo_free(bo_handle); - - r = amdgpu_hotunplug_teardown_test(); - CU_ASSERT_EQUAL(r , 0); - - *ptr = 0xdeafbeef; - - munmap(ptr, 4096); - close (dma_buf_fd); - - r = amdgpu_hotunplug_rescan(); - CU_ASSERT_EQUAL(r > 0, 1); -} - -static void amdgpu_hotunplug_with_exported_fence(void) -{ - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - uint32_t *ptr, sync_obj_handle, sync_obj_handle2; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - uint32_t major2, minor2; - amdgpu_device_handle device2; - amdgpu_context_handle context; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status = {0}; - int shared_fd; - - r = amdgpu_hotunplug_setup_test(); - CU_ASSERT_EQUAL(r , 0); - - r = amdgpu_device_initialize(drm_amdgpu[1], &major2, &minor2, &device2); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_create(device_handle, &context); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - for (i = 0; i < 16; ++i) - ptr[i] = GFX_COMPUTE_NOP; - - r = amdgpu_bo_list_create(device_handle, 1, &ib_result_handle, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = AMDGPU_HW_IP_GFX; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - - CU_ASSERT_EQUAL(amdgpu_cs_submit(context, 0, &ibs_request, 1), 0); - - fence_status.context = context; - fence_status.ip_type = AMDGPU_HW_IP_GFX; - fence_status.ip_instance = 0; - fence_status.fence = ibs_request.seq_no; - - CU_ASSERT_EQUAL(amdgpu_cs_fence_to_handle(device_handle, &fence_status, - AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ, - &sync_obj_handle), - 0); - - CU_ASSERT_EQUAL(amdgpu_cs_export_syncobj(device_handle, sync_obj_handle, &shared_fd), 0); - - CU_ASSERT_EQUAL(amdgpu_cs_import_syncobj(device2, shared_fd, &sync_obj_handle2), 0); - - CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device_handle, sync_obj_handle), 0); - - CU_ASSERT_EQUAL(amdgpu_bo_list_destroy(bo_list), 0); - CU_ASSERT_EQUAL(amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096), 0); - CU_ASSERT_EQUAL(amdgpu_cs_ctx_free(context), 0); - - r = amdgpu_hotunplug_remove(); - CU_ASSERT_EQUAL(r > 0, 1); - - CU_ASSERT_EQUAL(amdgpu_cs_syncobj_wait(device2, &sync_obj_handle2, 1, 100000000, 0, NULL), 0); - - CU_ASSERT_EQUAL(amdgpu_cs_destroy_syncobj(device2, sync_obj_handle2), 0); - - amdgpu_device_deinitialize(device2); - - r = amdgpu_hotunplug_teardown_test(); - CU_ASSERT_EQUAL(r , 0); - - r = amdgpu_hotunplug_rescan(); - CU_ASSERT_EQUAL(r > 0, 1); -} - - -CU_TestInfo hotunplug_tests[] = { - { "Unplug card and rescan the bus to plug it back", amdgpu_hotunplug_simple }, - { "Same as first test but with command submission", amdgpu_hotunplug_with_cs }, - { "Unplug with exported bo", amdgpu_hotunplug_with_exported_bo }, - { "Unplug with exported fence", amdgpu_hotunplug_with_exported_fence }, - CU_TEST_INFO_NULL, -}; diff --git a/tests/amdgpu/jpeg_tests.c b/tests/amdgpu/jpeg_tests.c deleted file mode 100644 index eccbfeb17..000000000 --- a/tests/amdgpu/jpeg_tests.c +++ /dev/null @@ -1,579 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include -#include - -#include "CUnit/Basic.h" - -#include "util_math.h" - -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include "amdgpu_test.h" -#include "decode_messages.h" - -/* jpeg registers */ -#define mmUVD_JPEG_CNTL 0x0200 -#define mmUVD_JPEG_RB_BASE 0x0201 -#define mmUVD_JPEG_RB_WPTR 0x0202 -#define mmUVD_JPEG_RB_RPTR 0x0203 -#define mmUVD_JPEG_RB_SIZE 0x0204 -#define mmUVD_JPEG_TIER_CNTL2 0x021a -#define mmUVD_JPEG_UV_TILING_CTRL 0x021c -#define mmUVD_JPEG_TILING_CTRL 0x021e -#define mmUVD_JPEG_OUTBUF_RPTR 0x0220 -#define mmUVD_JPEG_OUTBUF_WPTR 0x0221 -#define mmUVD_JPEG_PITCH 0x0222 -#define mmUVD_JPEG_INT_EN 0x0229 -#define mmUVD_JPEG_UV_PITCH 0x022b -#define mmUVD_JPEG_INDEX 0x023e -#define mmUVD_JPEG_DATA 0x023f -#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x0438 -#define mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x0439 -#define mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x045a -#define mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x045b -#define mmUVD_CTX_INDEX 0x0528 -#define mmUVD_CTX_DATA 0x0529 -#define mmUVD_SOFT_RESET 0x05a0 - -#define vcnipUVD_JPEG_DEC_SOFT_RST 0x402f -#define vcnipUVD_JRBC_IB_COND_RD_TIMER 0x408e -#define vcnipUVD_JRBC_IB_REF_DATA 0x408f -#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH 0x40e1 -#define vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW 0x40e0 -#define vcnipUVD_JPEG_RB_BASE 0x4001 -#define vcnipUVD_JPEG_RB_SIZE 0x4004 -#define vcnipUVD_JPEG_RB_WPTR 0x4002 -#define vcnipUVD_JPEG_PITCH 0x401f -#define vcnipUVD_JPEG_UV_PITCH 0x4020 -#define vcnipJPEG_DEC_ADDR_MODE 0x4027 -#define vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE 0x4024 -#define vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE 0x4025 -#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x40e3 -#define vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x40e2 -#define vcnipUVD_JPEG_INDEX 0x402c -#define vcnipUVD_JPEG_DATA 0x402d -#define vcnipUVD_JPEG_TIER_CNTL2 0x400f -#define vcnipUVD_JPEG_OUTBUF_RPTR 0x401e -#define vcnipUVD_JPEG_OUTBUF_CNTL 0x401c -#define vcnipUVD_JPEG_INT_EN 0x400a -#define vcnipUVD_JPEG_CNTL 0x4000 -#define vcnipUVD_JPEG_RB_RPTR 0x4003 -#define vcnipUVD_JPEG_OUTBUF_WPTR 0x401d - - -#define RDECODE_PKT_REG_J(x) ((unsigned)(x)&0x3FFFF) -#define RDECODE_PKT_RES_J(x) (((unsigned)(x)&0x3F) << 18) -#define RDECODE_PKT_COND_J(x) (((unsigned)(x)&0xF) << 24) -#define RDECODE_PKT_TYPE_J(x) (((unsigned)(x)&0xF) << 28) -#define RDECODE_PKTJ(reg, cond, type) (RDECODE_PKT_REG_J(reg) | \ - RDECODE_PKT_RES_J(0) | \ - RDECODE_PKT_COND_J(cond) | \ - RDECODE_PKT_TYPE_J(type)) - -#define UVD_BASE_INST0_SEG1 0x00007E00 -#define SOC15_REG_ADDR(reg) (UVD_BASE_INST0_SEG1 + reg) - -#define COND0 0 -#define COND1 1 -#define COND3 3 -#define TYPE0 0 -#define TYPE1 1 -#define TYPE3 3 -#define JPEG_DEC_DT_PITCH 0x100 -#define JPEG_DEC_BSD_SIZE 0x180 -#define JPEG_DEC_LUMA_OFFSET 0 -#define JPEG_DEC_CHROMA_OFFSET 0x1000 -#define JPEG_DEC_SUM 4096 -#define IB_SIZE 4096 -#define MAX_RESOURCES 16 - -struct amdgpu_jpeg_bo { - amdgpu_bo_handle handle; - amdgpu_va_handle va_handle; - uint64_t addr; - uint64_t size; - uint8_t *ptr; -}; - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t chip_rev; -static uint32_t chip_id; -static uint32_t asic_id; -static uint32_t chip_rev; -static uint32_t chip_id; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static amdgpu_va_handle ib_va_handle; -static uint64_t ib_mc_address; -static uint32_t *ib_cpu; -static uint32_t len; - -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; -bool jpeg_direct_reg; - -static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, - uint32_t val); -static void send_cmd_bitstream(uint64_t addr); -static void send_cmd_target(uint64_t addr); -static void send_cmd_bitstream_direct(uint64_t addr); -static void send_cmd_target_direct(uint64_t addr); - -static void amdgpu_cs_jpeg_decode(void); - -CU_TestInfo jpeg_tests[] = { - {"JPEG decode", amdgpu_cs_jpeg_decode}, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_jpeg_tests_enable(void) -{ - struct drm_amdgpu_info_hw_ip info; - int r; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, - &device_handle)) - return CU_FALSE; - - family_id = device_handle->info.family_id; - asic_id = device_handle->info.asic_id; - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_JPEG, 0, &info); - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - if (r != 0 || !info.available_rings || - (family_id < AMDGPU_FAMILY_RV && - (family_id == AMDGPU_FAMILY_AI && - (chip_id - chip_rev) < 0x32))) { /* Arcturus */ - printf("\n\nThe ASIC NOT support JPEG, suite disabled\n"); - return CU_FALSE; - } - - if (info.hw_ip_version_major == 1) - jpeg_direct_reg = false; - else if (info.hw_ip_version_major > 1 && info.hw_ip_version_major <= 4) - jpeg_direct_reg = true; - else - return CU_FALSE; - - return CU_TRUE; -} - -int suite_jpeg_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, &minor_version, - &device_handle); - if (r) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, &ib_handle, - (void **)&ib_cpu, &ib_mc_address, &ib_va_handle); - if (r) - return CUE_SINIT_FAILED; - - return CUE_SUCCESS; -} - -int suite_jpeg_tests_clean(void) -{ - int r; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static int submit(unsigned ndw, unsigned ip) -{ - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - int r; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = ndw; - - ibs_request.ip_type = ip; - - r = amdgpu_bo_list_create(device_handle, num_resources, resources, NULL, - &ibs_request.resources); - if (r) - return r; - - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = ip; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, AMDGPU_TIMEOUT_INFINITE, 0, - &expired); - if (r) - return r; - - return 0; -} - -static void alloc_resource(struct amdgpu_jpeg_bo *jpeg_bo, unsigned size, - unsigned domain) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - int r; - - req.alloc_size = ALIGN(size, 4096); - req.preferred_heap = domain; - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - jpeg_bo->addr = va; - jpeg_bo->handle = buf_handle; - jpeg_bo->size = req.alloc_size; - jpeg_bo->va_handle = va_handle; - r = amdgpu_bo_cpu_map(jpeg_bo->handle, (void **)&jpeg_bo->ptr); - CU_ASSERT_EQUAL(r, 0); - memset(jpeg_bo->ptr, 0, size); - r = amdgpu_bo_cpu_unmap(jpeg_bo->handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void free_resource(struct amdgpu_jpeg_bo *jpeg_bo) -{ - int r; - - r = amdgpu_bo_va_op(jpeg_bo->handle, 0, jpeg_bo->size, jpeg_bo->addr, 0, - AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(jpeg_bo->va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(jpeg_bo->handle); - CU_ASSERT_EQUAL(r, 0); - memset(jpeg_bo, 0, sizeof(*jpeg_bo)); -} - -static void set_reg_jpeg(unsigned reg, unsigned cond, unsigned type, - uint32_t val) -{ - ib_cpu[len++] = RDECODE_PKTJ(reg, cond, type); - ib_cpu[len++] = val; -} - -/* send a bitstream buffer command */ -static void send_cmd_bitstream(uint64_t addr) -{ - - /* jpeg soft reset */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); - - /* ensuring the Reset is asserted in SCLK domain */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); - - /* wait mem */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); - - /* ensuring the Reset is de-asserted in SCLK domain */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); - - /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_HIGH), COND0, TYPE0, - (addr >> 32)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_READ_64BIT_BAR_LOW), COND0, TYPE0, - (unsigned int)addr); - - /* set jpeg_rb_base */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_BASE), COND0, TYPE0, 0); - - /* set jpeg_rb_base */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_SIZE), COND0, TYPE0, 0xFFFFFFF0); - - /* set jpeg_rb_wptr */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_WPTR), COND0, TYPE0, - (JPEG_DEC_BSD_SIZE >> 2)); -} - -/* send a target buffer command */ -static void send_cmd_target(uint64_t addr) -{ - - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_PITCH), COND0, TYPE0, - (JPEG_DEC_DT_PITCH >> 4)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_PITCH), COND0, TYPE0, - (JPEG_DEC_DT_PITCH >> 4)); - - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TILING_CTRL), COND0, TYPE0, 0); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_UV_TILING_CTRL), COND0, TYPE0, 0); - - /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH), COND0, - TYPE0, (addr >> 32)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW), COND0, TYPE0, - (unsigned int)addr); - - /* set output buffer data address */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 0); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, - JPEG_DEC_LUMA_OFFSET); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INDEX), COND0, TYPE0, 1); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_DATA), COND0, TYPE0, - JPEG_DEC_CHROMA_OFFSET); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_TIER_CNTL2), COND0, TYPE3, 0); - - /* set output buffer read pointer */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_RPTR), COND0, TYPE0, 0); - - /* enable error interrupts */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_INT_EN), COND0, TYPE0, 0xFFFFFFFE); - - /* start engine command */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x6); - - /* wait for job completion, wait for job JBSI fetch done */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, - (JPEG_DEC_BSD_SIZE >> 2)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C2); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0x01400200); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_RB_RPTR), COND0, TYPE3, 0xFFFFFFFF); - - /* wait for job jpeg outbuf idle */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0xFFFFFFFF); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_OUTBUF_WPTR), COND0, TYPE3, - 0x00000001); - - /* stop engine */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0x4); - - /* asserting jpeg lmi drop */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, - (1 << 23 | 1 << 0)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE1, 0); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); - - /* asserting jpeg reset */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 1); - - /* ensure reset is asserted in sclk domain */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (1 << 9)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); - - /* de-assert jpeg reset */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_JPEG_CNTL), COND0, TYPE0, 0); - - /* ensure reset is de-asserted in sclk domain */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x01C3); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, (0 << 9)); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_SOFT_RESET), COND0, TYPE3, (1 << 9)); - - /* de-asserting jpeg lmi drop */ - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_INDEX), COND0, TYPE0, 0x0005); - set_reg_jpeg(SOC15_REG_ADDR(mmUVD_CTX_DATA), COND0, TYPE0, 0); -} - -/* send a bitstream buffer command */ -static void send_cmd_bitstream_direct(uint64_t addr) -{ - - /* jpeg soft reset */ - set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1); - - /* ensuring the Reset is asserted in SCLK domain */ - set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); - set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10)); - set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); - - /* wait mem */ - set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0); - - /* ensuring the Reset is de-asserted in SCLK domain */ - set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10)); - set_reg_jpeg(vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10)); - - /* set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address */ - set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, - (addr >> 32)); - set_reg_jpeg(vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr); - - /* set jpeg_rb_base */ - set_reg_jpeg(vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0); - - /* set jpeg_rb_base */ - set_reg_jpeg(vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0); - - /* set jpeg_rb_wptr */ - set_reg_jpeg(vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (JPEG_DEC_BSD_SIZE >> 2)); -} - -/* send a target buffer command */ -static void send_cmd_target_direct(uint64_t addr) -{ - - set_reg_jpeg(vcnipUVD_JPEG_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); - set_reg_jpeg(vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, (JPEG_DEC_DT_PITCH >> 4)); - - set_reg_jpeg(vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0); - set_reg_jpeg(vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0); - set_reg_jpeg(vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0); - - /* set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address */ - set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, - (addr >> 32)); - set_reg_jpeg(vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr); - - /* set output buffer data address */ - set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0); - set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_LUMA_OFFSET); - set_reg_jpeg(vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1); - set_reg_jpeg(vcnipUVD_JPEG_DATA, COND0, TYPE0, JPEG_DEC_CHROMA_OFFSET); - set_reg_jpeg(vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0); - - /* set output buffer read pointer */ - set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0); - set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0, - ((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6))); - - /* enable error interrupts */ - set_reg_jpeg(vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE); - - /* start engine command */ - set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0xE); - - /* wait for job completion, wait for job JBSI fetch done */ - set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, - (JPEG_DEC_BSD_SIZE >> 2)); - set_reg_jpeg(vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200); - set_reg_jpeg(vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF); - - /* wait for job jpeg outbuf idle */ - set_reg_jpeg(vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF); - set_reg_jpeg(vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001); - - /* stop engine */ - set_reg_jpeg(vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4); -} - -static void amdgpu_cs_jpeg_decode(void) -{ - - struct amdgpu_jpeg_bo dec_buf; - int size, r; - uint8_t *dec; - int sum = 0, i, j; - - size = 16 * 1024; /* 8K bitstream + 8K output */ - num_resources = 0; - alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = dec_buf.handle; - resources[num_resources++] = ib_handle; - r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - memcpy(dec_buf.ptr, jpeg_bitstream, sizeof(jpeg_bitstream)); - - len = 0; - - if (jpeg_direct_reg == true) { - send_cmd_bitstream_direct(dec_buf.addr); - send_cmd_target_direct(dec_buf.addr + (size / 2)); - } else { - send_cmd_bitstream(dec_buf.addr); - send_cmd_target(dec_buf.addr + (size / 2)); - } - - amdgpu_bo_cpu_unmap(dec_buf.handle); - r = submit(len, AMDGPU_HW_IP_VCN_JPEG); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - - dec = dec_buf.ptr + (size / 2); - - /* calculate result checksum */ - for (i = 0; i < 8; i++) - for (j = 0; j < 8; j++) - sum += *((dec + JPEG_DEC_LUMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); - for (i = 0; i < 4; i++) - for (j = 0; j < 8; j++) - sum += *((dec + JPEG_DEC_CHROMA_OFFSET + i * JPEG_DEC_DT_PITCH) + j); - - amdgpu_bo_cpu_unmap(dec_buf.handle); - CU_ASSERT_EQUAL(sum, JPEG_DEC_SUM); - - free_resource(&dec_buf); -} diff --git a/tests/amdgpu/meson.build b/tests/amdgpu/meson.build deleted file mode 100644 index 8618f6a19..000000000 --- a/tests/amdgpu/meson.build +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright © 2017-2018 Intel Corporation - -# Permission is hereby granted, free of charge, to any person obtaining a copy -# of this software and associated documentation files (the "Software"), to deal -# in the Software without restriction, including without limitation the rights -# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -# copies of the Software, and to permit persons to whom the Software is -# furnished to do so, subject to the following conditions: - -# The above copyright notice and this permission notice shall be included in -# all copies or substantial portions of the Software. - -# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE -# SOFTWARE. - -if dep_cunit.found() - amdgpu_test = executable( - 'amdgpu_test', - files( - 'amdgpu_test.c', 'basic_tests.c', 'bo_tests.c', 'cs_tests.c', - 'vce_tests.c', 'uvd_enc_tests.c', 'vcn_tests.c', 'deadlock_tests.c', - 'vm_tests.c', 'ras_tests.c', 'syncobj_tests.c', 'security_tests.c', - 'hotunplug_tests.c', 'jpeg_tests.c', 'cp_dma_tests.c', 'shader_test_util.c' - ), - dependencies : [dep_cunit, dep_threads, dep_atomic_ops], - include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], - link_with : [libdrm, libdrm_amdgpu], - install : with_install_tests, - ) -endif - -amdgpu_stress = executable( - 'amdgpu_stress', - files( - 'amdgpu_stress.c' - ), - dependencies : [dep_threads, dep_atomic_ops], - include_directories : [inc_root, inc_drm, include_directories('../../amdgpu')], - link_with : [libdrm, libdrm_amdgpu], - install : with_install_tests, -) diff --git a/tests/amdgpu/ras_tests.c b/tests/amdgpu/ras_tests.c deleted file mode 100644 index 810bf1727..000000000 --- a/tests/amdgpu/ras_tests.c +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include -#include -#include -#include "xf86drm.h" -#include - -#define PATH_SIZE PATH_MAX - -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) - -const char *ras_block_string[] = { - "umc", - "sdma", - "gfx", - "mmhub", - "athub", - "pcie_bif", - "hdp", - "xgmi_wafl", - "df", - "smn", - "sem", - "mp0", - "mp1", - "fuse", -}; - -#define ras_block_str(i) (ras_block_string[i]) - -enum amdgpu_ras_block { - AMDGPU_RAS_BLOCK__UMC = 0, - AMDGPU_RAS_BLOCK__SDMA, - AMDGPU_RAS_BLOCK__GFX, - AMDGPU_RAS_BLOCK__MMHUB, - AMDGPU_RAS_BLOCK__ATHUB, - AMDGPU_RAS_BLOCK__PCIE_BIF, - AMDGPU_RAS_BLOCK__HDP, - AMDGPU_RAS_BLOCK__XGMI_WAFL, - AMDGPU_RAS_BLOCK__DF, - AMDGPU_RAS_BLOCK__SMN, - AMDGPU_RAS_BLOCK__SEM, - AMDGPU_RAS_BLOCK__MP0, - AMDGPU_RAS_BLOCK__MP1, - AMDGPU_RAS_BLOCK__FUSE, - - AMDGPU_RAS_BLOCK__LAST -}; - -#define AMDGPU_RAS_BLOCK_COUNT AMDGPU_RAS_BLOCK__LAST -#define AMDGPU_RAS_BLOCK_MASK ((1ULL << AMDGPU_RAS_BLOCK_COUNT) - 1) - -enum amdgpu_ras_gfx_subblock { - /* CPC */ - AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START = 0, - AMDGPU_RAS_BLOCK__GFX_CPC_SCRATCH = - AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, - AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME1, - AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME1, - AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME1, - AMDGPU_RAS_BLOCK__GFX_DC_STATE_ME2, - AMDGPU_RAS_BLOCK__GFX_DC_CSINVOC_ME2, - AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, - AMDGPU_RAS_BLOCK__GFX_CPC_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_DC_RESTORE_ME2, - /* CPF */ - AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME2 = - AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_CPF_ROQ_ME1, - AMDGPU_RAS_BLOCK__GFX_CPF_TAG, - AMDGPU_RAS_BLOCK__GFX_CPF_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPF_TAG, - /* CPG */ - AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_CPG_DMA_ROQ = - AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_CPG_DMA_TAG, - AMDGPU_RAS_BLOCK__GFX_CPG_TAG, - AMDGPU_RAS_BLOCK__GFX_CPG_INDEX_END = AMDGPU_RAS_BLOCK__GFX_CPG_TAG, - /* GDS */ - AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_GDS_MEM = AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_GDS_INPUT_QUEUE, - AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_CMD_RAM_MEM, - AMDGPU_RAS_BLOCK__GFX_GDS_OA_PHY_DATA_RAM_MEM, - AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, - AMDGPU_RAS_BLOCK__GFX_GDS_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_GDS_OA_PIPE_MEM, - /* SPI */ - AMDGPU_RAS_BLOCK__GFX_SPI_SR_MEM, - /* SQ */ - AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_SQ_SGPR = AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, - AMDGPU_RAS_BLOCK__GFX_SQ_LDS_I, - AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, - AMDGPU_RAS_BLOCK__GFX_SQ_INDEX_END = AMDGPU_RAS_BLOCK__GFX_SQ_VGPR, - /* SQC (3 ranges) */ - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, - /* SQC range 0 */ - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START = - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_UTCL1_LFIFO = - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_START, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_WRITE_DATA_BUF, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU0_UTCL1_LFIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_WRITE_DATA_BUF, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_WRITE_DATA_BUF, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX0_END = - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU2_UTCL1_LFIFO, - /* SQC range 1 */ - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM = - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_UTCL1_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_BANK_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_TAG_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_HIT_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_DIRTY_BIT_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX1_END = - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKA_BANK_RAM, - /* SQC range 2 */ - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM = - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_UTCL1_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_BANK_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_TAG_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_HIT_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_MISS_FIFO, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_DIRTY_BIT_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END = - AMDGPU_RAS_BLOCK__GFX_SQC_DATA_BANKB_BANK_RAM, - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_SQC_INDEX2_END, - /* TA */ - AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO = - AMDGPU_RAS_BLOCK__GFX_TA_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TA_FS_AFIFO, - AMDGPU_RAS_BLOCK__GFX_TA_FL_LFIFO, - AMDGPU_RAS_BLOCK__GFX_TA_FX_LFIFO, - AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, - AMDGPU_RAS_BLOCK__GFX_TA_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TA_FS_CFIFO, - /* TCA */ - AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TCA_HOLE_FIFO = - AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCA_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_TCA_REQ_FIFO, - /* TCC (5 sub-ranges) */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, - /* TCC range 0 */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_START, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_0, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DIRTY_BANK_1, - AMDGPU_RAS_BLOCK__GFX_TCC_HIGH_RATE_TAG, - AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX0_END = - AMDGPU_RAS_BLOCK__GFX_TCC_LOW_RATE_TAG, - /* TCC range 1 */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_DEC = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX1_END = - AMDGPU_RAS_BLOCK__GFX_TCC_IN_USE_TRANSFER, - /* TCC range 2 */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_DATA = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_TCC_RETURN_CONTROL, - AMDGPU_RAS_BLOCK__GFX_TCC_UC_ATOMIC_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_RETURN, - AMDGPU_RAS_BLOCK__GFX_TCC_WRITE_CACHE_READ, - AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCC_SRC_FIFO_NEXT_RAM, - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX2_END = - AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_TAG_PROBE_FIFO, - /* TCC range 3 */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, - AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_START, - AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX3_END = - AMDGPU_RAS_BLOCK__GFX_TCC_LATENCY_FIFO_NEXT_RAM, - /* TCC range 4 */ - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, - AMDGPU_RAS_BLOCK__GFX_TCC_WRRET_TAG_WRITE_RETURN = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_START, - AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END = - AMDGPU_RAS_BLOCK__GFX_TCC_ATOMIC_RETURN_BUFFER, - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_TCC_INDEX4_END, - /* TCI */ - AMDGPU_RAS_BLOCK__GFX_TCI_WRITE_RAM, - /* TCP */ - AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM = - AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TCP_LFIFO_RAM, - AMDGPU_RAS_BLOCK__GFX_TCP_CMD_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCP_VM_FIFO, - AMDGPU_RAS_BLOCK__GFX_TCP_DB_RAM, - AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO0, - AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, - AMDGPU_RAS_BLOCK__GFX_TCP_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_TCP_UTCL1_LFIFO1, - /* TD */ - AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO = - AMDGPU_RAS_BLOCK__GFX_TD_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_HI, - AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, - AMDGPU_RAS_BLOCK__GFX_TD_INDEX_END = AMDGPU_RAS_BLOCK__GFX_TD_CS_FIFO, - /* EA (3 sub-ranges) */ - AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, - /* EA range 0 */ - AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START = - AMDGPU_RAS_BLOCK__GFX_EA_INDEX_START, - AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM = - AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_START, - AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_CMDMEM, - AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_DATAMEM, - AMDGPU_RAS_BLOCK__GFX_EA_RRET_TAGMEM, - AMDGPU_RAS_BLOCK__GFX_EA_WRET_TAGMEM, - AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_CMDMEM, - AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_CMDMEM, - AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, - AMDGPU_RAS_BLOCK__GFX_EA_INDEX0_END = - AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_DATAMEM, - /* EA range 1 */ - AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_PAGEMEM = - AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_START, - AMDGPU_RAS_BLOCK__GFX_EA_DRAMWR_PAGEMEM, - AMDGPU_RAS_BLOCK__GFX_EA_IORD_CMDMEM, - AMDGPU_RAS_BLOCK__GFX_EA_IOWR_CMDMEM, - AMDGPU_RAS_BLOCK__GFX_EA_IOWR_DATAMEM, - AMDGPU_RAS_BLOCK__GFX_EA_GMIRD_PAGEMEM, - AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, - AMDGPU_RAS_BLOCK__GFX_EA_INDEX1_END = - AMDGPU_RAS_BLOCK__GFX_EA_GMIWR_PAGEMEM, - /* EA range 2 */ - AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_EA_MAM_D0MEM = - AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_START, - AMDGPU_RAS_BLOCK__GFX_EA_MAM_D1MEM, - AMDGPU_RAS_BLOCK__GFX_EA_MAM_D2MEM, - AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, - AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END = - AMDGPU_RAS_BLOCK__GFX_EA_MAM_D3MEM, - AMDGPU_RAS_BLOCK__GFX_EA_INDEX_END = - AMDGPU_RAS_BLOCK__GFX_EA_INDEX2_END, - /* UTC VM L2 bank */ - AMDGPU_RAS_BLOCK__UTC_VML2_BANK_CACHE, - /* UTC VM walker */ - AMDGPU_RAS_BLOCK__UTC_VML2_WALKER, - /* UTC ATC L2 2MB cache */ - AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_2M_BANK, - /* UTC ATC L2 4KB cache */ - AMDGPU_RAS_BLOCK__UTC_ATCL2_CACHE_4K_BANK, - AMDGPU_RAS_BLOCK__GFX_MAX -}; - -enum amdgpu_ras_error_type { - AMDGPU_RAS_ERROR__NONE = 0, - AMDGPU_RAS_ERROR__PARITY = 1, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE = 2, - AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE = 4, - AMDGPU_RAS_ERROR__POISON = 8, -}; - -struct ras_inject_test_config { - char name[64]; - char block[32]; - int sub_block; - enum amdgpu_ras_error_type type; - uint64_t address; - uint64_t value; -}; - -struct ras_common_if { - enum amdgpu_ras_block block; - enum amdgpu_ras_error_type type; - uint32_t sub_block_index; - char name[32]; -}; - -struct ras_inject_if { - struct ras_common_if head; - uint64_t address; - uint64_t value; -}; - -struct ras_debug_if { - union { - struct ras_common_if head; - struct ras_inject_if inject; - }; - int op; -}; -/* for now, only umc, gfx, sdma has implemented. */ -#define DEFAULT_RAS_BLOCK_MASK_INJECT ((1 << AMDGPU_RAS_BLOCK__UMC) |\ - (1 << AMDGPU_RAS_BLOCK__GFX)) -#define DEFAULT_RAS_BLOCK_MASK_QUERY ((1 << AMDGPU_RAS_BLOCK__UMC) |\ - (1 << AMDGPU_RAS_BLOCK__GFX)) -#define DEFAULT_RAS_BLOCK_MASK_BASIC (1 << AMDGPU_RAS_BLOCK__UMC |\ - (1 << AMDGPU_RAS_BLOCK__SDMA) |\ - (1 << AMDGPU_RAS_BLOCK__GFX)) - -static uint32_t ras_block_mask_inject = DEFAULT_RAS_BLOCK_MASK_INJECT; -static uint32_t ras_block_mask_query = DEFAULT_RAS_BLOCK_MASK_INJECT; -static uint32_t ras_block_mask_basic = DEFAULT_RAS_BLOCK_MASK_BASIC; - -struct ras_test_mask { - uint32_t inject_mask; - uint32_t query_mask; - uint32_t basic_mask; -}; - -struct amdgpu_ras_data { - amdgpu_device_handle device_handle; - uint32_t id; - uint32_t capability; - struct ras_test_mask test_mask; -}; - -/* all devices who has ras supported */ -static struct amdgpu_ras_data devices[MAX_CARDS_SUPPORTED]; -static int devices_count; - -struct ras_DID_test_mask{ - uint16_t device_id; - uint16_t revision_id; - struct ras_test_mask test_mask; -}; - -/* white list for inject test. */ -#define RAS_BLOCK_MASK_ALL {\ - DEFAULT_RAS_BLOCK_MASK_INJECT,\ - DEFAULT_RAS_BLOCK_MASK_QUERY,\ - DEFAULT_RAS_BLOCK_MASK_BASIC\ -} - -#define RAS_BLOCK_MASK_QUERY_BASIC {\ - 0,\ - DEFAULT_RAS_BLOCK_MASK_QUERY,\ - DEFAULT_RAS_BLOCK_MASK_BASIC\ -} - -static const struct ras_inject_test_config umc_ras_inject_test[] = { - {"ras_umc.1.0", "umc", 0, AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, -}; - -static const struct ras_inject_test_config gfx_ras_inject_test[] = { - {"ras_gfx.2.0", "gfx", AMDGPU_RAS_BLOCK__GFX_CPC_UCODE, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.1", "gfx", AMDGPU_RAS_BLOCK__GFX_CPF_TAG, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.2", "gfx", AMDGPU_RAS_BLOCK__GFX_CPG_TAG, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.3", "gfx", AMDGPU_RAS_BLOCK__GFX_SQ_LDS_D, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.4", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_DATA_CU1_UTCL1_LFIFO, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.5", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKA_TAG_RAM, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.6", "gfx", AMDGPU_RAS_BLOCK__GFX_SQC_INST_BANKB_TAG_RAM, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.7", "gfx", AMDGPU_RAS_BLOCK__GFX_TA_FS_DFIFO, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.8", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.9", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_0_1, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.10", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_0, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.11", "gfx", AMDGPU_RAS_BLOCK__GFX_TCC_CACHE_DATA_BANK_1_1, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.12", "gfx", AMDGPU_RAS_BLOCK__GFX_TCP_CACHE_RAM, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.13", "gfx", AMDGPU_RAS_BLOCK__GFX_TD_SS_FIFO_LO, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, - {"ras_gfx.2.14", "gfx", AMDGPU_RAS_BLOCK__GFX_EA_DRAMRD_CMDMEM, - AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE, 0, 0}, -}; - -static const struct ras_DID_test_mask ras_DID_array[] = { - {0x66a1, 0x00, RAS_BLOCK_MASK_ALL}, - {0x66a1, 0x01, RAS_BLOCK_MASK_ALL}, - {0x66a1, 0x04, RAS_BLOCK_MASK_ALL}, -}; - -static uint32_t amdgpu_ras_find_block_id_by_name(const char *name) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) { - if (strcmp(name, ras_block_string[i]) == 0) - return i; - } - - return ARRAY_SIZE(ras_block_string); -} - -static char *amdgpu_ras_get_error_type_id(enum amdgpu_ras_error_type type) -{ - switch (type) { - case AMDGPU_RAS_ERROR__PARITY: - return "parity"; - case AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE: - return "single_correctable"; - case AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE: - return "multi_uncorrectable"; - case AMDGPU_RAS_ERROR__POISON: - return "poison"; - case AMDGPU_RAS_ERROR__NONE: - default: - return NULL; - } -} - -static struct ras_test_mask amdgpu_ras_get_test_mask(drmDevicePtr device) -{ - int i; - static struct ras_test_mask default_test_mask = RAS_BLOCK_MASK_QUERY_BASIC; - - for (i = 0; i < sizeof(ras_DID_array) / sizeof(ras_DID_array[0]); i++) { - if (ras_DID_array[i].device_id == device->deviceinfo.pci->device_id && - ras_DID_array[i].revision_id == device->deviceinfo.pci->revision_id) - return ras_DID_array[i].test_mask; - } - return default_test_mask; -} - -static uint32_t amdgpu_ras_lookup_capability(amdgpu_device_handle device_handle) -{ - union { - uint64_t feature_mask; - struct { - uint32_t enabled_features; - uint32_t supported_features; - }; - } features = { 0 }; - int ret; - - ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES, - sizeof(features), &features); - if (ret) - return 0; - - return features.supported_features; -} - -static int get_file_contents(char *file, char *buf, int size); - -static int amdgpu_ras_lookup_id(drmDevicePtr device) -{ - char path[PATH_SIZE]; - char str[128]; - drmPciBusInfo info; - int i; - int ret; - - for (i = 0; i < MAX_CARDS_SUPPORTED; i++) { - memset(str, 0, sizeof(str)); - memset(&info, 0, sizeof(info)); - snprintf(path, PATH_SIZE, "/sys/kernel/debug/dri/%d/name", i); - if (get_file_contents(path, str, sizeof(str)) <= 0) - continue; - - ret = sscanf(str, "amdgpu dev=%04hx:%02hhx:%02hhx.%01hhx", - &info.domain, &info.bus, &info.dev, &info.func); - if (ret != 4) - continue; - - if (memcmp(&info, device->businfo.pci, sizeof(info)) == 0) - return i; - } - return -1; -} - -//helpers - -static int test_card; -static char sysfs_path[PATH_SIZE]; -static char debugfs_path[PATH_SIZE]; -static uint32_t ras_mask; -static amdgpu_device_handle device_handle; - -static void set_test_card(int card) -{ - test_card = card; - snprintf(sysfs_path, PATH_SIZE, "/sys/class/drm/card%d/device/ras/", devices[card].id); - snprintf(debugfs_path, PATH_SIZE, "/sys/kernel/debug/dri/%d/ras/", devices[card].id); - ras_mask = devices[card].capability; - device_handle = devices[card].device_handle; - ras_block_mask_inject = devices[card].test_mask.inject_mask; - ras_block_mask_query = devices[card].test_mask.query_mask; - ras_block_mask_basic = devices[card].test_mask.basic_mask; -} - -static const char *get_ras_sysfs_root(void) -{ - return sysfs_path; -} - -static const char *get_ras_debugfs_root(void) -{ - return debugfs_path; -} - -static int set_file_contents(char *file, char *buf, int size) -{ - int n, fd; - fd = open(file, O_WRONLY); - if (fd == -1) - return -1; - n = write(fd, buf, size); - close(fd); - return n; -} - -static int get_file_contents(char *file, char *buf, int size) -{ - int n, fd; - fd = open(file, O_RDONLY); - if (fd == -1) - return -1; - n = read(fd, buf, size); - close(fd); - return n; -} - -static int is_file_ok(char *file, int flags) -{ - int fd; - - fd = open(file, flags); - if (fd == -1) - return -1; - close(fd); - return 0; -} - -static int amdgpu_ras_is_feature_enabled(enum amdgpu_ras_block block) -{ - uint32_t feature_mask; - int ret; - - ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES, - sizeof(feature_mask), &feature_mask); - if (ret) - return -1; - - return (1 << block) & feature_mask; -} - -static int amdgpu_ras_is_feature_supported(enum amdgpu_ras_block block) -{ - return (1 << block) & ras_mask; -} - -static int amdgpu_ras_invoke(struct ras_debug_if *data) -{ - char path[PATH_SIZE]; - int ret; - - snprintf(path, sizeof(path), "%s", get_ras_debugfs_root()); - strncat(path, "ras_ctrl", sizeof(path) - strlen(path)); - - ret = set_file_contents(path, (char *)data, sizeof(*data)) - - sizeof(*data); - return ret; -} - -static int amdgpu_ras_query_err_count(enum amdgpu_ras_block block, - unsigned long *ue, unsigned long *ce) -{ - char buf[64]; - char name[PATH_SIZE]; - - *ue = *ce = 0; - - if (amdgpu_ras_is_feature_supported(block) <= 0) - return -1; - - snprintf(name, sizeof(name), "%s", get_ras_sysfs_root()); - strncat(name, ras_block_str(block), sizeof(name) - strlen(name)); - strncat(name, "_err_count", sizeof(name) - strlen(name)); - - if (is_file_ok(name, O_RDONLY)) - return 0; - - if (get_file_contents(name, buf, sizeof(buf)) <= 0) - return -1; - - if (sscanf(buf, "ue: %lu\nce: %lu", ue, ce) != 2) - return -1; - - return 0; -} - -static int amdgpu_ras_inject(enum amdgpu_ras_block block, - uint32_t sub_block, enum amdgpu_ras_error_type type, - uint64_t address, uint64_t value) -{ - struct ras_debug_if data = { .op = 2, }; - struct ras_inject_if *inject = &data.inject; - int ret; - - if (amdgpu_ras_is_feature_enabled(block) <= 0) { - fprintf(stderr, "block id(%d) is not valid\n", block); - return -1; - } - - inject->head.block = block; - inject->head.type = type; - inject->head.sub_block_index = sub_block; - strncpy(inject->head.name, ras_block_str(block), sizeof(inject->head.name)-1); - inject->address = address; - inject->value = value; - - ret = amdgpu_ras_invoke(&data); - CU_ASSERT_EQUAL(ret, 0); - if (ret) - return -1; - - return 0; -} - -//tests -static void amdgpu_ras_features_test(int enable) -{ - struct ras_debug_if data; - int ret; - int i; - - data.op = enable; - for (i = 0; i < AMDGPU_RAS_BLOCK__LAST; i++) { - struct ras_common_if head = { - .block = i, - .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE, - .sub_block_index = 0, - .name = "", - }; - - if (amdgpu_ras_is_feature_supported(i) <= 0) - continue; - - data.head = head; - - ret = amdgpu_ras_invoke(&data); - CU_ASSERT_EQUAL(ret, 0); - - if (ret) - continue; - - ret = enable ^ amdgpu_ras_is_feature_enabled(i); - CU_ASSERT_EQUAL(ret, 0); - } -} - -static void amdgpu_ras_disable_test(void) -{ - int i; - for (i = 0; i < devices_count; i++) { - set_test_card(i); - amdgpu_ras_features_test(0); - } -} - -static void amdgpu_ras_enable_test(void) -{ - int i; - for (i = 0; i < devices_count; i++) { - set_test_card(i); - amdgpu_ras_features_test(1); - } -} - -static void __amdgpu_ras_ip_inject_test(const struct ras_inject_test_config *ip_test, - uint32_t size) -{ - int i, ret; - unsigned long old_ue, old_ce; - unsigned long ue, ce; - uint32_t block; - int timeout; - bool pass; - - for (i = 0; i < size; i++) { - timeout = 3; - pass = false; - - block = amdgpu_ras_find_block_id_by_name(ip_test[i].block); - - /* Ensure one valid ip block */ - if (block == ARRAY_SIZE(ras_block_string)) - break; - - /* Ensure RAS feature for the IP block is enabled by kernel */ - if (amdgpu_ras_is_feature_supported(block) <= 0) - break; - - ret = amdgpu_ras_query_err_count(block, &old_ue, &old_ce); - CU_ASSERT_EQUAL(ret, 0); - if (ret) - break; - - ret = amdgpu_ras_inject(block, - ip_test[i].sub_block, - ip_test[i].type, - ip_test[i].address, - ip_test[i].value); - CU_ASSERT_EQUAL(ret, 0); - if (ret) - break; - - while (timeout > 0) { - sleep(5); - - ret = amdgpu_ras_query_err_count(block, &ue, &ce); - CU_ASSERT_EQUAL(ret, 0); - if (ret) - break; - - if (old_ue != ue || old_ce != ce) { - pass = true; - sleep(20); - break; - } - timeout -= 1; - } - printf("\t Test %s@block %s, subblock %d, error_type %s, address %ld, value %ld: %s\n", - ip_test[i].name, - ip_test[i].block, - ip_test[i].sub_block, - amdgpu_ras_get_error_type_id(ip_test[i].type), - ip_test[i].address, - ip_test[i].value, - pass ? "Pass" : "Fail"); - } -} - -static void __amdgpu_ras_inject_test(void) -{ - printf("...\n"); - - /* run UMC ras inject test */ - __amdgpu_ras_ip_inject_test(umc_ras_inject_test, - ARRAY_SIZE(umc_ras_inject_test)); - - /* run GFX ras inject test */ - __amdgpu_ras_ip_inject_test(gfx_ras_inject_test, - ARRAY_SIZE(gfx_ras_inject_test)); -} - -static void amdgpu_ras_inject_test(void) -{ - int i; - for (i = 0; i < devices_count; i++) { - set_test_card(i); - __amdgpu_ras_inject_test(); - } -} - -static void __amdgpu_ras_query_test(void) -{ - unsigned long ue, ce; - int ret; - int i; - - for (i = 0; i < AMDGPU_RAS_BLOCK__LAST; i++) { - if (amdgpu_ras_is_feature_supported(i) <= 0) - continue; - - if (!((1 << i) & ras_block_mask_query)) - continue; - - ret = amdgpu_ras_query_err_count(i, &ue, &ce); - CU_ASSERT_EQUAL(ret, 0); - } -} - -static void amdgpu_ras_query_test(void) -{ - int i; - for (i = 0; i < devices_count; i++) { - set_test_card(i); - __amdgpu_ras_query_test(); - } -} - -static void amdgpu_ras_basic_test(void) -{ - int ret; - int i; - int j; - uint32_t features; - char path[PATH_SIZE]; - - ret = is_file_ok("/sys/module/amdgpu/parameters/ras_mask", O_RDONLY); - CU_ASSERT_EQUAL(ret, 0); - - for (i = 0; i < devices_count; i++) { - set_test_card(i); - - ret = amdgpu_query_info(device_handle, AMDGPU_INFO_RAS_ENABLED_FEATURES, - sizeof(features), &features); - CU_ASSERT_EQUAL(ret, 0); - - snprintf(path, sizeof(path), "%s", get_ras_debugfs_root()); - strncat(path, "ras_ctrl", sizeof(path) - strlen(path)); - - ret = is_file_ok(path, O_WRONLY); - CU_ASSERT_EQUAL(ret, 0); - - snprintf(path, sizeof(path), "%s", get_ras_sysfs_root()); - strncat(path, "features", sizeof(path) - strlen(path)); - - ret = is_file_ok(path, O_RDONLY); - CU_ASSERT_EQUAL(ret, 0); - - for (j = 0; j < AMDGPU_RAS_BLOCK__LAST; j++) { - ret = amdgpu_ras_is_feature_supported(j); - if (ret <= 0) - continue; - - if (!((1 << j) & ras_block_mask_basic)) - continue; - - snprintf(path, sizeof(path), "%s", get_ras_sysfs_root()); - strncat(path, ras_block_str(j), sizeof(path) - strlen(path)); - strncat(path, "_err_count", sizeof(path) - strlen(path)); - - ret = is_file_ok(path, O_RDONLY); - CU_ASSERT_EQUAL(ret, 0); - - snprintf(path, sizeof(path), "%s", get_ras_debugfs_root()); - strncat(path, ras_block_str(j), sizeof(path) - strlen(path)); - strncat(path, "_err_inject", sizeof(path) - strlen(path)); - - ret = is_file_ok(path, O_WRONLY); - CU_ASSERT_EQUAL(ret, 0); - } - } -} - -CU_TestInfo ras_tests[] = { - { "ras basic test", amdgpu_ras_basic_test }, - { "ras query test", amdgpu_ras_query_test }, - { "ras inject test", amdgpu_ras_inject_test }, - { "ras disable test", amdgpu_ras_disable_test }, - { "ras enable test", amdgpu_ras_enable_test }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_ras_tests_enable(void) -{ - amdgpu_device_handle device_handle; - uint32_t major_version; - uint32_t minor_version; - int i; - drmDevicePtr device; - - for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) { - if (amdgpu_device_initialize(drm_amdgpu[i], &major_version, - &minor_version, &device_handle)) - continue; - - if (drmGetDevice2(drm_amdgpu[i], - DRM_DEVICE_GET_PCI_REVISION, - &device)) - continue; - - if (device->bustype == DRM_BUS_PCI && - amdgpu_ras_lookup_capability(device_handle)) { - amdgpu_device_deinitialize(device_handle); - return CU_TRUE; - } - - if (amdgpu_device_deinitialize(device_handle)) - continue; - } - - return CU_FALSE; -} - -int suite_ras_tests_init(void) -{ - drmDevicePtr device; - amdgpu_device_handle device_handle; - uint32_t major_version; - uint32_t minor_version; - uint32_t capability; - struct ras_test_mask test_mask; - int id; - int i; - int r; - - for (i = 0; i < MAX_CARDS_SUPPORTED && drm_amdgpu[i] >= 0; i++) { - r = amdgpu_device_initialize(drm_amdgpu[i], &major_version, - &minor_version, &device_handle); - if (r) - continue; - - if (drmGetDevice2(drm_amdgpu[i], - DRM_DEVICE_GET_PCI_REVISION, - &device)) { - amdgpu_device_deinitialize(device_handle); - continue; - } - - if (device->bustype != DRM_BUS_PCI) { - amdgpu_device_deinitialize(device_handle); - continue; - } - - capability = amdgpu_ras_lookup_capability(device_handle); - if (capability == 0) { - amdgpu_device_deinitialize(device_handle); - continue; - - } - - id = amdgpu_ras_lookup_id(device); - if (id == -1) { - amdgpu_device_deinitialize(device_handle); - continue; - } - - test_mask = amdgpu_ras_get_test_mask(device); - - devices[devices_count++] = (struct amdgpu_ras_data) { - device_handle, id, capability, test_mask, - }; - } - - if (devices_count == 0) - return CUE_SINIT_FAILED; - - return CUE_SUCCESS; -} - -int suite_ras_tests_clean(void) -{ - int r; - int i; - int ret = CUE_SUCCESS; - - for (i = 0; i < devices_count; i++) { - r = amdgpu_device_deinitialize(devices[i].device_handle); - if (r) - ret = CUE_SCLEAN_FAILED; - } - return ret; -} diff --git a/tests/amdgpu/security_tests.c b/tests/amdgpu/security_tests.c deleted file mode 100644 index e6c9f9a82..000000000 --- a/tests/amdgpu/security_tests.c +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright 2019 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#include -#include -#ifdef __FreeBSD__ -#include -#else -#include -#endif -#include -#include - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; - -static struct drm_amdgpu_info_hw_ip sdma_info; - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(_Arr) (sizeof(_Arr)/sizeof((_Arr)[0])) -#endif - - -/* --------------------- Secure bounce test ------------------------ * - * - * The secure bounce test tests that we can evict a TMZ buffer, - * and page it back in, via a bounce buffer, as it encryption/decryption - * depends on its physical address, and have the same data, i.e. data - * integrity is preserved. - * - * The steps are as follows (from Christian K.): - * - * Buffer A which is TMZ protected and filled by the CPU with a - * certain pattern. That the GPU is reading only random nonsense from - * that pattern is irrelevant for the test. - * - * This buffer A is then secure copied into buffer B which is also - * TMZ protected. - * - * Buffer B is moved around, from VRAM to GTT, GTT to SYSTEM, - * etc. - * - * Then, we use another secure copy of buffer B back to buffer A. - * - * And lastly we check with the CPU the pattern. - * - * Assuming that we don't have memory contention and buffer A stayed - * at the same place, we should still see the same pattern when read - * by the CPU. - * - * If we don't see the same pattern then something in the buffer - * migration code is not working as expected. - */ - -#define SECURE_BOUNCE_TEST_STR "secure bounce" -#define SECURE_BOUNCE_FAILED_STR SECURE_BOUNCE_TEST_STR " failed" - -#define PRINT_ERROR(_Res) fprintf(stderr, "%s:%d: %s (%d)\n", \ - __func__, __LINE__, strerror(-(_Res)), _Res) - -#define PACKET_LCOPY_SIZE 7 -#define PACKET_NOP_SIZE 12 - -struct sec_amdgpu_bo { - struct amdgpu_bo *bo; - struct amdgpu_va *va; -}; - -struct command_ctx { - struct amdgpu_device *dev; - struct amdgpu_cs_ib_info cs_ibinfo; - struct amdgpu_cs_request cs_req; - struct amdgpu_context *context; - int ring_id; -}; - -/** - * amdgpu_bo_alloc_map -- Allocate and map a buffer object (BO) - * @dev: The AMDGPU device this BO belongs to. - * @size: The size of the BO. - * @alignment: Alignment of the BO. - * @gem_domain: One of AMDGPU_GEM_DOMAIN_xyz. - * @alloc_flags: One of AMDGPU_GEM_CREATE_xyz. - * @sbo: the result - * - * Allocate a buffer object (BO) with the desired attributes - * as specified by the argument list and write out the result - * into @sbo. - * - * Return 0 on success and @sbo->bo and @sbo->va are set, - * or -errno on error. - */ -static int amdgpu_bo_alloc_map(struct amdgpu_device *dev, - unsigned size, - unsigned alignment, - unsigned gem_domain, - uint64_t alloc_flags, - struct sec_amdgpu_bo *sbo) -{ - void *cpu; - uint64_t mc_addr; - - return amdgpu_bo_alloc_and_map_raw(dev, - size, - alignment, - gem_domain, - alloc_flags, - 0, - &sbo->bo, - &cpu, &mc_addr, - &sbo->va); -} - -static void amdgpu_bo_unmap_free(struct sec_amdgpu_bo *sbo, - const uint64_t size) -{ - (void) amdgpu_bo_unmap_and_free(sbo->bo, - sbo->va, - sbo->va->address, - size); - sbo->bo = NULL; - sbo->va = NULL; -} - -static void amdgpu_sdma_lcopy(uint32_t *packet, - const uint64_t dst, - const uint64_t src, - const uint32_t size, - const int secure) -{ - /* Set the packet to Linear copy with TMZ set. - */ - packet[0] = htole32(secure << 18 | 1); - packet[1] = htole32(size-1); - packet[2] = htole32(0); - packet[3] = htole32((uint32_t)(src & 0xFFFFFFFFU)); - packet[4] = htole32((uint32_t)(src >> 32)); - packet[5] = htole32((uint32_t)(dst & 0xFFFFFFFFU)); - packet[6] = htole32((uint32_t)(dst >> 32)); -} - -static void amdgpu_sdma_nop(uint32_t *packet, uint32_t nop_count) -{ - /* A packet of the desired number of NOPs. - */ - packet[0] = htole32(nop_count << 16); - for ( ; nop_count > 0; nop_count--) - packet[nop_count-1] = 0; -} - -/** - * amdgpu_bo_lcopy -- linear copy with TMZ set, using sDMA - * @dev: AMDGPU device to which both buffer objects belong to - * @dst: destination buffer object - * @src: source buffer object - * @size: size of memory to move, in bytes. - * @secure: Set to 1 to perform secure copy, 0 for clear - * - * Issues and waits for completion of a Linear Copy with TMZ - * set, to the sDMA engine. @size should be a multiple of - * at least 16 bytes. - */ -static void amdgpu_bo_lcopy(struct command_ctx *ctx, - struct sec_amdgpu_bo *dst, - struct sec_amdgpu_bo *src, - const uint32_t size, - int secure) -{ - struct amdgpu_bo *bos[] = { dst->bo, src->bo }; - uint32_t packet[PACKET_LCOPY_SIZE]; - - amdgpu_sdma_lcopy(packet, - dst->va->address, - src->va->address, - size, secure); - amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context, - AMDGPU_HW_IP_DMA, ctx->ring_id, - ARRAY_SIZE(packet), packet, - ARRAY_SIZE(bos), bos, - &ctx->cs_ibinfo, &ctx->cs_req, - secure == 1); -} - -/** - * amdgpu_bo_move -- Evoke a move of the buffer object (BO) - * @dev: device to which this buffer object belongs to - * @bo: the buffer object to be moved - * @whereto: one of AMDGPU_GEM_DOMAIN_xyz - * @secure: set to 1 to submit secure IBs - * - * Evokes a move of the buffer object @bo to the GEM domain - * descibed by @whereto. - * - * Returns 0 on sucess; -errno on error. - */ -static int amdgpu_bo_move(struct command_ctx *ctx, - struct amdgpu_bo *bo, - uint64_t whereto, - int secure) -{ - struct amdgpu_bo *bos[] = { bo }; - struct drm_amdgpu_gem_op gop = { - .handle = bo->handle, - .op = AMDGPU_GEM_OP_SET_PLACEMENT, - .value = whereto, - }; - uint32_t packet[PACKET_NOP_SIZE]; - int res; - - /* Change the buffer's placement. - */ - res = drmIoctl(ctx->dev->fd, DRM_IOCTL_AMDGPU_GEM_OP, &gop); - if (res) - return -errno; - - /* Now issue a NOP to actually evoke the MM to move - * it to the desired location. - */ - amdgpu_sdma_nop(packet, PACKET_NOP_SIZE); - amdgpu_test_exec_cs_helper_raw(ctx->dev, ctx->context, - AMDGPU_HW_IP_DMA, ctx->ring_id, - ARRAY_SIZE(packet), packet, - ARRAY_SIZE(bos), bos, - &ctx->cs_ibinfo, &ctx->cs_req, - secure == 1); - return 0; -} - -/* Safe, O Sec! - */ -static const uint8_t secure_pattern[] = { 0x5A, 0xFE, 0x05, 0xEC }; - -#define SECURE_BUFFER_SIZE (4 * 1024 * sizeof(secure_pattern)) - -static void amdgpu_secure_bounce(void) -{ - struct sec_amdgpu_bo alice, bob; - struct command_ctx sb_ctx; - long page_size; - uint8_t *pp; - int res; - - page_size = sysconf(_SC_PAGESIZE); - - memset(&sb_ctx, 0, sizeof(sb_ctx)); - sb_ctx.dev = device_handle; - res = amdgpu_cs_ctx_create(sb_ctx.dev, &sb_ctx.context); - if (res) { - PRINT_ERROR(res); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - return; - } - - /* Use the first present ring. - */ - res = ffs(sdma_info.available_rings) - 1; - if (res == -1) { - PRINT_ERROR(-ENOENT); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - goto Out_free_ctx; - } - sb_ctx.ring_id = res; - - /* Allocate a buffer named Alice in VRAM. - */ - res = amdgpu_bo_alloc_map(device_handle, - SECURE_BUFFER_SIZE, - page_size, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_ENCRYPTED, - &alice); - if (res) { - PRINT_ERROR(res); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - return; - } - - /* Fill Alice with a pattern. - */ - for (pp = alice.bo->cpu_ptr; - pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; - pp += sizeof(secure_pattern)) - memcpy(pp, secure_pattern, sizeof(secure_pattern)); - - /* Allocate a buffer named Bob in VRAM. - */ - res = amdgpu_bo_alloc_map(device_handle, - SECURE_BUFFER_SIZE, - page_size, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_ENCRYPTED, - &bob); - if (res) { - PRINT_ERROR(res); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - goto Out_free_Alice; - } - - /* sDMA TMZ copy from Alice to Bob. - */ - amdgpu_bo_lcopy(&sb_ctx, &bob, &alice, SECURE_BUFFER_SIZE, 1); - - /* Move Bob to the GTT domain. - */ - res = amdgpu_bo_move(&sb_ctx, bob.bo, AMDGPU_GEM_DOMAIN_GTT, 0); - if (res) { - PRINT_ERROR(res); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - goto Out_free_all; - } - - /* sDMA TMZ copy from Bob to Alice. - */ - amdgpu_bo_lcopy(&sb_ctx, &alice, &bob, SECURE_BUFFER_SIZE, 1); - - /* Verify the contents of Alice. - */ - for (pp = alice.bo->cpu_ptr; - pp < (__typeof__(pp)) alice.bo->cpu_ptr + SECURE_BUFFER_SIZE; - pp += sizeof(secure_pattern)) { - res = memcmp(pp, secure_pattern, sizeof(secure_pattern)); - if (res) { - fprintf(stderr, SECURE_BOUNCE_FAILED_STR); - CU_FAIL(SECURE_BOUNCE_FAILED_STR); - break; - } - } - -Out_free_all: - amdgpu_bo_unmap_free(&bob, SECURE_BUFFER_SIZE); -Out_free_Alice: - amdgpu_bo_unmap_free(&alice, SECURE_BUFFER_SIZE); -Out_free_ctx: - res = amdgpu_cs_ctx_free(sb_ctx.context); - CU_ASSERT_EQUAL(res, 0); -} - -/* ----------------------------------------------------------------- */ - -static void amdgpu_security_alloc_buf_test(void) -{ - amdgpu_bo_handle bo; - amdgpu_va_handle va_handle; - uint64_t bo_mc; - int r; - - /* Test secure buffer allocation in VRAM */ - bo = gpu_mem_alloc(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_VRAM, - AMDGPU_GEM_CREATE_ENCRYPTED, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test secure buffer allocation in system memory */ - bo = gpu_mem_alloc(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_ENCRYPTED, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); - - /* Test secure buffer allocation in invisible VRAM */ - bo = gpu_mem_alloc(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, - AMDGPU_GEM_CREATE_ENCRYPTED | - AMDGPU_GEM_CREATE_NO_CPU_ACCESS, - &bo_mc, &va_handle); - - r = gpu_mem_free(bo, va_handle, bo_mc, 4096); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_security_gfx_submission_test(void) -{ - amdgpu_command_submission_write_linear_helper_with_secure(device_handle, - AMDGPU_HW_IP_GFX, - true); -} - -static void amdgpu_security_sdma_submission_test(void) -{ - amdgpu_command_submission_write_linear_helper_with_secure(device_handle, - AMDGPU_HW_IP_DMA, - true); -} - -/* ----------------------------------------------------------------- */ - -CU_TestInfo security_tests[] = { - { "allocate secure buffer test", amdgpu_security_alloc_buf_test }, - { "graphics secure command submission", amdgpu_security_gfx_submission_test }, - { "sDMA secure command submission", amdgpu_security_sdma_submission_test }, - { SECURE_BOUNCE_TEST_STR, amdgpu_secure_bounce }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_security_tests_enable(void) -{ - CU_BOOL enable = CU_TRUE; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - - if (!(device_handle->dev_info.ids_flags & AMDGPU_IDS_FLAGS_TMZ)) { - printf("\n\nDon't support TMZ (trust memory zone), security suite disabled\n"); - enable = CU_FALSE; - } - - if ((major_version < 3) || - ((major_version == 3) && (minor_version < 37))) { - printf("\n\nDon't support TMZ (trust memory zone), kernel DRM version (%d.%d)\n", - major_version, minor_version); - printf("is older, security suite disabled\n"); - enable = CU_FALSE; - } - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - return enable; -} - -int suite_security_tests_init(void) -{ - int res; - - res = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (res) { - PRINT_ERROR(res); - return CUE_SINIT_FAILED; - } - - res = amdgpu_query_hw_ip_info(device_handle, - AMDGPU_HW_IP_DMA, - 0, &sdma_info); - if (res) { - PRINT_ERROR(res); - return CUE_SINIT_FAILED; - } - - return CUE_SUCCESS; -} - -int suite_security_tests_clean(void) -{ - int res; - - res = amdgpu_device_deinitialize(device_handle); - if (res) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} diff --git a/tests/amdgpu/shader_code.h b/tests/amdgpu/shader_code.h deleted file mode 100755 index 74d32bb58..000000000 --- a/tests/amdgpu/shader_code.h +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _shader_code_h_ -#define _shader_code_h_ - -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#endif - -enum amdgpu_test_gfx_version { - AMDGPU_TEST_GFX_V9 = 0, - AMDGPU_TEST_GFX_V10, - AMDGPU_TEST_GFX_V11, - AMDGPU_TEST_GFX_MAX, -}; - -enum cs_type { - CS_BUFFERCLEAR = 0, - CS_BUFFERCOPY, - CS_HANG, - CS_HANG_SLOW, -}; - -enum ps_type { - PS_CONST, - PS_TEX, - PS_HANG, - PS_HANG_SLOW -}; - -enum vs_type { - VS_RECTPOSTEXFAST, -}; - -struct reg_info { - uint32_t reg_offset; ///< Memory mapped register offset - uint32_t reg_value; ///< register value -}; - -#include "shader_code_hang.h" -#include "shader_code_gfx9.h" -#include "shader_code_gfx10.h" -#include "shader_code_gfx11.h" - -struct shader_test_cs_shader { - const uint32_t *shader; - uint32_t shader_size; - const struct reg_info *sh_reg; - uint32_t num_sh_reg; - const struct reg_info *context_reg; - uint32_t num_context_reg; -}; - -struct shader_test_ps_shader { - const uint32_t *shader; - unsigned shader_size; - const uint32_t patchinfo_code_size; - const uint32_t *patchinfo_code; - const uint32_t *patchinfo_code_offset; - const struct reg_info *sh_reg; - const uint32_t num_sh_reg; - const struct reg_info *context_reg; - const uint32_t num_context_reg; -}; - -struct shader_test_vs_shader { - const uint32_t *shader; - uint32_t shader_size; - const struct reg_info *sh_reg; - uint32_t num_sh_reg; - const struct reg_info *context_reg; - uint32_t num_context_reg; -}; - -static const struct shader_test_cs_shader shader_test_cs[AMDGPU_TEST_GFX_MAX][2] = { - // gfx9, cs_bufferclear - {{bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}, - // gfx9, cs_buffercopy - {buffercopy_cs_shader_gfx9, sizeof(buffercopy_cs_shader_gfx9), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}}, - // gfx10, cs_bufferclear - {{bufferclear_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}, - // gfx10, cs_buffercopy - {buffercopy_cs_shader_gfx10, sizeof(bufferclear_cs_shader_gfx10), bufferclear_cs_shader_registers_gfx9, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx9)}}, - // gfx11, cs_bufferclear - {{bufferclear_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}, - // gfx11, cs_buffercopy - {buffercopy_cs_shader_gfx11, sizeof(bufferclear_cs_shader_gfx11), bufferclear_cs_shader_registers_gfx11, ARRAY_SIZE(bufferclear_cs_shader_registers_gfx11)}}, -}; - -#define SHADER_PS_INFO(_ps, _n) \ - {ps_##_ps##_shader_gfx##_n, sizeof(ps_##_ps##_shader_gfx##_n), \ - ps_##_ps##_shader_patchinfo_code_size_gfx##_n, \ - ps_##_ps##_shader_patchinfo_code_gfx##_n, \ - ps_##_ps##_shader_patchinfo_offset_gfx##_n, \ - ps_##_ps##_sh_registers_gfx##_n, ps_##_ps##_num_sh_registers_gfx##_n, \ - ps_##_ps##_context_registers_gfx##_n, ps_##_ps##_num_context_registers_gfx##_n} -static const struct shader_test_ps_shader shader_test_ps[AMDGPU_TEST_GFX_MAX][2] = { - {SHADER_PS_INFO(const, 9), SHADER_PS_INFO(tex, 9)}, - {SHADER_PS_INFO(const, 10), SHADER_PS_INFO(tex, 10)}, - {SHADER_PS_INFO(const, 11), SHADER_PS_INFO(tex, 11)}, -}; - -#define SHADER_VS_INFO(_vs, _n) \ - {vs_##_vs##_shader_gfx##_n, sizeof(vs_##_vs##_shader_gfx##_n), \ - vs_##_vs##_sh_registers_gfx##_n, vs_##_vs##_num_sh_registers_gfx##_n, \ - vs_##_vs##_context_registers_gfx##_n, vs_##_vs##_num_context_registers_gfx##_n} -static const struct shader_test_vs_shader shader_test_vs[AMDGPU_TEST_GFX_MAX][1] = { - {SHADER_VS_INFO(RectPosTexFast, 9)}, - {SHADER_VS_INFO(RectPosTexFast, 10)}, - {SHADER_VS_INFO(RectPosTexFast, 11)}, -}; - -struct shader_test_gfx_info { - const uint32_t *preamble_cache; - uint32_t size_preamble_cache; - const uint32_t *cached_cmd; - uint32_t size_cached_cmd; - uint32_t sh_reg_base; - uint32_t context_reg_base; -}; - -#define SHADER_TEST_GFX_INFO(_n) \ - preamblecache_gfx##_n, sizeof(preamblecache_gfx##_n), \ - cached_cmd_gfx##_n, sizeof(cached_cmd_gfx##_n), \ - sh_reg_base_gfx##_n, context_reg_base_gfx##_n - -static struct shader_test_gfx_info shader_test_gfx_info[AMDGPU_TEST_GFX_MAX] = { - {SHADER_TEST_GFX_INFO(9),}, - {SHADER_TEST_GFX_INFO(10),}, - {SHADER_TEST_GFX_INFO(11),}, -}; -#endif diff --git a/tests/amdgpu/shader_code_gfx10.h b/tests/amdgpu/shader_code_gfx10.h deleted file mode 100755 index 4849bbc9b..000000000 --- a/tests/amdgpu/shader_code_gfx10.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _shader_code_gfx10_h_ -#define _shader_code_gfx10_h_ - -static const uint32_t bufferclear_cs_shader_gfx10[] = { - 0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205, - 0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004, - 0xBF810000 -}; - -static const uint32_t buffercopy_cs_shader_gfx10[] = { - 0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201, - 0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000 -}; - -static const uint32_t ps_const_shader_gfx10[] = { - 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203, - 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, - 0xF8001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_const_shader_patchinfo_code_size_gfx10 = 6; - -static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 }, - { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, - { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 } - } -}; - -static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = { - 0x00000004 -}; - -static const uint32_t ps_const_num_sh_registers_gfx10 = 2; - -static const struct reg_info ps_const_sh_registers_gfx10[] = { - {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 }, - {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } -}; - -static const struct reg_info ps_const_context_registers_gfx10[] = -{ - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } -}; - -static const uint32_t ps_const_num_context_registers_gfx10 = 7; - -static const uint32_t ps_tex_shader_gfx10[] = { - 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, - 0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A, - 0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70, - 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, - 0xF8001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = { - 0x0000000C -}; - -static const uint32_t ps_tex_shader_patchinfo_code_size_gfx10 = 6; - -static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 }, - { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, - { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 } - } -}; - -static const struct reg_info ps_tex_sh_registers_gfx10[] = -{ - {0x2C0A, 0xc0081}, //0x020C0080 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0080 }, - {0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } -}; - -static const uint32_t ps_tex_num_sh_registers_gfx10 = 2; - -// Holds Context Register Information -static const struct reg_info ps_tex_context_registers_gfx10[] = -{ - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } -}; - -static const uint32_t ps_tex_num_context_registers_gfx10 = 7; - -static const uint32_t vs_RectPosTexFast_shader_gfx10[] = { - 0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206, - 0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200, - 0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207, - 0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001, - 0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002, - 0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209, - 0xF80008CF, 0x05030100, 0xF800020F, 0x05060402, - 0xBF810000 -}; - -static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] = -{ - {0x2C4A, 0x080C0041 }, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x080C0041 }, - {0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 } -}; - -static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx10 = 2; - -// Holds Context Register Information -static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] = -{ - {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 }, - {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */} -}; - -static const uint32_t vs_RectPosTexFast_num_context_registers_gfx10 = 2; - -static const uint32_t preamblecache_gfx10[] = { - 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, - 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, - 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, - 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0, - 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0, - 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0, - 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0, - 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20, - 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, - 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0, - 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0, - 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, - 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0, - 0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2, - 0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0, - 0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff, - 0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0, - 0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0, - 0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 -}; - -static const uint32_t cached_cmd_gfx10[] = { - 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, - 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, - 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18, - 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, - 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, - 0xc0026900, 0x292, 0x20, 0x6020000, - 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 -}; - -static const uint32_t sh_reg_base_gfx10 = 0x2C00; -static const uint32_t context_reg_base_gfx10 = 0xA000; - -#endif diff --git a/tests/amdgpu/shader_code_gfx11.h b/tests/amdgpu/shader_code_gfx11.h deleted file mode 100755 index d9ee0a7c2..000000000 --- a/tests/amdgpu/shader_code_gfx11.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _shader_code_gfx11_h_ -#define _shader_code_gfx11_h_ - -static const uint32_t bufferclear_cs_shader_gfx11[] = { - 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF, - 0x7E020205, 0x7E040206, 0x7E060207, 0xBF870004, - 0xD6460004, 0x04010C08, 0x7E000204, 0xE01C0000, - 0x80800004, 0xBFB60003, 0xBFB00000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000 -}; - -static const struct reg_info bufferclear_cs_shader_registers_gfx11[] = { - {0x2e12, 0x600C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x600C0041 }, - {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 }, - {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 }, - {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 }, - {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 } -}; - -static const uint32_t buffercopy_cs_shader_gfx11[] = { - 0xB0802006, 0xBF840003, 0x360000FF, 0x000003FF, - 0xBF870001, 0xD6460001, 0x04010C08, 0xE00C0000, - 0x80800201, 0xBF8903F7, 0xE01C0000, 0x80810201, - 0xBFB60003, 0xBFB00000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000 -}; - -static const uint32_t ps_const_shader_gfx11[] = { - 0xB0802006, 0xBF840003, 0x7E000200, 0x7E020201, - 0x7E040202, 0x7E060203, 0x5E000300, 0x5E020702, - 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100, - 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000 -}; - -static const uint32_t ps_const_shader_patchinfo_code_size_gfx11 = 6; - -static const uint32_t ps_const_shader_patchinfo_code_gfx11[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR - { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR - { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR - { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR - { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR - { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR - } -}; - -static const uint32_t ps_const_shader_patchinfo_offset_gfx11[] = { - 0x00000006 -}; - -static const uint32_t ps_const_num_sh_registers_gfx11 = 2; - -static const struct reg_info ps_const_sh_registers_gfx11[] = { - {0x2C0A, 0x020C0000}, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0000 }, - {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } -}; - -static const struct reg_info ps_const_context_registers_gfx11[] = { - {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000000 }, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, - {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004 }, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } -}; - -static const uint32_t ps_const_num_context_registers_gfx11 = 7; - -static const uint32_t ps_tex_shader_gfx11[] = -{ - 0xB0802006, 0xBF840003, 0xBEFD000C, 0xBE8E017E, - 0xBEFE1D7E, 0xCE000003, 0xCE000102, 0xCD000104, - 0x040E0103, 0xCD000000, 0x040A0102, 0xBF870112, - 0xCD010703, 0x04120303, 0xCD010700, 0x04020302, - 0x8BFE0E7E, 0xF06C0F05, 0x08000003, 0x00000000, - 0xBEFE010E, 0xBF8903F7, 0x5E000300, 0x5E020702, - 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100, - 0xBFB00000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000 -}; - -static const uint32_t ps_tex_shader_patchinfo_offset_gfx11[] = -{ - 0x00000016 -}; - -// Denotes the Patch Info Code Length -static const uint32_t ps_tex_shader_patchinfo_code_size_gfx11 = 6; - -static const uint32_t ps_tex_shader_patchinfo_code_gfx11[][10][6] = -{ - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000890, 0x00000000 }, // SI_EXPORT_FMT_ZERO - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000801, 0x00000000 }, // SI_EXPORT_FMT_32_R - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_32_GR - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000300 }, // SI_EXPORT_FMT_32_AR - { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_FP16_ABGR - { 0xD7220000, 0x00020300, 0xD7220001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_UNORM16_ABGR - { 0xD7210000, 0x00020300, 0xD7210001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SNORM16_ABGR - { 0xD7230000, 0x00020300, 0xD7230001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_uint32_t16_ABGR - { 0xD7240000, 0x00020300, 0xD7240001, 0x00020702, 0xF8000803, 0x00000100 }, // SI_EXPORT_FMT_SINT16_ABGR - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800080F, 0x03020100 } // SI_EXPORT_FMT_32_ABGR - } -}; -// Holds Sh Register Information -static const struct reg_info ps_tex_sh_registers_gfx11[] = -{ - {0x2C0A, 0x020C0081 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0081 }, - {0x2C0B, 0x00000018 } //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } -}; - -static const uint32_t ps_tex_num_sh_registers_gfx11 = 2; - -// Holds Context Register Information -static const struct reg_info ps_tex_context_registers_gfx11[] = -{ - {0xA1B4, 0x00000002 }, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000001 }, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, - {0xA08F, 0x0000000F }, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010 }, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000 }, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000 }, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004 } //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } -}; - -static const uint32_t ps_tex_num_context_registers_gfx11 = 7; - - -static const uint32_t vs_RectPosTexFast_shader_gfx11[] = -{ - 0xB0802006, 0xBEFE01C1, 0xBF840003, 0xF408050A, - 0xF80000B0, 0xD71F0001, 0x000100C1, 0x9300FF03, - 0x00040018, 0x9301FF02, 0x0009000C, 0xBF870091, - 0xD7200001, 0x000202C1, 0xD60B0001, 0x04058000, - 0xBF870001, 0xD4490000, 0x00000301, 0xBE862100, - 0x7E040B05, 0xBFA5001C, 0x7E06020A, 0x7E08020E, - 0x7E0A020F, 0xBF8701B4, 0x060404F3, 0x7E140211, - 0x7E0E0210, 0x7C240480, 0x060404F3, 0xD5010003, - 0x01AA0608, 0xD5010004, 0x01AA080C, 0xBF870003, - 0xD4120012, 0x00010102, 0x7E04020B, 0xBEEA1F12, - 0xBF870483, 0xD5010008, 0x01AA080C, 0xD5010006, - 0x01AA0608, 0xBF870003, 0xD5010004, 0x004A0409, - 0xD5010009, 0x004A0A0D, 0xBEFE0106, 0x9302FF02, - 0x00090016, 0xBF870009, 0xD4C9007E, 0x00000501, - 0xBFA50002, 0xF8000941, 0x00000000, 0xBF89FFF0, - 0x8BFE0006, 0xD71F0000, 0x000100C1, 0xBFA50013, - 0x7E1602F2, 0x9300FF03, 0x00040018, 0x8B01FF05, - 0x00007FFF, 0xBF8704B2, 0xD7200000, 0x000200C1, - 0x7E0202F2, 0x84018901, 0x80018001, 0xBF870002, - 0xD60B0000, 0x04018000, 0xF80008CF, 0x01070406, - 0xBF89FC07, 0xE0744000, 0x01850800, 0xBFB00000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, - 0xBF9F0000, 0xBF9F0000, 0xBF9F0000, 0xBF9F0000 -}; - -static const struct reg_info vs_RectPosTexFast_sh_registers_gfx11[] = -{ - {0x2C8A, 0x020C00C2}, //{ mmSPI_SHADER_PGM_RSRC1_GS, 0x020C00C2 }, - {0x2C8B, 0x0008001C}, //{ mmSPI_SHADER_PGM_RSRC2_GS, 0x0008001C } -}; - -static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx11 = 2; - -// Holds Context Register Information -static const struct reg_info vs_RectPosTexFast_context_registers_gfx11[] = -{ - {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 }, - {0xA1C2, 0x00000001}, //{ mmSPI_SHADER_IDX_FORMAT, 0x00000001 }, - {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */}, - {0xA2E4, 0x00000000}, //{ mmVGT_GS_INSTANCE_CNT, 0x00000000 }, - {0xA2AB, 0x00000004}, //{ mmVGT_ESGS_RING_ITEMSIZE, 0x00000004 }, - {0xA2CE, 0x00000001}, //{ mmVGT_GS_MAX_VERT_OUT, 0x00000001 } -}; - -static const uint32_t vs_RectPosTexFast_num_context_registers_gfx11 = 6; - -static const uint32_t preamblecache_gfx11[] = { - 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, - 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, - 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, 0xc0016900, 0x208, 0x0, - 0xc0016900, 0x2a1, 0x0, 0xc0016900, 0x2ad, 0x0, 0xc0016900, 0x2dc, 0x0, - 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xc0046900, 0x310, 0x0, 0x3, 0x0, 0x100000, 0xc0016900, 0x349, 0x0, - 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, 0xc0016900, 0x376, 0x0, - 0xc0016900, 0x385, 0x0, 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x204, 0x90000, 0x4, 0xc0016900, 0x20c, 0x0, 0xc0026900, 0x20e, 0x0, 0x0, - 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, - 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0x0, 0xc0016900, 0x2a6, 0x0, - 0xc0016900, 0x210, 0x0, 0xc0016900, 0x2db, 0x0, 0xc0016900, 0x2e4, 0x0, - 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x0, 0xc0016900, 0x206, 0x300, - 0xc0016900, 0x212, 0x200, 0xc0016900, 0xf4, 0x0, 0xc0016900, 0x18, 0x0, - 0xc0016900, 0x1d4, 0xff, 0xc0016900, 0x2ce, 0x1, 0xc0016900, 0x2d3, 0x20001, - 0xc0016900, 0x1ff, 0x80, 0xc0016900, 0x2d5, 0x6012010, 0xc0017a00, 0x20000243, 0x0, - 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, 0xc0017900, 0x24b, 0x0, - 0xc0017900, 0x259, 0xffffffff, 0xc0017900, 0x25f, 0x0, 0xc0017900, 0x260, 0x0, - 0xc0017900, 0x262, 0x0, 0xc0017900, 0x444, 0x0, 0xc0017900, 0x445, 0x0, - 0xc0017600, 0x6, 0x0, 0xc0017600, 0x80, 0x0, 0xc0017600, 0xb0, 0x0, - 0xc0047600, 0xb2, 0x0, 0x0, 0x0, 0x0, 0xc0017600, 0x30, 0x0, - 0xc0047600, 0x32, 0x0, 0x0, 0x0, 0x0 -}; - -static const uint32_t cached_cmd_gfx11[] = { - 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, - 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, - 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, - 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, - 0xc0026900, 0x292, 0x20, 0x6020000, - 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0, - 0xc0046900, 0x1d5, 0x0, 0x0, 0x0, 0x0, 0xc0016900, 0x104, 0x4a00005, - 0xc0016900, 0x1f, 0xf2a0055, 0xc0017900, 0x266, 0x4 -}; -static const uint32_t sh_reg_base_gfx11 = 0x2C00; -static const uint32_t context_reg_base_gfx11 = 0xA000; - -#endif diff --git a/tests/amdgpu/shader_code_gfx9.h b/tests/amdgpu/shader_code_gfx9.h deleted file mode 100755 index 3ad1ca8fb..000000000 --- a/tests/amdgpu/shader_code_gfx9.h +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _shader_code_gfx9_h_ -#define _shader_code_gfx9_h_ - -static const uint32_t bufferclear_cs_shader_gfx9[] = { - 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, - 0x7e020280, 0x7e040204, 0x7e060205, 0x7e080206, - 0x7e0a0207, 0xe01c2000, 0x80000200, 0xbf8c0000, - 0xbf810000 -}; - -static const struct reg_info bufferclear_cs_shader_registers_gfx9[] = { - {0x2e12, 0x000C0041}, //{ mmCOMPUTE_PGM_RSRC1, 0x000C0041 }, - {0x2e13, 0x00000090}, //{ mmCOMPUTE_PGM_RSRC2, 0x00000090 }, - {0x2e07, 0x00000040}, //{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 }, - {0x2e08, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 }, - {0x2e09, 0x00000001}, //{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 } -}; - -static const uint32_t buffercopy_cs_shader_gfx9[] = { - 0x260000ff, 0x000003ff, 0xd1fd0000, 0x04010c08, - 0x7e020280, 0xe00c2000, 0x80000200, 0xbf8c0f70, - 0xe01c2000, 0x80010200, 0xbf810000 -}; - -static const uint32_t ps_const_shader_gfx9[] = { - 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203, - 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, - 0xC4001C0F, 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_const_shader_patchinfo_code_size_gfx9 = 6; - -static const uint32_t ps_const_shader_patchinfo_code_gfx9[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000300 }, - { 0xD2960000, 0x00020300, 0xD2960001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2950000, 0x00020300, 0xD2950001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2940000, 0x00020300, 0xD2940001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2970000, 0x00020300, 0xD2970001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xD2980000, 0x00020300, 0xD2980001, 0x00020702, 0xC4001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x03020100 } - } -}; - -static const uint32_t ps_const_shader_patchinfo_offset_gfx9[] = { - 0x00000004 -}; - -static const uint32_t ps_const_num_sh_registers_gfx9 = 2; - -static const struct reg_info ps_const_sh_registers_gfx9[] = { - {0x2C0A, 0x000C0040},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0040 }, - {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } -}; - -static const uint32_t ps_const_num_context_registers_gfx9 = 7; - -static const struct reg_info ps_const_context_registers_gfx9[] = { - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 } -}; - -static const uint32_t ps_tex_shader_gfx9[] = { - 0xBEFC000C, 0xBE8E017E, 0xBEFE077E, 0xD4180000, - 0xD4190001, 0xD41C0100, 0xD41D0101, 0xF0800F00, - 0x00400206, 0xBEFE010E, 0xBF8C0F70, 0xD2960000, - 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, - 0x00000100, 0xBF810000 -}; - -static const uint32_t ps_tex_shader_patchinfo_offset_gfx9[] = { - 0x0000000B -}; - -static const uint32_t ps_tex_shader_patchinfo_code_size_gfx9 = 6; - -static const uint32_t ps_tex_shader_patchinfo_code_gfx9[][10][6] = { - {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001890, 0x00000000 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001801, 0x00000002 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000302 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC4001803, 0x00000502 }, - { 0xD2960000, 0x00020702, 0xD2960001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2950000, 0x00020702, 0xD2950001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2940000, 0x00020702, 0xD2940001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2970000, 0x00020702, 0xD2970001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xD2980000, 0x00020702, 0xD2980001, 0x00020B04, 0xC4001C0F, 0x00000100 }, - { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xC400180F, 0x05040302 } - } -}; - -static const uint32_t ps_tex_num_sh_registers_gfx9 = 2; -static const struct reg_info ps_tex_sh_registers_gfx9[] = { - {0x2C0A, 0x000C0081},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0081 }, - {0x2C0B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } -}; - -static const uint32_t ps_tex_num_context_registers_gfx9 = 7; - -static const struct reg_info ps_tex_context_registers_gfx9[] = { - {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, - {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, - {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, - {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, - {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, - {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, - {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 } -}; - -static const uint32_t vs_RectPosTexFast_shader_gfx9[] = { - 0x7E000B00, 0x020000F3, 0xD042000A, 0x00010100, - 0x7E020202, 0x7E040200, 0x020000F3, 0x7E060206, - 0x7E080204, 0xD1000001, 0x002A0302, 0x7C840080, - 0x7E000200, 0x7E040203, 0x7E0A0201, 0xD1000003, - 0x002A0704, 0x7E0C0207, 0x7E0E0205, 0x00000101, - 0x00020505, 0x7E040208, 0x7E0A02F2, 0x00060903, - 0x00080D07, 0x7E0C0209, 0xC40008CF, 0x05020100, - 0xC400020F, 0x05060403, 0xBF810000 -}; - -static const struct reg_info vs_RectPosTexFast_sh_registers_gfx9[] = -{ - {0x2C4A, 0x000C0081}, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x000C0081 }, - {0x2C4B, 0x00000018}, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 } -}; - -static const uint32_t vs_RectPosTexFast_num_sh_registers_gfx9 = 2; - -// Holds Context Register Information -static const struct reg_info vs_RectPosTexFast_context_registers_gfx9[] = -{ - {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 }, - {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */} -}; - -static const uint32_t vs_RectPosTexFast_num_context_registers_gfx9 = 2; - -static const uint32_t preamblecache_gfx9[] = { - 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, - 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, - 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, - 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0, - 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0, - 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0, - 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0, - 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, - 0xc0036900, 0x311, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0x1e, 0x20, - 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, - 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x19, 0x0, - 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, - 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0, - 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, - 0xc0016900, 0x314, 0x0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0, - 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, - 0xc0016900, 0x18, 0x2, 0xc0016900, 0x206, 0x300, 0xc0017900, 0x20000243, 0x0, - 0xc0017900, 0x248, 0xffffffff, 0xc0017900, 0x249, 0x0, 0xc0017900, 0x24a, 0x0, - 0xc0017900, 0x24b, 0x0 -}; - -static const uint32_t cached_cmd_gfx9[] = { - 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, - 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, - 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, - 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x12, - 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, - 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, - 0xc0026900, 0x292, 0x20, 0x60201b8, - 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 -}; - -static const uint32_t sh_reg_base_gfx9 = 0x2C00; -static const uint32_t context_reg_base_gfx9 = 0xA000; - -#endif diff --git a/tests/amdgpu/shader_code_hang.h b/tests/amdgpu/shader_code_hang.h deleted file mode 100755 index 070bd7186..000000000 --- a/tests/amdgpu/shader_code_hang.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright 2022 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _shader_code_hang_h_ -#define _shader_code_hang_h_ - -static const unsigned int memcpy_shader_hang[] = { - 0xFFFFFFFF, 0xBEFE0A7E, 0xBEFC0304, 0xC0C20100, - 0xC0800300, 0xC8080000, 0xC80C0100, 0xC8090001, - 0xC80D0101, 0xBF8C007F, 0xF0800F00, 0x00010002, - 0xBEFE040C, 0xBF8C0F70, 0xBF800000, 0xBF800000, - 0xF800180F, 0x03020100, 0xBF810000 -}; - -struct shader_test_shader_bin { - const uint32_t *shader; - uint32_t header_length; - uint32_t body_length; - uint32_t foot_length; -}; - -static const unsigned int memcpy_cs_hang_slow_ai_codes[] = { - 0xd1fd0000, 0x04010c08, 0xe00c2000, 0x80000100, - 0xbf8c0f70, 0xe01c2000, 0x80010100, 0xbf810000 -}; - -static struct shader_test_shader_bin memcpy_cs_hang_slow_ai = { - memcpy_cs_hang_slow_ai_codes, 4, 3, 1 -}; - -static const unsigned int memcpy_cs_hang_slow_rv_codes[] = { - 0x8e00860c, 0x32000000, 0xe00c2000, 0x80010100, - 0xbf8c0f70, 0xe01c2000, 0x80020100, 0xbf810000 -}; - -static struct shader_test_shader_bin memcpy_cs_hang_slow_rv = { - memcpy_cs_hang_slow_rv_codes, 4, 3, 1 -}; - -static const unsigned int memcpy_cs_hang_slow_nv_codes[] = { - 0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100, - 0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000 -}; - -static struct shader_test_shader_bin memcpy_cs_hang_slow_nv = { - memcpy_cs_hang_slow_nv_codes, 4, 3, 1 -}; - - -static const unsigned int memcpy_ps_hang_slow_ai_codes[] = { - 0xbefc000c, 0xbe8e017e, 0xbefe077e, 0xd4080000, - 0xd4090001, 0xd40c0100, 0xd40d0101, 0xf0800f00, - 0x00400002, 0xbefe010e, 0xbf8c0f70, 0xbf800000, - 0xbf800000, 0xbf800000, 0xbf800000, 0xc400180f, - 0x03020100, 0xbf810000 -}; - -static struct shader_test_shader_bin memcpy_ps_hang_slow_ai = { - memcpy_ps_hang_slow_ai_codes, 7, 2, 9 -}; - -static const unsigned int memcpy_ps_hang_slow_navi10_codes[] = { - 0xBEFC030C,0xBE8E047E,0xBEFE0A7E,0xC8080000, - 0xC80C0100,0xC8090001,0xC80D0101,0xF0800F0A, - 0x00400402,0x00000003,0xBEFE040E,0xBF8C0F70, - 0xBF800000,0xBF800000,0xBF800000,0xBF800000, - 0xF800180F,0x07060504,0xBF810000 -}; - -static struct shader_test_shader_bin memcpy_ps_hang_slow_navi10 = { - memcpy_ps_hang_slow_navi10_codes, 7, 3, 9 -}; - -static const unsigned int memcpy_ps_hang_slow_navi21_codes[] = { - 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, 0xC8000100, 0xC8090001, 0xC8010101, 0x87FE0E7E, // header - 0xF0800F0A, 0x00400002, 0x00000000, // body - image_sample instruction - 0xBFA3FFE3, 0xBEFE040E, 0xBF8C3F70, 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100, 0xBF810000 // footer -}; - -static struct shader_test_shader_bin memcpy_ps_hang_slow_navi21 = { - memcpy_ps_hang_slow_navi21_codes, 8, 3, 10 -}; - -#endif diff --git a/tests/amdgpu/shader_test_util.c b/tests/amdgpu/shader_test_util.c deleted file mode 100755 index 60148fb8f..000000000 --- a/tests/amdgpu/shader_test_util.c +++ /dev/null @@ -1,2156 +0,0 @@ -#include -#include -#include -#include -#include -#include - -#include "CUnit/Basic.h" -#include "amdgpu_test.h" -#include "shader_code.h" - -#define PACKET3_DISPATCH_DIRECT 0x15 -#define PACKET3_CONTEXT_CONTROL 0x28 -#define PACKET3_DRAW_INDEX_AUTO 0x2D -#define PACKET3_SET_CONTEXT_REG 0x69 -#define PACKET3_SET_SH_REG 0x76 -#define PACKET3_SET_SH_REG_OFFSET 0x77 -#define PACKET3_SET_UCONFIG_REG 0x79 -#define PACKET3_SET_SH_REG_INDEX 0x9B - -#define PACKET_TYPE3 3 -#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ - (((op) & 0xFF) << 8) | \ - ((n) & 0x3FFF) << 16) -#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1) - - -struct shader_test_bo { - amdgpu_bo_handle bo; - unsigned size; - unsigned heap; - void *ptr; - uint64_t mc_address; - amdgpu_va_handle va; -}; - -struct shader_test_draw { - struct shader_test_bo ps_bo; - enum ps_type ps_type; - struct shader_test_bo vs_bo; - enum vs_type vs_type; -}; -struct shader_test_dispatch { - struct shader_test_bo cs_bo; - enum cs_type cs_type; -}; - -struct shader_test_info { - amdgpu_device_handle device_handle; - enum amdgpu_test_gfx_version version; - unsigned ip; - unsigned ring; - int hang; - int hang_slow; -}; - -struct shader_test_priv { - const struct shader_test_info *info; - unsigned cmd_curr; - - union { - struct shader_test_draw shader_draw; - struct shader_test_dispatch shader_dispatch; - }; - struct shader_test_bo vtx_attributes_mem; - struct shader_test_bo cmd; - struct shader_test_bo src; - struct shader_test_bo dst; -}; - -static int shader_test_bo_alloc(amdgpu_device_handle device_handle, - struct shader_test_bo *shader_test_bo) -{ - return amdgpu_bo_alloc_and_map(device_handle, shader_test_bo->size, 4096, - shader_test_bo->heap, 0, - &(shader_test_bo->bo), (void **)&(shader_test_bo->ptr), - &(shader_test_bo->mc_address), &(shader_test_bo->va)); -} - -static int shader_test_bo_free(struct shader_test_bo *shader_test_bo) -{ - return amdgpu_bo_unmap_and_free(shader_test_bo->bo, shader_test_bo->va, - shader_test_bo->mc_address, - shader_test_bo->size); -} - -void shader_test_for_each(amdgpu_device_handle device_handle, unsigned ip, - void (*fn)(struct shader_test_info *test_info)) -{ - int r; - uint32_t ring_id; - struct shader_test_info test_info = {0}; - struct drm_amdgpu_info_hw_ip info = {0}; - - r = amdgpu_query_hw_ip_info(device_handle, ip, 0, &info); - CU_ASSERT_EQUAL(r, 0); - if (!info.available_rings) { - printf("SKIP ... as there's no %s ring\n", - (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute"); - return; - } - - switch (info.hw_ip_version_major) { - case 9: - test_info.version = AMDGPU_TEST_GFX_V9; - break; - case 10: - test_info.version = AMDGPU_TEST_GFX_V10; - break; - case 11: - test_info.version = AMDGPU_TEST_GFX_V11; - break; - default: - printf("SKIP ... unsupported gfx version %d\n", info.hw_ip_version_major); - return; - } - - test_info.device_handle = device_handle; - test_info.ip = ip; - - printf("\n"); - for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) { - printf("%s ring %d\n", (ip == AMDGPU_HW_IP_GFX) ? "graphics": "compute", - ring_id); - test_info.ring = ring_id; - fn(&test_info); - } -} - -static void write_context_control(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - if (test_priv->info->ip == AMDGPU_HW_IP_GFX) { - ptr[i++] = PACKET3(PACKET3_CONTEXT_CONTROL, 1); - ptr[i++] = 0x80000000; - ptr[i++] = 0x80000000; - } - - test_priv->cmd_curr = i; -} - -static void shader_test_load_shader_hang_slow(struct shader_test_bo *shader_bo, - struct shader_test_shader_bin *shader_bin) -{ - int i, j, loop; - - loop = (shader_bo->size / sizeof(uint32_t) - shader_bin->header_length - - shader_bin->foot_length) / shader_bin->body_length; - - memcpy(shader_bo->ptr, shader_bin->shader, shader_bin->header_length * sizeof(uint32_t)); - - j = shader_bin->header_length; - for (i = 0; i < loop; i++) { - memcpy(shader_bo->ptr + j, - shader_bin->shader + shader_bin->header_length, - shader_bin->body_length * sizeof(uint32_t)); - j += shader_bin->body_length; - } - - memcpy(shader_bo->ptr + j, - shader_bin->shader + shader_bin->header_length + shader_bin->body_length, - shader_bin->foot_length * sizeof(uint32_t)); -} - -static void amdgpu_dispatch_load_cs_shader_hang_slow(struct shader_test_priv *test_priv) -{ - struct amdgpu_gpu_info gpu_info = {0}; - struct shader_test_shader_bin *cs_shader_bin; - int r; - - r = amdgpu_query_gpu_info(test_priv->info->device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - switch (gpu_info.family_id) { - case AMDGPU_FAMILY_AI: - cs_shader_bin = &memcpy_cs_hang_slow_ai; - break; - case AMDGPU_FAMILY_RV: - cs_shader_bin = &memcpy_cs_hang_slow_rv; - break; - default: - cs_shader_bin = &memcpy_cs_hang_slow_nv; - break; - } - - shader_test_load_shader_hang_slow(&test_priv->shader_dispatch.cs_bo, cs_shader_bin); -} - -static void amdgpu_dispatch_load_cs_shader(struct shader_test_priv *test_priv) -{ - if (test_priv->info->hang) { - if (test_priv->info->hang_slow) - amdgpu_dispatch_load_cs_shader_hang_slow(test_priv); - else - memcpy(test_priv->shader_dispatch.cs_bo.ptr, memcpy_shader_hang, - sizeof(memcpy_shader_hang)); - } else { - memcpy(test_priv->shader_dispatch.cs_bo.ptr, - shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type].shader, - shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type].shader_size); - } -} - -static void amdgpu_dispatch_init_gfx9(struct shader_test_priv *test_priv) -{ - int i; - uint32_t *ptr = test_priv->cmd.ptr; - - /* Write context control and load shadowing register if necessary */ - write_context_control(test_priv); - - i = test_priv->cmd_curr; - - /* Issue commands to set default compute state. */ - /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 3); - ptr[i++] = 0x204; - i += 3; - - /* clear mmCOMPUTE_TMPRING_SIZE */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x218; - ptr[i++] = 0; - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_init_gfx10(struct shader_test_priv *test_priv) -{ - int i; - uint32_t *ptr = test_priv->cmd.ptr; - - amdgpu_dispatch_init_gfx9(test_priv); - - i = test_priv->cmd_curr; - - /* mmCOMPUTE_SHADER_CHKSUM */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x22a; - ptr[i++] = 0; - /* mmCOMPUTE_REQ_CTRL */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 6); - ptr[i++] = 0x222; - i += 6; - /* mmCP_COHER_START_DELAY */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x7b; - ptr[i++] = 0x20; - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_init_gfx11(struct shader_test_priv *test_priv) -{ - int i; - uint32_t *ptr = test_priv->cmd.ptr; - - /* Write context control and load shadowing register if necessary */ - write_context_control(test_priv); - - i = test_priv->cmd_curr; - - /* Issue commands to set default compute state. */ - /* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 3); - ptr[i++] = 0x204; - i += 3; - - /* clear mmCOMPUTE_TMPRING_SIZE */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x218; - ptr[i++] = 0; - - /* mmCOMPUTE_REQ_CTRL */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x222; - ptr[i++] = 0; - - /* mmCOMPUTE_USER_ACCUM_0 .. 3*/ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x224; - i += 4; - - /* mmCOMPUTE_SHADER_CHKSUM */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x22a; - ptr[i++] = 0; - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_init(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - amdgpu_dispatch_init_gfx9(test_priv); - break; - case AMDGPU_TEST_GFX_V10: - amdgpu_dispatch_init_gfx10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_dispatch_init_gfx11(test_priv); - break; - } -} - -static void amdgpu_dispatch_write_cumask(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - /* Issue commands to set cu mask used in current dispatch */ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x216; - ptr[i++] = 0xffffffff; - ptr[i++] = 0xffffffff; - /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x219; - ptr[i++] = 0xffffffff; - ptr[i++] = 0xffffffff; - break; - case AMDGPU_TEST_GFX_V10: - case AMDGPU_TEST_GFX_V11: - /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG_INDEX, 2); - ptr[i++] = 0x30000216; - ptr[i++] = 0xffffffff; - ptr[i++] = 0xffffffff; - /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG_INDEX, 2); - ptr[i++] = 0x30000219; - ptr[i++] = 0xffffffff; - ptr[i++] = 0xffffffff; - break; - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_write2hw_gfx9(struct shader_test_priv *test_priv) -{ - const struct shader_test_cs_shader *cs_shader = &shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type]; - int j, i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address; - - /* Writes shader state to HW */ - /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x20c; - ptr[i++] = (shader_addr >> 8); - ptr[i++] = (shader_addr >> 40); - /* write sh regs*/ - for (j = 0; j < cs_shader->num_sh_reg; j++) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - /* - Gfx9ShRegBase */ - ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[test_priv->info->version].sh_reg_base; - ptr[i++] = cs_shader->sh_reg[j].reg_value; - } - - /* Write constant data */ - if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x74fac; - - /* Sets a range of pixel shader constants */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - } else { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->src.mc_address; - ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->src.size / 16; - ptr[i++] = 0x74fac; - - /* Writes the UAV constant data to the SGPRs. */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x74fac; - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_write2hw_gfx10(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_cs_shader *cs_shader = &shader_test_cs[test_priv->info->version][test_priv->shader_dispatch.cs_type]; - int j; - uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address; - - /* Writes shader state to HW */ - /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x20c; - ptr[i++] = (shader_addr >> 8); - ptr[i++] = (shader_addr >> 40); - /* write sh regs*/ - for (j = 0; j < cs_shader->num_sh_reg; j++) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - /* - Gfx9ShRegBase */ - ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[test_priv->info->version].sh_reg_base; - ptr[i++] = cs_shader->sh_reg[j].reg_value; - } - - /* mmCOMPUTE_PGM_RSRC3 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x228; - ptr[i++] = 0; - - if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x1104bfac; - - /* Sets a range of pixel shader constants */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - } else { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->src.mc_address; - ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->src.size / 16; - ptr[i++] = 0x1104bfac; - - /* Writes the UAV constant data to the SGPRs. */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address>> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x1104bfac; - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_write2hw_gfx11(struct shader_test_priv *test_priv) -{ - enum amdgpu_test_gfx_version version = test_priv->info->version; - const struct shader_test_cs_shader *cs_shader = &shader_test_cs[version][test_priv->shader_dispatch.cs_type]; - int j, i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - uint64_t shader_addr = test_priv->shader_dispatch.cs_bo.mc_address; - - /* Writes shader state to HW */ - /* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x20c; - ptr[i++] = (shader_addr >> 8); - ptr[i++] = (shader_addr >> 40); - - /* write sh regs*/ - for (j = 0; j < cs_shader->num_sh_reg; j++) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - /* - Gfx9ShRegBase */ - ptr[i++] = cs_shader->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base; - ptr[i++] = cs_shader->sh_reg[j].reg_value; - if (cs_shader->sh_reg[j].reg_offset == 0x2E12) - ptr[i-1] &= ~(1<<29); - } - - /* mmCOMPUTE_PGM_RSRC3 */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x228; - ptr[i++] = 0x3f0; - - /* Write constant data */ - /* Writes the texture resource constants data to the SGPRs */ - if (CS_BUFFERCLEAR == test_priv->shader_dispatch.cs_type) { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x1003dfac; - - /* Sets a range of pixel shader constants */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - ptr[i++] = 0x22222222; - } else { - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x240; - ptr[i++] = test_priv->src.mc_address; - ptr[i++] = (test_priv->src.mc_address >> 32) | 0x100000; - ptr[i++] = test_priv->src.size / 16; - ptr[i++] = 0x1003dfac; - - /* Writes the UAV constant data to the SGPRs. */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x244; - ptr[i++] = test_priv->dst.mc_address; - ptr[i++] = (test_priv->dst.mc_address>> 32) | 0x100000; - ptr[i++] = test_priv->dst.size / 16; - ptr[i++] = 0x1003dfac; - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_dispatch_write2hw(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - amdgpu_dispatch_write2hw_gfx9(test_priv); - break; - case AMDGPU_TEST_GFX_V10: - amdgpu_dispatch_write2hw_gfx10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_dispatch_write2hw_gfx11(test_priv); - break; - } -} - -static void amdgpu_dispatch_write_dispatch_cmd(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - /* clear mmCOMPUTE_RESOURCE_LIMITS */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x215; - ptr[i++] = 0; - - /* dispatch direct command */ - ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3); - ptr[i++] = (test_priv->dst.size / 16 + 0x40 - 1 ) / 0x40;//0x10; - ptr[i++] = 1; - ptr[i++] = 1; - ptr[i++] = 1; - - test_priv->cmd_curr = i; -} -static void amdgpu_test_dispatch_memset(struct shader_test_info *test_info) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle resources[3]; - struct shader_test_priv test_priv; - struct shader_test_bo *cmd = &(test_priv.cmd); - struct shader_test_bo *dst = &(test_priv.dst); - struct shader_test_bo *shader = &(test_priv.shader_dispatch.cs_bo); - uint32_t *ptr_cmd; - uint8_t *ptr_dst; - int i, r; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info= {0}; - amdgpu_bo_list_handle bo_list; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - uint8_t cptr[16]; - - memset(&test_priv, 0, sizeof(test_priv)); - test_priv.info = test_info; - test_priv.shader_dispatch.cs_type = CS_BUFFERCLEAR; - r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - cmd->size = 4096; - cmd->heap = AMDGPU_GEM_DOMAIN_GTT; - r = shader_test_bo_alloc(test_info->device_handle, cmd); - CU_ASSERT_EQUAL(r, 0); - ptr_cmd = cmd->ptr; - memset(ptr_cmd, 0, cmd->size); - - shader->size = 4096; - shader->heap = AMDGPU_GEM_DOMAIN_VRAM; - r = shader_test_bo_alloc(test_info->device_handle, shader); - CU_ASSERT_EQUAL(r, 0); - memset(shader->ptr, 0, shader->size); - amdgpu_dispatch_load_cs_shader(&test_priv); - - dst->size = 0x4000; - dst->heap = AMDGPU_GEM_DOMAIN_VRAM; - r = shader_test_bo_alloc(test_info->device_handle, dst); - CU_ASSERT_EQUAL(r, 0); - - amdgpu_dispatch_init(&test_priv); - - /* Issue commands to set cu mask used in current dispatch */ - amdgpu_dispatch_write_cumask(&test_priv); - - /* Writes shader state to HW */ - amdgpu_dispatch_write2hw(&test_priv); - - amdgpu_dispatch_write_dispatch_cmd(&test_priv); - - i = test_priv.cmd_curr; - while (i & 7) - ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ - test_priv.cmd_curr = i; - - resources[0] = dst->bo; - resources[1] = shader->bo; - resources[2] = cmd->bo; - r = amdgpu_bo_list_create(test_info->device_handle, 3, resources, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ib_info.ib_mc_address = cmd->mc_address; - ib_info.size = test_priv.cmd_curr; - ibs_request.ip_type = test_info->ip; - ibs_request.ring = test_info->ring; - ibs_request.resources = bo_list; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - /* submit CS */ - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - fence_status.ip_type = test_info->ip; - fence_status.ip_instance = 0; - fence_status.ring = test_info->ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request.seq_no; - - /* wait for IB accomplished */ - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - /* verify if memset test result meets with expected */ - i = 0; - ptr_dst = (uint8_t *)(dst->ptr); - memset(cptr, 0x22, 16); - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - i = dst->size - 16; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - i = dst->size / 2; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - - r = shader_test_bo_free(dst); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(shader); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(cmd); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static -void amdgpu_test_dispatch_memcpy(struct shader_test_info *test_info) -{ - struct shader_test_priv test_priv; - amdgpu_context_handle context_handle; - amdgpu_bo_handle resources[4]; - struct shader_test_bo *cmd = &(test_priv.cmd); - struct shader_test_bo *src = &(test_priv.src); - struct shader_test_bo *dst = &(test_priv.dst); - struct shader_test_bo *shader = &(test_priv.shader_dispatch.cs_bo); - uint32_t *ptr_cmd; - uint8_t *ptr_src; - uint8_t *ptr_dst; - int i, r; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info= {0}; - uint32_t expired, hang_state, hangs; - amdgpu_bo_list_handle bo_list; - struct amdgpu_cs_fence fence_status = {0}; - - memset(&test_priv, 0, sizeof(test_priv)); - test_priv.info = test_info; - test_priv.cmd.size = 4096; - test_priv.cmd.heap = AMDGPU_GEM_DOMAIN_GTT; - - test_priv.shader_dispatch.cs_bo.heap = AMDGPU_GEM_DOMAIN_VRAM; - test_priv.shader_dispatch.cs_type = CS_BUFFERCOPY; - test_priv.src.heap = AMDGPU_GEM_DOMAIN_VRAM; - test_priv.dst.heap = AMDGPU_GEM_DOMAIN_VRAM; - if (test_info->hang_slow) { - test_priv.shader_dispatch.cs_bo.size = 0x4000000; - test_priv.src.size = 0x4000000; - test_priv.dst.size = 0x4000000; - } else { - test_priv.shader_dispatch.cs_bo.size = 4096; - test_priv.src.size = 0x4000; - test_priv.dst.size = 0x4000; - } - - r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_alloc(test_info->device_handle, cmd); - CU_ASSERT_EQUAL(r, 0); - ptr_cmd = cmd->ptr; - memset(ptr_cmd, 0, cmd->size); - - r = shader_test_bo_alloc(test_info->device_handle, shader); - CU_ASSERT_EQUAL(r, 0); - memset(shader->ptr, 0, shader->size); - amdgpu_dispatch_load_cs_shader(&test_priv); - - r = shader_test_bo_alloc(test_info->device_handle, src); - CU_ASSERT_EQUAL(r, 0); - ptr_src = (uint8_t *)(src->ptr); - memset(ptr_src, 0x55, src->size); - - r = shader_test_bo_alloc(test_info->device_handle, dst); - CU_ASSERT_EQUAL(r, 0); - - amdgpu_dispatch_init(&test_priv); - - /* Issue commands to set cu mask used in current dispatch */ - amdgpu_dispatch_write_cumask(&test_priv); - - /* Writes shader state to HW */ - amdgpu_dispatch_write2hw(&test_priv); - - amdgpu_dispatch_write_dispatch_cmd(&test_priv); - - i = test_priv.cmd_curr; - while (i & 7) - ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ - test_priv.cmd_curr = i; - - resources[0] = shader->bo; - resources[1] = src->bo; - resources[2] = dst->bo; - resources[3] = cmd->bo; - r = amdgpu_bo_list_create(test_info->device_handle, 4, resources, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ib_info.ib_mc_address = cmd->mc_address; - ib_info.size = test_priv.cmd_curr; - ibs_request.ip_type = test_info->ip; - ibs_request.ring = test_info->ring; - ibs_request.resources = bo_list; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - fence_status.ip_type = test_info->ip; - fence_status.ip_instance = 0; - fence_status.ring = test_info->ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request.seq_no; - - /* wait for IB accomplished */ - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - - if (!test_info->hang) { - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - /* verify if memcpy test result meets with expected */ - i = 0; - ptr_dst = (uint8_t *)dst->ptr; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - i = dst->size - 16; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - i = dst->size / 2; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - } else { - r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); - } - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(src); - CU_ASSERT_EQUAL(r, 0); - r = shader_test_bo_free(dst); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(shader); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(cmd); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void shader_test_dispatch_cb(struct shader_test_info *test_info) -{ - amdgpu_test_dispatch_memset(test_info); - amdgpu_test_dispatch_memcpy(test_info); -} -static void shader_test_dispatch_hang_cb(struct shader_test_info *test_info) -{ - test_info->hang = 0; - amdgpu_test_dispatch_memcpy(test_info); - - test_info->hang = 1; - amdgpu_test_dispatch_memcpy(test_info); - - test_info->hang = 0; - amdgpu_test_dispatch_memcpy(test_info); -} - -static void shader_test_dispatch_hang_slow_cb(struct shader_test_info *test_info) -{ - test_info->hang = 0; - test_info->hang_slow = 0; - amdgpu_test_dispatch_memcpy(test_info); - - test_info->hang = 1; - test_info->hang_slow = 1; - amdgpu_test_dispatch_memcpy(test_info); - - test_info->hang = 0; - test_info->hang_slow = 0; - amdgpu_test_dispatch_memcpy(test_info); -} - -void amdgpu_test_dispatch_helper(amdgpu_device_handle device_handle, unsigned ip) -{ - shader_test_for_each(device_handle, ip, shader_test_dispatch_cb); -} - -void amdgpu_test_dispatch_hang_helper(amdgpu_device_handle device_handle, uint32_t ip) -{ - shader_test_for_each(device_handle, ip, shader_test_dispatch_hang_cb); -} - -void amdgpu_test_dispatch_hang_slow_helper(amdgpu_device_handle device_handle, uint32_t ip) -{ - shader_test_for_each(device_handle, ip, shader_test_dispatch_hang_slow_cb); -} - -static void amdgpu_draw_load_ps_shader_hang_slow(struct shader_test_priv *test_priv) -{ - struct amdgpu_gpu_info gpu_info = {0}; - struct shader_test_shader_bin *ps_shader_bin = &memcpy_ps_hang_slow_navi21; - int r; - - r = amdgpu_query_gpu_info(test_priv->info->device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - switch (gpu_info.family_id) { - case AMDGPU_FAMILY_AI: - case AMDGPU_FAMILY_RV: - ps_shader_bin = &memcpy_ps_hang_slow_ai; - break; - case AMDGPU_FAMILY_NV: - if (gpu_info.chip_external_rev < 40) - ps_shader_bin = &memcpy_ps_hang_slow_navi10; - break; - } - - shader_test_load_shader_hang_slow(&test_priv->shader_draw.ps_bo, ps_shader_bin); -} - -static uint32_t round_up_size(uint32_t size) -{ - return (size + 255) & ~255; -} -static void amdgpu_draw_load_ps_shader(struct shader_test_priv *test_priv) -{ - uint8_t *ptr_shader = test_priv->shader_draw.ps_bo.ptr; - const struct shader_test_ps_shader *shader; - uint32_t shader_offset, num_export_fmt; - uint32_t mem_offset, patch_code_offset; - int i; - - if (test_priv->info->hang) { - if (test_priv->info->hang_slow) - amdgpu_draw_load_ps_shader_hang_slow(test_priv); - else - memcpy(ptr_shader, memcpy_shader_hang, sizeof(memcpy_shader_hang)); - - return; - } - - shader = &shader_test_ps[test_priv->info->version][test_priv->shader_draw.ps_type]; - num_export_fmt = 10; - shader_offset = round_up_size(shader->shader_size); - /* write main shader program */ - for (i = 0 ; i < num_export_fmt; i++) { - mem_offset = i * shader_offset; - memcpy(ptr_shader + mem_offset, shader->shader, shader->shader_size); - } - - /* overwrite patch codes */ - for (i = 0 ; i < num_export_fmt; i++) { - mem_offset = i * shader_offset + shader->patchinfo_code_offset[0] * sizeof(uint32_t); - patch_code_offset = i * shader->patchinfo_code_size; - memcpy(ptr_shader + mem_offset, - shader->patchinfo_code + patch_code_offset, - shader->patchinfo_code_size * sizeof(uint32_t)); - } -} - -/* load RectPosTexFast_VS */ -static void amdgpu_draw_load_vs_shader(struct shader_test_priv *test_priv) -{ - uint8_t *ptr_shader = test_priv->shader_draw.vs_bo.ptr; - const struct shader_test_vs_shader *shader = &shader_test_vs[test_priv->info->version][test_priv->shader_draw.vs_type]; - - memcpy(ptr_shader, shader->shader, shader->shader_size); -} - -static void amdgpu_draw_init(struct shader_test_priv *test_priv) -{ - int i; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version]; - - /* Write context control and load shadowing register if necessary */ - write_context_control(test_priv); - i = test_priv->cmd_curr; - - if (test_priv->info->version == AMDGPU_TEST_GFX_V11) { - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x446; - ptr[i++] = (test_priv->vtx_attributes_mem.mc_address >> 16); - // mmSPI_ATTRIBUTE_RING_SIZE - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x447; - ptr[i++] = 0x20001; - } - memcpy(ptr + i, gfx_info->preamble_cache, gfx_info->size_preamble_cache); - - test_priv->cmd_curr = i + gfx_info->size_preamble_cache/sizeof(uint32_t); -} - -static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx9(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - /* setup color buffer */ - /* offset reg - 0xA318 CB_COLOR0_BASE - 0xA319 CB_COLOR0_BASE_EXT - 0xA31A CB_COLOR0_ATTRIB2 - 0xA31B CB_COLOR0_VIEW - 0xA31C CB_COLOR0_INFO - 0xA31D CB_COLOR0_ATTRIB - 0xA31E CB_COLOR0_DCC_CONTROL - 0xA31F CB_COLOR0_CMASK - 0xA320 CB_COLOR0_CMASK_BASE_EXT - 0xA321 CB_COLOR0_FMASK - 0xA322 CB_COLOR0_FMASK_BASE_EXT - 0xA323 CB_COLOR0_CLEAR_WORD0 - 0xA324 CB_COLOR0_CLEAR_WORD1 - 0xA325 CB_COLOR0_DCC_BASE - 0xA326 CB_COLOR0_DCC_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 15); - ptr[i++] = 0x318; - ptr[i++] = test_priv->dst.mc_address >> 8; - ptr[i++] = test_priv->dst.mc_address >> 40; - ptr[i++] = test_priv->info->hang_slow ? 0x3ffc7ff : 0x7c01f; - ptr[i++] = 0; - ptr[i++] = 0x50438; - ptr[i++] = 0x10140000; - i += 9; - - /* mmCB_MRT0_EPITCH */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1e8; - ptr[i++] = test_priv->info->hang_slow ? 0xfff : 0x1f; - - /* 0xA32B CB_COLOR1_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x32b; - ptr[i++] = 0; - - /* 0xA33A CB_COLOR1_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x33a; - ptr[i++] = 0; - - /* SPI_SHADER_COL_FORMAT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1c5; - ptr[i++] = 9; - - /* Setup depth buffer */ - /* mmDB_Z_INFO */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0xe; - i += 2; - - test_priv->cmd_curr = i; -} -static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - /* setup color buffer */ - /* 0xA318 CB_COLOR0_BASE - 0xA319 CB_COLOR0_PITCH - 0xA31A CB_COLOR0_SLICE - 0xA31B CB_COLOR0_VIEW - 0xA31C CB_COLOR0_INFO - 0xA31D CB_COLOR0_ATTRIB - 0xA31E CB_COLOR0_DCC_CONTROL - 0xA31F CB_COLOR0_CMASK - 0xA320 CB_COLOR0_CMASK_SLICE - 0xA321 CB_COLOR0_FMASK - 0xA322 CB_COLOR0_FMASK_SLICE - 0xA323 CB_COLOR0_CLEAR_WORD0 - 0xA324 CB_COLOR0_CLEAR_WORD1 - 0xA325 CB_COLOR0_DCC_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 14); - ptr[i++] = 0x318; - ptr[i++] = test_priv->dst.mc_address >> 8; - i += 3; - ptr[i++] = 0x50438; - i += 9; - - /* 0xA390 CB_COLOR0_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x390; - ptr[i++] = test_priv->dst.mc_address >> 40; - - /* 0xA398 CB_COLOR0_CMASK_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x398; - ptr[i++] = 0; - - /* 0xA3A0 CB_COLOR0_FMASK_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3a0; - ptr[i++] = 0; - - /* 0xA3A8 CB_COLOR0_DCC_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3a8; - ptr[i++] = 0; - - /* 0xA3B0 CB_COLOR0_ATTRIB2 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3b0; - ptr[i++] = test_priv->info->hang_slow ? 0x3ffc7ff : 0x7c01f; - - /* 0xA3B8 CB_COLOR0_ATTRIB3 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3b8; - ptr[i++] = 0x9014000; - - /* 0xA32B CB_COLOR1_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x32b; - ptr[i++] = 0; - - /* 0xA33A CB_COLOR1_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x33a; - ptr[i++] = 0; - - /* SPI_SHADER_COL_FORMAT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1c5; - ptr[i++] = 9; - - /* Setup depth buffer */ - /* mmDB_Z_INFO */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0x10; - i += 2; - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - /* mmCB_COLOR0_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x318; - ptr[i++] = test_priv->dst.mc_address >> 8; - /* mmCB_COLOR0_VIEW .. mmCB_COLOR0_DCC_CONTROL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 4); - ptr[i++] = 0x31b; - i++; - ptr[i++] = 0x5040e; - i += 2; - /* mmCB_COLOR0_DCC_BASE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x325; - ptr[i++] = 0; - /* mmCB_COLOR0_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x390; - ptr[i++] = (test_priv->dst.mc_address >> 40) & 0xFF; - /* mmCB_COLOR0_DCC_BASE_EXT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3a8; - ptr[i++] = 0; - /* mmCB_COLOR0_ATTRIB2 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3b0; - ptr[i++] = test_priv->info->hang_slow ? 0x1ffc7ff : 0x7c01f; - /* mmCB_COLOR0_ATTRIB3 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x3b8; - ptr[i++] = test_priv->info->hang_slow ? 0x1028000 : 0x1018000; - /* mmCB_COLOR0_INFO */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x32b; - ptr[i++] = 0; - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x33a; - ptr[i++] = 0; - /* mmSPI_SHADER_COL_FORMAT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1c5; - ptr[i++] = 0x9; - /* mmDB_Z_INFO */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0x10; - i += 2; - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_setup_and_write_drawblt_surf_info(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - amdgpu_draw_setup_and_write_drawblt_surf_info_gfx9(test_priv); - break; - case AMDGPU_TEST_GFX_V10: - amdgpu_draw_setup_and_write_drawblt_surf_info_gfx10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_draw_setup_and_write_drawblt_surf_info_gfx11(test_priv); - break; - } -} - -static void amdgpu_draw_setup_and_write_drawblt_state_gfx9(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version]; - - /* mmPA_SC_TILE_STEERING_OVERRIDE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - ptr[i++] = 0; - - ptr[i++] = 0xffff1000; - ptr[i++] = 0xc0021000; - - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - ptr[i++] = 1; - - /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16); - ptr[i++] = 0x2fe; - i += 16; - - /* mmPA_SC_CENTROID_PRIORITY_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0x2f5; - i += 2; - - memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd); - if (test_priv->info->hang_slow) - *(ptr + i + 12) = 0x8000800; - - test_priv->cmd_curr = i + gfx_info->size_cached_cmd/sizeof(uint32_t); -} - -static void amdgpu_draw_setup_and_write_drawblt_state_gfx10(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version]; - - /* mmPA_SC_TILE_STEERING_OVERRIDE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - ptr[i++] = 0; - - ptr[i++] = 0xffff1000; - ptr[i++] = 0xc0021000; - - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - ptr[i++] = 0; - - /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16); - ptr[i++] = 0x2fe; - i += 16; - - /* mmPA_SC_CENTROID_PRIORITY_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0x2f5; - i += 2; - - memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd); - if (test_priv->info->hang_slow) - *(ptr + i + 12) = 0x8000800; - i += gfx_info->size_cached_cmd/sizeof(uint32_t); - - /* mmCB_RMI_GL2_CACHE_CONTROL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x104; - ptr[i++] = 0x40aa0055; - /* mmDB_RMI_L2_CACHE_CONTROL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1f; - ptr[i++] = 0x2a0055; - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_setup_and_write_drawblt_state_gfx11(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version]; - - /* mmPA_SC_TILE_STEERING_OVERRIDE */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - ptr[i++] = 0; - - ptr[i++] = 0xffff1000; - ptr[i++] = 0xc0021000; - - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0xd7; - i++; - - /* mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 16); - ptr[i++] = 0x2fe; - i += 16; - - /* mmPA_SC_CENTROID_PRIORITY_0 */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 2); - ptr[i++] = 0x2f5; - i += 2; - - memcpy(ptr + i, gfx_info->cached_cmd, gfx_info->size_cached_cmd); - if (test_priv->info->hang_slow) - *(ptr + i + 12) = 0x8000800; - - test_priv->cmd_curr = i + gfx_info->size_cached_cmd/sizeof(uint32_t); -} - -static void amdgpu_draw_setup_and_write_drawblt_state(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - amdgpu_draw_setup_and_write_drawblt_state_gfx9(test_priv); - break; - case AMDGPU_TEST_GFX_V10: - amdgpu_draw_setup_and_write_drawblt_state_gfx10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_draw_setup_and_write_drawblt_state_gfx11(test_priv); - break; - } -} - -static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx9(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address; - enum ps_type ps = test_priv->shader_draw.ps_type; - - /* mmPA_CL_VS_OUT_CNTL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x207; - ptr[i++] = 0; - - /* mmSPI_SHADER_PGM_RSRC3_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x46; - ptr[i++] = 0xffff; - - /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x48; - ptr[i++] = shader_addr >> 8; - ptr[i++] = shader_addr >> 40; - - /* mmSPI_SHADER_PGM_RSRC1_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x4a; - ptr[i++] = 0xc0081; - - /* mmSPI_SHADER_PGM_RSRC2_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x4b; - ptr[i++] = 0x18; - - /* mmSPI_VS_OUT_CONFIG */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1b1; - ptr[i++] = 2; - - /* mmSPI_SHADER_POS_FORMAT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1c3; - ptr[i++] = 4; - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x4c; - i += 2; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x50; - i += 2; - if (ps == PS_CONST) { - i += 2; - } else if (ps == PS_TEX) { - ptr[i++] = 0x3f800000; - ptr[i++] = 0x3f800000; - } - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x54; - i += 4; - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address; - enum ps_type ps = test_priv->shader_draw.ps_type; - - /* mmPA_CL_VS_OUT_CNTL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x207; - ptr[i++] = 0; - - /* mmSPI_SHADER_PGM_RSRC3_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000046; - ptr[i++] = 0xffff; - /* mmSPI_SHADER_PGM_RSRC4_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000041; - ptr[i++] = 0xffff; - - /* mmSPI_SHADER_PGM_LO_VS...mmSPI_SHADER_PGM_HI_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x48; - ptr[i++] = shader_addr >> 8; - ptr[i++] = shader_addr >> 40; - - /* mmSPI_SHADER_PGM_RSRC1_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x4a; - ptr[i++] = 0xc0041; - /* mmSPI_SHADER_PGM_RSRC2_VS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = 0x4b; - ptr[i++] = 0x18; - - /* mmSPI_VS_OUT_CONFIG */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1b1; - ptr[i++] = 2; - - /* mmSPI_SHADER_POS_FORMAT */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1c3; - ptr[i++] = 4; - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x4c; - i += 2; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x50; - i += 2; - if (ps == PS_CONST) { - i += 2; - } else if (ps == PS_TEX) { - ptr[i++] = 0x3f800000; - ptr[i++] = 0x3f800000; - } - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x54; - i += 4; - - test_priv->cmd_curr = i; -} - - -static void amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - const struct shader_test_gfx_info *gfx_info = &shader_test_gfx_info[test_priv->info->version]; - uint64_t shader_addr = test_priv->shader_draw.vs_bo.mc_address; - const struct shader_test_vs_shader *shader = &shader_test_vs[test_priv->info->version][test_priv->shader_draw.vs_type]; - enum ps_type ps = test_priv->shader_draw.ps_type; - int j, offset; - - /* mmPA_CL_VS_OUT_CNTL */ - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x207; - ptr[i++] = 0; - - /* mmSPI_SHADER_PGM_RSRC3_GS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000087; - ptr[i++] = 0xffff; - /* mmSPI_SHADER_PGM_RSRC4_GS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000081; - ptr[i++] = 0x1fff0001; - - /* mmSPI_SHADER_PGM_LO_ES */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0xc8; - ptr[i++] = shader_addr >> 8; - ptr[i++] = shader_addr >> 40; - - /* write sh reg */ - for (j = 0; j < shader->num_sh_reg; j++) { - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = shader->sh_reg[j].reg_offset - gfx_info->sh_reg_base; - ptr[i++] = shader->sh_reg[j].reg_value; - } - /* write context reg */ - for (j = 0; j < shader->num_context_reg; j++) { - switch (shader->context_reg[j].reg_offset) { - case 0xA1B1: //mmSPI_VS_OUT_CONFIG - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base; - ptr[i++] = 2; - break; - case 0xA1C3: //mmSPI_SHADER_POS_FORMAT - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base; - ptr[i++] = 4; - break; - case 0xA2E4: //mmVGT_GS_INSTANCE_CNT - case 0xA2CE: //mmVGT_GS_MAX_VERT_OUT - break; - default: - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = shader->context_reg[j].reg_offset - gfx_info->context_reg_base; - ptr[i++] = shader->context_reg[j].reg_value; - break; - } - } - - // write constant - // dst rect - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x8c; - i += 2; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - ptr[i++] = test_priv->info->hang_slow ? 0x45000000 : 0x42000000; - // src rect - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x90; - i += 2; - if (ps == PS_CONST) { - i += 2; - } else if (ps == PS_TEX) { - ptr[i++] = 0x3f800000; - ptr[i++] = 0x3f800000; - } - - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr[i++] = 0x94; - i += 4; - // vtx_attributes_mem - ptr[i++] = 0xc02f1000; - offset = i * sizeof(uint32_t); - i += 44; - ptr[i++] = test_priv->vtx_attributes_mem.mc_address & 0xffffffff; - ptr[i++] = 0xc0100000 | ((test_priv->vtx_attributes_mem.mc_address >> 32) & 0xffff); - ptr[i++] = test_priv->vtx_attributes_mem.size / 16; - ptr[i++] = 0x2043ffac; - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_OFFSET, 2); - ptr[i++] = 0x98; - ptr[i++] = offset; - i++; - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_vs_RectPosTexFast_write2hw(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - amdgpu_draw_vs_RectPosTexFast_write2hw_gfx9(test_priv); - break; - case AMDGPU_TEST_GFX_V10: - amdgpu_draw_vs_RectPosTexFast_write2hw_gfx10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_draw_vs_RectPosTexFast_write2hw_gfx11(test_priv); - break; - } -} - -static void amdgpu_draw_ps_write2hw_gfx9_10(struct shader_test_priv *test_priv) -{ - int i, j; - uint64_t shader_addr = test_priv->shader_draw.ps_bo.mc_address; - const struct shader_test_ps_shader *ps = &shader_test_ps[test_priv->info->version][test_priv->shader_draw.ps_type]; - uint32_t *ptr = test_priv->cmd.ptr; - - i = test_priv->cmd_curr; - - if (test_priv->info->version == AMDGPU_TEST_GFX_V9) { - /* 0x2c07 SPI_SHADER_PGM_RSRC3_PS - 0x2c08 SPI_SHADER_PGM_LO_PS - 0x2c09 SPI_SHADER_PGM_HI_PS */ - /* multiplicator 9 is from SPI_SHADER_COL_FORMAT */ - if (!test_priv->info->hang) - shader_addr += 256 * 9; - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 3); - ptr[i++] = 0x7; - ptr[i++] = 0xffff; - ptr[i++] = shader_addr >> 8; - ptr[i++] = shader_addr >> 40; - } else { - //if (!test_priv->info->hang) - shader_addr += 256 * 9; - /* 0x2c08 SPI_SHADER_PGM_LO_PS - 0x2c09 SPI_SHADER_PGM_HI_PS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x8; - ptr[i++] = shader_addr >> 8; - ptr[i++] = shader_addr >> 40; - - /* mmSPI_SHADER_PGM_RSRC3_PS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000007; - ptr[i++] = 0xffff; - /* mmSPI_SHADER_PGM_RSRC4_PS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000001; - ptr[i++] = 0xffff; - } - - for (j = 0; j < ps->num_sh_reg; j++) { - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = ps->sh_reg[j].reg_offset - 0x2c00; - ptr[i++] = ps->sh_reg[j].reg_value; - } - - for (j = 0; j < ps->num_context_reg; j++) { - if (ps->context_reg[j].reg_offset != 0xA1C5) { - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = ps->context_reg[j].reg_offset - 0xa000; - ptr[i++] = ps->context_reg[j].reg_value; - } - - if (ps->context_reg[j].reg_offset == 0xA1B4) { - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1b3; - ptr[i++] = 2; - } - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_ps_write2hw_gfx11(struct shader_test_priv *test_priv) -{ - int i, j; - uint64_t shader_addr = test_priv->shader_draw.ps_bo.mc_address; - enum amdgpu_test_gfx_version version = test_priv->info->version; - const struct shader_test_ps_shader *ps = &shader_test_ps[version][test_priv->shader_draw.ps_type]; - uint32_t *ptr = test_priv->cmd.ptr; - uint32_t export_shader_offset; - - i = test_priv->cmd_curr; - - /* SPI_SHADER_PGM_LO_PS - SPI_SHADER_PGM_HI_PS */ - shader_addr >>= 8; - if (!test_priv->info->hang) { - export_shader_offset = (round_up_size(ps->shader_size) * 9) >> 8; - shader_addr += export_shader_offset; - } - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 2); - ptr[i++] = 0x8; - ptr[i++] = shader_addr & 0xffffffff; - ptr[i++] = (shader_addr >> 32) & 0xffffffff; - /* mmSPI_SHADER_PGM_RSRC3_PS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000007; - ptr[i++] = 0xffff; - /* mmSPI_SHADER_PGM_RSRC4_PS */ - ptr[i++] = PACKET3(PACKET3_SET_SH_REG_INDEX, 1); - ptr[i++] = 0x30000001; - ptr[i++] = 0x3fffff; - - for (j = 0; j < ps->num_sh_reg; j++) { - ptr[i++] = PACKET3(PACKET3_SET_SH_REG, 1); - ptr[i++] = ps->sh_reg[j].reg_offset - shader_test_gfx_info[version].sh_reg_base; - ptr[i++] = ps->sh_reg[j].reg_value; - } - - for (j = 0; j < ps->num_context_reg; j++) { - /* !mmSPI_SHADER_COL_FORMAT */ - if (ps->context_reg[j].reg_offset != 0xA1C5) { - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = ps->context_reg[j].reg_offset - shader_test_gfx_info[version].context_reg_base; - ptr[i++] = ps->context_reg[j].reg_value; - } - - /* mmSPI_PS_INPUT_ADDR */ - if (ps->context_reg[j].reg_offset == 0xA1B4) { - ptr[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr[i++] = 0x1b3; - ptr[i++] = 2; - } - } - - test_priv->cmd_curr = i; -} - -static void amdgpu_draw_ps_write2hw(struct shader_test_priv *test_priv) -{ - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - case AMDGPU_TEST_GFX_V10: - amdgpu_draw_ps_write2hw_gfx9_10(test_priv); - break; - case AMDGPU_TEST_GFX_V11: - amdgpu_draw_ps_write2hw_gfx11(test_priv); - break; - } -} - -static void amdgpu_draw_draw(struct shader_test_priv *test_priv) -{ - int i = test_priv->cmd_curr; - uint32_t *ptr = test_priv->cmd.ptr; - - switch (test_priv->info->version) { - case AMDGPU_TEST_GFX_V9: - /* mmIA_MULTI_VGT_PARAM */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x40000258; - ptr[i++] = 0xd00ff; - /* mmVGT_PRIMITIVE_TYPE */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x10000242; - ptr[i++] = 0x11; - break; - case AMDGPU_TEST_GFX_V10: - /* mmGE_CNTL */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x25b; - ptr[i++] = 0xff; - /* mmVGT_PRIMITIVE_TYPE */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x242; - ptr[i++] = 0x11; - break; - case AMDGPU_TEST_GFX_V11: - /* mmGE_CNTL */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x25b; - ptr[i++] = 0x80fc80; - /* mmVGT_PRIMITIVE_TYPE */ - ptr[i++] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); - ptr[i++] = 0x242; - ptr[i++] = 0x11; - break; - } - - ptr[i++] = PACKET3(PACKET3_DRAW_INDEX_AUTO, 1); - ptr[i++] = 3; - ptr[i++] = 2; - - test_priv->cmd_curr = i; -} - -static void amdgpu_memset_draw_test(struct shader_test_info *test_info) -{ - struct shader_test_priv test_priv; - amdgpu_context_handle context_handle; - struct shader_test_bo *ps_bo = &(test_priv.shader_draw.ps_bo); - struct shader_test_bo *vs_bo = &(test_priv.shader_draw.vs_bo); - struct shader_test_bo *dst = &(test_priv.dst); - struct shader_test_bo *cmd = &(test_priv.cmd); - struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem); - amdgpu_bo_handle resources[5]; - uint8_t *ptr_dst; - uint32_t *ptr_cmd; - int i, r; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - amdgpu_bo_list_handle bo_list; - uint8_t cptr[16]; - - memset(&test_priv, 0, sizeof(test_priv)); - test_priv.info = test_info; - - r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - ps_bo->size = 0x2000; - ps_bo->heap = AMDGPU_GEM_DOMAIN_VRAM; - r = shader_test_bo_alloc(test_info->device_handle, ps_bo); - CU_ASSERT_EQUAL(r, 0); - memset(ps_bo->ptr, 0, ps_bo->size); - - vs_bo->size = 4096; - vs_bo->heap = AMDGPU_GEM_DOMAIN_VRAM; - r = shader_test_bo_alloc(test_info->device_handle, vs_bo); - CU_ASSERT_EQUAL(r, 0); - memset(vs_bo->ptr, 0, vs_bo->size); - - test_priv.shader_draw.ps_type = PS_CONST; - amdgpu_draw_load_ps_shader(&test_priv); - - test_priv.shader_draw.vs_type = VS_RECTPOSTEXFAST; - amdgpu_draw_load_vs_shader(&test_priv); - - cmd->size = 4096; - cmd->heap = AMDGPU_GEM_DOMAIN_GTT; - r = shader_test_bo_alloc(test_info->device_handle, cmd); - CU_ASSERT_EQUAL(r, 0); - ptr_cmd = cmd->ptr; - memset(ptr_cmd, 0, cmd->size); - - dst->size = 0x4000; - dst->heap = AMDGPU_GEM_DOMAIN_VRAM; - r = shader_test_bo_alloc(test_info->device_handle, dst); - CU_ASSERT_EQUAL(r, 0); - - if (test_info->version == AMDGPU_TEST_GFX_V11) { - vtx_attributes_mem->size = 0x4040000; - vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM; - - r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem); - CU_ASSERT_EQUAL(r, 0); - } - - amdgpu_draw_init(&test_priv); - - amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv); - - amdgpu_draw_setup_and_write_drawblt_state(&test_priv); - - amdgpu_draw_vs_RectPosTexFast_write2hw(&test_priv); - - amdgpu_draw_ps_write2hw(&test_priv); - - i = test_priv.cmd_curr; - /* ps constant data */ - ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr_cmd[i++] = 0xc; - ptr_cmd[i++] = 0x33333333; - ptr_cmd[i++] = 0x33333333; - ptr_cmd[i++] = 0x33333333; - ptr_cmd[i++] = 0x33333333; - test_priv.cmd_curr = i; - - amdgpu_draw_draw(&test_priv); - - i = test_priv.cmd_curr; - while (i & 7) - ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ - test_priv.cmd_curr = i; - - i = 0; - resources[i++] = dst->bo; - resources[i++] = ps_bo->bo; - resources[i++] = vs_bo->bo; - resources[i++] = cmd->bo; - if (vtx_attributes_mem->size) - resources[i++] = vtx_attributes_mem->bo; - r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ib_info.ib_mc_address = cmd->mc_address; - ib_info.size = test_priv.cmd_curr; - ibs_request.ip_type = test_info->ip; - ibs_request.ring = test_info->ring; - ibs_request.resources = bo_list; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - /* submit CS */ - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - fence_status.ip_type = test_info->ip; - fence_status.ip_instance = 0; - fence_status.ring = test_info->ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request.seq_no; - - /* wait for IB accomplished */ - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - /* verify if memset test result meets with expected */ - i = 0; - ptr_dst = dst->ptr; - memset(cptr, 0x33, 16); - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - i = dst->size - 16; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - i = dst->size / 2; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, cptr, 16), 0); - - if (vtx_attributes_mem->size) { - r = shader_test_bo_free(vtx_attributes_mem); - CU_ASSERT_EQUAL(r, 0); - } - - r = shader_test_bo_free(dst); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(cmd); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(ps_bo); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(vs_bo); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_memcpy_draw_test(struct shader_test_info *test_info) -{ - struct shader_test_priv test_priv; - amdgpu_context_handle context_handle; - struct shader_test_bo *ps_bo = &(test_priv.shader_draw.ps_bo); - struct shader_test_bo *vs_bo = &(test_priv.shader_draw.vs_bo); - struct shader_test_bo *src = &(test_priv.src); - struct shader_test_bo *dst = &(test_priv.dst); - struct shader_test_bo *cmd = &(test_priv.cmd); - struct shader_test_bo *vtx_attributes_mem = &(test_priv.vtx_attributes_mem); - amdgpu_bo_handle resources[6]; - uint8_t *ptr_dst; - uint8_t *ptr_src; - uint32_t *ptr_cmd; - int i, r; - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - uint32_t hang_state, hangs; - uint32_t expired; - amdgpu_bo_list_handle bo_list; - struct amdgpu_cs_fence fence_status = {0}; - - memset(&test_priv, 0, sizeof(test_priv)); - test_priv.info = test_info; - test_priv.cmd.size = 4096; - test_priv.cmd.heap = AMDGPU_GEM_DOMAIN_GTT; - - ps_bo->heap = AMDGPU_GEM_DOMAIN_VRAM; - test_priv.shader_draw.ps_type = PS_TEX; - vs_bo->size = 4096; - vs_bo->heap = AMDGPU_GEM_DOMAIN_VRAM; - test_priv.shader_draw.vs_type = VS_RECTPOSTEXFAST; - test_priv.src.heap = AMDGPU_GEM_DOMAIN_VRAM; - test_priv.dst.heap = AMDGPU_GEM_DOMAIN_VRAM; - if (test_info->hang_slow) { - test_priv.shader_draw.ps_bo.size = 16*1024*1024; - test_priv.src.size = 0x4000000; - test_priv.dst.size = 0x4000000; - } else { - test_priv.shader_draw.ps_bo.size = 0x2000; - test_priv.src.size = 0x4000; - test_priv.dst.size = 0x4000; - } - - r = amdgpu_cs_ctx_create(test_info->device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_alloc(test_info->device_handle, ps_bo); - CU_ASSERT_EQUAL(r, 0); - memset(ps_bo->ptr, 0, ps_bo->size); - - r = shader_test_bo_alloc(test_info->device_handle, vs_bo); - CU_ASSERT_EQUAL(r, 0); - memset(vs_bo->ptr, 0, vs_bo->size); - - amdgpu_draw_load_ps_shader(&test_priv); - amdgpu_draw_load_vs_shader(&test_priv); - - r = shader_test_bo_alloc(test_info->device_handle, cmd); - CU_ASSERT_EQUAL(r, 0); - ptr_cmd = cmd->ptr; - memset(ptr_cmd, 0, cmd->size); - - r = shader_test_bo_alloc(test_info->device_handle, src); - CU_ASSERT_EQUAL(r, 0); - ptr_src = src->ptr; - memset(ptr_src, 0x55, src->size); - - r = shader_test_bo_alloc(test_info->device_handle, dst); - CU_ASSERT_EQUAL(r, 0); - - if (test_info->version == AMDGPU_TEST_GFX_V11) { - vtx_attributes_mem->size = 0x4040000; - vtx_attributes_mem->heap = AMDGPU_GEM_DOMAIN_VRAM; - - r = shader_test_bo_alloc(test_info->device_handle, vtx_attributes_mem); - CU_ASSERT_EQUAL(r, 0); - } - - amdgpu_draw_init(&test_priv); - - amdgpu_draw_setup_and_write_drawblt_surf_info(&test_priv); - - amdgpu_draw_setup_and_write_drawblt_state(&test_priv); - - amdgpu_draw_vs_RectPosTexFast_write2hw(&test_priv); - - amdgpu_draw_ps_write2hw(&test_priv); - - // write ps user constant data - i = test_priv.cmd_curr; - ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 8); - switch (test_info->version) { - case AMDGPU_TEST_GFX_V9: - ptr_cmd[i++] = 0xc; - ptr_cmd[i++] = src->mc_address >> 8; - ptr_cmd[i++] = src->mc_address >> 40 | 0x10e00000; - ptr_cmd[i++] = test_info->hang_slow ? 0x1ffcfff : 0x7c01f; - ptr_cmd[i++] = 0x90500fac; - ptr_cmd[i++] = test_info->hang_slow ? 0x1ffe000 : 0x3e000; - i += 3; - break; - case AMDGPU_TEST_GFX_V10: - ptr_cmd[i++] = 0xc; - ptr_cmd[i++] = src->mc_address >> 8; - ptr_cmd[i++] = src->mc_address >> 40 | 0xc4b00000; - ptr_cmd[i++] = test_info->hang_slow ? 0x81ffc1ff : 0x8007c007; - ptr_cmd[i++] = 0x90500fac; - i += 2; - ptr_cmd[i++] = test_info->hang_slow ? 0 : 0x400; - i++; - break; - case AMDGPU_TEST_GFX_V11: - ptr_cmd[i++] = 0xc; - ptr_cmd[i++] = src->mc_address >> 8; - ptr_cmd[i++] = src->mc_address >> 40 | 0xc4b00000; - ptr_cmd[i++] = test_info->hang_slow ? 0x1ffc1ff : 0x7c007; - ptr_cmd[i++] = test_info->hang_slow ? 0x90a00fac : 0x90600fac; - i += 2; - ptr_cmd[i++] = 0x400; - i++; - break; - } - - ptr_cmd[i++] = PACKET3(PACKET3_SET_SH_REG, 4); - ptr_cmd[i++] = 0x14; - ptr_cmd[i++] = 0x92; - i += 3; - - ptr_cmd[i++] = PACKET3(PACKET3_SET_CONTEXT_REG, 1); - ptr_cmd[i++] = 0x191; - ptr_cmd[i++] = 0; - test_priv.cmd_curr = i; - - amdgpu_draw_draw(&test_priv); - - i = test_priv.cmd_curr; - while (i & 7) - ptr_cmd[i++] = 0xffff1000; /* type3 nop packet */ - test_priv.cmd_curr = i; - - i = 0; - resources[i++] = dst->bo; - resources[i++] = src->bo; - resources[i++] = ps_bo->bo; - resources[i++] = vs_bo->bo; - resources[i++] = cmd->bo; - if (vtx_attributes_mem->size) - resources[i++] = vtx_attributes_mem->bo; - r = amdgpu_bo_list_create(test_info->device_handle, i, resources, NULL, &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ib_info.ib_mc_address = cmd->mc_address; - ib_info.size = test_priv.cmd_curr; - ibs_request.ip_type = test_info->ip; - ibs_request.ring = test_info->ring; - ibs_request.resources = bo_list; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - fence_status.ip_type = test_info->ip; - fence_status.ip_instance = 0; - fence_status.ring = test_info->ring; - fence_status.context = context_handle; - fence_status.fence = ibs_request.seq_no; - - /* wait for IB accomplished */ - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (!test_info->hang) { - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(expired, true); - - /* verify if memcpy test result meets with expected */ - i = 0; - ptr_dst = dst->ptr; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - i = dst->size - 16; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - i = dst->size / 2; - CU_ASSERT_EQUAL(memcmp(ptr_dst + i, ptr_src + i, 16), 0); - } else { - r = amdgpu_cs_query_reset_state(context_handle, &hang_state, &hangs); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(hang_state, AMDGPU_CTX_UNKNOWN_RESET); - } - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - if (vtx_attributes_mem->size) { - r = shader_test_bo_free(vtx_attributes_mem); - CU_ASSERT_EQUAL(r, 0); - } - - r = shader_test_bo_free(src); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(dst); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(cmd); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(ps_bo); - CU_ASSERT_EQUAL(r, 0); - - r = shader_test_bo_free(vs_bo); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void shader_test_draw_cb(struct shader_test_info *test_info) -{ - amdgpu_memset_draw_test(test_info); - amdgpu_memcpy_draw_test(test_info); -} - -static void shader_test_draw_hang_cb(struct shader_test_info *test_info) -{ - test_info->hang = 0; - amdgpu_memcpy_draw_test(test_info); - - test_info->hang = 1; - amdgpu_memcpy_draw_test(test_info); - - test_info->hang = 0; - amdgpu_memcpy_draw_test(test_info); -} - -static void shader_test_draw_hang_slow_cb(struct shader_test_info *test_info) -{ - test_info->hang = 0; - test_info->hang_slow = 0; - amdgpu_memcpy_draw_test(test_info); - - test_info->hang = 1; - test_info->hang_slow = 1; - amdgpu_memcpy_draw_test(test_info); - - test_info->hang = 0; - test_info->hang_slow = 0; - amdgpu_memcpy_draw_test(test_info); -} - - -void amdgpu_test_draw_helper(amdgpu_device_handle device_handle) -{ - shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_cb); -} - -void amdgpu_test_draw_hang_helper(amdgpu_device_handle device_handle) -{ - shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_hang_cb); -} - -void amdgpu_test_draw_hang_slow_helper(amdgpu_device_handle device_handle) -{ - shader_test_for_each(device_handle, AMDGPU_HW_IP_GFX, shader_test_draw_hang_slow_cb); -} diff --git a/tests/amdgpu/syncobj_tests.c b/tests/amdgpu/syncobj_tests.c deleted file mode 100644 index 690bea018..000000000 --- a/tests/amdgpu/syncobj_tests.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include "CUnit/Basic.h" -#include "xf86drm.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; - -static uint32_t family_id; -static uint32_t chip_id; -static uint32_t chip_rev; - -static void amdgpu_syncobj_timeline_test(void); - -CU_BOOL suite_syncobj_timeline_tests_enable(void) -{ - int r; - uint64_t cap = 0; - - r = drmGetCap(drm_amdgpu[0], DRM_CAP_SYNCOBJ_TIMELINE, &cap); - if (r || cap == 0) - return CU_FALSE; - - return CU_TRUE; -} - -int suite_syncobj_timeline_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } - - return CUE_SUCCESS; -} - -int suite_syncobj_timeline_tests_clean(void) -{ - int r = amdgpu_device_deinitialize(device_handle); - - if (r == 0) - return CUE_SUCCESS; - else - return CUE_SCLEAN_FAILED; -} - - -CU_TestInfo syncobj_timeline_tests[] = { - { "syncobj timeline test", amdgpu_syncobj_timeline_test }, - CU_TEST_INFO_NULL, -}; - -#define GFX_COMPUTE_NOP 0xffff1000 -#define SDMA_NOP 0x0 -static int syncobj_command_submission_helper(uint32_t syncobj_handle, bool - wait_or_signal, uint64_t point) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct drm_amdgpu_cs_chunk chunks[2]; - struct drm_amdgpu_cs_chunk_data chunk_data; - struct drm_amdgpu_cs_chunk_syncobj syncobj_data; - struct amdgpu_cs_fence fence_status; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - uint32_t expired; - int i, r; - uint64_t seq_no; - static uint32_t *ptr; - struct amdgpu_gpu_info gpu_info = {0}; - unsigned gc_ip_type; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - family_id = device_handle->info.family_id; - chip_id = device_handle->info.chip_external_rev; - chip_rev = device_handle->info.chip_rev; - - gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? - AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - - for (i = 0; i < 16; ++i) - ptr[i] = wait_or_signal ? GFX_COMPUTE_NOP: SDMA_NOP; - - chunks[0].chunk_id = AMDGPU_CHUNK_ID_IB; - chunks[0].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4; - chunks[0].chunk_data = (uint64_t)(uintptr_t)&chunk_data; - chunk_data.ib_data._pad = 0; - chunk_data.ib_data.va_start = ib_result_mc_address; - chunk_data.ib_data.ib_bytes = 16 * 4; - chunk_data.ib_data.ip_type = wait_or_signal ? gc_ip_type : - AMDGPU_HW_IP_DMA; - chunk_data.ib_data.ip_instance = 0; - chunk_data.ib_data.ring = 0; - chunk_data.ib_data.flags = AMDGPU_IB_FLAG_EMIT_MEM_SYNC; - - chunks[1].chunk_id = wait_or_signal ? - AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT : - AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL; - chunks[1].length_dw = sizeof(struct drm_amdgpu_cs_chunk_syncobj) / 4; - chunks[1].chunk_data = (uint64_t)(uintptr_t)&syncobj_data; - syncobj_data.handle = syncobj_handle; - syncobj_data.point = point; - syncobj_data.flags = DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT; - - r = amdgpu_cs_submit_raw(device_handle, - context_handle, - bo_list, - 2, - chunks, - &seq_no); - CU_ASSERT_EQUAL(r, 0); - - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = wait_or_signal ? gc_ip_type : - AMDGPU_HW_IP_DMA; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); - - return r; -} - -struct syncobj_point { - uint32_t syncobj_handle; - uint64_t point; -}; - -static void *syncobj_wait(void *data) -{ - struct syncobj_point *sp = (struct syncobj_point *)data; - int r; - - r = syncobj_command_submission_helper(sp->syncobj_handle, true, - sp->point); - CU_ASSERT_EQUAL(r, 0); - - return (void *)(long)r; -} - -static void *syncobj_signal(void *data) -{ - struct syncobj_point *sp = (struct syncobj_point *)data; - int r; - - r = syncobj_command_submission_helper(sp->syncobj_handle, false, - sp->point); - CU_ASSERT_EQUAL(r, 0); - - return (void *)(long)r; -} - -static void amdgpu_syncobj_timeline_test(void) -{ - static pthread_t wait_thread; - static pthread_t signal_thread; - static pthread_t c_thread; - struct syncobj_point sp1, sp2, sp3; - uint32_t syncobj_handle; - uint64_t payload; - uint64_t wait_point, signal_point; - uint64_t timeout; - struct timespec tp; - int r, sync_fd; - void *tmp; - - r = amdgpu_cs_create_syncobj2(device_handle, 0, &syncobj_handle); - CU_ASSERT_EQUAL(r, 0); - - // wait on point 5 - sp1.syncobj_handle = syncobj_handle; - sp1.point = 5; - r = pthread_create(&wait_thread, NULL, syncobj_wait, &sp1); - CU_ASSERT_EQUAL(r, 0); - - // signal on point 10 - sp2.syncobj_handle = syncobj_handle; - sp2.point = 10; - r = pthread_create(&signal_thread, NULL, syncobj_signal, &sp2); - CU_ASSERT_EQUAL(r, 0); - - r = pthread_join(wait_thread, &tmp); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(tmp, 0); - - r = pthread_join(signal_thread, &tmp); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(tmp, 0); - - //query timeline payload - r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, - &payload, 1); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(payload, 10); - - //signal on point 16 - sp3.syncobj_handle = syncobj_handle; - sp3.point = 16; - r = pthread_create(&c_thread, NULL, syncobj_signal, &sp3); - CU_ASSERT_EQUAL(r, 0); - //CPU wait on point 16 - wait_point = 16; - timeout = 0; - clock_gettime(CLOCK_MONOTONIC, &tp); - timeout = tp.tv_sec * 1000000000ULL + tp.tv_nsec; - timeout += 0x10000000000; //10s - r = amdgpu_cs_syncobj_timeline_wait(device_handle, &syncobj_handle, - &wait_point, 1, timeout, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL | - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - NULL); - - CU_ASSERT_EQUAL(r, 0); - r = pthread_join(c_thread, &tmp); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(tmp, 0); - - // export point 16 and import to point 18 - r = amdgpu_cs_syncobj_export_sync_file2(device_handle, syncobj_handle, - 16, - DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT, - &sync_fd); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_syncobj_import_sync_file2(device_handle, syncobj_handle, - 18, sync_fd); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, - &payload, 1); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(payload, 18); - - // CPU signal on point 20 - signal_point = 20; - r = amdgpu_cs_syncobj_timeline_signal(device_handle, &syncobj_handle, - &signal_point, 1); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_cs_syncobj_query(device_handle, &syncobj_handle, - &payload, 1); - CU_ASSERT_EQUAL(r, 0); - CU_ASSERT_EQUAL(payload, 20); - - r = amdgpu_cs_destroy_syncobj(device_handle, syncobj_handle); - CU_ASSERT_EQUAL(r, 0); - -} diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c deleted file mode 100644 index b4251bcf3..000000000 --- a/tests/amdgpu/uvd_enc_tests.c +++ /dev/null @@ -1,491 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include - -#include "CUnit/Basic.h" - -#include "util_math.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include "frame.h" -#include "uve_ib.h" - -#define IB_SIZE 4096 -#define MAX_RESOURCES 16 - -struct amdgpu_uvd_enc_bo { - amdgpu_bo_handle handle; - amdgpu_va_handle va_handle; - uint64_t addr; - uint64_t size; - uint8_t *ptr; -}; - -struct amdgpu_uvd_enc { - unsigned width; - unsigned height; - struct amdgpu_uvd_enc_bo session; - struct amdgpu_uvd_enc_bo vbuf; - struct amdgpu_uvd_enc_bo bs; - struct amdgpu_uvd_enc_bo fb; - struct amdgpu_uvd_enc_bo cpb; -}; - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static amdgpu_va_handle ib_va_handle; -static uint64_t ib_mc_address; -static uint32_t *ib_cpu; - -static struct amdgpu_uvd_enc enc; -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; - -static void amdgpu_cs_uvd_enc_create(void); -static void amdgpu_cs_uvd_enc_session_init(void); -static void amdgpu_cs_uvd_enc_encode(void); -static void amdgpu_cs_uvd_enc_destroy(void); - - -CU_TestInfo uvd_enc_tests[] = { - { "UVD ENC create", amdgpu_cs_uvd_enc_create }, - { "UVD ENC session init", amdgpu_cs_uvd_enc_session_init }, - { "UVD ENC encode", amdgpu_cs_uvd_enc_encode }, - { "UVD ENC destroy", amdgpu_cs_uvd_enc_destroy }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_uvd_enc_tests_enable(void) -{ - int r; - struct drm_amdgpu_info_hw_ip info; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0, &info); - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - if (!info.available_rings) - printf("\n\nThe ASIC NOT support UVD ENC, suite disabled.\n"); - - return (r == 0 && (info.available_rings ? CU_TRUE : CU_FALSE)); -} - - -int suite_uvd_enc_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (r) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_handle, (void**)&ib_cpu, - &ib_mc_address, &ib_va_handle); - if (r) - return CUE_SINIT_FAILED; - - return CUE_SUCCESS; -} - -int suite_uvd_enc_tests_clean(void) -{ - int r; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static int submit(unsigned ndw, unsigned ip) -{ - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - int r; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = ndw; - - ibs_request.ip_type = ip; - - r = amdgpu_bo_list_create(device_handle, num_resources, resources, - NULL, &ibs_request.resources); - if (r) - return r; - - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = ip; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - return 0; -} - -static void alloc_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo, - unsigned size, unsigned domain) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - int r; - - req.alloc_size = ALIGN(size, 4096); - req.preferred_heap = domain; - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - uvd_enc_bo->addr = va; - uvd_enc_bo->handle = buf_handle; - uvd_enc_bo->size = req.alloc_size; - uvd_enc_bo->va_handle = va_handle; - r = amdgpu_bo_cpu_map(uvd_enc_bo->handle, (void **)&uvd_enc_bo->ptr); - CU_ASSERT_EQUAL(r, 0); - memset(uvd_enc_bo->ptr, 0, size); - r = amdgpu_bo_cpu_unmap(uvd_enc_bo->handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void free_resource(struct amdgpu_uvd_enc_bo *uvd_enc_bo) -{ - int r; - - r = amdgpu_bo_va_op(uvd_enc_bo->handle, 0, uvd_enc_bo->size, - uvd_enc_bo->addr, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(uvd_enc_bo->va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(uvd_enc_bo->handle); - CU_ASSERT_EQUAL(r, 0); - memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo)); -} - -static void amdgpu_cs_uvd_enc_create(void) -{ - enc.width = 160; - enc.height = 128; - - num_resources = 0; - alloc_resource(&enc.session, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.session.handle; - resources[num_resources++] = ib_handle; -} - -static void check_result(struct amdgpu_uvd_enc *enc) -{ - uint64_t sum; - uint32_t s = 175602; - uint32_t *ptr, size; - int j, r; - - r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr); - CU_ASSERT_EQUAL(r, 0); - ptr = (uint32_t *)enc->fb.ptr; - size = ptr[6]; - r = amdgpu_bo_cpu_unmap(enc->fb.handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_map(enc->bs.handle, (void **)&enc->bs.ptr); - CU_ASSERT_EQUAL(r, 0); - for (j = 0, sum = 0; j < size; ++j) - sum += enc->bs.ptr[j]; - CU_ASSERT_EQUAL(sum, s); - r = amdgpu_bo_cpu_unmap(enc->bs.handle); - CU_ASSERT_EQUAL(r, 0); - -} - -static void amdgpu_cs_uvd_enc_session_init(void) -{ - int len, r; - - len = 0; - memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); - len += sizeof(uve_session_info) / 4; - ib_cpu[len++] = enc.session.addr >> 32; - ib_cpu[len++] = enc.session.addr; - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0x000000d8; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_op_init, sizeof(uve_op_init)); - len += sizeof(uve_op_init) / 4; - - memcpy((ib_cpu + len), uve_session_init, sizeof(uve_session_init)); - len += sizeof(uve_session_init) / 4; - - memcpy((ib_cpu + len), uve_layer_ctrl, sizeof(uve_layer_ctrl)); - len += sizeof(uve_layer_ctrl) / 4; - - memcpy((ib_cpu + len), uve_slice_ctrl, sizeof(uve_slice_ctrl)); - len += sizeof(uve_slice_ctrl) / 4; - - memcpy((ib_cpu + len), uve_spec_misc, sizeof(uve_spec_misc)); - len += sizeof(uve_spec_misc) / 4; - - memcpy((ib_cpu + len), uve_rc_session_init, sizeof(uve_rc_session_init)); - len += sizeof(uve_rc_session_init) / 4; - - memcpy((ib_cpu + len), uve_deblocking_filter, sizeof(uve_deblocking_filter)); - len += sizeof(uve_deblocking_filter) / 4; - - memcpy((ib_cpu + len), uve_quality_params, sizeof(uve_quality_params)); - len += sizeof(uve_quality_params) / 4; - - memcpy((ib_cpu + len), uve_op_init_rc, sizeof(uve_op_init_rc)); - len += sizeof(uve_op_init_rc) / 4; - - memcpy((ib_cpu + len), uve_op_init_rc_vbv_level, sizeof(uve_op_init_rc_vbv_level)); - len += sizeof(uve_op_init_rc_vbv_level) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_uvd_enc_encode(void) -{ - int len, r, i; - uint64_t luma_offset, chroma_offset; - uint32_t vbuf_size, bs_size = 0x003f4800, cpb_size; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - - - num_resources = 0; - alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.fb.handle; - alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.bs.handle; - alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.vbuf.handle; - alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.cpb.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(enc.vbuf.ptr, 0, vbuf_size); - for (i = 0; i < enc.height; ++i) { - memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - for (i = 0; i < enc.height / 2; ++i) { - memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - - r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); - CU_ASSERT_EQUAL(r, 0); - - len = 0; - memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); - len += sizeof(uve_session_info) / 4; - ib_cpu[len++] = enc.session.addr >> 32; - ib_cpu[len++] = enc.session.addr; - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0x000005e0; - ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000001; - - memcpy((ib_cpu + len), uve_nalu_buffer_1, sizeof(uve_nalu_buffer_1)); - len += sizeof(uve_nalu_buffer_1) / 4; - - memcpy((ib_cpu + len), uve_nalu_buffer_2, sizeof(uve_nalu_buffer_2)); - len += sizeof(uve_nalu_buffer_2) / 4; - - memcpy((ib_cpu + len), uve_nalu_buffer_3, sizeof(uve_nalu_buffer_3)); - len += sizeof(uve_nalu_buffer_3) / 4; - - memcpy((ib_cpu + len), uve_nalu_buffer_4, sizeof(uve_nalu_buffer_4)); - len += sizeof(uve_nalu_buffer_4) / 4; - - memcpy((ib_cpu + len), uve_slice_header, sizeof(uve_slice_header)); - len += sizeof(uve_slice_header) / 4; - - ib_cpu[len++] = 0x00000254; - ib_cpu[len++] = 0x00000010; - ib_cpu[len++] = enc.cpb.addr >> 32; - ib_cpu[len++] = enc.cpb.addr; - memcpy((ib_cpu + len), uve_ctx_buffer, sizeof(uve_ctx_buffer)); - len += sizeof(uve_ctx_buffer) / 4; - - memcpy((ib_cpu + len), uve_bitstream_buffer, sizeof(uve_bitstream_buffer)); - len += sizeof(uve_bitstream_buffer) / 4; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = enc.bs.addr >> 32; - ib_cpu[len++] = enc.bs.addr; - ib_cpu[len++] = 0x003f4800; - ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_feedback_buffer, sizeof(uve_feedback_buffer)); - len += sizeof(uve_feedback_buffer) / 4; - ib_cpu[len++] = enc.fb.addr >> 32; - ib_cpu[len++] = enc.fb.addr; - ib_cpu[len++] = 0x00000010; - ib_cpu[len++] = 0x00000028; - - memcpy((ib_cpu + len), uve_feedback_buffer_additional, sizeof(uve_feedback_buffer_additional)); - len += sizeof(uve_feedback_buffer_additional) / 4; - - memcpy((ib_cpu + len), uve_intra_refresh, sizeof(uve_intra_refresh)); - len += sizeof(uve_intra_refresh) / 4; - - memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); - len += sizeof(uve_layer_select) / 4; - - memcpy((ib_cpu + len), uve_rc_layer_init, sizeof(uve_rc_layer_init)); - len += sizeof(uve_rc_layer_init) / 4; - - memcpy((ib_cpu + len), uve_layer_select, sizeof(uve_layer_select)); - len += sizeof(uve_layer_select) / 4; - - memcpy((ib_cpu + len), uve_rc_per_pic, sizeof(uve_rc_per_pic)); - len += sizeof(uve_rc_per_pic) / 4; - - unsigned luma_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16); - luma_offset = enc.vbuf.addr; - chroma_offset = luma_offset + luma_size; - ib_cpu[len++] = 0x00000054; - ib_cpu[len++] = 0x0000000c; - ib_cpu[len++] = 0x00000002; - ib_cpu[len++] = 0x003f4800; - ib_cpu[len++] = luma_offset >> 32; - ib_cpu[len++] = luma_offset; - ib_cpu[len++] = chroma_offset >> 32; - ib_cpu[len++] = chroma_offset; - memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param)); - ib_cpu[len] = ALIGN(enc.width, align); - ib_cpu[len + 1] = ALIGN(enc.width, align); - len += sizeof(uve_encode_param) / 4; - - memcpy((ib_cpu + len), uve_op_speed_enc_mode, sizeof(uve_op_speed_enc_mode)); - len += sizeof(uve_op_speed_enc_mode) / 4; - - memcpy((ib_cpu + len), uve_op_encode, sizeof(uve_op_encode)); - len += sizeof(uve_op_encode) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - - check_result(&enc); - - free_resource(&enc.fb); - free_resource(&enc.bs); - free_resource(&enc.vbuf); - free_resource(&enc.cpb); -} - -static void amdgpu_cs_uvd_enc_destroy(void) -{ - int len, r; - - num_resources = 0; - resources[num_resources++] = ib_handle; - - len = 0; - memcpy((ib_cpu + len), uve_session_info, sizeof(uve_session_info)); - len += sizeof(uve_session_info) / 4; - ib_cpu[len++] = enc.session.addr >> 32; - ib_cpu[len++] = enc.session.addr; - - memcpy((ib_cpu + len), uve_task_info, sizeof(uve_task_info)); - len += sizeof(uve_task_info) / 4; - ib_cpu[len++] = 0xffffffff; - ib_cpu[len++] = 0x00000002; - ib_cpu[len++] = 0x00000000; - - memcpy((ib_cpu + len), uve_op_close, sizeof(uve_op_close)); - len += sizeof(uve_op_close) / 4; - - r = submit(len, AMDGPU_HW_IP_UVD_ENC); - CU_ASSERT_EQUAL(r, 0); - - free_resource(&enc.session); -} diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h deleted file mode 100644 index cb72be228..000000000 --- a/tests/amdgpu/uve_ib.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _uve_ib_h_ -#define _uve_ib_h_ - -static const uint32_t uve_session_info[] = { - 0x00000018, - 0x00000001, - 0x00000000, - 0x00010000, -}; - -static const uint32_t uve_task_info[] = { - 0x00000014, - 0x00000002, -}; - -static const uint32_t uve_session_init[] = { - 0x00000020, - 0x00000003, - 0x000000c0, - 0x00000080, - 0x00000020, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_layer_ctrl[] = { - 0x00000010, - 0x00000004, - 0x00000001, - 0x00000001, -}; - -static const uint32_t uve_layer_select[] = { - 0x0000000c, - 0x00000005, - 0x00000000, -}; - -static const uint32_t uve_slice_ctrl[] = { - 0x00000014, - 0x00000006, - 0x00000000, - 0x00000006, - 0x00000006, -}; - -static const uint32_t uve_spec_misc[] = { - 0x00000024, - 0x00000007, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000001, - 0x00000001, -}; - -static const uint32_t uve_rc_session_init[] = { - 0x00000010, - 0x00000008, - 0x00000000, - 0x00000040, -}; - -static const uint32_t uve_rc_layer_init[] = { - 0x00000028, - 0x00000009, - 0x001e8480, - 0x001e8480, - 0x0000001e, - 0x00000001, - 0x0001046a, - 0x0001046a, - 0x0001046a, - 0xaaaaaaaa, -}; - -static const uint32_t uve_deblocking_filter[] = { - 0x00000020, - 0x0000000e, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_quality_params[] = { - 0x00000014, - 0x0000000d, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_feedback_buffer[] = { - 0x0000001c, - 0x00000012, - 0x00000000, -}; - -static const uint32_t uve_feedback_buffer_additional[] = { - 0x00000108, - 0x00000014, - 0x00000001, - 0x00000010, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_nalu_buffer_1[] = { - 0x00000018, - 0x00000013, - 0x00000001, - 0x00000007, - 0x00000001, - 0x46011000, -}; - -static const uint32_t uve_nalu_buffer_2[] = { - 0x0000002c, - 0x00000013, - 0x00000002, - 0x0000001b, - 0x00000001, - 0x40010c01, - 0xffff0160, - 0x00000300, - 0xb0000003, - 0x00000300, - 0x962c0900, -}; - -static const uint32_t uve_nalu_buffer_3[] = { - 0x00000034, - 0x00000013, - 0x00000003, - 0x00000023, - 0x00000001, - 0x42010101, - 0x60000003, - 0x00b00000, - 0x03000003, - 0x0096a018, - 0x2020708f, - 0xcb924295, - 0x12e08000, -}; - -static const uint32_t uve_nalu_buffer_4[] = { - 0x0000001c, - 0x00000013, - 0x00000004, - 0x0000000b, - 0x00000001, - 0x4401e0f1, - 0x80992000, -}; - -static const uint32_t uve_slice_header[] = { - 0x000000c8, - 0x0000000b, - 0x28010000, - 0x40000000, - 0x60000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000002, - 0x00000010, - 0x00000003, - 0x00000000, - 0x00000002, - 0x00000002, - 0x00000004, - 0x00000000, - 0x00000001, - 0x00000000, - 0x00000002, - 0x00000003, - 0x00000005, - 0x00000000, - 0x00000002, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_encode_param[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, - 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_intra_refresh[] = { - 0x00000014, - 0x0000000f, - 0x00000000, - 0x00000000, - 0x00000001, -}; - -static const uint32_t uve_ctx_buffer[] = { - 0x00000000, - 0x00000000, - 0x000000a0, - 0x000000a0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t uve_bitstream_buffer[] = { - 0x0000001c, - 0x00000011, -}; - -static const uint32_t uve_rc_per_pic[] = { - 0x00000024, - 0x0000000a, - 0x0000001a, - 0x00000000, - 0x00000033, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000001, -}; - -static const uint32_t uve_op_init[] = { - 0x00000008, - 0x08000001, -}; - -static const uint32_t uve_op_close[] = { - 0x00000008, - 0x08000002, -}; - -static const uint32_t uve_op_encode[] = { - 0x00000008, - 0x08000003, -}; - -static const uint32_t uve_op_init_rc[] = { - 0x00000008, - 0x08000004, -}; - -static const uint32_t uve_op_init_rc_vbv_level[] = { - 0x00000008, - 0x08000005, -}; - -static const uint32_t uve_op_speed_enc_mode[] = { - 0x00000008, - 0x08000006, -}; - -static const uint32_t uve_op_balance_enc_mode[] = { - 0x00000008, - 0x08000007, -}; - -static const uint32_t uve_op_quality_enc_mode[] = { - 0x00000008, - 0x08000008, -}; -#endif /*_uve_ib_h*/ diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h deleted file mode 100644 index f3108a040..000000000 --- a/tests/amdgpu/vce_ib.h +++ /dev/null @@ -1,335 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#ifndef _vce_ib_h_ -#define _vce_ib_h_ - -static const uint32_t vce_session[] = { - 0x0000000c, - 0x00000001, - 0x400c0001, -}; - -static uint32_t vce_taskinfo[8] = { - 0x00000020, - 0x00000002, - 0xffffffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_create[] = { - 0x00000030, - 0x01000001, - 0x00000000, - 0x00000042, - 0x0000002a, - 0x00000000, - 0x000000a0, - 0x00000080, - 0x000000a0, - 0x000000a0, - 0x00000010, - 0x00000201, -}; - -static const uint32_t vce_rate_ctrl[] = { - 0x00000070, - 0x04000005, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x0000001c, - 0x0000001c, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000033, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_config_ext[] = { - 0x0000000c, - 0x04000001, - 0x00000003, -}; - -static const uint32_t vce_motion_est[] = { - 0x00000068, - 0x04000007, - 0x00000001, - 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000010, - 0x00000010, - 0x00000010, - 0x00000010, - 0x00000000, - 0x00000000, - 0x00000000, - 0x000000fe, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000001, - 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_rdo[] = { - 0x0000004c, - 0x04000008, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_pic_ctrl[] = { - 0x00000074, - 0x04000002, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000aa0, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000040, - 0x00000000, - 0x00000000, - 0x00000001, - 0x00000002, - 0x00000001, - 0x00000001, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_feedback[] = { - 0x00000014, - 0x05000005, - 0x00000000, - 0xffffffff, - 0x00000001, -}; - -static const uint32_t vce_context_buffer[] = { - 0x00000010, - 0x05000001, - 0x00000000, - 0xffffffff, -}; - -static const uint32_t vce_bs_buffer[] = { - 0x00000014, - 0x05000004, - 0x00000000, - 0xffffffff, - 0x00154000, -}; - -static const uint32_t vce_aux_buffer[] = { - 0x00000048, - 0x05000002, - 0x0000f000, - 0x00016800, - 0x0001e000, - 0x00025800, - 0x0002d000, - 0x00034800, - 0x0003c000, - 0x00043800, - 0x00007800, - 0x00007800, - 0x00007800, - 0x00007800, - 0x00007800, - 0x00007800, - 0x00007800, - 0x00007800, -}; - -static uint32_t vce_encode[88] = { - 0x00000160, - 0x03000001, - 0x00000011, - 0x00000000, - 0x00154000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, - 0x00000000, - 0xffffffff, - 0x00000080, - 0x000000a0, - 0x000000a0, - 0x00010000, - 0x00000000, - 0x00000003, - 0x00000001, - 0x00000000, - 0x00000000, - 0x00000001, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, - 0xffffffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, - 0xffffffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0xffffffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -static const uint32_t vce_destroy[] = { - 0x00000008, - 0x02000001, -}; - -static const uint32_t vce_mv_buffer[] = { - 0x00000038, - 0x0500000d, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; -#endif /*_vce_ib_h*/ diff --git a/tests/amdgpu/vce_tests.c b/tests/amdgpu/vce_tests.c deleted file mode 100644 index 9aa0a8eb6..000000000 --- a/tests/amdgpu/vce_tests.c +++ /dev/null @@ -1,764 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include - -#include "CUnit/Basic.h" - -#include "util_math.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -#include "vce_ib.h" -#include "frame.h" - -#define IB_SIZE 4096 -#define MAX_RESOURCES 16 -#define FW_53_0_03 ((53 << 24) | (0 << 16) | (03 << 8)) - -struct amdgpu_vce_bo { - amdgpu_bo_handle handle; - amdgpu_va_handle va_handle; - uint64_t addr; - uint64_t size; - uint8_t *ptr; -}; - -struct amdgpu_vce_encode { - unsigned width; - unsigned height; - struct amdgpu_vce_bo vbuf; - struct amdgpu_vce_bo bs[2]; - struct amdgpu_vce_bo fb[2]; - struct amdgpu_vce_bo cpb; - unsigned ib_len; - bool two_instance; - struct amdgpu_vce_bo mvrefbuf; - struct amdgpu_vce_bo mvb; - unsigned mvbuf_size; -}; - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t vce_harvest_config; -static uint32_t chip_rev; -static uint32_t chip_id; -static uint32_t ids_flags; -static bool is_mv_supported = true; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static amdgpu_va_handle ib_va_handle; -static uint64_t ib_mc_address; -static uint32_t *ib_cpu; - -static struct amdgpu_vce_encode enc; -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; - -static void amdgpu_cs_vce_create(void); -static void amdgpu_cs_vce_encode(void); -static void amdgpu_cs_vce_encode_mv(void); -static void amdgpu_cs_vce_destroy(void); - -CU_TestInfo vce_tests[] = { - { "VCE create", amdgpu_cs_vce_create }, - { "VCE encode", amdgpu_cs_vce_encode }, - { "VCE MV dump", amdgpu_cs_vce_encode_mv }, - { "VCE destroy", amdgpu_cs_vce_destroy }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_vce_tests_enable(void) -{ - uint32_t version, feature; - CU_BOOL ret_mv = CU_FALSE; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - family_id = device_handle->info.family_id; - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - ids_flags = device_handle->info.ids_flags; - - amdgpu_query_firmware_version(device_handle, AMDGPU_INFO_FW_VCE, 0, - 0, &version, &feature); - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - if (family_id >= AMDGPU_FAMILY_RV || family_id == AMDGPU_FAMILY_SI || - asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) { - printf("\n\nThe ASIC NOT support VCE, suite disabled\n"); - return CU_FALSE; - } - - if (!(chip_id == (chip_rev + 0x3C) || /* FIJI */ - chip_id == (chip_rev + 0x50) || /* Polaris 10*/ - chip_id == (chip_rev + 0x5A) || /* Polaris 11*/ - chip_id == (chip_rev + 0x64) || /* Polaris 12*/ - (family_id >= AMDGPU_FAMILY_AI && !ids_flags))) /* dGPU > Polaris */ - printf("\n\nThe ASIC NOT support VCE MV, suite disabled\n"); - else if (FW_53_0_03 > version) - printf("\n\nThe ASIC FW version NOT support VCE MV, suite disabled\n"); - else - ret_mv = CU_TRUE; - - if (ret_mv == CU_FALSE) { - amdgpu_set_test_active("VCE Tests", "VCE MV dump", ret_mv); - is_mv_supported = false; - } - - return CU_TRUE; -} - -int suite_vce_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - - return CUE_SINIT_FAILED; - } - - family_id = device_handle->info.family_id; - vce_harvest_config = device_handle->info.vce_harvest_config; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_handle, (void**)&ib_cpu, - &ib_mc_address, &ib_va_handle); - if (r) - return CUE_SINIT_FAILED; - - memset(&enc, 0, sizeof(struct amdgpu_vce_encode)); - - return CUE_SUCCESS; -} - -int suite_vce_tests_clean(void) -{ - int r; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static int submit(unsigned ndw, unsigned ip) -{ - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - int r; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = ndw; - - ibs_request.ip_type = ip; - - r = amdgpu_bo_list_create(device_handle, num_resources, resources, - NULL, &ibs_request.resources); - if (r) - return r; - - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = ip; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - return 0; -} - -static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - int r; - - req.alloc_size = ALIGN(size, 4096); - req.preferred_heap = domain; - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - vce_bo->addr = va; - vce_bo->handle = buf_handle; - vce_bo->size = req.alloc_size; - vce_bo->va_handle = va_handle; - r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr); - CU_ASSERT_EQUAL(r, 0); - memset(vce_bo->ptr, 0, size); - r = amdgpu_bo_cpu_unmap(vce_bo->handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void free_resource(struct amdgpu_vce_bo *vce_bo) -{ - int r; - - r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size, - vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(vce_bo->va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(vce_bo->handle); - CU_ASSERT_EQUAL(r, 0); - memset(vce_bo, 0, sizeof(*vce_bo)); -} - -static void amdgpu_cs_vce_create(void) -{ - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int len, r; - - enc.width = vce_create[6]; - enc.height = vce_create[7]; - - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; - resources[num_resources++] = ib_handle; - - len = 0; - memcpy(ib_cpu, vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); - ib_cpu[len + 8] = ALIGN(enc.width, align); - ib_cpu[len + 9] = ALIGN(enc.width, align); - if (is_mv_supported == true) {/* disableTwoInstance */ - if (family_id >= AMDGPU_FAMILY_AI) - ib_cpu[len + 11] = 0x01000001; - else - ib_cpu[len + 11] = 0x01000201; - } - len += sizeof(vce_create) / 4; - memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); - ib_cpu[len + 2] = enc.fb[0].addr >> 32; - ib_cpu[len + 3] = enc.fb[0].addr; - len += sizeof(vce_feedback) / 4; - - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); - - free_resource(&enc.fb[0]); -} - -static void amdgpu_cs_vce_config(void) -{ - int len = 0, r; - - memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - ib_cpu[len + 3] = 2; - ib_cpu[len + 6] = 0xffffffff; - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl)); - len += sizeof(vce_rate_ctrl) / 4; - memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext)); - len += sizeof(vce_config_ext) / 4; - memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est)); - len += sizeof(vce_motion_est) / 4; - memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo)); - len += sizeof(vce_rdo) / 4; - memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl)); - if (is_mv_supported == true) - ib_cpu[len + 27] = 0x00000001; /* encSliceMode */ - len += sizeof(vce_pic_ctrl) / 4; - - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) -{ - - uint64_t luma_offset, chroma_offset; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); - int len = 0, i, r; - - luma_offset = enc->vbuf.addr; - chroma_offset = luma_offset + luma_size; - - memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); - ib_cpu[len + 2] = enc->bs[0].addr >> 32; - ib_cpu[len + 3] = enc->bs[0].addr; - len += sizeof(vce_bs_buffer) / 4; - memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); - ib_cpu[len + 2] = enc->cpb.addr >> 32; - ib_cpu[len + 3] = enc->cpb.addr; - len += sizeof(vce_context_buffer) / 4; - memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); - for (i = 0; i < 8; ++i) - ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); - for (i = 0; i < 8; ++i) - ib_cpu[len + 10 + i] = luma_size * 1.5; - len += sizeof(vce_aux_buffer) / 4; - memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); - ib_cpu[len + 2] = enc->fb[0].addr >> 32; - ib_cpu[len + 3] = enc->fb[0].addr; - len += sizeof(vce_feedback) / 4; - memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); - ib_cpu[len + 9] = luma_offset >> 32; - ib_cpu[len + 10] = luma_offset; - ib_cpu[len + 11] = chroma_offset >> 32; - ib_cpu[len + 12] = chroma_offset; - ib_cpu[len + 14] = ALIGN(enc->width, align); - ib_cpu[len + 15] = ALIGN(enc->width, align); - ib_cpu[len + 73] = luma_size * 1.5; - ib_cpu[len + 74] = luma_size * 2.5; - len += sizeof(vce_encode) / 4; - enc->ib_len = len; - if (!enc->two_instance) { - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); - } -} - -static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) -{ - uint64_t luma_offset, chroma_offset; - int len, i, r; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); - - len = (enc->two_instance) ? enc->ib_len : 0; - luma_offset = enc->vbuf.addr; - chroma_offset = luma_offset + luma_size; - - if (!enc->two_instance) { - memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - } - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); - ib_cpu[len + 2] = enc->bs[1].addr >> 32; - ib_cpu[len + 3] = enc->bs[1].addr; - len += sizeof(vce_bs_buffer) / 4; - memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); - ib_cpu[len + 2] = enc->cpb.addr >> 32; - ib_cpu[len + 3] = enc->cpb.addr; - len += sizeof(vce_context_buffer) / 4; - memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); - for (i = 0; i < 8; ++i) - ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); - for (i = 0; i < 8; ++i) - ib_cpu[len + 10 + i] = luma_size * 1.5; - len += sizeof(vce_aux_buffer) / 4; - memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); - ib_cpu[len + 2] = enc->fb[1].addr >> 32; - ib_cpu[len + 3] = enc->fb[1].addr; - len += sizeof(vce_feedback) / 4; - memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); - ib_cpu[len + 2] = 0; - ib_cpu[len + 9] = luma_offset >> 32; - ib_cpu[len + 10] = luma_offset; - ib_cpu[len + 11] = chroma_offset >> 32; - ib_cpu[len + 12] = chroma_offset; - ib_cpu[len + 14] = ALIGN(enc->width, align); - ib_cpu[len + 15] = ALIGN(enc->width, align); - ib_cpu[len + 18] = 0; - ib_cpu[len + 19] = 0; - ib_cpu[len + 56] = 3; - ib_cpu[len + 57] = 0; - ib_cpu[len + 58] = 0; - ib_cpu[len + 59] = luma_size * 1.5; - ib_cpu[len + 60] = luma_size * 2.5; - ib_cpu[len + 73] = 0; - ib_cpu[len + 74] = luma_size; - ib_cpu[len + 81] = 1; - ib_cpu[len + 82] = 1; - len += sizeof(vce_encode) / 4; - - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); -} - -static void check_result(struct amdgpu_vce_encode *enc) -{ - uint64_t sum; - uint32_t s[2] = {180325, 15946}; - uint32_t *ptr, size; - int i, j, r; - - for (i = 0; i < 2; ++i) { - r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr); - CU_ASSERT_EQUAL(r, 0); - ptr = (uint32_t *)enc->fb[i].ptr; - size = ptr[4] - ptr[9]; - r = amdgpu_bo_cpu_unmap(enc->fb[i].handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr); - CU_ASSERT_EQUAL(r, 0); - for (j = 0, sum = 0; j < size; ++j) - sum += enc->bs[i].ptr[j]; - CU_ASSERT_EQUAL(sum, s[i]); - r = amdgpu_bo_cpu_unmap(enc->bs[i].handle); - CU_ASSERT_EQUAL(r, 0); - } -} - -static void amdgpu_cs_vce_encode(void) -{ - uint32_t vbuf_size, bs_size = 0x154000, cpb_size; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - cpb_size = vbuf_size * 10; - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; - alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[1].handle; - alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.bs[0].handle; - alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.bs[1].handle; - alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.vbuf.handle; - alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.cpb.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(enc.vbuf.ptr, 0, vbuf_size); - for (i = 0; i < enc.height; ++i) { - memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - for (i = 0; i < enc.height / 2; ++i) { - memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - - r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); - CU_ASSERT_EQUAL(r, 0); - - amdgpu_cs_vce_config(); - - if (family_id >= AMDGPU_FAMILY_VI) { - vce_taskinfo[3] = 3; - amdgpu_cs_vce_encode_idr(&enc); - amdgpu_cs_vce_encode_p(&enc); - check_result(&enc); - - /* two pipes */ - vce_encode[16] = 0; - amdgpu_cs_vce_encode_idr(&enc); - amdgpu_cs_vce_encode_p(&enc); - check_result(&enc); - - /* two instances */ - if (vce_harvest_config == 0) { - enc.two_instance = true; - vce_taskinfo[2] = 0x83; - vce_taskinfo[4] = 1; - amdgpu_cs_vce_encode_idr(&enc); - vce_taskinfo[2] = 0xffffffff; - vce_taskinfo[4] = 2; - amdgpu_cs_vce_encode_p(&enc); - check_result(&enc); - } - } else { - vce_taskinfo[3] = 3; - vce_encode[16] = 0; - amdgpu_cs_vce_encode_idr(&enc); - amdgpu_cs_vce_encode_p(&enc); - check_result(&enc); - } - - free_resource(&enc.fb[0]); - free_resource(&enc.fb[1]); - free_resource(&enc.bs[0]); - free_resource(&enc.bs[1]); - free_resource(&enc.vbuf); - free_resource(&enc.cpb); -} - -static void amdgpu_cs_vce_mv(struct amdgpu_vce_encode *enc) -{ - uint64_t luma_offset, chroma_offset; - uint64_t mv_ref_luma_offset; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - unsigned luma_size = ALIGN(enc->width, align) * ALIGN(enc->height, 16); - int len = 0, i, r; - - luma_offset = enc->vbuf.addr; - chroma_offset = luma_offset + luma_size; - mv_ref_luma_offset = enc->mvrefbuf.addr; - - memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); - ib_cpu[len + 2] = enc->bs[0].addr >> 32; - ib_cpu[len + 3] = enc->bs[0].addr; - len += sizeof(vce_bs_buffer) / 4; - memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); - ib_cpu[len + 2] = enc->cpb.addr >> 32; - ib_cpu[len + 3] = enc->cpb.addr; - len += sizeof(vce_context_buffer) / 4; - memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); - for (i = 0; i < 8; ++i) - ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2); - for (i = 0; i < 8; ++i) - ib_cpu[len + 10 + i] = luma_size * 1.5; - len += sizeof(vce_aux_buffer) / 4; - memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); - ib_cpu[len + 2] = enc->fb[0].addr >> 32; - ib_cpu[len + 3] = enc->fb[0].addr; - len += sizeof(vce_feedback) / 4; - memcpy((ib_cpu + len), vce_mv_buffer, sizeof(vce_mv_buffer)); - ib_cpu[len + 2] = mv_ref_luma_offset >> 32; - ib_cpu[len + 3] = mv_ref_luma_offset; - ib_cpu[len + 4] = ALIGN(enc->width, align); - ib_cpu[len + 5] = ALIGN(enc->width, align); - ib_cpu[len + 6] = luma_size; - ib_cpu[len + 7] = enc->mvb.addr >> 32; - ib_cpu[len + 8] = enc->mvb.addr; - len += sizeof(vce_mv_buffer) / 4; - memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); - ib_cpu[len + 2] = 0; - ib_cpu[len + 3] = 0; - ib_cpu[len + 4] = 0x154000; - ib_cpu[len + 9] = luma_offset >> 32; - ib_cpu[len + 10] = luma_offset; - ib_cpu[len + 11] = chroma_offset >> 32; - ib_cpu[len + 12] = chroma_offset; - ib_cpu[len + 13] = ALIGN(enc->height, 16);; - ib_cpu[len + 14] = ALIGN(enc->width, align); - ib_cpu[len + 15] = ALIGN(enc->width, align); - /* encDisableMBOffloading-encDisableTwoPipeMode-encInputPicArrayMode-encInputPicAddrMode */ - ib_cpu[len + 16] = 0x01010000; - ib_cpu[len + 18] = 0; /* encPicType */ - ib_cpu[len + 19] = 0; /* encIdrFlag */ - ib_cpu[len + 20] = 0; /* encIdrPicId */ - ib_cpu[len + 21] = 0; /* encMGSKeyPic */ - ib_cpu[len + 22] = 0; /* encReferenceFlag */ - ib_cpu[len + 23] = 0; /* encTemporalLayerIndex */ - ib_cpu[len + 55] = 0; /* pictureStructure */ - ib_cpu[len + 56] = 0; /* encPicType -ref[0] */ - ib_cpu[len + 61] = 0; /* pictureStructure */ - ib_cpu[len + 62] = 0; /* encPicType -ref[1] */ - ib_cpu[len + 67] = 0; /* pictureStructure */ - ib_cpu[len + 68] = 0; /* encPicType -ref1 */ - ib_cpu[len + 81] = 1; /* frameNumber */ - ib_cpu[len + 82] = 2; /* pictureOrderCount */ - ib_cpu[len + 83] = 0xffffffff; /* numIPicRemainInRCGOP */ - ib_cpu[len + 84] = 0xffffffff; /* numPPicRemainInRCGOP */ - ib_cpu[len + 85] = 0xffffffff; /* numBPicRemainInRCGOP */ - ib_cpu[len + 86] = 0xffffffff; /* numIRPicRemainInRCGOP */ - ib_cpu[len + 87] = 0; /* remainedIntraRefreshPictures */ - len += sizeof(vce_encode) / 4; - - enc->ib_len = len; - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); -} - -static void check_mv_result(struct amdgpu_vce_encode *enc) -{ - uint64_t sum; - uint32_t s = 140790; - int j, r; - - r = amdgpu_bo_cpu_map(enc->fb[0].handle, (void **)&enc->fb[0].ptr); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_unmap(enc->fb[0].handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_map(enc->mvb.handle, (void **)&enc->mvb.ptr); - CU_ASSERT_EQUAL(r, 0); - for (j = 0, sum = 0; j < enc->mvbuf_size; ++j) - sum += enc->mvb.ptr[j]; - CU_ASSERT_EQUAL(sum, s); - r = amdgpu_bo_cpu_unmap(enc->mvb.handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_vce_encode_mv(void) -{ - uint32_t vbuf_size, bs_size = 0x154000, cpb_size; - unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16; - int i, r; - - vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5; - enc.mvbuf_size = ALIGN(enc.width, 16) * ALIGN(enc.height, 16) / 8; - cpb_size = vbuf_size * 10; - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; - alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.bs[0].handle; - alloc_resource(&enc.mvb, enc.mvbuf_size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.mvb.handle; - alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.vbuf.handle; - alloc_resource(&enc.mvrefbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.mvrefbuf.handle; - alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = enc.cpb.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(enc.vbuf.ptr, 0, vbuf_size); - for (i = 0; i < enc.height; ++i) { - memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - for (i = 0; i < enc.height / 2; ++i) { - memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i * enc.width), enc.width); - enc.vbuf.ptr += ALIGN(enc.width, align); - } - - r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_cpu_map(enc.mvrefbuf.handle, (void **)&enc.mvrefbuf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(enc.mvrefbuf.ptr, 0, vbuf_size); - for (i = 0; i < enc.height; ++i) { - memcpy(enc.mvrefbuf.ptr, (frame + (enc.height - i -1) * enc.width), enc.width); - enc.mvrefbuf.ptr += ALIGN(enc.width, align); - } - for (i = 0; i < enc.height / 2; ++i) { - memcpy(enc.mvrefbuf.ptr, - ((frame + enc.height * enc.width) + (enc.height / 2 - i -1) * enc.width), enc.width); - enc.mvrefbuf.ptr += ALIGN(enc.width, align); - } - - r = amdgpu_bo_cpu_unmap(enc.mvrefbuf.handle); - CU_ASSERT_EQUAL(r, 0); - - amdgpu_cs_vce_config(); - - vce_taskinfo[3] = 3; - amdgpu_cs_vce_mv(&enc); - check_mv_result(&enc); - - free_resource(&enc.fb[0]); - free_resource(&enc.bs[0]); - free_resource(&enc.vbuf); - free_resource(&enc.cpb); - free_resource(&enc.mvrefbuf); - free_resource(&enc.mvb); -} - -static void amdgpu_cs_vce_destroy(void) -{ - int len, r; - - num_resources = 0; - alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc.fb[0].handle; - resources[num_resources++] = ib_handle; - - len = 0; - memcpy(ib_cpu, vce_session, sizeof(vce_session)); - len += sizeof(vce_session) / 4; - memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); - ib_cpu[len + 3] = 1; - len += sizeof(vce_taskinfo) / 4; - memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); - ib_cpu[len + 2] = enc.fb[0].addr >> 32; - ib_cpu[len + 3] = enc.fb[0].addr; - len += sizeof(vce_feedback) / 4; - memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy)); - len += sizeof(vce_destroy) / 4; - - r = submit(len, AMDGPU_HW_IP_VCE); - CU_ASSERT_EQUAL(r, 0); - - free_resource(&enc.fb[0]); -} diff --git a/tests/amdgpu/vcn_tests.c b/tests/amdgpu/vcn_tests.c deleted file mode 100644 index c83fdb533..000000000 --- a/tests/amdgpu/vcn_tests.c +++ /dev/null @@ -1,1652 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include -#include -#include -#include - -#include "CUnit/Basic.h" - -#include -#include "util_math.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" -#include "decode_messages.h" -#include "frame.h" - -#define IB_SIZE 4096 -#define MAX_RESOURCES 16 - -#define DECODE_CMD_MSG_BUFFER 0x00000000 -#define DECODE_CMD_DPB_BUFFER 0x00000001 -#define DECODE_CMD_DECODING_TARGET_BUFFER 0x00000002 -#define DECODE_CMD_FEEDBACK_BUFFER 0x00000003 -#define DECODE_CMD_PROB_TBL_BUFFER 0x00000004 -#define DECODE_CMD_SESSION_CONTEXT_BUFFER 0x00000005 -#define DECODE_CMD_BITSTREAM_BUFFER 0x00000100 -#define DECODE_CMD_IT_SCALING_TABLE_BUFFER 0x00000204 -#define DECODE_CMD_CONTEXT_BUFFER 0x00000206 - -#define DECODE_IB_PARAM_DECODE_BUFFER (0x00000001) - -#define DECODE_CMDBUF_FLAGS_MSG_BUFFER (0x00000001) -#define DECODE_CMDBUF_FLAGS_DPB_BUFFER (0x00000002) -#define DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER (0x00000004) -#define DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER (0x00000008) -#define DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER (0x00000010) -#define DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER (0x00000200) -#define DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER (0x00000800) -#define DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER (0x00001000) -#define DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER (0x00100000) - -static bool vcn_dec_sw_ring = false; -static bool vcn_unified_ring = false; - -#define H264_NAL_TYPE_NON_IDR_SLICE 1 -#define H264_NAL_TYPE_DP_A_SLICE 2 -#define H264_NAL_TYPE_DP_B_SLICE 3 -#define H264_NAL_TYPE_DP_C_SLICE 0x4 -#define H264_NAL_TYPE_IDR_SLICE 0x5 -#define H264_NAL_TYPE_SEI 0x6 -#define H264_NAL_TYPE_SEQ_PARAM 0x7 -#define H264_NAL_TYPE_PIC_PARAM 0x8 -#define H264_NAL_TYPE_ACCESS_UNIT 0x9 -#define H264_NAL_TYPE_END_OF_SEQ 0xa -#define H264_NAL_TYPE_END_OF_STREAM 0xb -#define H264_NAL_TYPE_FILLER_DATA 0xc -#define H264_NAL_TYPE_SEQ_EXTENSION 0xd - -#define H264_START_CODE 0x000001 - -struct amdgpu_vcn_bo { - amdgpu_bo_handle handle; - amdgpu_va_handle va_handle; - uint64_t addr; - uint64_t size; - uint8_t *ptr; -}; - -typedef struct rvcn_decode_buffer_s { - unsigned int valid_buf_flag; - unsigned int msg_buffer_address_hi; - unsigned int msg_buffer_address_lo; - unsigned int dpb_buffer_address_hi; - unsigned int dpb_buffer_address_lo; - unsigned int target_buffer_address_hi; - unsigned int target_buffer_address_lo; - unsigned int session_contex_buffer_address_hi; - unsigned int session_contex_buffer_address_lo; - unsigned int bitstream_buffer_address_hi; - unsigned int bitstream_buffer_address_lo; - unsigned int context_buffer_address_hi; - unsigned int context_buffer_address_lo; - unsigned int feedback_buffer_address_hi; - unsigned int feedback_buffer_address_lo; - unsigned int luma_hist_buffer_address_hi; - unsigned int luma_hist_buffer_address_lo; - unsigned int prob_tbl_buffer_address_hi; - unsigned int prob_tbl_buffer_address_lo; - unsigned int sclr_coeff_buffer_address_hi; - unsigned int sclr_coeff_buffer_address_lo; - unsigned int it_sclr_table_buffer_address_hi; - unsigned int it_sclr_table_buffer_address_lo; - unsigned int sclr_target_buffer_address_hi; - unsigned int sclr_target_buffer_address_lo; - unsigned int cenc_size_info_buffer_address_hi; - unsigned int cenc_size_info_buffer_address_lo; - unsigned int mpeg2_pic_param_buffer_address_hi; - unsigned int mpeg2_pic_param_buffer_address_lo; - unsigned int mpeg2_mb_control_buffer_address_hi; - unsigned int mpeg2_mb_control_buffer_address_lo; - unsigned int mpeg2_idct_coeff_buffer_address_hi; - unsigned int mpeg2_idct_coeff_buffer_address_lo; -} rvcn_decode_buffer_t; - -typedef struct rvcn_decode_ib_package_s { - unsigned int package_size; - unsigned int package_type; -} rvcn_decode_ib_package_t; - - -struct amdgpu_vcn_reg { - uint32_t data0; - uint32_t data1; - uint32_t cmd; - uint32_t nop; - uint32_t cntl; -}; - -typedef struct BufferInfo_t { - uint32_t numOfBitsInBuffer; - const uint8_t *decBuffer; - uint8_t decData; - uint32_t decBufferSize; - const uint8_t *end; -} bufferInfo; - -typedef struct h264_decode_t { - uint8_t profile; - uint8_t level_idc; - uint8_t nal_ref_idc; - uint8_t nal_unit_type; - uint32_t pic_width, pic_height; - uint32_t slice_type; -} h264_decode; - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t chip_rev; -static uint32_t chip_id; -static uint32_t asic_id; -static uint32_t chip_rev; -static struct amdgpu_vcn_bo enc_buf; -static struct amdgpu_vcn_bo cpb_buf; -static uint32_t enc_task_id; - -static amdgpu_context_handle context_handle; -static amdgpu_bo_handle ib_handle; -static amdgpu_va_handle ib_va_handle; -static uint64_t ib_mc_address; -static uint32_t *ib_cpu; -static uint32_t *ib_checksum; -static uint32_t *ib_size_in_dw; - -static rvcn_decode_buffer_t *decode_buffer; -struct amdgpu_vcn_bo session_ctx_buf; - -static amdgpu_bo_handle resources[MAX_RESOURCES]; -static unsigned num_resources; - -static uint8_t vcn_reg_index; -static struct amdgpu_vcn_reg reg[] = { - {0x81c4, 0x81c5, 0x81c3, 0x81ff, 0x81c6}, - {0x504, 0x505, 0x503, 0x53f, 0x506}, - {0x10, 0x11, 0xf, 0x29, 0x26d}, -}; - -uint32_t gWidth, gHeight, gSliceType; -static uint32_t vcn_ip_version_major; -static uint32_t vcn_ip_version_minor; -static void amdgpu_cs_vcn_dec_create(void); -static void amdgpu_cs_vcn_dec_decode(void); -static void amdgpu_cs_vcn_dec_destroy(void); - -static void amdgpu_cs_vcn_enc_create(void); -static void amdgpu_cs_vcn_enc_encode(void); -static void amdgpu_cs_vcn_enc_destroy(void); - -static void amdgpu_cs_sq_head(uint32_t *base, int *offset, bool enc); -static void amdgpu_cs_sq_ib_tail(uint32_t *end); -static void h264_check_0s (bufferInfo * bufInfo, int count); -static int32_t h264_se (bufferInfo * bufInfo); -static inline uint32_t bs_read_u1(bufferInfo *bufinfo); -static inline int bs_eof(bufferInfo *bufinfo); -static inline uint32_t bs_read_u(bufferInfo* bufinfo, int n); -static inline uint32_t bs_read_ue(bufferInfo* bufinfo); -static uint32_t remove_03 (uint8_t *bptr, uint32_t len); -static void scaling_list (uint32_t ix, uint32_t sizeOfScalingList, bufferInfo *bufInfo); -static void h264_parse_sequence_parameter_set (h264_decode * dec, bufferInfo *bufInfo); -static void h264_slice_header (h264_decode *dec, bufferInfo *bufInfo); -static uint8_t h264_parse_nal (h264_decode *dec, bufferInfo *bufInfo); -static uint32_t h264_find_next_start_code (uint8_t *pBuf, uint32_t bufLen); -static int verify_checksum(uint8_t *buffer, uint32_t buffer_size); - -CU_TestInfo vcn_tests[] = { - - { "VCN DEC create", amdgpu_cs_vcn_dec_create }, - { "VCN DEC decode", amdgpu_cs_vcn_dec_decode }, - { "VCN DEC destroy", amdgpu_cs_vcn_dec_destroy }, - - { "VCN ENC create", amdgpu_cs_vcn_enc_create }, - { "VCN ENC encode", amdgpu_cs_vcn_enc_encode }, - { "VCN ENC destroy", amdgpu_cs_vcn_enc_destroy }, - CU_TEST_INFO_NULL, -}; - -CU_BOOL suite_vcn_tests_enable(void) -{ - struct drm_amdgpu_info_hw_ip info; - bool enc_ring, dec_ring; - int r; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - family_id = device_handle->info.family_id; - asic_id = device_handle->info.asic_id; - chip_rev = device_handle->info.chip_rev; - chip_id = device_handle->info.chip_external_rev; - - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_ENC, 0, &info); - if (!r) { - vcn_ip_version_major = info.hw_ip_version_major; - vcn_ip_version_minor = info.hw_ip_version_minor; - enc_ring = !!info.available_rings; - /* in vcn 4.0 it re-uses encoding queue as unified queue */ - if (vcn_ip_version_major >= 4) { - vcn_unified_ring = true; - vcn_dec_sw_ring = true; - dec_ring = enc_ring; - } else { - r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_VCN_DEC, 0, &info); - dec_ring = !!info.available_rings; - } - } - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - if (r) { - printf("\n\nASIC query hw info failed\n"); - return CU_FALSE; - } - - if (!(dec_ring || enc_ring) || - (family_id < AMDGPU_FAMILY_RV && - (family_id == AMDGPU_FAMILY_AI && - (chip_id - chip_rev) < 0x32))) { /* Arcturus */ - printf("\n\nThe ASIC NOT support VCN, suite disabled\n"); - return CU_FALSE; - } - - if (!dec_ring) { - amdgpu_set_test_active("VCN Tests", "VCN DEC create", CU_FALSE); - amdgpu_set_test_active("VCN Tests", "VCN DEC decode", CU_FALSE); - amdgpu_set_test_active("VCN Tests", "VCN DEC destroy", CU_FALSE); - } - - if (family_id == AMDGPU_FAMILY_AI || !enc_ring) { - amdgpu_set_test_active("VCN Tests", "VCN ENC create", CU_FALSE); - amdgpu_set_test_active("VCN Tests", "VCN ENC encode", CU_FALSE); - amdgpu_set_test_active("VCN Tests", "VCN ENC destroy", CU_FALSE); - } - - if (vcn_ip_version_major == 1) - vcn_reg_index = 0; - else if (vcn_ip_version_major == 2 && vcn_ip_version_minor == 0) - vcn_reg_index = 1; - else if ((vcn_ip_version_major == 2 && vcn_ip_version_minor >= 5) || - vcn_ip_version_major == 3) - vcn_reg_index = 2; - - return CU_TRUE; -} - -int suite_vcn_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - if (r) - return CUE_SINIT_FAILED; - - family_id = device_handle->info.family_id; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - if (r) - return CUE_SINIT_FAILED; - - r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_handle, (void**)&ib_cpu, - &ib_mc_address, &ib_va_handle); - if (r) - return CUE_SINIT_FAILED; - - return CUE_SUCCESS; -} - -int suite_vcn_tests_clean(void) -{ - int r; - - r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, - ib_mc_address, IB_SIZE); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_cs_ctx_free(context_handle); - if (r) - return CUE_SCLEAN_FAILED; - - r = amdgpu_device_deinitialize(device_handle); - if (r) - return CUE_SCLEAN_FAILED; - - return CUE_SUCCESS; -} - -static void amdgpu_cs_sq_head(uint32_t *base, int *offset, bool enc) -{ - /* signature */ - *(base + (*offset)++) = 0x00000010; - *(base + (*offset)++) = 0x30000002; - ib_checksum = base + (*offset)++; - ib_size_in_dw = base + (*offset)++; - - /* engine info */ - *(base + (*offset)++) = 0x00000010; - *(base + (*offset)++) = 0x30000001; - *(base + (*offset)++) = enc ? 2 : 3; - *(base + (*offset)++) = 0x00000000; -} - -static void amdgpu_cs_sq_ib_tail(uint32_t *end) -{ - uint32_t size_in_dw; - uint32_t checksum = 0; - - /* if the pointers are invalid, no need to process */ - if (ib_checksum == NULL || ib_size_in_dw == NULL) - return; - - size_in_dw = end - ib_size_in_dw - 1; - *ib_size_in_dw = size_in_dw; - *(ib_size_in_dw + 4) = size_in_dw * sizeof(uint32_t); - - for (int i = 0; i < size_in_dw; i++) - checksum += *(ib_checksum + 2 + i); - - *ib_checksum = checksum; - - ib_checksum = NULL; - ib_size_in_dw = NULL; -} - -static int submit(unsigned ndw, unsigned ip) -{ - struct amdgpu_cs_request ibs_request = {0}; - struct amdgpu_cs_ib_info ib_info = {0}; - struct amdgpu_cs_fence fence_status = {0}; - uint32_t expired; - int r; - - ib_info.ib_mc_address = ib_mc_address; - ib_info.size = ndw; - - ibs_request.ip_type = ip; - - r = amdgpu_bo_list_create(device_handle, num_resources, resources, - NULL, &ibs_request.resources); - if (r) - return r; - - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); - if (r) - return r; - - r = amdgpu_bo_list_destroy(ibs_request.resources); - if (r) - return r; - - fence_status.context = context_handle; - fence_status.ip_type = ip; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE, - 0, &expired); - if (r) - return r; - - return 0; -} - -static void alloc_resource(struct amdgpu_vcn_bo *vcn_bo, - unsigned size, unsigned domain) -{ - struct amdgpu_bo_alloc_request req = {0}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle va_handle; - uint64_t va = 0; - int r; - - req.alloc_size = ALIGN(size, 4096); - req.preferred_heap = domain; - r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_va_range_alloc(device_handle, - amdgpu_gpu_va_range_general, - req.alloc_size, 1, 0, &va, - &va_handle, 0); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - vcn_bo->addr = va; - vcn_bo->handle = buf_handle; - vcn_bo->size = req.alloc_size; - vcn_bo->va_handle = va_handle; - r = amdgpu_bo_cpu_map(vcn_bo->handle, (void **)&vcn_bo->ptr); - CU_ASSERT_EQUAL(r, 0); - memset(vcn_bo->ptr, 0, size); - r = amdgpu_bo_cpu_unmap(vcn_bo->handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void free_resource(struct amdgpu_vcn_bo *vcn_bo) -{ - int r; - - r = amdgpu_bo_va_op(vcn_bo->handle, 0, vcn_bo->size, - vcn_bo->addr, 0, AMDGPU_VA_OP_UNMAP); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_va_range_free(vcn_bo->va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_free(vcn_bo->handle); - CU_ASSERT_EQUAL(r, 0); - memset(vcn_bo, 0, sizeof(*vcn_bo)); -} - -static void vcn_dec_cmd(uint64_t addr, unsigned cmd, int *idx) -{ - if (vcn_dec_sw_ring == false) { - ib_cpu[(*idx)++] = reg[vcn_reg_index].data0; - ib_cpu[(*idx)++] = addr; - ib_cpu[(*idx)++] = reg[vcn_reg_index].data1; - ib_cpu[(*idx)++] = addr >> 32; - ib_cpu[(*idx)++] = reg[vcn_reg_index].cmd; - ib_cpu[(*idx)++] = cmd << 1; - return; - } - - /* Support decode software ring message */ - if (!(*idx)) { - rvcn_decode_ib_package_t *ib_header; - - if (vcn_unified_ring) - amdgpu_cs_sq_head(ib_cpu, idx, false); - - ib_header = (rvcn_decode_ib_package_t *)&ib_cpu[*idx]; - ib_header->package_size = sizeof(struct rvcn_decode_buffer_s) + - sizeof(struct rvcn_decode_ib_package_s); - - (*idx)++; - ib_header->package_type = (DECODE_IB_PARAM_DECODE_BUFFER); - (*idx)++; - - decode_buffer = (rvcn_decode_buffer_t *)&(ib_cpu[*idx]); - *idx += sizeof(struct rvcn_decode_buffer_s) / 4; - memset(decode_buffer, 0, sizeof(struct rvcn_decode_buffer_s)); - } - - switch(cmd) { - case DECODE_CMD_MSG_BUFFER: - decode_buffer->valid_buf_flag |= DECODE_CMDBUF_FLAGS_MSG_BUFFER; - decode_buffer->msg_buffer_address_hi = (addr >> 32); - decode_buffer->msg_buffer_address_lo = (addr); - break; - case DECODE_CMD_DPB_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DPB_BUFFER); - decode_buffer->dpb_buffer_address_hi = (addr >> 32); - decode_buffer->dpb_buffer_address_lo = (addr); - break; - case DECODE_CMD_DECODING_TARGET_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_DECODING_TARGET_BUFFER); - decode_buffer->target_buffer_address_hi = (addr >> 32); - decode_buffer->target_buffer_address_lo = (addr); - break; - case DECODE_CMD_FEEDBACK_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_FEEDBACK_BUFFER); - decode_buffer->feedback_buffer_address_hi = (addr >> 32); - decode_buffer->feedback_buffer_address_lo = (addr); - break; - case DECODE_CMD_PROB_TBL_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_PROB_TBL_BUFFER); - decode_buffer->prob_tbl_buffer_address_hi = (addr >> 32); - decode_buffer->prob_tbl_buffer_address_lo = (addr); - break; - case DECODE_CMD_SESSION_CONTEXT_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_SESSION_CONTEXT_BUFFER); - decode_buffer->session_contex_buffer_address_hi = (addr >> 32); - decode_buffer->session_contex_buffer_address_lo = (addr); - break; - case DECODE_CMD_BITSTREAM_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_BITSTREAM_BUFFER); - decode_buffer->bitstream_buffer_address_hi = (addr >> 32); - decode_buffer->bitstream_buffer_address_lo = (addr); - break; - case DECODE_CMD_IT_SCALING_TABLE_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_IT_SCALING_BUFFER); - decode_buffer->it_sclr_table_buffer_address_hi = (addr >> 32); - decode_buffer->it_sclr_table_buffer_address_lo = (addr); - break; - case DECODE_CMD_CONTEXT_BUFFER: - decode_buffer->valid_buf_flag |= (DECODE_CMDBUF_FLAGS_CONTEXT_BUFFER); - decode_buffer->context_buffer_address_hi = (addr >> 32); - decode_buffer->context_buffer_address_lo = (addr); - break; - default: - printf("Not Support!\n"); - } -} - -static void amdgpu_cs_vcn_dec_create(void) -{ - struct amdgpu_vcn_bo msg_buf; - unsigned ip; - int len, r; - - num_resources = 0; - alloc_resource(&msg_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); - alloc_resource(&session_ctx_buf, 32 * 4096, AMDGPU_GEM_DOMAIN_VRAM); - resources[num_resources++] = msg_buf.handle; - resources[num_resources++] = session_ctx_buf.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(msg_buf.ptr, 0, 4096); - memcpy(msg_buf.ptr, vcn_dec_create_msg, sizeof(vcn_dec_create_msg)); - - len = 0; - - vcn_dec_cmd(session_ctx_buf.addr, 5, &len); - if (vcn_dec_sw_ring == true) { - vcn_dec_cmd(msg_buf.addr, 0, &len); - } else { - ib_cpu[len++] = reg[vcn_reg_index].data0; - ib_cpu[len++] = msg_buf.addr; - ib_cpu[len++] = reg[vcn_reg_index].data1; - ib_cpu[len++] = msg_buf.addr >> 32; - ib_cpu[len++] = reg[vcn_reg_index].cmd; - ib_cpu[len++] = 0; - for (; len % 16; ) { - ib_cpu[len++] = reg[vcn_reg_index].nop; - ib_cpu[len++] = 0; - } - } - - if (vcn_unified_ring) { - amdgpu_cs_sq_ib_tail(ib_cpu + len); - ip = AMDGPU_HW_IP_VCN_ENC; - } else - ip = AMDGPU_HW_IP_VCN_DEC; - - r = submit(len, ip); - - CU_ASSERT_EQUAL(r, 0); - - free_resource(&msg_buf); -} - -static void amdgpu_cs_vcn_dec_decode(void) -{ - const unsigned dpb_size = 15923584, dt_size = 737280; - uint64_t msg_addr, fb_addr, bs_addr, dpb_addr, ctx_addr, dt_addr, it_addr, sum; - struct amdgpu_vcn_bo dec_buf; - int size, len, i, r; - unsigned ip; - uint8_t *dec; - - size = 4*1024; /* msg */ - size += 4*1024; /* fb */ - size += 4096; /*it_scaling_table*/ - size += ALIGN(sizeof(uvd_bitstream), 4*1024); - size += ALIGN(dpb_size, 4*1024); - size += ALIGN(dt_size, 4*1024); - - num_resources = 0; - alloc_resource(&dec_buf, size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = dec_buf.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(dec_buf.handle, (void **)&dec_buf.ptr); - dec = dec_buf.ptr; - - CU_ASSERT_EQUAL(r, 0); - memset(dec_buf.ptr, 0, size); - memcpy(dec_buf.ptr, vcn_dec_decode_msg, sizeof(vcn_dec_decode_msg)); - memcpy(dec_buf.ptr + sizeof(vcn_dec_decode_msg), - avc_decode_msg, sizeof(avc_decode_msg)); - - dec += 4*1024; - memcpy(dec, feedback_msg, sizeof(feedback_msg)); - dec += 4*1024; - memcpy(dec, uvd_it_scaling_table, sizeof(uvd_it_scaling_table)); - - dec += 4*1024; - memcpy(dec, uvd_bitstream, sizeof(uvd_bitstream)); - - dec += ALIGN(sizeof(uvd_bitstream), 4*1024); - - dec += ALIGN(dpb_size, 4*1024); - - msg_addr = dec_buf.addr; - fb_addr = msg_addr + 4*1024; - it_addr = fb_addr + 4*1024; - bs_addr = it_addr + 4*1024; - dpb_addr = ALIGN(bs_addr + sizeof(uvd_bitstream), 4*1024); - ctx_addr = ALIGN(dpb_addr + 0x006B9400, 4*1024); - dt_addr = ALIGN(dpb_addr + dpb_size, 4*1024); - - len = 0; - vcn_dec_cmd(session_ctx_buf.addr, 0x5, &len); - vcn_dec_cmd(msg_addr, 0x0, &len); - vcn_dec_cmd(dpb_addr, 0x1, &len); - vcn_dec_cmd(dt_addr, 0x2, &len); - vcn_dec_cmd(fb_addr, 0x3, &len); - vcn_dec_cmd(bs_addr, 0x100, &len); - vcn_dec_cmd(it_addr, 0x204, &len); - vcn_dec_cmd(ctx_addr, 0x206, &len); - - if (vcn_dec_sw_ring == false) { - ib_cpu[len++] = reg[vcn_reg_index].cntl; - ib_cpu[len++] = 0x1; - for (; len % 16; ) { - ib_cpu[len++] = reg[vcn_reg_index].nop; - ib_cpu[len++] = 0; - } - } - - if (vcn_unified_ring) { - amdgpu_cs_sq_ib_tail(ib_cpu + len); - ip = AMDGPU_HW_IP_VCN_ENC; - } else - ip = AMDGPU_HW_IP_VCN_DEC; - - r = submit(len, ip); - CU_ASSERT_EQUAL(r, 0); - - for (i = 0, sum = 0; i < dt_size; ++i) - sum += dec[i]; - - CU_ASSERT_EQUAL(sum, SUM_DECODE); - - free_resource(&dec_buf); -} - -static void amdgpu_cs_vcn_dec_destroy(void) -{ - struct amdgpu_vcn_bo msg_buf; - unsigned ip; - int len, r; - - num_resources = 0; - alloc_resource(&msg_buf, 1024, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = msg_buf.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(msg_buf.handle, (void **)&msg_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - - memset(msg_buf.ptr, 0, 1024); - memcpy(msg_buf.ptr, vcn_dec_destroy_msg, sizeof(vcn_dec_destroy_msg)); - - len = 0; - vcn_dec_cmd(session_ctx_buf.addr, 5, &len); - if (vcn_dec_sw_ring == true) { - vcn_dec_cmd(msg_buf.addr, 0, &len); - } else { - ib_cpu[len++] = reg[vcn_reg_index].data0; - ib_cpu[len++] = msg_buf.addr; - ib_cpu[len++] = reg[vcn_reg_index].data1; - ib_cpu[len++] = msg_buf.addr >> 32; - ib_cpu[len++] = reg[vcn_reg_index].cmd; - ib_cpu[len++] = 0; - for (; len % 16; ) { - ib_cpu[len++] = reg[vcn_reg_index].nop; - ib_cpu[len++] = 0; - } - } - - if (vcn_unified_ring) { - amdgpu_cs_sq_ib_tail(ib_cpu + len); - ip = AMDGPU_HW_IP_VCN_ENC; - } else - ip = AMDGPU_HW_IP_VCN_DEC; - - r = submit(len, ip); - CU_ASSERT_EQUAL(r, 0); - - free_resource(&msg_buf); - free_resource(&session_ctx_buf); -} - -static void amdgpu_cs_vcn_enc_create(void) -{ - int len, r; - uint32_t *p_task_size = NULL; - uint32_t task_offset = 0, st_offset; - uint32_t *st_size = NULL; - unsigned width = 160, height = 128, buf_size; - uint32_t fw_maj = 1, fw_min = 9; - - if (vcn_ip_version_major == 2) { - fw_maj = 1; - fw_min = 1; - } else if (vcn_ip_version_major == 3) { - fw_maj = 1; - fw_min = 0; - } - - gWidth = width; - gHeight = height; - buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2; - enc_task_id = 1; - - num_resources = 0; - alloc_resource(&enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); - alloc_resource(&cpb_buf, buf_size * 2, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc_buf.handle; - resources[num_resources++] = cpb_buf.handle; - resources[num_resources++] = ib_handle; - - r = amdgpu_bo_cpu_map(enc_buf.handle, (void**)&enc_buf.ptr); - memset(enc_buf.ptr, 0, 128 * 1024); - r = amdgpu_bo_cpu_unmap(enc_buf.handle); - - r = amdgpu_bo_cpu_map(cpb_buf.handle, (void**)&enc_buf.ptr); - memset(enc_buf.ptr, 0, buf_size * 2); - r = amdgpu_bo_cpu_unmap(cpb_buf.handle); - - len = 0; - - if (vcn_unified_ring) - amdgpu_cs_sq_head(ib_cpu, &len, true); - - /* session info */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */ - ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0)); - ib_cpu[len++] = enc_buf.addr >> 32; - ib_cpu[len++] = enc_buf.addr; - ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */ - *st_size = (len - st_offset) * 4; - - /* task info */ - task_offset = len; - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */ - p_task_size = &ib_cpu[len++]; - ib_cpu[len++] = enc_task_id++; /* task_id */ - ib_cpu[len++] = 0; /* feedback */ - *st_size = (len - st_offset) * 4; - - /* op init */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x01000001; /* RENCODE_IB_OP_INITIALIZE */ - *st_size = (len - st_offset) * 4; - - /* session_init */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000003; /* RENCODE_IB_PARAM_SESSION_INIT */ - ib_cpu[len++] = 1; /* RENCODE_ENCODE_STANDARD_H264 */ - ib_cpu[len++] = width; - ib_cpu[len++] = height; - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; /* pre encode mode */ - ib_cpu[len++] = 0; /* chroma enabled : false */ - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; - *st_size = (len - st_offset) * 4; - - /* slice control */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00200001; /* RENCODE_H264_IB_PARAM_SLICE_CONTROL */ - ib_cpu[len++] = 0; /* RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS */ - ib_cpu[len++] = ALIGN(width, 16) / 16 * ALIGN(height, 16) / 16; - *st_size = (len - st_offset) * 4; - - /* enc spec misc */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00200002; /* RENCODE_H264_IB_PARAM_SPEC_MISC */ - ib_cpu[len++] = 0; /* constrained intra pred flag */ - ib_cpu[len++] = 0; /* cabac enable */ - ib_cpu[len++] = 0; /* cabac init idc */ - ib_cpu[len++] = 1; /* half pel enabled */ - ib_cpu[len++] = 1; /* quarter pel enabled */ - ib_cpu[len++] = 100; /* BASELINE profile */ - ib_cpu[len++] = 11; /* level */ - if (vcn_ip_version_major >= 3) { - ib_cpu[len++] = 0; /* b_picture_enabled */ - ib_cpu[len++] = 0; /* weighted_bipred_idc */ - } - *st_size = (len - st_offset) * 4; - - /* deblocking filter */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00200004; /* RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER */ - ib_cpu[len++] = 0; /* disable deblocking filter idc */ - ib_cpu[len++] = 0; /* alpha c0 offset */ - ib_cpu[len++] = 0; /* tc offset */ - ib_cpu[len++] = 0; /* cb offset */ - ib_cpu[len++] = 0; /* cr offset */ - *st_size = (len - st_offset) * 4; - - /* layer control */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000004; /* RENCODE_IB_PARAM_LAYER_CONTROL */ - ib_cpu[len++] = 1; /* max temporal layer */ - ib_cpu[len++] = 1; /* no of temporal layer */ - *st_size = (len - st_offset) * 4; - - /* rc_session init */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000006; /* RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT */ - ib_cpu[len++] = 0; /* rate control */ - ib_cpu[len++] = 48; /* vbv buffer level */ - *st_size = (len - st_offset) * 4; - - /* quality params */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000009; /* RENCODE_IB_PARAM_QUALITY_PARAMS */ - ib_cpu[len++] = 0; /* vbaq mode */ - ib_cpu[len++] = 0; /* scene change sensitivity */ - ib_cpu[len++] = 0; /* scene change min idr interval */ - ib_cpu[len++] = 0; - if (vcn_ip_version_major >= 3) - ib_cpu[len++] = 0; - *st_size = (len - st_offset) * 4; - - /* layer select */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000005; /* RENCODE_IB_PARAM_LAYER_SELECT */ - ib_cpu[len++] = 0; /* temporal layer */ - *st_size = (len - st_offset) * 4; - - /* rc layer init */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000007; /* RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT */ - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; - ib_cpu[len++] = 25; - ib_cpu[len++] = 1; - ib_cpu[len++] = 0x01312d00; - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; - ib_cpu[len++] = 0; - *st_size = (len - st_offset) * 4; - - /* layer select */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000005; /* RENCODE_IB_PARAM_LAYER_SELECT */ - ib_cpu[len++] = 0; /* temporal layer */ - *st_size = (len - st_offset) * 4; - - /* rc per pic */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000008; /* RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE */ - ib_cpu[len++] = 20; - ib_cpu[len++] = 0; - ib_cpu[len++] = 51; - ib_cpu[len++] = 0; - ib_cpu[len++] = 1; - ib_cpu[len++] = 0; - ib_cpu[len++] = 1; - ib_cpu[len++] = 0; - *st_size = (len - st_offset) * 4; - - /* op init rc */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x01000004; /* RENCODE_IB_OP_INIT_RC */ - *st_size = (len - st_offset) * 4; - - /* op init rc vbv */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x01000005; /* RENCODE_IB_OP_INIT_RC_VBV_BUFFER_LEVEL */ - *st_size = (len - st_offset) * 4; - - *p_task_size = (len - task_offset) * 4; - - if (vcn_unified_ring) - amdgpu_cs_sq_ib_tail(ib_cpu + len); - - r = submit(len, AMDGPU_HW_IP_VCN_ENC); - CU_ASSERT_EQUAL(r, 0); -} - -static int32_t h264_se (bufferInfo * bufInfo) -{ - uint32_t ret; - - ret = bs_read_ue (bufInfo); - if ((ret & 0x1) == 0) { - ret >>= 1; - int32_t temp = 0 - ret; - return temp; - } - - return (ret + 1) >> 1; -} - -static void h264_check_0s (bufferInfo * bufInfo, int count) -{ - uint32_t val; - - val = bs_read_u (bufInfo, count); - if (val != 0) { - printf ("field error - %d bits should be 0 is %x\n", count, val); - } -} - -static inline int bs_eof(bufferInfo * bufinfo) -{ - if (bufinfo->decBuffer >= bufinfo->end) - return 1; - else - return 0; -} - -static inline uint32_t bs_read_u1(bufferInfo *bufinfo) -{ - uint32_t r = 0; - uint32_t temp = 0; - - bufinfo->numOfBitsInBuffer--; - if (! bs_eof(bufinfo)) { - temp = (((bufinfo->decData)) >> bufinfo->numOfBitsInBuffer); - r = temp & 0x01; - } - - if (bufinfo->numOfBitsInBuffer == 0) { - bufinfo->decBuffer++; - bufinfo->decData = *bufinfo->decBuffer; - bufinfo->numOfBitsInBuffer = 8; - } - - return r; -} - -static inline uint32_t bs_read_u(bufferInfo* bufinfo, int n) -{ - uint32_t r = 0; - int i; - - for (i = 0; i < n; i++) { - r |= ( bs_read_u1(bufinfo) << ( n - i - 1 ) ); - } - - return r; -} - -static inline uint32_t bs_read_ue(bufferInfo* bufinfo) -{ - int32_t r = 0; - int i = 0; - - while( (bs_read_u1(bufinfo) == 0) && (i < 32) && (!bs_eof(bufinfo))) { - i++; - } - r = bs_read_u(bufinfo, i); - r += (1 << i) - 1; - return r; -} - -static uint32_t remove_03 (uint8_t * bptr, uint32_t len) -{ - uint32_t nal_len = 0; - while (nal_len + 2 < len) { - if (bptr[0] == 0 && bptr[1] == 0 && bptr[2] == 3) { - bptr += 2; - nal_len += 2; - len--; - memmove (bptr, bptr + 1, len - nal_len); - } else { - bptr++; - nal_len++; - } - } - return len; -} - -static void scaling_list (uint32_t ix, uint32_t sizeOfScalingList, bufferInfo * bufInfo) -{ - uint32_t lastScale = 8, nextScale = 8; - uint32_t jx; - int deltaScale; - - for (jx = 0; jx < sizeOfScalingList; jx++) { - if (nextScale != 0) { - deltaScale = h264_se (bufInfo); - nextScale = (lastScale + deltaScale + 256) % 256; - } - if (nextScale == 0) { - lastScale = lastScale; - } else { - lastScale = nextScale; - } - } -} - -static void h264_parse_sequence_parameter_set (h264_decode * dec, bufferInfo * bufInfo) -{ - uint32_t temp; - - dec->profile = bs_read_u (bufInfo, 8); - bs_read_u (bufInfo, 1); /* constaint_set0_flag */ - bs_read_u (bufInfo, 1); /* constaint_set1_flag */ - bs_read_u (bufInfo, 1); /* constaint_set2_flag */ - bs_read_u (bufInfo, 1); /* constaint_set3_flag */ - bs_read_u (bufInfo, 1); /* constaint_set4_flag */ - bs_read_u (bufInfo, 1); /* constaint_set5_flag */ - - - h264_check_0s (bufInfo, 2); - dec->level_idc = bs_read_u (bufInfo, 8); - bs_read_ue (bufInfo); /* SPS id*/ - - if (dec->profile == 100 || dec->profile == 110 || - dec->profile == 122 || dec->profile == 144) { - uint32_t chroma_format_idc = bs_read_ue (bufInfo); - if (chroma_format_idc == 3) { - bs_read_u (bufInfo, 1); /* residual_colour_transform_flag */ - } - bs_read_ue (bufInfo); /* bit_depth_luma_minus8 */ - bs_read_ue (bufInfo); /* bit_depth_chroma_minus8 */ - bs_read_u (bufInfo, 1); /* qpprime_y_zero_transform_bypass_flag */ - uint32_t seq_scaling_matrix_present_flag = bs_read_u (bufInfo, 1); - - if (seq_scaling_matrix_present_flag) { - for (uint32_t ix = 0; ix < 8; ix++) { - temp = bs_read_u (bufInfo, 1); - if (temp) { - scaling_list (ix, ix < 6 ? 16 : 64, bufInfo); - } - } - } - } - - bs_read_ue (bufInfo); /* log2_max_frame_num_minus4 */ - uint32_t pic_order_cnt_type = bs_read_ue (bufInfo); - - if (pic_order_cnt_type == 0) { - bs_read_ue (bufInfo); /* log2_max_pic_order_cnt_lsb_minus4 */ - } else if (pic_order_cnt_type == 1) { - bs_read_u (bufInfo, 1); /* delta_pic_order_always_zero_flag */ - h264_se (bufInfo); /* offset_for_non_ref_pic */ - h264_se (bufInfo); /* offset_for_top_to_bottom_field */ - temp = bs_read_ue (bufInfo); - for (uint32_t ix = 0; ix < temp; ix++) { - h264_se (bufInfo); /* offset_for_ref_frame[index] */ - } - } - bs_read_ue (bufInfo); /* num_ref_frames */ - bs_read_u (bufInfo, 1); /* gaps_in_frame_num_flag */ - uint32_t PicWidthInMbs = bs_read_ue (bufInfo) + 1; - - dec->pic_width = PicWidthInMbs * 16; - uint32_t PicHeightInMapUnits = bs_read_ue (bufInfo) + 1; - - dec->pic_height = PicHeightInMapUnits * 16; - uint32_t frame_mbs_only_flag = bs_read_u (bufInfo, 1); - if (!frame_mbs_only_flag) { - bs_read_u (bufInfo, 1); /* mb_adaptive_frame_field_flag */ - } - bs_read_u (bufInfo, 1); /* direct_8x8_inference_flag */ - temp = bs_read_u (bufInfo, 1); - if (temp) { - bs_read_ue (bufInfo); /* frame_crop_left_offset */ - bs_read_ue (bufInfo); /* frame_crop_right_offset */ - bs_read_ue (bufInfo); /* frame_crop_top_offset */ - bs_read_ue (bufInfo); /* frame_crop_bottom_offset */ - } - temp = bs_read_u (bufInfo, 1); /* VUI Parameters */ -} - -static void h264_slice_header (h264_decode * dec, bufferInfo * bufInfo) -{ - uint32_t temp; - - bs_read_ue (bufInfo); /* first_mb_in_slice */ - temp = bs_read_ue (bufInfo); - dec->slice_type = ((temp > 5) ? (temp - 5) : temp); -} - -static uint8_t h264_parse_nal (h264_decode * dec, bufferInfo * bufInfo) -{ - uint8_t type = 0; - - h264_check_0s (bufInfo, 1); - dec->nal_ref_idc = bs_read_u (bufInfo, 2); - dec->nal_unit_type = type = bs_read_u (bufInfo, 5); - switch (type) - { - case H264_NAL_TYPE_NON_IDR_SLICE: - case H264_NAL_TYPE_IDR_SLICE: - h264_slice_header (dec, bufInfo); - break; - case H264_NAL_TYPE_SEQ_PARAM: - h264_parse_sequence_parameter_set (dec, bufInfo); - break; - case H264_NAL_TYPE_PIC_PARAM: - case H264_NAL_TYPE_SEI: - case H264_NAL_TYPE_ACCESS_UNIT: - case H264_NAL_TYPE_SEQ_EXTENSION: - /* NOP */ - break; - default: - printf ("Nal type unknown %d \n ", type); - break; - } - return type; -} - -static uint32_t h264_find_next_start_code (uint8_t * pBuf, uint32_t bufLen) -{ - uint32_t val; - uint32_t offset, startBytes; - - offset = startBytes = 0; - if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 0 && pBuf[3] == 1) { - pBuf += 4; - offset = 4; - startBytes = 1; - } else if (pBuf[0] == 0 && pBuf[1] == 0 && pBuf[2] == 1) { - pBuf += 3; - offset = 3; - startBytes = 1; - } - val = 0xffffffff; - while (offset < bufLen - 3) { - val <<= 8; - val |= *pBuf++; - offset++; - if (val == H264_START_CODE) - return offset - 4; - - if ((val & 0x00ffffff) == H264_START_CODE) - return offset - 3; - } - if (bufLen - offset <= 3 && startBytes == 0) { - startBytes = 0; - return 0; - } - - return offset; -} - -static int verify_checksum(uint8_t *buffer, uint32_t buffer_size) -{ - uint32_t buffer_pos = 0; - int done = 0; - h264_decode dec; - - memset(&dec, 0, sizeof(h264_decode)); - do { - uint32_t ret; - - ret = h264_find_next_start_code (buffer + buffer_pos, - buffer_size - buffer_pos); - if (ret == 0) { - done = 1; - if (buffer_pos == 0) { - fprintf (stderr, - "couldn't find start code in buffer from 0\n"); - } - } else { - /* have a complete NAL from buffer_pos to end */ - if (ret > 3) { - uint32_t nal_len; - bufferInfo bufinfo; - - nal_len = remove_03 (buffer + buffer_pos, ret); - bufinfo.decBuffer = buffer + buffer_pos + (buffer[buffer_pos + 2] == 1 ? 3 : 4); - bufinfo.decBufferSize = (nal_len - (buffer[buffer_pos + 2] == 1 ? 3 : 4)) * 8; - bufinfo.end = buffer + buffer_pos + nal_len; - bufinfo.numOfBitsInBuffer = 8; - bufinfo.decData = *bufinfo.decBuffer; - h264_parse_nal (&dec, &bufinfo); - } - buffer_pos += ret; /* buffer_pos points to next code */ - } - } while (done == 0); - - if ((dec.pic_width == gWidth) && - (dec.pic_height == gHeight) && - (dec.slice_type == gSliceType)) - return 0; - else - return -1; -} - -static void check_result(struct amdgpu_vcn_bo fb_buf, struct amdgpu_vcn_bo bs_buf, int frame_type) -{ - uint32_t *fb_ptr; - uint8_t *bs_ptr; - uint32_t size; - int r; -/* uint64_t s[3] = {0, 1121279001727, 1059312481445}; */ - - r = amdgpu_bo_cpu_map(fb_buf.handle, (void **)&fb_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - fb_ptr = (uint32_t*)fb_buf.ptr; - size = fb_ptr[6]; - r = amdgpu_bo_cpu_unmap(fb_buf.handle); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_map(bs_buf.handle, (void **)&bs_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - - bs_ptr = (uint8_t*)bs_buf.ptr; - r = verify_checksum(bs_ptr, size); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_cpu_unmap(bs_buf.handle); - - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_cs_vcn_ib_zero_count(int *len, int num) -{ - for (int i = 0; i < num; i++) - ib_cpu[(*len)++] = 0; -} - -static void amdgpu_cs_vcn_enc_encode_frame(int frame_type) -{ - struct amdgpu_vcn_bo bs_buf, fb_buf, input_buf; - int len, r; - unsigned width = 160, height = 128, buf_size; - uint32_t *p_task_size = NULL; - uint32_t task_offset = 0, st_offset; - uint32_t *st_size = NULL; - uint32_t fw_maj = 1, fw_min = 9; - - if (vcn_ip_version_major == 2) { - fw_maj = 1; - fw_min = 1; - } else if (vcn_ip_version_major == 3) { - fw_maj = 1; - fw_min = 0; - } - gSliceType = frame_type; - buf_size = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2; - - num_resources = 0; - alloc_resource(&bs_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); - alloc_resource(&fb_buf, 4096, AMDGPU_GEM_DOMAIN_GTT); - alloc_resource(&input_buf, buf_size, AMDGPU_GEM_DOMAIN_GTT); - resources[num_resources++] = enc_buf.handle; - resources[num_resources++] = cpb_buf.handle; - resources[num_resources++] = bs_buf.handle; - resources[num_resources++] = fb_buf.handle; - resources[num_resources++] = input_buf.handle; - resources[num_resources++] = ib_handle; - - - r = amdgpu_bo_cpu_map(bs_buf.handle, (void**)&bs_buf.ptr); - memset(bs_buf.ptr, 0, 4096); - r = amdgpu_bo_cpu_unmap(bs_buf.handle); - - r = amdgpu_bo_cpu_map(fb_buf.handle, (void**)&fb_buf.ptr); - memset(fb_buf.ptr, 0, 4096); - r = amdgpu_bo_cpu_unmap(fb_buf.handle); - - r = amdgpu_bo_cpu_map(input_buf.handle, (void **)&input_buf.ptr); - CU_ASSERT_EQUAL(r, 0); - - for (int i = 0; i < ALIGN(height, 32) * 3 / 2; i++) - memcpy(input_buf.ptr + i * ALIGN(width, 256), frame + i * width, width); - - r = amdgpu_bo_cpu_unmap(input_buf.handle); - CU_ASSERT_EQUAL(r, 0); - - len = 0; - - if (vcn_unified_ring) - amdgpu_cs_sq_head(ib_cpu, &len, true); - - /* session info */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */ - ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0)); - ib_cpu[len++] = enc_buf.addr >> 32; - ib_cpu[len++] = enc_buf.addr; - ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE */; - *st_size = (len - st_offset) * 4; - - /* task info */ - task_offset = len; - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */ - p_task_size = &ib_cpu[len++]; - ib_cpu[len++] = enc_task_id++; /* task_id */ - ib_cpu[len++] = 1; /* feedback */ - *st_size = (len - st_offset) * 4; - - if (frame_type == 2) { - /* sps */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1 */ - else - ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn */ - ib_cpu[len++] = 0x00000002; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS */ - ib_cpu[len++] = 0x00000011; /* sps len */ - ib_cpu[len++] = 0x00000001; /* start code */ - ib_cpu[len++] = 0x6764440b; - ib_cpu[len++] = 0xac54c284; - ib_cpu[len++] = 0x68078442; - ib_cpu[len++] = 0x37000000; - *st_size = (len - st_offset) * 4; - - /* pps */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x00000020; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU vcn 1*/ - else - ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU other vcn*/ - ib_cpu[len++] = 0x00000003; /* RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS */ - ib_cpu[len++] = 0x00000008; /* pps len */ - ib_cpu[len++] = 0x00000001; /* start code */ - ib_cpu[len++] = 0x68ce3c80; - *st_size = (len - st_offset) * 4; - } - - /* slice header */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x0000000a; /* RENCODE_IB_PARAM_SLICE_HEADER vcn 1 */ - else - ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_SLICE_HEADER other vcn */ - if (frame_type == 2) { - ib_cpu[len++] = 0x65000000; - ib_cpu[len++] = 0x11040000; - } else { - ib_cpu[len++] = 0x41000000; - ib_cpu[len++] = 0x34210000; - } - ib_cpu[len++] = 0xe0000000; - amdgpu_cs_vcn_ib_zero_count(&len, 13); - - ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000008; - ib_cpu[len++] = 0x00020000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000015; - ib_cpu[len++] = 0x00020001; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000001; - ib_cpu[len++] = 0x00000003; - amdgpu_cs_vcn_ib_zero_count(&len, 22); - *st_size = (len - st_offset) * 4; - - /* encode params */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x0000000b; /* RENCODE_IB_PARAM_ENCODE_PARAMS vcn 1 */ - else - ib_cpu[len++] = 0x0000000f; /* RENCODE_IB_PARAM_ENCODE_PARAMS other vcn */ - ib_cpu[len++] = frame_type; - ib_cpu[len++] = 0x0001f000; - ib_cpu[len++] = input_buf.addr >> 32; - ib_cpu[len++] = input_buf.addr; - ib_cpu[len++] = (input_buf.addr + ALIGN(width, 256) * ALIGN(height, 32)) >> 32; - ib_cpu[len++] = input_buf.addr + ALIGN(width, 256) * ALIGN(height, 32); - ib_cpu[len++] = 0x00000100; - ib_cpu[len++] = 0x00000080; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0xffffffff; - ib_cpu[len++] = 0x00000000; - *st_size = (len - st_offset) * 4; - - /* encode params h264 */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00200003; /* RENCODE_H264_IB_PARAM_ENCODE_PARAMS */ - if (vcn_ip_version_major <= 2) { - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0xffffffff; - } else { - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0xffffffff; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0xffffffff; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000001; - } - *st_size = (len - st_offset) * 4; - - /* encode context */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x0000000d; /* ENCODE_CONTEXT_BUFFER vcn 1 */ - else - ib_cpu[len++] = 0x00000011; /* ENCODE_CONTEXT_BUFFER other vcn */ - ib_cpu[len++] = cpb_buf.addr >> 32; - ib_cpu[len++] = cpb_buf.addr; - ib_cpu[len++] = 0x00000000; /* swizzle mode */ - ib_cpu[len++] = 0x00000100; /* luma pitch */ - ib_cpu[len++] = 0x00000100; /* chroma pitch */ - ib_cpu[len++] = 0x00000002; /* no reconstructed picture */ - ib_cpu[len++] = 0x00000000; /* reconstructed pic 1 luma offset */ - ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32); /* pic1 chroma offset */ - if(vcn_ip_version_major == 4) - amdgpu_cs_vcn_ib_zero_count(&len, 2); - ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32) * 3 / 2; /* pic2 luma offset */ - ib_cpu[len++] = ALIGN(width, 256) * ALIGN(height, 32) * 5 / 2; /* pic2 chroma offset */ - - amdgpu_cs_vcn_ib_zero_count(&len, 280); - *st_size = (len - st_offset) * 4; - - /* bitstream buffer */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x0000000e; /* VIDEO_BITSTREAM_BUFFER vcn 1 */ - else - ib_cpu[len++] = 0x00000012; /* VIDEO_BITSTREAM_BUFFER other vcn */ - - ib_cpu[len++] = 0x00000000; /* mode */ - ib_cpu[len++] = bs_buf.addr >> 32; - ib_cpu[len++] = bs_buf.addr; - ib_cpu[len++] = 0x0001f000; - ib_cpu[len++] = 0x00000000; - *st_size = (len - st_offset) * 4; - - /* feedback */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x00000010; /* FEEDBACK_BUFFER vcn 1 */ - else - ib_cpu[len++] = 0x00000015; /* FEEDBACK_BUFFER vcn 2,3 */ - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = fb_buf.addr >> 32; - ib_cpu[len++] = fb_buf.addr; - ib_cpu[len++] = 0x00000010; - ib_cpu[len++] = 0x00000028; - *st_size = (len - st_offset) * 4; - - /* intra refresh */ - st_offset = len; - st_size = &ib_cpu[len++]; - if(vcn_ip_version_major == 1) - ib_cpu[len++] = 0x0000000c; /* INTRA_REFRESH vcn 1 */ - else - ib_cpu[len++] = 0x00000010; /* INTRA_REFRESH vcn 2,3 */ - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - *st_size = (len - st_offset) * 4; - - if(vcn_ip_version_major != 1) { - /* Input Format */ - st_offset = len; - st_size = &ib_cpu[len++]; - ib_cpu[len++] = 0x0000000c; - ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_VOLUME_G22_BT709 */ - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_BIT_DEPTH_8_BIT */ - ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_PACKING_FORMAT_NV12 */ - *st_size = (len - st_offset) * 4; - - /* Output Format */ - st_offset = len; - st_size = &ib_cpu[len++]; - ib_cpu[len++] = 0x0000000d; - ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_VOLUME_G22_BT709 */ - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; - ib_cpu[len++] = 0x00000000; /* RENCODE_COLOR_BIT_DEPTH_8_BIT */ - *st_size = (len - st_offset) * 4; - } - /* op_speed */ - st_offset = len; - st_size = &ib_cpu[len++]; - ib_cpu[len++] = 0x01000006; /* SPEED_ENCODING_MODE */ - *st_size = (len - st_offset) * 4; - - /* op_enc */ - st_offset = len; - st_size = &ib_cpu[len++]; - ib_cpu[len++] = 0x01000003; - *st_size = (len - st_offset) * 4; - - *p_task_size = (len - task_offset) * 4; - - if (vcn_unified_ring) - amdgpu_cs_sq_ib_tail(ib_cpu + len); - - r = submit(len, AMDGPU_HW_IP_VCN_ENC); - CU_ASSERT_EQUAL(r, 0); - - /* check result */ - check_result(fb_buf, bs_buf, frame_type); - - free_resource(&fb_buf); - free_resource(&bs_buf); - free_resource(&input_buf); -} - -static void amdgpu_cs_vcn_enc_encode(void) -{ - amdgpu_cs_vcn_enc_encode_frame(2); /* IDR frame */ -} - -static void amdgpu_cs_vcn_enc_destroy(void) -{ - int len = 0, r; - uint32_t *p_task_size = NULL; - uint32_t task_offset = 0, st_offset; - uint32_t *st_size = NULL; - uint32_t fw_maj = 1, fw_min = 9; - - if (vcn_ip_version_major == 2) { - fw_maj = 1; - fw_min = 1; - } else if (vcn_ip_version_major == 3) { - fw_maj = 1; - fw_min = 0; - } - - num_resources = 0; -/* alloc_resource(&enc_buf, 128 * 1024, AMDGPU_GEM_DOMAIN_GTT); */ - resources[num_resources++] = enc_buf.handle; - resources[num_resources++] = ib_handle; - - if (vcn_unified_ring) - amdgpu_cs_sq_head(ib_cpu, &len, true); - - /* session info */ - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000001; /* RENCODE_IB_PARAM_SESSION_INFO */ - ib_cpu[len++] = ((fw_maj << 16) | (fw_min << 0)); - ib_cpu[len++] = enc_buf.addr >> 32; - ib_cpu[len++] = enc_buf.addr; - ib_cpu[len++] = 1; /* RENCODE_ENGINE_TYPE_ENCODE; */ - *st_size = (len - st_offset) * 4; - - /* task info */ - task_offset = len; - st_offset = len; - st_size = &ib_cpu[len++]; /* size */ - ib_cpu[len++] = 0x00000002; /* RENCODE_IB_PARAM_TASK_INFO */ - p_task_size = &ib_cpu[len++]; - ib_cpu[len++] = enc_task_id++; /* task_id */ - ib_cpu[len++] = 0; /* feedback */ - *st_size = (len - st_offset) * 4; - - /* op close */ - st_offset = len; - st_size = &ib_cpu[len++]; - ib_cpu[len++] = 0x01000002; /* RENCODE_IB_OP_CLOSE_SESSION */ - *st_size = (len - st_offset) * 4; - - *p_task_size = (len - task_offset) * 4; - - if (vcn_unified_ring) - amdgpu_cs_sq_ib_tail(ib_cpu + len); - - r = submit(len, AMDGPU_HW_IP_VCN_ENC); - CU_ASSERT_EQUAL(r, 0); - - free_resource(&cpb_buf); - free_resource(&enc_buf); -} diff --git a/tests/amdgpu/vm_tests.c b/tests/amdgpu/vm_tests.c deleted file mode 100644 index b94999c54..000000000 --- a/tests/amdgpu/vm_tests.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * -*/ - -#include "CUnit/Basic.h" - -#include "amdgpu_test.h" -#include "amdgpu_drm.h" -#include "amdgpu_internal.h" - -static amdgpu_device_handle device_handle; -static uint32_t major_version; -static uint32_t minor_version; -static uint32_t family_id; -static uint32_t chip_id; -static uint32_t chip_rev; - -static void amdgpu_vmid_reserve_test(void); -static void amdgpu_vm_unaligned_map(void); -static void amdgpu_vm_mapping_test(void); - -CU_BOOL suite_vm_tests_enable(void) -{ - CU_BOOL enable = CU_TRUE; - - if (amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle)) - return CU_FALSE; - - if (device_handle->info.family_id == AMDGPU_FAMILY_SI) { - printf("\n\nCurrently hangs the CP on this ASIC, VM suite disabled\n"); - enable = CU_FALSE; - } - - if (amdgpu_device_deinitialize(device_handle)) - return CU_FALSE; - - return enable; -} - -int suite_vm_tests_init(void) -{ - int r; - - r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, - &minor_version, &device_handle); - - if (r) { - if ((r == -EACCES) && (errno == EACCES)) - printf("\n\nError:%s. " - "Hint:Try to run this test program as root.", - strerror(errno)); - return CUE_SINIT_FAILED; - } - - return CUE_SUCCESS; -} - -int suite_vm_tests_clean(void) -{ - int r = amdgpu_device_deinitialize(device_handle); - - if (r == 0) - return CUE_SUCCESS; - else - return CUE_SCLEAN_FAILED; -} - - -CU_TestInfo vm_tests[] = { - { "resere vmid test", amdgpu_vmid_reserve_test }, - { "unaligned map", amdgpu_vm_unaligned_map }, - { "vm mapping test", amdgpu_vm_mapping_test }, - CU_TEST_INFO_NULL, -}; - -static void amdgpu_vmid_reserve_test(void) -{ - amdgpu_context_handle context_handle; - amdgpu_bo_handle ib_result_handle; - void *ib_result_cpu; - uint64_t ib_result_mc_address; - struct amdgpu_cs_request ibs_request; - struct amdgpu_cs_ib_info ib_info; - struct amdgpu_cs_fence fence_status; - uint32_t expired, flags; - int i, r; - amdgpu_bo_list_handle bo_list; - amdgpu_va_handle va_handle; - static uint32_t *ptr; - struct amdgpu_gpu_info gpu_info = {0}; - unsigned gc_ip_type; - - r = amdgpu_query_gpu_info(device_handle, &gpu_info); - CU_ASSERT_EQUAL(r, 0); - - family_id = device_handle->info.family_id; - chip_id = device_handle->info.chip_external_rev; - chip_rev = device_handle->info.chip_rev; - - gc_ip_type = (asic_is_gfx_pipe_removed(family_id, chip_id, chip_rev)) ? - AMDGPU_HW_IP_COMPUTE : AMDGPU_HW_IP_GFX; - - r = amdgpu_cs_ctx_create(device_handle, &context_handle); - CU_ASSERT_EQUAL(r, 0); - - flags = 0; - r = amdgpu_vm_reserve_vmid(device_handle, flags); - CU_ASSERT_EQUAL(r, 0); - - - r = amdgpu_bo_alloc_and_map(device_handle, 4096, 4096, - AMDGPU_GEM_DOMAIN_GTT, 0, - &ib_result_handle, &ib_result_cpu, - &ib_result_mc_address, &va_handle); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_get_bo_list(device_handle, ib_result_handle, NULL, - &bo_list); - CU_ASSERT_EQUAL(r, 0); - - ptr = ib_result_cpu; - - for (i = 0; i < 16; ++i) - ptr[i] = 0xffff1000; - - memset(&ib_info, 0, sizeof(struct amdgpu_cs_ib_info)); - ib_info.ib_mc_address = ib_result_mc_address; - ib_info.size = 16; - - memset(&ibs_request, 0, sizeof(struct amdgpu_cs_request)); - ibs_request.ip_type = gc_ip_type; - ibs_request.ring = 0; - ibs_request.number_of_ibs = 1; - ibs_request.ibs = &ib_info; - ibs_request.resources = bo_list; - ibs_request.fence_info.handle = NULL; - - r = amdgpu_cs_submit(context_handle, 0,&ibs_request, 1); - CU_ASSERT_EQUAL(r, 0); - - - memset(&fence_status, 0, sizeof(struct amdgpu_cs_fence)); - fence_status.context = context_handle; - fence_status.ip_type = gc_ip_type; - fence_status.ip_instance = 0; - fence_status.ring = 0; - fence_status.fence = ibs_request.seq_no; - - r = amdgpu_cs_query_fence_status(&fence_status, - AMDGPU_TIMEOUT_INFINITE,0, &expired); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_list_destroy(bo_list); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_bo_unmap_and_free(ib_result_handle, va_handle, - ib_result_mc_address, 4096); - CU_ASSERT_EQUAL(r, 0); - - flags = 0; - r = amdgpu_vm_unreserve_vmid(device_handle, flags); - CU_ASSERT_EQUAL(r, 0); - - - r = amdgpu_cs_ctx_free(context_handle); - CU_ASSERT_EQUAL(r, 0); -} - -static void amdgpu_vm_unaligned_map(void) -{ - const uint64_t map_size = (4ULL << 30) - (2 << 12); - struct amdgpu_bo_alloc_request request = {}; - amdgpu_bo_handle buf_handle; - amdgpu_va_handle handle; - uint64_t vmc_addr; - int r; - - request.alloc_size = 4ULL << 30; - request.phys_alignment = 4096; - request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM; - request.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; - - r = amdgpu_bo_alloc(device_handle, &request, &buf_handle); - /* Don't let the test fail if the device doesn't have enough VRAM */ - if (r) - return; - - r = amdgpu_va_range_alloc(device_handle, amdgpu_gpu_va_range_general, - 4ULL << 30, 1ULL << 30, 0, &vmc_addr, - &handle, 0); - CU_ASSERT_EQUAL(r, 0); - if (r) - goto error_va_alloc; - - vmc_addr += 1 << 12; - - r = amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, - AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - if (r) - goto error_va_alloc; - - amdgpu_bo_va_op(buf_handle, 0, map_size, vmc_addr, 0, - AMDGPU_VA_OP_UNMAP); - -error_va_alloc: - amdgpu_bo_free(buf_handle); -} - -static void amdgpu_vm_mapping_test(void) -{ - struct amdgpu_bo_alloc_request req = {0}; - struct drm_amdgpu_info_device dev_info; - const uint64_t size = 4096; - amdgpu_bo_handle buf; - uint64_t addr; - int r; - - req.alloc_size = size; - req.phys_alignment = 0; - req.preferred_heap = AMDGPU_GEM_DOMAIN_GTT; - req.flags = 0; - - r = amdgpu_bo_alloc(device_handle, &req, &buf); - CU_ASSERT_EQUAL(r, 0); - - r = amdgpu_query_info(device_handle, AMDGPU_INFO_DEV_INFO, - sizeof(dev_info), &dev_info); - CU_ASSERT_EQUAL(r, 0); - - addr = dev_info.virtual_address_offset; - r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - addr = dev_info.virtual_address_max - size; - r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - if (dev_info.high_va_offset) { - addr = dev_info.high_va_offset; - r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - - addr = dev_info.high_va_max - size; - r = amdgpu_bo_va_op(buf, 0, size, addr, 0, AMDGPU_VA_OP_MAP); - CU_ASSERT_EQUAL(r, 0); - } - - amdgpu_bo_free(buf); -} diff --git a/tests/drmdevice.c b/tests/drmdevice.c index b4b62d9c5..53ee85d43 100644 --- a/tests/drmdevice.c +++ b/tests/drmdevice.c @@ -98,6 +98,12 @@ print_device_info(drmDevicePtr device, int i, bool print_revision) printf(" %s\n", *compatible); compatible++; } + } else if (device->bustype == DRM_BUS_FAUX) { + printf("| +-> faux\n"); + + printf("+-> businfo\n"); + printf(" +-> faux\n"); + printf(" +-> name %s\n", device->businfo.faux->name); } else { printf("Unknown/unhandled bustype\n"); } diff --git a/tests/etnaviv/cmdstream.xml.h b/tests/etnaviv/cmdstream.xml.h deleted file mode 100644 index 109285c51..000000000 --- a/tests/etnaviv/cmdstream.xml.h +++ /dev/null @@ -1,242 +0,0 @@ -#ifndef CMDSTREAM_XML -#define CMDSTREAM_XML - -/* Autogenerated file, DO NOT EDIT manually! - -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://0x04.net/cgit/index.cgi/rules-ng-ng -git clone git://0x04.net/rules-ng-ng - -The rules-ng-ng source files this header was generated from are: -- cmdstream.xml ( 12621 bytes, from 2016-09-06 14:44:16) -- copyright.xml ( 1597 bytes, from 2016-09-06 14:44:16) -- common.xml ( 20583 bytes, from 2016-09-06 14:14:12) - -Copyright (C) 2012-2016 by the following authors: -- Wladimir J. van der Laan -- Christian Gmeiner -- Lucas Stach -- Russell King - -Permission is hereby granted, free of charge, to any person obtaining a -copy of this software and associated documentation files (the "Software"), -to deal in the Software without restriction, including without limitation -the rights to use, copy, modify, merge, publish, distribute, sub license, -and/or sell copies of the Software, and to permit persons to whom the -Software is furnished to do so, subject to the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial portions -of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL -THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -DEALINGS IN THE SOFTWARE. -*/ - - -#define FE_OPCODE_LOAD_STATE 0x00000001 -#define FE_OPCODE_END 0x00000002 -#define FE_OPCODE_NOP 0x00000003 -#define FE_OPCODE_DRAW_2D 0x00000004 -#define FE_OPCODE_DRAW_PRIMITIVES 0x00000005 -#define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006 -#define FE_OPCODE_WAIT 0x00000007 -#define FE_OPCODE_LINK 0x00000008 -#define FE_OPCODE_STALL 0x00000009 -#define FE_OPCODE_CALL 0x0000000a -#define FE_OPCODE_RETURN 0x0000000b -#define FE_OPCODE_CHIP_SELECT 0x0000000d -#define PRIMITIVE_TYPE_POINTS 0x00000001 -#define PRIMITIVE_TYPE_LINES 0x00000002 -#define PRIMITIVE_TYPE_LINE_STRIP 0x00000003 -#define PRIMITIVE_TYPE_TRIANGLES 0x00000004 -#define PRIMITIVE_TYPE_TRIANGLE_STRIP 0x00000005 -#define PRIMITIVE_TYPE_TRIANGLE_FAN 0x00000006 -#define PRIMITIVE_TYPE_LINE_LOOP 0x00000007 -#define PRIMITIVE_TYPE_QUADS 0x00000008 -#define VIV_FE_LOAD_STATE 0x00000000 - -#define VIV_FE_LOAD_STATE_HEADER 0x00000000 -#define VIV_FE_LOAD_STATE_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_LOAD_STATE_HEADER_OP__SHIFT 27 -#define VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE 0x08000000 -#define VIV_FE_LOAD_STATE_HEADER_FIXP 0x04000000 -#define VIV_FE_LOAD_STATE_HEADER_COUNT__MASK 0x03ff0000 -#define VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT 16 -#define VIV_FE_LOAD_STATE_HEADER_COUNT(x) (((x) << VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT) & VIV_FE_LOAD_STATE_HEADER_COUNT__MASK) -#define VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK 0x0000ffff -#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT 0 -#define VIV_FE_LOAD_STATE_HEADER_OFFSET(x) (((x) << VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT) & VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK) -#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR 2 - -#define VIV_FE_END 0x00000000 - -#define VIV_FE_END_HEADER 0x00000000 -#define VIV_FE_END_HEADER_EVENT_ID__MASK 0x0000001f -#define VIV_FE_END_HEADER_EVENT_ID__SHIFT 0 -#define VIV_FE_END_HEADER_EVENT_ID(x) (((x) << VIV_FE_END_HEADER_EVENT_ID__SHIFT) & VIV_FE_END_HEADER_EVENT_ID__MASK) -#define VIV_FE_END_HEADER_EVENT_ENABLE 0x00000100 -#define VIV_FE_END_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_END_HEADER_OP__SHIFT 27 -#define VIV_FE_END_HEADER_OP_END 0x10000000 - -#define VIV_FE_NOP 0x00000000 - -#define VIV_FE_NOP_HEADER 0x00000000 -#define VIV_FE_NOP_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_NOP_HEADER_OP__SHIFT 27 -#define VIV_FE_NOP_HEADER_OP_NOP 0x18000000 - -#define VIV_FE_DRAW_2D 0x00000000 - -#define VIV_FE_DRAW_2D_HEADER 0x00000000 -#define VIV_FE_DRAW_2D_HEADER_COUNT__MASK 0x0000ff00 -#define VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT 8 -#define VIV_FE_DRAW_2D_HEADER_COUNT(x) (((x) << VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_COUNT__MASK) -#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK 0x07ff0000 -#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT 16 -#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT(x) (((x) << VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK) -#define VIV_FE_DRAW_2D_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_DRAW_2D_HEADER_OP__SHIFT 27 -#define VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D 0x20000000 - -#define VIV_FE_DRAW_2D_TOP_LEFT 0x00000008 -#define VIV_FE_DRAW_2D_TOP_LEFT_X__MASK 0x0000ffff -#define VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT 0 -#define VIV_FE_DRAW_2D_TOP_LEFT_X(x) (((x) << VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_X__MASK) -#define VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK 0xffff0000 -#define VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT 16 -#define VIV_FE_DRAW_2D_TOP_LEFT_Y(x) (((x) << VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK) - -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT 0x0000000c -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK 0x0000ffff -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT 0 -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x) (((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK) -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK 0xffff0000 -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT 16 -#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(x) (((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK) - -#define VIV_FE_DRAW_PRIMITIVES 0x00000000 - -#define VIV_FE_DRAW_PRIMITIVES_HEADER 0x00000000 -#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__SHIFT 27 -#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP_DRAW_PRIMITIVES 0x28000000 - -#define VIV_FE_DRAW_PRIMITIVES_COMMAND 0x00000004 -#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK 0x000000ff -#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT 0 -#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE(x) (((x) << VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK) - -#define VIV_FE_DRAW_PRIMITIVES_START 0x00000008 - -#define VIV_FE_DRAW_PRIMITIVES_COUNT 0x0000000c - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES 0x00000000 - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER 0x00000000 -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__SHIFT 27 -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP_DRAW_INDEXED_PRIMITIVES 0x30000000 - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND 0x00000004 -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK 0x000000ff -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT 0 -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE(x) (((x) << VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK) - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_START 0x00000008 - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COUNT 0x0000000c - -#define VIV_FE_DRAW_INDEXED_PRIMITIVES_OFFSET 0x00000010 - -#define VIV_FE_WAIT 0x00000000 - -#define VIV_FE_WAIT_HEADER 0x00000000 -#define VIV_FE_WAIT_HEADER_DELAY__MASK 0x0000ffff -#define VIV_FE_WAIT_HEADER_DELAY__SHIFT 0 -#define VIV_FE_WAIT_HEADER_DELAY(x) (((x) << VIV_FE_WAIT_HEADER_DELAY__SHIFT) & VIV_FE_WAIT_HEADER_DELAY__MASK) -#define VIV_FE_WAIT_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_WAIT_HEADER_OP__SHIFT 27 -#define VIV_FE_WAIT_HEADER_OP_WAIT 0x38000000 - -#define VIV_FE_LINK 0x00000000 - -#define VIV_FE_LINK_HEADER 0x00000000 -#define VIV_FE_LINK_HEADER_PREFETCH__MASK 0x0000ffff -#define VIV_FE_LINK_HEADER_PREFETCH__SHIFT 0 -#define VIV_FE_LINK_HEADER_PREFETCH(x) (((x) << VIV_FE_LINK_HEADER_PREFETCH__SHIFT) & VIV_FE_LINK_HEADER_PREFETCH__MASK) -#define VIV_FE_LINK_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_LINK_HEADER_OP__SHIFT 27 -#define VIV_FE_LINK_HEADER_OP_LINK 0x40000000 - -#define VIV_FE_LINK_ADDRESS 0x00000004 - -#define VIV_FE_STALL 0x00000000 - -#define VIV_FE_STALL_HEADER 0x00000000 -#define VIV_FE_STALL_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_STALL_HEADER_OP__SHIFT 27 -#define VIV_FE_STALL_HEADER_OP_STALL 0x48000000 - -#define VIV_FE_STALL_TOKEN 0x00000004 -#define VIV_FE_STALL_TOKEN_FROM__MASK 0x0000001f -#define VIV_FE_STALL_TOKEN_FROM__SHIFT 0 -#define VIV_FE_STALL_TOKEN_FROM(x) (((x) << VIV_FE_STALL_TOKEN_FROM__SHIFT) & VIV_FE_STALL_TOKEN_FROM__MASK) -#define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00 -#define VIV_FE_STALL_TOKEN_TO__SHIFT 8 -#define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK) - -#define VIV_FE_CALL 0x00000000 - -#define VIV_FE_CALL_HEADER 0x00000000 -#define VIV_FE_CALL_HEADER_PREFETCH__MASK 0x0000ffff -#define VIV_FE_CALL_HEADER_PREFETCH__SHIFT 0 -#define VIV_FE_CALL_HEADER_PREFETCH(x) (((x) << VIV_FE_CALL_HEADER_PREFETCH__SHIFT) & VIV_FE_CALL_HEADER_PREFETCH__MASK) -#define VIV_FE_CALL_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_CALL_HEADER_OP__SHIFT 27 -#define VIV_FE_CALL_HEADER_OP_CALL 0x50000000 - -#define VIV_FE_CALL_ADDRESS 0x00000004 - -#define VIV_FE_CALL_RETURN_PREFETCH 0x00000008 - -#define VIV_FE_CALL_RETURN_ADDRESS 0x0000000c - -#define VIV_FE_RETURN 0x00000000 - -#define VIV_FE_RETURN_HEADER 0x00000000 -#define VIV_FE_RETURN_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_RETURN_HEADER_OP__SHIFT 27 -#define VIV_FE_RETURN_HEADER_OP_RETURN 0x58000000 - -#define VIV_FE_CHIP_SELECT 0x00000000 - -#define VIV_FE_CHIP_SELECT_HEADER 0x00000000 -#define VIV_FE_CHIP_SELECT_HEADER_OP__MASK 0xf8000000 -#define VIV_FE_CHIP_SELECT_HEADER_OP__SHIFT 27 -#define VIV_FE_CHIP_SELECT_HEADER_OP_CHIP_SELECT 0x68000000 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP15 0x00008000 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP14 0x00004000 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP13 0x00002000 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP12 0x00001000 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP11 0x00000800 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP10 0x00000400 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP9 0x00000200 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP8 0x00000100 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP7 0x00000080 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP6 0x00000040 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP5 0x00000020 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP4 0x00000010 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP3 0x00000008 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP2 0x00000004 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP1 0x00000002 -#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP0 0x00000001 - - -#endif /* CMDSTREAM_XML */ diff --git a/tests/etnaviv/etnaviv_2d_test.c b/tests/etnaviv/etnaviv_2d_test.c old mode 100644 new mode 100755 index e774ce9c5..9fcdae184 --- a/tests/etnaviv/etnaviv_2d_test.c +++ b/tests/etnaviv/etnaviv_2d_test.c @@ -31,7 +31,7 @@ #include "xf86drm.h" #include "etnaviv_drmif.h" -#include +#include "etnaviv_drm.h" #include "state.xml.h" #include "state_2d.xml.h" diff --git a/tests/etnaviv/etnaviv_bo_cache_test.c b/tests/etnaviv/etnaviv_bo_cache_test.c index 904a54754..7fb062930 100644 --- a/tests/etnaviv/etnaviv_bo_cache_test.c +++ b/tests/etnaviv/etnaviv_bo_cache_test.c @@ -34,7 +34,7 @@ #include "xf86drm.h" #include "etnaviv_drmif.h" -#include +#include "etnaviv_drm.h" static void test_cache(struct etna_device *dev) { diff --git a/tests/exynos/exynos_fimg2d_test.c b/tests/exynos/exynos_fimg2d_test.c index d85e2f6b6..b1baa5032 100644 --- a/tests/exynos/exynos_fimg2d_test.c +++ b/tests/exynos/exynos_fimg2d_test.c @@ -31,7 +31,6 @@ #include #include -#include #include #include diff --git a/tests/modetest/Android.bp b/tests/modetest/Android.bp old mode 100644 new mode 100755 index 02a17fe94..f60c7ac71 --- a/tests/modetest/Android.bp +++ b/tests/modetest/Android.bp @@ -1,15 +1,6 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] -cc_test { +cc_binary { name: "modetest", defaults: [ "libdrm_defaults", @@ -18,4 +9,5 @@ cc_test { shared_libs: ["libdrm"], static_libs: ["libdrm_util"], + vendor_available: true, } diff --git a/tests/modetest/Android.sources.bp b/tests/modetest/Android.sources.bp old mode 100644 new mode 100755 diff --git a/tests/modetest/Makefile.sources b/tests/modetest/Makefile.sources deleted file mode 100644 index 399af0df1..000000000 --- a/tests/modetest/Makefile.sources +++ /dev/null @@ -1,6 +0,0 @@ -MODETEST_FILES := \ - buffers.c \ - buffers.h \ - cursor.c \ - cursor.h \ - modetest.c diff --git a/tests/modetest/buffers.c b/tests/modetest/buffers.c old mode 100644 new mode 100755 index 576e2cc7f..81ca77ff3 --- a/tests/modetest/buffers.c +++ b/tests/modetest/buffers.c @@ -114,11 +114,13 @@ struct bo * bo_create(int fd, unsigned int format, unsigned int width, unsigned int height, unsigned int handles[4], unsigned int pitches[4], - unsigned int offsets[4], enum util_fill_pattern pattern) + unsigned int offsets[4], enum util_fill_pattern pattern, + unsigned long seed) { - unsigned int virtual_height; + unsigned int virtual_height, xsub, ysub; struct bo *bo; unsigned int bpp; + bool is_planar; void *planes[3] = { 0, }; void *virtual; int ret; @@ -145,6 +147,10 @@ bo_create(int fd, unsigned int format, case DRM_FORMAT_NV42: case DRM_FORMAT_YUV420: case DRM_FORMAT_YVU420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YUV444: + case DRM_FORMAT_YVU444: bpp = 8; break; @@ -223,26 +229,42 @@ bo_create(int fd, unsigned int format, case DRM_FORMAT_NV15: case DRM_FORMAT_YUV420: case DRM_FORMAT_YVU420: - virtual_height = height * 3 / 2; + is_planar = true; + xsub = 2; + ysub = 2; break; case DRM_FORMAT_NV16: case DRM_FORMAT_NV61: case DRM_FORMAT_NV20: - virtual_height = height * 2; + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YVU422: + is_planar = true; + xsub = 2; + ysub = 1; break; case DRM_FORMAT_NV24: case DRM_FORMAT_NV42: case DRM_FORMAT_NV30: - virtual_height = height * 3; + case DRM_FORMAT_YUV444: + case DRM_FORMAT_YVU444: + is_planar = true; + xsub = 1; + ysub = 1; break; default: - virtual_height = height; + is_planar = false; + xsub = 1; + ysub = 1; break; } + virtual_height = height; + if (is_planar) + virtual_height += height * 2 / xsub / ysub; + bo = bo_create_dumb(fd, width, virtual_height, bpp); if (!bo) return NULL; @@ -275,25 +297,14 @@ bo_create(int fd, unsigned int format, case DRM_FORMAT_NV16: case DRM_FORMAT_NV61: case DRM_FORMAT_NV15: - case DRM_FORMAT_NV20: - offsets[0] = 0; - handles[0] = bo->handle; - pitches[0] = bo->pitch; - pitches[1] = pitches[0]; - offsets[1] = pitches[0] * height; - handles[1] = bo->handle; - - planes[0] = virtual; - planes[1] = virtual + offsets[1]; - break; - case DRM_FORMAT_NV24: case DRM_FORMAT_NV42: + case DRM_FORMAT_NV20: case DRM_FORMAT_NV30: offsets[0] = 0; handles[0] = bo->handle; pitches[0] = bo->pitch; - pitches[1] = pitches[0] * 2; + pitches[1] = pitches[0] * 2 / xsub; offsets[1] = pitches[0] * height; handles[1] = bo->handle; @@ -303,14 +314,18 @@ bo_create(int fd, unsigned int format, case DRM_FORMAT_YUV420: case DRM_FORMAT_YVU420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YUV444: + case DRM_FORMAT_YVU444: offsets[0] = 0; handles[0] = bo->handle; pitches[0] = bo->pitch; - pitches[1] = pitches[0] / 2; + pitches[1] = pitches[0] / xsub; offsets[1] = pitches[0] * height; handles[1] = bo->handle; pitches[2] = pitches[1]; - offsets[2] = offsets[1] + pitches[1] * height / 2; + offsets[2] = offsets[1] + pitches[1] * height / ysub; handles[2] = bo->handle; planes[0] = virtual; @@ -372,7 +387,7 @@ bo_create(int fd, unsigned int format, break; } - util_fill_pattern(format, pattern, planes, width, height, pitches[0]); + util_fill_pattern(format, pattern, planes, width, height, pitches[0], seed); bo_unmap(bo); return bo; diff --git a/tests/modetest/buffers.h b/tests/modetest/buffers.h old mode 100644 new mode 100755 index cbd54e9ed..d7db67bf9 --- a/tests/modetest/buffers.h +++ b/tests/modetest/buffers.h @@ -34,7 +34,8 @@ struct bo; struct bo *bo_create(int fd, unsigned int format, unsigned int width, unsigned int height, unsigned int handles[4], unsigned int pitches[4], - unsigned int offsets[4], enum util_fill_pattern pattern); + unsigned int offsets[4], enum util_fill_pattern pattern, + unsigned long seed); void bo_destroy(struct bo *bo); void bo_dump(struct bo *bo, const char *filename); diff --git a/tests/modetest/cursor.c b/tests/modetest/cursor.c old mode 100644 new mode 100755 diff --git a/tests/modetest/cursor.h b/tests/modetest/cursor.h old mode 100644 new mode 100755 diff --git a/tests/modetest/meson.build b/tests/modetest/meson.build old mode 100644 new mode 100755 diff --git a/tests/modetest/modetest.c b/tests/modetest/modetest.c old mode 100644 new mode 100755 index d9e761e6c..3c0a8803a --- a/tests/modetest/modetest.c +++ b/tests/modetest/modetest.c @@ -70,6 +70,7 @@ static enum util_fill_pattern primary_fill = UTIL_PATTERN_SMPTE; static enum util_fill_pattern secondary_fill = UTIL_PATTERN_TILES; +static unsigned long pattern_seed = 0; static drmModeModeInfo user_mode; struct crtc { @@ -1199,7 +1200,7 @@ bo_fb_create(int fd, unsigned int fourcc, const uint32_t w, const uint32_t h, struct bo *bo; unsigned int fb_id; - bo = bo_create(fd, fourcc, w, h, handles, pitches, offsets, pat); + bo = bo_create(fd, fourcc, w, h, handles, pitches, offsets, pat, pattern_seed); if (bo == NULL) return -1; @@ -1857,7 +1858,7 @@ static void set_cursors(struct device *dev, struct pipe_arg *pipes, unsigned int * translucent alpha */ bo = bo_create(dev->fd, DRM_FORMAT_ARGB8888, cw, ch, handles, pitches, - offsets, UTIL_PATTERN_PLAIN); + offsets, UTIL_PATTERN_PLAIN, pattern_seed); if (bo == NULL) return; @@ -1973,7 +1974,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg) unsigned int len; unsigned int i; const char *p; - char *endp; + const char *endp; + char *endp_tok; pipe->vrefresh = 0; pipe->crtc_id = (uint32_t)-1; @@ -2011,7 +2013,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg) return -1; if (*endp == '@') { arg = endp + 1; - pipe->crtc_id = strtoul(arg, &endp, 10); + pipe->crtc_id = strtoul(arg, &endp_tok, 10); + endp = endp_tok; } if (*endp != ':') return -1; @@ -2027,8 +2030,8 @@ static int parse_connector(struct pipe_arg *pipe, const char *arg) pipe->mode_str[len] = '\0'; if (*p == '-') { - pipe->vrefresh = strtof(p + 1, &endp); - p = endp; + pipe->vrefresh = strtof(p + 1, &endp_tok); + p = endp_tok; } if (*p == '@') { @@ -2126,6 +2129,16 @@ static void parse_fill_patterns(char *arg) secondary_fill = util_pattern_enum(fill); } +static void parse_seed(const char *arg) +{ + unsigned long seed; + char *rest; + + seed = strtoul(arg, &rest, 10); + if (arg != rest) + pattern_seed = seed; +} + static void usage(char *name) { fprintf(stderr, "usage: %s [-acDdefMoPpsCvrw]\n", name); @@ -2149,6 +2162,7 @@ static void usage(char *name) fprintf(stderr, "\t-w ::\tset property, see 'property'\n"); fprintf(stderr, "\t-a \tuse atomic API\n"); fprintf(stderr, "\t-F pattern1,pattern2\tspecify fill patterns\n"); + fprintf(stderr, "\t-S \tspecify seed of noise patterns\n"); fprintf(stderr, "\t-o \t Dump writeback output buffer to file\n"); fprintf(stderr, "\n Generic options:\n\n"); @@ -2179,7 +2193,7 @@ static void usage(char *name) exit(0); } -static char optstr[] = "acdD:efF:M:P:ps:Cvrw:o:"; +static char optstr[] = "acdD:efF:M:P:ps:Cvrw:o:S:"; int main(int argc, char **argv) { @@ -2276,6 +2290,9 @@ int main(int argc, char **argv) count++; break; + case 'S': + parse_seed(optarg); + break; case 'C': test_cursor = 1; break; diff --git a/tests/proptest/Android.bp b/tests/proptest/Android.bp old mode 100644 new mode 100755 index e13d060bc..379e08c11 --- a/tests/proptest/Android.bp +++ b/tests/proptest/Android.bp @@ -1,13 +1,4 @@ -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - -cc_test { +cc_binary { name: "proptest", defaults: ["libdrm_defaults"], srcs: ["proptest.c"], diff --git a/tests/proptest/Makefile.sources b/tests/proptest/Makefile.sources deleted file mode 100644 index 446110d68..000000000 --- a/tests/proptest/Makefile.sources +++ /dev/null @@ -1,2 +0,0 @@ -PROPTEST_FILES := \ - proptest.c diff --git a/tests/proptest/meson.build b/tests/proptest/meson.build old mode 100644 new mode 100755 diff --git a/tests/proptest/proptest.c b/tests/proptest/proptest.c old mode 100644 new mode 100755 diff --git a/tests/util/Android.bp b/tests/util/Android.bp old mode 100644 new mode 100755 index 0322c2ace..9c1698e38 --- a/tests/util/Android.bp +++ b/tests/util/Android.bp @@ -21,15 +21,6 @@ // IN THE SOFTWARE. // -package { - // See: http://go/android-license-faq - // A large-scale-change added 'default_applicable_licenses' to import - // all of the 'license_kinds' from "external_libdrm_license" - // to get the below license kinds: - // SPDX-license-identifier-MIT - default_applicable_licenses: ["external_libdrm_license"], -} - build = ["Android.sources.bp"] cc_library_static { @@ -41,4 +32,5 @@ cc_library_static { shared_libs: ["libdrm"], header_libs: ["libdrm_test_headers"], export_header_lib_headers: ["libdrm_test_headers"], + vendor_available: true, } diff --git a/tests/util/Android.sources.bp b/tests/util/Android.sources.bp old mode 100644 new mode 100755 diff --git a/tests/util/Makefile.sources b/tests/util/Makefile.sources deleted file mode 100644 index e5f851136..000000000 --- a/tests/util/Makefile.sources +++ /dev/null @@ -1,8 +0,0 @@ -UTIL_FILES := \ - common.h \ - format.c \ - format.h \ - kms.c \ - kms.h \ - pattern.c \ - pattern.h diff --git a/tests/util/common.h b/tests/util/common.h old mode 100644 new mode 100755 diff --git a/tests/util/format.c b/tests/util/format.c old mode 100644 new mode 100755 index eda3c671d..c62354417 --- a/tests/util/format.c +++ b/tests/util/format.c @@ -62,6 +62,10 @@ static const struct util_format_info format_info[] = { /* YUV planar */ { DRM_FORMAT_YUV420, "YU12", MAKE_YUV_INFO(YUV_YCbCr, 2, 2, 1) }, { DRM_FORMAT_YVU420, "YV12", MAKE_YUV_INFO(YUV_YCrCb, 2, 2, 1) }, + { DRM_FORMAT_YUV422, "YU16", MAKE_YUV_INFO(YUV_YCbCr, 2, 1, 1) }, + { DRM_FORMAT_YVU422, "YV16", MAKE_YUV_INFO(YUV_YCrCb, 2, 1, 1) }, + { DRM_FORMAT_YUV444, "YU24", MAKE_YUV_INFO(YUV_YCbCr, 1, 1, 1) }, + { DRM_FORMAT_YVU444, "YV24", MAKE_YUV_INFO(YUV_YCrCb, 1, 1, 1) }, /* RGB16 */ { DRM_FORMAT_ARGB4444, "AR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 4, 12) }, { DRM_FORMAT_XRGB4444, "XR12", MAKE_RGB_INFO(4, 8, 4, 4, 4, 0, 0, 0) }, diff --git a/tests/util/format.h b/tests/util/format.h old mode 100644 new mode 100755 diff --git a/tests/util/kms.c b/tests/util/kms.c old mode 100644 new mode 100755 index 34a841803..5c66da3f5 --- a/tests/util/kms.c +++ b/tests/util/kms.c @@ -42,6 +42,8 @@ #include #include #include +#include +#include #include "xf86drm.h" #include "xf86drmMode.h" @@ -96,58 +98,42 @@ const char *util_lookup_connector_status_name(unsigned int status) ARRAY_SIZE(connector_status_names)); } -static const char * const modules[] = { - "i915", - "amdgpu", - "radeon", - "nouveau", - "vmwgfx", - "omapdrm", - "exynos", - "tilcdc", - "msm", - "sti", - "tegra", - "imx-drm", - "rockchip", - "atmel-hlcdc", - "fsl-dcu-drm", - "vc4", - "virtio_gpu", - "mediatek", - "meson", - "pl111", - "stm", - "sun4i-drm", - "armada-drm", - "komeda", - "imx-dcss", - "mxsfb-drm", - "simpledrm", - "imx-lcdif", - "vkms", -}; - int util_open(const char *device, const char *module) { - int fd; + int fd = -1; + drmVersionPtr version; - if (module) { + if (module || device) { fd = drmOpen(module, device); if (fd < 0) { - fprintf(stderr, "failed to open device '%s': %s\n", - module, strerror(errno)); + fprintf(stderr, "failed to open device '%s' with busid '%s': %s\n", + module, device, strerror(errno)); return -errno; } } else { unsigned int i; + drmDevicePtr devices[64]; + int num_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices)); + if (num_devices < 0) { + fprintf(stderr, "drmGetDevices2() failed with %s\n", strerror(num_devices)); + return num_devices; + } - for (i = 0; i < ARRAY_SIZE(modules); i++) { - printf("trying to open device '%s'...", modules[i]); + for (i = 0; i < num_devices; i++) { + drmDevicePtr device = devices[i]; + // Select only primary nodes + if ((device->available_nodes & 1 << DRM_NODE_PRIMARY) == 0) + continue; + + printf("trying to open device '%s'... ", device->nodes[DRM_NODE_PRIMARY]); + fd = open(device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC); - fd = drmOpen(modules[i], device); if (fd < 0) { printf("failed\n"); + } else if (!drmIsKMS(fd)) { + printf("is not a KMS device\n"); + close(fd); + fd = -1; } else { printf("done\n"); break; @@ -160,5 +146,15 @@ int util_open(const char *device, const char *module) } } + version = drmGetVersion(fd); + printf("opened device `%s` on driver `%s` (version %d.%d.%d at %s)\n", + version->desc, + version->name, + version->version_major, + version->version_minor, + version->version_patchlevel, + version->date); + drmFreeVersion(version); + return fd; } diff --git a/tests/util/kms.h b/tests/util/kms.h old mode 100644 new mode 100755 diff --git a/tests/util/meson.build b/tests/util/meson.build old mode 100644 new mode 100755 diff --git a/tests/util/pattern.c b/tests/util/pattern.c old mode 100644 new mode 100755 index 2ff9c0334..358699a4f --- a/tests/util/pattern.c +++ b/tests/util/pattern.c @@ -23,11 +23,13 @@ * IN THE SOFTWARE. */ +#include #include #include #include #include #include +#include #include @@ -40,6 +42,13 @@ #include "format.h" #include "pattern.h" +struct color_rgba { + uint16_t red; + uint16_t green; + uint16_t blue; + uint16_t alpha; +}; + struct color_rgb24 { unsigned int value:24; } __attribute__((__packed__)); @@ -301,6 +310,16 @@ static void write_pixels_10bpp(unsigned char *mem, mem[4] = ((d >> 2) & 0xff); } +static void update_pixels_10bpp(unsigned char *mem, uint64_t val, uint64_t mask) +{ + int i; + + for (i = 0; i < 5; i++, mask >>= 8, val >>= 8) { + mem[i] &= ~(mask & 0xff); + mem[i] |= (mask & 0xff) & val; + } +} + static void fill_smpte_yuv_planar_10bpp(const struct util_yuv_info *yuv, unsigned char *y_mem, unsigned char *uv_mem, @@ -1229,10 +1248,14 @@ static void fill_smpte(const struct util_format_info *info, void *planes[3], stride); case DRM_FORMAT_YUV420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YUV444: return fill_smpte_yuv_planar(&info->yuv, planes[0], planes[1], planes[2], width, height, stride); case DRM_FORMAT_YVU420: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YVU444: return fill_smpte_yuv_planar(&info->yuv, planes[0], planes[2], planes[1], width, height, stride); @@ -1646,10 +1669,14 @@ static void fill_tiles(const struct util_format_info *info, void *planes[3], width, height, stride); case DRM_FORMAT_YUV420: + case DRM_FORMAT_YUV422: + case DRM_FORMAT_YUV444: return fill_tiles_yuv_planar(info, planes[0], planes[1], planes[2], width, height, stride); case DRM_FORMAT_YVU420: + case DRM_FORMAT_YVU422: + case DRM_FORMAT_YVU444: return fill_tiles_yuv_planar(info, planes[0], planes[2], planes[1], width, height, stride); @@ -1841,6 +1868,267 @@ static void fill_gradient(const struct util_format_info *info, void *planes[3], } } +static struct color_rgba get_black_white_value(uint64_t index) +{ + const struct color_rgba colors[] = { + { .red = 0, .green = 0, .blue = 0, .alpha = 255 }, /* black */ + { .red = 255, .green = 255, .blue = 255, .alpha = 255 }, /* white */ + }; + + return colors[index & 0x1]; +} + +static struct color_rgba get_noise_color_value() +{ + struct color_rgba color = { + .red = rand(), + .green = rand(), + .blue = rand(), + .alpha = 255 + }; + + return color; +} + +static struct color_rgba get_rgb_color(uint64_t index, + enum util_fill_pattern pattern) +{ + struct color_rgba color = { + .red = 0, + .green = 0, + .blue = 0, + .alpha = 0 + }; + + switch (pattern) { + case UTIL_PATTERN_NOISE: + color = get_black_white_value(rand()); + + case UTIL_PATTERN_NOISE_COLOR: + color = get_noise_color_value(); + + case UTIL_PATTERN_BLACK_WHITE: + color = get_black_white_value(index); + + default: + break; + } + + return color; +} + +static void insert_value_yuv_packed(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color) +{ + struct color_yuv val = MAKE_YUV_601(color->red, color->green, color->blue); + const struct util_yuv_info *yuv = &info->yuv; + unsigned char *y_mem = (yuv->order & YUV_YC) ? planes[0] : planes[0] + 1; + unsigned char *c_mem = (yuv->order & YUV_CY) ? planes[0] : planes[0] + 1; + unsigned int u = (yuv->order & YUV_YCrCb) ? 2 : 0; + unsigned int v = (yuv->order & YUV_YCbCr) ? 2 : 0; + + if (x & 0x1) + return; + + y_mem += stride * y; + c_mem += stride * y; + + y_mem[2*x] = val.y; + c_mem[2*x+u] = val.u; + y_mem[2*x+2] = val.y; + c_mem[2*x+v] = val.v; +} + +static void insert_value_yuv_planar(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color) +{ + struct color_yuv val = MAKE_YUV_601(color->red, color->green, color->blue); + const struct util_yuv_info *yuv = &info->yuv; + unsigned int cs = yuv->chroma_stride; + unsigned int xsub = yuv->xsub; + unsigned int ysub = yuv->ysub; + unsigned int chroma_offset = (y + 1) / ysub; + unsigned char *y_mem = planes[0] + (y * stride); + unsigned char *u_mem = planes[1]; + unsigned char *v_mem = planes[2]; + + switch (info->format) { + case DRM_FORMAT_NV42: + u_mem = info->yuv.order & YUV_YCbCr ? planes[1] : planes[1] + 1; + v_mem = info->yuv.order & YUV_YCrCb ? planes[1] : planes[1] + 1; + break; + case DRM_FORMAT_YVU420: + u_mem = planes[2]; + v_mem = planes[1]; + break; + case DRM_FORMAT_YUV420: + default: + break; + } + + u_mem += (chroma_offset * (stride * cs / xsub)); + v_mem += (chroma_offset * (stride * cs / xsub)); + + y_mem[x] = val.y; + u_mem[x/xsub*cs] = val.u; + v_mem[x/xsub*cs] = val.v; +} + +static inline bool is_power_of_two(unsigned long val) +{ + return (val != 0) && ((val & (val - 1)) == 0); +} + +static bool check_yuv(const struct util_yuv_info *info) +{ + if (__builtin_expect( + is_power_of_two(info->xsub) && + is_power_of_two(info->ysub) && + is_power_of_two(info->chroma_stride), 1)) { + return true; + } + + return false; +} + +static void insert_value_yuv_planar_10bpp(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color) +{ + struct color_yuv val = MAKE_YUV_601(color->red, color->green, color->blue); + const struct util_yuv_info *yuv = &info->yuv; + unsigned int cs = yuv->chroma_stride; + unsigned int xsub = yuv->xsub; + unsigned int ysub = yuv->ysub; + unsigned int xstep = cs * xsub; + unsigned int ysub_mask = ysub - 1; + unsigned int xsub_mask = xsub - 1; + unsigned int xstep_mask = xstep - 1; + unsigned char *y_mem = planes[0] + (y * stride); + unsigned char *uv_mem = planes[1] + (y * (stride * cs / xsub)); + unsigned int block_start = ((x & 0x3) * 5) / 4; + unsigned int bit_start = (x & 0x3) * 10; + + /* Plus two because val.y is only 8 bits */ + update_pixels_10bpp(&y_mem[block_start], val.y << (bit_start + 2), + 0x3ff << bit_start); + + /* This logic only works when xsub, ysub and chroma stride is power of two. */ + assert(check_yuv(&info->yuv)); + + if (y & ysub_mask) + return; + + if (x & xsub_mask) + return; + + block_start = ((x & ~xstep_mask) * 5) / xstep; + bit_start = x & xstep_mask ? 0 : 20; + + update_pixels_10bpp(&uv_mem[block_start], + ((val.u << 2) | (val.v << 12)) << bit_start, + 0xfffff << bit_start); +} + + +static void insert_value_rgb32(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color) +{ + uint32_t *row = planes[0] + (stride * y); + uint32_t val = MAKE_RGBA10(&info->rgb, color->red, color->green, + color->blue, color->alpha); + + row[x] = val; +} + +static void insert_value_rgb16fp(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color) +{ + uint64_t *row = planes[0] + (stride * y); + uint64_t val = MAKE_RGBA10FP16(&info->rgb, color->red, color->green, + color->blue, color->alpha); + + row[x] = val; +} + +static void fill_simple_patterns(const struct util_format_info *info, + void *planes[3], unsigned int width, + unsigned int height, unsigned int stride, + enum util_fill_pattern pattern) +{ + void (*func_insert_value)(const struct util_format_info *info, + void *planes[3], unsigned int stride, + unsigned int x, unsigned int y, + const struct color_rgba* color); + int x, y; + + switch (info->format) { + case DRM_FORMAT_UYVY: + case DRM_FORMAT_VYUY: + case DRM_FORMAT_YUYV: + case DRM_FORMAT_YVYU: + func_insert_value = &insert_value_yuv_packed; + break; + case DRM_FORMAT_NV12: + case DRM_FORMAT_NV21: + case DRM_FORMAT_NV16: + case DRM_FORMAT_NV61: + case DRM_FORMAT_NV24: + case DRM_FORMAT_NV42: + case DRM_FORMAT_YUV420: + case DRM_FORMAT_YVU420: + func_insert_value = &insert_value_yuv_planar; + break; + case DRM_FORMAT_NV15: + case DRM_FORMAT_NV20: + case DRM_FORMAT_NV30: + func_insert_value = &insert_value_yuv_planar_10bpp; + break; + case DRM_FORMAT_ARGB8888: + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ABGR8888: + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_RGBA8888: + case DRM_FORMAT_RGBX8888: + case DRM_FORMAT_BGRA8888: + case DRM_FORMAT_BGRX8888: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_BGRA1010102: + case DRM_FORMAT_BGRX1010102: + func_insert_value = &insert_value_rgb32; + break; + case DRM_FORMAT_XRGB16161616F: + case DRM_FORMAT_XBGR16161616F: + case DRM_FORMAT_ARGB16161616F: + case DRM_FORMAT_ABGR16161616F: + func_insert_value = &insert_value_rgb16fp; + break; + default: + return; + } + + for (y = 0; y < height; y++) { + for (x = 0; x < width; x++) { + struct color_rgba color = get_rgb_color((width * y) + x, pattern); + (*func_insert_value)(info, planes, stride, x, y, &color); + } + } +} + /* * util_fill_pattern - Fill a buffer with a test pattern * @format: Pixel format @@ -1849,13 +2137,14 @@ static void fill_gradient(const struct util_format_info *info, void *planes[3], * @width: Width in pixels * @height: Height in pixels * @stride: Line stride (pitch) in bytes + * @seed: Seed for noise patterns if zero a default time based seed will be used * * Fill the buffers with the test pattern specified by the pattern parameter. * Supported formats vary depending on the selected pattern. */ void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern, void *planes[3], unsigned int width, - unsigned int height, unsigned int stride) + unsigned int height, unsigned int stride, unsigned long seed) { const struct util_format_info *info; @@ -1863,6 +2152,18 @@ void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern, if (info == NULL) return; + switch (pattern) { + case UTIL_PATTERN_NOISE: + case UTIL_PATTERN_NOISE_COLOR: + if (!seed) + seed = time(NULL); + srand(seed); + printf("Seed used for noise patterns %lu\n", seed); + break; + default: + break; + } + switch (pattern) { case UTIL_PATTERN_TILES: return fill_tiles(info, planes, width, height, stride); @@ -1876,6 +2177,12 @@ void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern, case UTIL_PATTERN_GRADIENT: return fill_gradient(info, planes, width, height, stride); + case UTIL_PATTERN_NOISE: + case UTIL_PATTERN_NOISE_COLOR: + case UTIL_PATTERN_BLACK_WHITE: + return fill_simple_patterns(info, planes, width, height, stride, + pattern); + default: printf("Error: unsupported test pattern %u.\n", pattern); break; @@ -1887,6 +2194,9 @@ static const char *pattern_names[] = { [UTIL_PATTERN_SMPTE] = "smpte", [UTIL_PATTERN_PLAIN] = "plain", [UTIL_PATTERN_GRADIENT] = "gradient", + [UTIL_PATTERN_NOISE] = "noise", + [UTIL_PATTERN_NOISE_COLOR] = "noise-color", + [UTIL_PATTERN_BLACK_WHITE] = "black-white", }; enum util_fill_pattern util_pattern_enum(const char *name) diff --git a/tests/util/pattern.h b/tests/util/pattern.h old mode 100644 new mode 100755 index e500aba3b..064e5a997 --- a/tests/util/pattern.h +++ b/tests/util/pattern.h @@ -33,11 +33,14 @@ enum util_fill_pattern { UTIL_PATTERN_PLAIN, UTIL_PATTERN_SMPTE, UTIL_PATTERN_GRADIENT, + UTIL_PATTERN_NOISE, + UTIL_PATTERN_NOISE_COLOR, + UTIL_PATTERN_BLACK_WHITE, }; void util_fill_pattern(uint32_t format, enum util_fill_pattern pattern, void *planes[3], unsigned int width, - unsigned int height, unsigned int stride); + unsigned int height, unsigned int stride, unsigned long seed); void util_smpte_fill_lut(unsigned int ncolors, struct drm_color_lut *lut); diff --git a/util_math.h b/util_math.h index 35bf45129..04a0966c0 100644 --- a/util_math.h +++ b/util_math.h @@ -24,6 +24,8 @@ #ifndef _UTIL_MATH_H_ #define _UTIL_MATH_H_ +#include + #define MIN2( A, B ) ( (A)<(B) ? (A) : (B) ) #define MAX2( A, B ) ( (A)>(B) ? (A) : (B) ) #define MAX3( A, B, C ) ((A) > (B) ? MAX2(A, C) : MAX2(B, C)) @@ -31,4 +33,25 @@ #define __align_mask(value, mask) (((value) + (mask)) & ~(mask)) #define ALIGN(value, alignment) __align_mask(value, (__typeof__(value))((alignment) - 1)) +static inline unsigned +util_last_bit64(uint64_t u) +{ +#if defined(HAVE___BUILTIN_CLZLL) + return u == 0 ? 0 : 64 - __builtin_clzll(u); +#elif defined(_MSC_VER) && (_M_AMD64 || _M_ARM64 || _M_IA64) + unsigned long index; + if (_BitScanReverse64(&index, u)) + return index + 1; + else + return 0; +#else + unsigned r = 0; + while (u) { + r++; + u >>= 1; + } + return r; +#endif +} + #endif /*_UTIL_MATH_H_*/ diff --git a/vc4/Makefile.sources b/vc4/Makefile.sources deleted file mode 100644 index 8bf97ff1e..000000000 --- a/vc4/Makefile.sources +++ /dev/null @@ -1,3 +0,0 @@ -LIBDRM_VC4_H_FILES := \ - vc4_packet.h \ - vc4_qpu_defines.h diff --git a/vc4/libdrm_vc4.pc.in b/vc4/libdrm_vc4.pc.in old mode 100644 new mode 100755 diff --git a/vc4/meson.build b/vc4/meson.build old mode 100644 new mode 100755 diff --git a/vc4/vc4_packet.h b/vc4/vc4_packet.h old mode 100644 new mode 100755 diff --git a/vc4/vc4_qpu_defines.h b/vc4/vc4_qpu_defines.h old mode 100644 new mode 100755 diff --git a/xf86drm.c b/xf86drm.c index d2e5636f5..53d135469 100644 --- a/xf86drm.c +++ b/xf86drm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include #include @@ -60,7 +61,6 @@ #if HAVE_SYS_SYSCTL_H #include #endif -#include #include #if defined(__FreeBSD__) @@ -81,10 +81,6 @@ #include "util_math.h" -#ifdef __ANDROID__ -#include -#endif - #ifdef __DragonFly__ #define DRM_MAJOR 145 #endif @@ -206,18 +202,6 @@ static const struct drmFormatVendorModifierInfo arm_mode_value_table[] = { { AFBC_FORMAT_MOD_USM, "USM" }, }; -static bool is_x_t_amd_gfx9_tile(uint64_t tile) -{ - switch (tile) { - case AMD_FMT_MOD_TILE_GFX9_64K_S_X: - case AMD_FMT_MOD_TILE_GFX9_64K_D_X: - case AMD_FMT_MOD_TILE_GFX9_64K_R_X: - return true; - } - - return false; -} - static bool drmGetAfbcFormatModifierNameFromArm(uint64_t modifier, FILE *fp) { @@ -364,167 +348,169 @@ drmGetFormatModifierNameFromNvidia(uint64_t modifier) * testing against TEGRA_TILE */ if ((modifier & 0x10) == 0x10) { char *mod_nvidia; - asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64"," + if (asprintf(&mod_nvidia, "BLOCK_LINEAR_2D,HEIGHT=%"PRIu64",KIND=%"PRIu64"," "GEN=%"PRIu64",SECTOR=%"PRIu64",COMPRESSION=%"PRIu64"", height, - kind, gen, sector, compression); + kind, gen, sector, compression) < 0) + mod_nvidia = NULL; return mod_nvidia; } return NULL; } -static void -drmGetFormatModifierNameFromAmdDcc(uint64_t modifier, FILE *fp) -{ - uint64_t dcc_max_compressed_block = - AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier); - uint64_t dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier); - - const char *dcc_max_compressed_block_str = NULL; - - fprintf(fp, ",DCC"); - - if (dcc_retile) - fprintf(fp, ",DCC_RETILE"); - - if (!dcc_retile && AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier)) - fprintf(fp, ",DCC_PIPE_ALIGN"); - - if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier)) - fprintf(fp, ",DCC_INDEPENDENT_64B"); - - if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier)) - fprintf(fp, ",DCC_INDEPENDENT_128B"); - - switch (dcc_max_compressed_block) { - case AMD_FMT_MOD_DCC_BLOCK_64B: - dcc_max_compressed_block_str = "64B"; - break; - case AMD_FMT_MOD_DCC_BLOCK_128B: - dcc_max_compressed_block_str = "128B"; - break; - case AMD_FMT_MOD_DCC_BLOCK_256B: - dcc_max_compressed_block_str = "256B"; - break; - } - - if (dcc_max_compressed_block_str) - fprintf(fp, ",DCC_MAX_COMPRESSED_BLOCK=%s", - dcc_max_compressed_block_str); - - if (AMD_FMT_MOD_GET(DCC_CONSTANT_ENCODE, modifier)) - fprintf(fp, ",DCC_CONSTANT_ENCODE"); -} - -static void -drmGetFormatModifierNameFromAmdTile(uint64_t modifier, FILE *fp) -{ - uint64_t pipe_xor_bits, bank_xor_bits, packers, rb; - uint64_t pipe, pipe_align, dcc, dcc_retile, tile_version; - - pipe_align = AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); - pipe_xor_bits = AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier); - dcc = AMD_FMT_MOD_GET(DCC, modifier); - dcc_retile = AMD_FMT_MOD_GET(DCC_RETILE, modifier); - tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier); - - fprintf(fp, ",PIPE_XOR_BITS=%"PRIu64, pipe_xor_bits); - - if (tile_version == AMD_FMT_MOD_TILE_VER_GFX9) { - bank_xor_bits = AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier); - fprintf(fp, ",BANK_XOR_BITS=%"PRIu64, bank_xor_bits); - } - - if (tile_version == AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) { - packers = AMD_FMT_MOD_GET(PACKERS, modifier); - fprintf(fp, ",PACKERS=%"PRIu64, packers); - } - - if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9) { - rb = AMD_FMT_MOD_GET(RB, modifier); - fprintf(fp, ",RB=%"PRIu64, rb); - } - - if (dcc && tile_version == AMD_FMT_MOD_TILE_VER_GFX9 && - (dcc_retile || pipe_align)) { - pipe = AMD_FMT_MOD_GET(PIPE, modifier); - fprintf(fp, ",PIPE_%"PRIu64, pipe); - } -} - static char * drmGetFormatModifierNameFromAmd(uint64_t modifier) { - uint64_t tile, tile_version, dcc; + static const char *gfx9_gfx11_tile_strings[32] = { + "LINEAR", + "256B_S", + "256B_D", + "256B_R", + "4KB_Z", + "4KB_S", + "4KB_D", + "4KB_R", + "64KB_Z", + "64KB_S", + "64KB_D", + "64KB_R", + "INVALID12", + "INVALID13", + "INVALID14", + "INVALID15", + "64KB_Z_T", + "64KB_S_T", + "64KB_D_T", + "64KB_R_T", + "4KB_Z_X", + "4KB_S_X", + "4KB_D_X", + "4KB_R_X", + "64KB_Z_X", + "64KB_S_X", + "64KB_D_X", + "64KB_R_X", + "256KB_Z_X", + "256KB_S_X", + "256KB_D_X", + "256KB_R_X", + }; + static const char *gfx12_tile_strings[32] = { + "LINEAR", + "256B_2D", + "4KB_2D", + "64KB_2D", + "256KB_2D", + "4KB_3D", + "64KB_3D", + "256KB_3D", + /* other values are unused */ + }; + uint64_t tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier); FILE *fp; char *mod_amd = NULL; size_t size = 0; - const char *str_tile = NULL; - const char *str_tile_version = NULL; - - tile = AMD_FMT_MOD_GET(TILE, modifier); - tile_version = AMD_FMT_MOD_GET(TILE_VERSION, modifier); - dcc = AMD_FMT_MOD_GET(DCC, modifier); - fp = open_memstream(&mod_amd, &size); if (!fp) return NULL; - /* add tile */ switch (tile_version) { case AMD_FMT_MOD_TILE_VER_GFX9: - str_tile_version = "GFX9"; + fprintf(fp, "GFX9"); break; case AMD_FMT_MOD_TILE_VER_GFX10: - str_tile_version = "GFX10"; + fprintf(fp, "GFX10"); break; case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: - str_tile_version = "GFX10_RBPLUS"; + fprintf(fp, "GFX10_RBPLUS"); break; case AMD_FMT_MOD_TILE_VER_GFX11: - str_tile_version = "GFX11"; + fprintf(fp, "GFX11"); break; - } - - if (str_tile_version) { - fprintf(fp, "%s", str_tile_version); - } else { + case AMD_FMT_MOD_TILE_VER_GFX12: + fprintf(fp, "GFX12"); + break; + default: fclose(fp); free(mod_amd); return NULL; } - /* add tile str */ - switch (tile) { - case AMD_FMT_MOD_TILE_GFX9_64K_S: - str_tile = "GFX9_64K_S"; - break; - case AMD_FMT_MOD_TILE_GFX9_64K_D: - str_tile = "GFX9_64K_D"; - break; - case AMD_FMT_MOD_TILE_GFX9_64K_S_X: - str_tile = "GFX9_64K_S_X"; - break; - case AMD_FMT_MOD_TILE_GFX9_64K_D_X: - str_tile = "GFX9_64K_D_X"; - break; - case AMD_FMT_MOD_TILE_GFX9_64K_R_X: - str_tile = "GFX9_64K_R_X"; - break; - case AMD_FMT_MOD_TILE_GFX11_256K_R_X: - str_tile = "GFX11_256K_R_X"; - break; - } + if (tile_version >= AMD_FMT_MOD_TILE_VER_GFX12) { + unsigned tile = AMD_FMT_MOD_GET(TILE, modifier); + + fprintf(fp, ",%s", gfx12_tile_strings[tile]); + + if (AMD_FMT_MOD_GET(DCC, modifier)) { + fprintf(fp, ",DCC,DCC_MAX_COMPRESSED_BLOCK=%uB", + 64 << AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier)); + + /* Other DCC fields are unused by GFX12. */ + } + } else { + unsigned tile = AMD_FMT_MOD_GET(TILE, modifier); + + fprintf(fp, ",%s", gfx9_gfx11_tile_strings[tile]); + + /* All *_T and *_X modes are affected by chip-specific fields. */ + if (tile >= 16) { + fprintf(fp, ",PIPE_XOR_BITS=%u", + (unsigned)AMD_FMT_MOD_GET(PIPE_XOR_BITS, modifier)); + + switch (tile_version) { + case AMD_FMT_MOD_TILE_VER_GFX9: + fprintf(fp, ",BANK_XOR_BITS=%u", + (unsigned)AMD_FMT_MOD_GET(BANK_XOR_BITS, modifier)); + break; + + case AMD_FMT_MOD_TILE_VER_GFX10: + /* Nothing else for GFX10. */ + break; + + case AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS: + case AMD_FMT_MOD_TILE_VER_GFX11: + /* This also determines the DCC layout, but DCC is only legal + * with tile=27 and tile=31 (*_R_X modes). + */ + fprintf(fp, ",PACKERS=%u", + (unsigned)AMD_FMT_MOD_GET(PACKERS, modifier)); + break; + } + } + + if (AMD_FMT_MOD_GET(DCC, modifier)) { + if (tile_version == AMD_FMT_MOD_TILE_VER_GFX9 && + (AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier) || + AMD_FMT_MOD_GET(DCC_RETILE, modifier))) { + /* These two only determine the layout of + * the non-displayable DCC plane. + */ + fprintf(fp, ",RB=%u", + (unsigned)AMD_FMT_MOD_GET(RB, modifier)); + fprintf(fp, ",PIPE=%u", + (unsigned)AMD_FMT_MOD_GET(PIPE, modifier)); + } + + fprintf(fp, ",DCC,DCC_MAX_COMPRESSED_BLOCK=%uB", + 64 << AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier)); + + if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier)) + fprintf(fp, ",DCC_INDEPENDENT_64B"); - if (str_tile) - fprintf(fp, ",%s", str_tile); + if (AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier)) + fprintf(fp, ",DCC_INDEPENDENT_128B"); - if (dcc) - drmGetFormatModifierNameFromAmdDcc(modifier, fp); + if (AMD_FMT_MOD_GET(DCC_CONSTANT_ENCODE, modifier)) + fprintf(fp, ",DCC_CONSTANT_ENCODE"); - if (tile_version >= AMD_FMT_MOD_TILE_VER_GFX9 && is_x_t_amd_gfx9_tile(tile)) - drmGetFormatModifierNameFromAmdTile(modifier, fp); + if (AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier)) + fprintf(fp, ",DCC_PIPE_ALIGN"); + + if (AMD_FMT_MOD_GET(DCC_RETILE, modifier)) + fprintf(fp, ",DCC_RETILE"); + } + } fclose(fp); return mod_amd; @@ -557,7 +543,8 @@ drmGetFormatModifierNameFromAmlogic(uint64_t modifier) else opts_str = "0"; - asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str); + if (asprintf(&mod_amlogic, "FBC,LAYOUT=%s,OPTIONS=%s", layout_str, opts_str) < 0) + mod_amlogic = NULL; return mod_amlogic; } @@ -621,7 +608,8 @@ drmGetFormatModifierNameFromVivante(uint64_t modifier) break; } - asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression); + if (asprintf(&mod_vivante, "%s%s%s", color_tiling, tile_status, compression) < 0) + mod_vivante = NULL; return mod_vivante; } @@ -658,22 +646,16 @@ drm_public void drmSetServerInfo(drmServerInfoPtr info) static int DRM_PRINTFLIKE(1, 0) drmDebugPrint(const char *format, va_list ap) { -#if defined( __ANDROID__) && !defined(__ANDROID_RECOVERY__) - return __android_log_vprint(ANDROID_LOG_DEBUG, "libdrm", format, ap); -#else return vfprintf(stderr, format, ap); -#endif } drm_public void drmMsg(const char *format, ...) { va_list ap; -#ifndef __ANDROID__ const char *env; if (((env = getenv("LIBGL_DEBUG")) && strstr(env, "verbose")) || (drm_server_info && drm_server_info->debug_print)) -#endif { va_start(ap, format); if (drm_server_info) { @@ -1000,6 +982,11 @@ static int drmOpenMinor(int minor, int create, int type) * * \return 1 if the DRM driver is loaded, 0 otherwise. * + * \deprecated + * This function doesn't work when a device goes away (as is often the case + * with simpledrm). drmGetDevices2 should be used instead to enumerate DRM + * devices. + * * \internal * Determine the presence of the kernel driver by attempting to open the 0 * minor and get version information. For backward compatibility with older @@ -1309,48 +1296,6 @@ drm_public int drmOpenRender(int minor) return drmOpenMinor(minor, 0, DRM_NODE_RENDER); } -/** - * Open the DRM device with specified type of specified framebuffer. - * - * Looks up the associated DRM device with specified type of the - * specified framebuffer and opens it. - * - * \param fb the index of framebuffer. - * \param type the device node type to open, PRIMARY, CONTROL or RENDER - * - * \return a file descriptor on success, or a negative value on error. - * - */ -drm_public int drmOpenByFB(int fb, int type) -{ -#ifdef __linux__ - DIR *sysdir; - struct dirent *ent; - char buf[64]; - const char *name = drmGetMinorName(type); - int fd = -1, len = strlen(name); - - snprintf(buf, sizeof(buf), "/sys/class/graphics/fb%d/device/drm", fb); - sysdir = opendir(buf); - if (!sysdir) - return -errno; - - while ((ent = readdir(sysdir))) { - if (!strncmp(ent->d_name, name, len)) { - snprintf(buf, sizeof(buf), "%s/%s", DRM_DIR_NAME, ent->d_name); - fd = open(buf, O_RDWR | O_CLOEXEC, 0); - break; - } - } - - closedir(sysdir); - return fd; -#else -#warning "Missing implementation of drmOpenByFB" - return -EINVAL; -#endif -} - /** * Free the version information returned by drmGetVersion(). * @@ -1407,11 +1352,11 @@ static void drmCopyVersion(drmVersionPtr d, const drm_version_t *s) d->version_minor = s->version_minor; d->version_patchlevel = s->version_patchlevel; d->name_len = s->name_len; - d->name = strdup(s->name); + d->name = s->name ? strdup(s->name) : NULL; d->date_len = s->date_len; - d->date = strdup(s->date); + d->date = s->date ? strdup(s->date) : NULL; d->desc_len = s->desc_len; - d->desc = strdup(s->desc); + d->desc = s->desc ? strdup(s->desc) : NULL; } @@ -3651,6 +3596,7 @@ static int get_subsystem_type(const char *device_path) { "/spi", DRM_BUS_PLATFORM }, { "/host1x", DRM_BUS_HOST1X }, { "/virtio", DRM_BUS_VIRTIO }, + { "/faux", DRM_BUS_FAUX }, }; strncpy(path, device_path, PATH_MAX); @@ -3854,6 +3800,9 @@ drm_public int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b) case DRM_BUS_HOST1X: return memcmp(a->businfo.host1x, b->businfo.host1x, sizeof(drmHost1xBusInfo)) == 0; + case DRM_BUS_FAUX: + return memcmp(a->businfo.faux, b->businfo.faux, sizeof(drmFauxBusInfo)) == 0; + default: break; } @@ -4516,6 +4465,62 @@ static int drmProcessHost1xDevice(drmDevicePtr *device, return ret; } +static int drmParseFauxBusInfo(int maj, int min, char *fullname) +{ +#ifdef __linux__ + char path[PATH_MAX + 1] = ""; + char real_path[PATH_MAX + 1] = ""; + char *name; + + snprintf(path, sizeof(path), "/sys/dev/char/%d:%d/device", maj, min); + + if (!realpath(path, real_path)) + return -errno; + + name = basename(real_path); + if (!name) + return -ENOENT; + + strncpy(fullname, name, DRM_FAUX_DEVICE_NAME_LEN - 1); + fullname[DRM_FAUX_DEVICE_NAME_LEN - 1] = '\0'; + + return 0; +#else +#warning "Missing implementation of drmParseFauxBusInfo" + return -EINVAL; +#endif +} + +static int drmProcessFauxDevice(drmDevicePtr *device, + const char *node, int node_type, + int maj, int min, bool fetch_deviceinfo, + uint32_t flags) +{ + drmDevicePtr dev; + char *ptr; + int ret; + + dev = drmDeviceAlloc(node_type, node, sizeof(drmFauxBusInfo), 0, &ptr); + if (!dev) + return -ENOMEM; + + dev->bustype = DRM_BUS_FAUX; + + dev->businfo.faux = (drmFauxBusInfoPtr)ptr; + + ret = drmParseFauxBusInfo(maj, min, dev->businfo.faux->name); + if (ret < 0) + goto free_device; + + *device = dev; + + return 0; + +free_device: + free(dev); + return ret; +} + static int process_device(drmDevicePtr *device, const char *d_name, int req_subsystem_type, @@ -4523,14 +4528,24 @@ process_device(drmDevicePtr *device, const char *d_name, { struct stat sbuf; char node[PATH_MAX + 1]; - int node_type, subsystem_type; + int node_type, subsystem_type, written; unsigned int maj, min; + const int max_node_length = ALIGN(drmGetMaxNodeName(), sizeof(void *)); node_type = drmGetNodeType(d_name); if (node_type < 0) return -1; - snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name); + written = snprintf(node, PATH_MAX, "%s/%s", DRM_DIR_NAME, d_name); + if (written < 0) + return -1; + + /* anything longer than this will be truncated in drmDeviceAlloc. + * Account for NULL byte + */ + if (written + 1 > max_node_length) + return -1; + if (stat(node, &sbuf)) return -1; @@ -4558,6 +4573,9 @@ process_device(drmDevicePtr *device, const char *d_name, case DRM_BUS_HOST1X: return drmProcessHost1xDevice(device, node, node_type, maj, min, fetch_deviceinfo, flags); + case DRM_BUS_FAUX: + return drmProcessFauxDevice(device, node, node_type, maj, min, + fetch_deviceinfo, flags); default: return -1; } @@ -4637,6 +4655,8 @@ drm_public int drmGetDeviceFromDevId(dev_t find_rdev, uint32_t flags, drmDeviceP const char *dev_name; int node_type, subsystem_type; int maj, min, n, ret; + const int max_node_length = ALIGN(drmGetMaxNodeName(), sizeof(void *)); + struct stat sbuf; if (device == NULL) return -EINVAL; @@ -4655,9 +4675,14 @@ drm_public int drmGetDeviceFromDevId(dev_t find_rdev, uint32_t flags, drmDeviceP if (!dev_name) return -EINVAL; + /* anything longer than this will be truncated in drmDeviceAlloc. + * Account for NULL byte + */ n = snprintf(node, PATH_MAX, dev_name, DRM_DIR_NAME, min); if (n == -1 || n >= PATH_MAX) return -errno; + if (n + 1 > max_node_length) + return -EINVAL; if (stat(node, &sbuf)) return -EINVAL; diff --git a/xf86drm.h b/xf86drm.h index 1950df731..b45337a48 100644 --- a/xf86drm.h +++ b/xf86drm.h @@ -1,10 +1,10 @@ /** - * \file xf86drm.h + * \file xf86drm.h * OS-independent header for DRM user-level library interface. * * \author Rickard E. (Rik) Faith */ - + /* * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. @@ -197,9 +197,9 @@ typedef enum { typedef enum { /** \name Flags for DMA buffer dispatch */ /*@{*/ - DRM_DMA_BLOCK = 0x01, /**< + DRM_DMA_BLOCK = 0x01, /**< * Block until buffer dispatched. - * + * * \note the buffer may not yet have been * processed by the hardware -- getting a * hardware lock with the hardware quiescent @@ -605,7 +605,6 @@ extern int drmOpenWithType(const char *name, const char *busid, extern int drmOpenControl(int minor); /* deprecated: always fails */ extern int drmOpenRender(int minor); -extern int drmOpenByFB(int fb, int type); extern int drmClose(int fd); extern drmVersionPtr drmGetVersion(int fd); extern drmVersionPtr drmGetLibVersion(int fd); @@ -694,7 +693,7 @@ extern int drmGetLock(int fd, drmLockFlags flags); extern int drmUnlock(int fd, drm_context_t context); extern int drmFinish(int fd, int context, drmLockFlags flags); -extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, +extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, drm_handle_t * handle); /* AGP/GART support: X server (root) only */ @@ -780,7 +779,7 @@ typedef struct _drmEventContext { int version; void (*vblank_handler)(int fd, - unsigned int sequence, + unsigned int sequence, unsigned int tv_sec, unsigned int tv_usec, void *user_data); @@ -844,6 +843,7 @@ extern char *drmGetRenderDeviceNameFromFd(int fd); #define DRM_BUS_USB 1 #define DRM_BUS_PLATFORM 2 #define DRM_BUS_HOST1X 3 +#define DRM_BUS_FAUX 4 typedef struct _drmPciBusInfo { uint16_t domain; @@ -890,6 +890,12 @@ typedef struct _drmHost1xDeviceInfo { char **compatible; /* NULL terminated list of compatible strings */ } drmHost1xDeviceInfo, *drmHost1xDeviceInfoPtr; +#define DRM_FAUX_DEVICE_NAME_LEN 512 + +typedef struct _drmFauxBusInfo { + char name[DRM_FAUX_DEVICE_NAME_LEN]; +} drmFauxBusInfo, *drmFauxBusInfoPtr; + typedef struct _drmDevice { char **nodes; /* DRM_NODE_MAX sized array */ int available_nodes; /* DRM_NODE_* bitmask */ @@ -899,6 +905,7 @@ typedef struct _drmDevice { drmUsbBusInfoPtr usb; drmPlatformBusInfoPtr platform; drmHost1xBusInfoPtr host1x; + drmFauxBusInfoPtr faux; } businfo; union { drmPciDeviceInfoPtr pci; @@ -927,6 +934,11 @@ extern int drmGetDeviceFromDevId(dev_t dev_id, uint32_t flags, drmDevicePtr *dev */ extern int drmGetNodeTypeFromDevId(dev_t devid); +/** + * Check if two drmDevice pointers represent the same DRM device. + * + * Returns 1 if the devices are equal, 0 otherwise. + */ extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b); extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle);