Hi,
In the documentation for ADC settings for the T3.x, and 4.x, sampling intervals are given in terms of ADCK.
In both the T3.x and T4,x documentation it says ADCK depends on ADC_F_BUS, But it does not say say anything about ADC_F_BUS, nor the relationship between them. So, we do not what the value is for ADCK and we do not know the time actual conversion time.
This is a critical parameter of course, because the ADC sampling capacitor has to charge to within 1LSB within this time, to achieve a faithful representation of the input.
The conversion times are similarly ambiquous being specified only as slow to fast and very fast, but without sufficient information to know what these mean in terms of actual time.
Could you please fill this in, so that we can determine the actual sampling and conversion times?
Thank
Hi,
In the documentation for ADC settings for the T3.x, and 4.x, sampling intervals are given in terms of ADCK.
In both the T3.x and T4,x documentation it says ADCK depends on ADC_F_BUS, But it does not say say anything about ADC_F_BUS, nor the relationship between them. So, we do not what the value is for ADCK and we do not know the time actual conversion time.
This is a critical parameter of course, because the ADC sampling capacitor has to charge to within 1LSB within this time, to achieve a faithful representation of the input.
The conversion times are similarly ambiquous being specified only as slow to fast and very fast, but without sufficient information to know what these mean in terms of actual time.
Could you please fill this in, so that we can determine the actual sampling and conversion times?
Thank