From d465ed8c05027b743cb40420f17c8b62cba1075a Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Tue, 8 Jul 2025 16:53:11 +0200 Subject: [PATCH 01/26] target/sim: Add libfesvr support in Questa & VCS --- cheshire.mk | 2 +- target/sim/vcs/start.cheshire_soc.sh | 2 +- target/sim/vsim/start.cheshire_soc.tcl | 3 +++ 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/cheshire.mk b/cheshire.mk index f838911b7..8e0028af8 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -149,7 +149,7 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS)" > $@ - echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11" -cpppath "$(CXX_PATH)"' >> $@ + echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml $(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 6352c5203..e8623fb3a 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -50,7 +50,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=/scratch/ga25f6/riscv-isa-sim/install/lib -L/scratch/ga25f6/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index e6a005d4a..c732b1969 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -48,6 +48,9 @@ if { [info exists USE_DRAMSYS] } { } } +# Need to link fesvr library +append flags "-gblso /scratch/ga25f6/riscv-isa-sim/install/lib/libfesvr.so" + # tclint-disable-next-line command-args eval "vsim -c ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${pargs} ${flags} From 95c0d40d6e61ffae2c1d854aba9ed22c8150c529 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Tue, 8 Jul 2025 18:00:34 +0200 Subject: [PATCH 02/26] SimDTM : Add sv module and dpi to use the dtm from fesvr to boot pk and run an helloworld --- Bender.yml | 1 + hw/cheshire_soc.sv | 24 ++++--- sw/apps/helloworld.c | 6 ++ sw/apps/pk_dram | Bin 0 -> 80704 bytes target/sim/src/SimDTM.sv | 83 +++++++++++++++++++++++++ target/sim/src/elfloader.cpp | 62 ++++++++++++++++++ target/sim/src/fixture_cheshire_soc.sv | 16 ++++- target/sim/src/tb_cheshire_soc.sv | 6 +- target/sim/src/vip_cheshire_soc.sv | 48 +++++++++++++- 9 files changed, 233 insertions(+), 13 deletions(-) create mode 100644 sw/apps/helloworld.c create mode 100755 sw/apps/pk_dram create mode 100644 target/sim/src/SimDTM.sv diff --git a/Bender.yml b/Bender.yml index edddb742b..eaae185c8 100644 --- a/Bender.yml +++ b/Bender.yml @@ -47,6 +47,7 @@ sources: - target: any(simulation, test) files: + - target/sim/src/SimDTM.sv - target/sim/models/s25fs512s.v - target/sim/models/24FC1025.v - target/sim/src/vip_cheshire_soc.sv diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index b3b625443..a4a0aa754 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -105,7 +105,15 @@ module cheshire_soc import cheshire_pkg::*; #( output logic [UsbNumPorts-1:0] usb_dm_oe_o, input logic [UsbNumPorts-1:0] usb_dp_i, output logic [UsbNumPorts-1:0] usb_dp_o, - output logic [UsbNumPorts-1:0] usb_dp_oe_o + output logic [UsbNumPorts-1:0] usb_dp_oe_o, + // DMI interface + input dm::dmi_req_t dmi_req_i, + input logic dmi_req_valid_i, + output logic dmi_req_ready_o, + + output dm::dmi_resp_t dmi_resp_o, + input logic dmi_resp_ready_i, + output logic dmi_resp_valid_o ); `include "axi/typedef.svh" @@ -913,13 +921,13 @@ module cheshire_soc import cheshire_pkg::*; #( .master_r_rdata_i ( dbg_sba_rdata ), .master_r_err_i ( dbg_sba_err ), .master_r_other_err_i ( 1'b0 ), - .dmi_rst_ni ( dbg_dmi_rst_n ), - .dmi_req_valid_i ( dbg_dmi_req_valid ), - .dmi_req_ready_o ( dbg_dmi_req_ready ), - .dmi_req_i ( dbg_dmi_req ), - .dmi_resp_valid_o ( dbg_dmi_rsp_valid ), - .dmi_resp_ready_i ( dbg_dmi_rsp_ready ), - .dmi_resp_o ( dbg_dmi_rsp ) + .dmi_rst_ni ( rst_ni ), // not handled by SimDTM and his done like this in dmi_jtag + .dmi_req_valid_i ( dmi_req_valid_i ), + .dmi_req_ready_o ( dmi_req_ready_o ), + .dmi_req_i ( dmi_req_i ), + .dmi_resp_valid_o ( dmi_resp_valid_o ), + .dmi_resp_ready_i ( dmi_resp_ready_i ), + .dmi_resp_o ( dmi_resp_o ) ); axi_mst_req_t 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b/target/sim/src/SimDTM.sv @@ -0,0 +1,83 @@ +// See LICENSE.SiFive for license details. +//VCS coverage exclude_file + +import "DPI-C" function int debug_tick +( + output bit debug_req_valid, + input bit debug_req_ready, + output int debug_req_bits_addr, + output int debug_req_bits_op, + output int debug_req_bits_data, + + input bit debug_resp_valid, + output bit debug_resp_ready, + input int debug_resp_bits_resp, + input int debug_resp_bits_data +); + +module SimDTM( + input clk, + input reset, + + output debug_req_valid, + input debug_req_ready, + output [ 6:0] debug_req_bits_addr, + output [ 1:0] debug_req_bits_op, + output [31:0] debug_req_bits_data, + + input debug_resp_valid, + output debug_resp_ready, + input [ 1:0] debug_resp_bits_resp, + input [31:0] debug_resp_bits_data, + + output [31:0] exit +); + + //bit r_reset; + + wire #0.1 __debug_req_ready = debug_req_ready; + wire #0.1 __debug_resp_valid = debug_resp_valid; + wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; + wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data; + + bit __debug_req_valid; + int __debug_req_bits_addr; + int __debug_req_bits_op; + int __debug_req_bits_data; + bit __debug_resp_ready; + int __exit; + + assign #0.1 debug_req_valid = __debug_req_valid; + assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0]; + assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0]; + assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0]; + assign #0.1 debug_resp_ready = __debug_resp_ready; + assign #0.1 exit = __exit; + + always @(posedge clk) + begin + /* reset condition was not working... + r_reset <= reset; + if (reset || r_reset) */ + if(!reset) + begin + __debug_req_valid = 0; + __debug_resp_ready = 0; + __exit = 0; + end + else + begin + __exit = debug_tick( + __debug_req_valid, + __debug_req_ready, + __debug_req_bits_addr, + __debug_req_bits_op, + __debug_req_bits_data, + __debug_resp_valid, + __debug_resp_ready, + __debug_resp_bits_resp, + __debug_resp_bits_data + ); + end + end +endmodule diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp index b02860c91..f03538e66 100644 --- a/target/sim/src/elfloader.cpp +++ b/target/sim/src/elfloader.cpp @@ -9,6 +9,7 @@ // Christopher Reinwardt #include +#include #include #include #if defined (__unix__) || (defined (__APPLE__) && defined (__MACH__)) @@ -30,6 +31,7 @@ #include #include #include +#include #define IS_ELF(hdr) \ ((hdr).e_ident[0] == 0x7f && (hdr).e_ident[1] == 'E' && \ @@ -160,6 +162,16 @@ extern "C" { char get_section(long long *address_ret, long long *len_ret); char read_section(long long address, const svOpenArrayHandle buffer, long long len); char read_elf(const char *filename); + int debug_tick( + unsigned char* debug_req_valid, + unsigned char debug_req_ready, + int* debug_req_bits_addr, + int* debug_req_bits_op, + int* debug_req_bits_data, + unsigned char debug_resp_valid, + unsigned char* debug_resp_ready, + int debug_resp_bits_resp, + int debug_resp_bits_data); } static void write (uint64_t address, uint64_t len, uint8_t *buf) @@ -398,3 +410,53 @@ extern "C" char read_elf(const char *filename) { return 0; } #endif + +dtm_t* dtm; +/*------------------------ +From SimDTM.cc +------------------------*/ +extern "C" int debug_tick +( + unsigned char* debug_req_valid, + unsigned char debug_req_ready, + int* debug_req_bits_addr, + int* debug_req_bits_op, + int* debug_req_bits_data, + unsigned char debug_resp_valid, + unsigned char* debug_resp_ready, + int debug_resp_bits_resp, + int debug_resp_bits_data +) +{ + if (!dtm) { + //the list of argv are the program that will be runned after pk is booted. + // Need to find a way to make it easier to change programs, maybe like it was done... + int htif_argc = 3; + char* htif_argv[htif_argc]; + htif_argv[0] = (char*)"htif"; + htif_argv[1] = (char*)"/scratch/ga25f6/cheshire/sw/apps/pk_dram"; + htif_argv[2] = (char*)"/scratch/ga25f6/cheshire/sw/apps/helloworld.o"; + + dtm = new dtm_t(htif_argc, htif_argv); + } + + + dtm_t::resp resp_bits; + resp_bits.resp = debug_resp_bits_resp; + resp_bits.data = debug_resp_bits_data; + + dtm->tick + ( + debug_req_ready, + debug_resp_valid, + resp_bits + ); + + *debug_resp_ready = dtm->resp_ready(); + *debug_req_valid = dtm->req_valid(); + *debug_req_bits_addr = dtm->req_bits().addr; + *debug_req_bits_op = dtm->req_bits().op; + *debug_req_bits_data = dtm->req_bits().data; + + return dtm->done() ? (dtm->exit_code() << 1 | 1) : 0; +} diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 056f0b338..1b9745f1c 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -63,6 +63,14 @@ module fixture_cheshire_soc #( logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i; logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o; + //DMI + dm::dmi_req_t dmi_req; + logic dmi_req_valid; + logic dmi_req_ready; + dm::dmi_resp_t dmi_resp; + logic dmi_resp_ready; + logic dmi_resp_valid; + cheshire_soc #( .Cfg ( DutCfg ), .ExtHartinfo ( '0 ), @@ -142,7 +150,13 @@ module fixture_cheshire_soc #( .usb_dm_oe_o ( ), .usb_dp_i ( '0 ), .usb_dp_o ( ), - .usb_dp_oe_o ( ) + .usb_dp_oe_o ( ), + .dmi_req_valid_i ( dmi_req_valid ), + .dmi_req_ready_o ( dmi_req_ready ), + .dmi_req_i ( dmi_req ), + .dmi_resp_valid_o ( dmi_resp_valid ), + .dmi_resp_ready_i ( dmi_resp_ready ), + .dmi_resp_o ( dmi_resp ) ); //////////////////////// diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index 57a15e8b6..548c08250 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -46,8 +46,8 @@ module tb_cheshire_soc #( fix.vip.jtag_elf_run(preload_elf); fix.vip.jtag_wait_for_eoc(exit_code); end 1: begin // Serial Link - fix.vip.slink_elf_run(preload_elf); - fix.vip.slink_wait_for_eoc(exit_code); + /*fix.vip.slink_elf_run(preload_elf); + fix.vip.slink_wait_for_eoc(exit_code);*/ end 2: begin // UART fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end default: begin @@ -65,7 +65,7 @@ module tb_cheshire_soc #( // Wait for the UART to finish reading the current byte wait (fix.vip.uart_reading_byte == 0); - $finish; + //$finish; end endmodule diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index e32e5410f..6dccf4631 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -72,7 +72,14 @@ module vip_cheshire_soc import cheshire_pkg::*; #( output logic [SlinkNumChan-1:0] slink_rcv_clk_i, input logic [SlinkNumChan-1:0] slink_rcv_clk_o, output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, - input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o + input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o, + // DMI + output dm::dmi_req_t dmi_req, + output logic dmi_req_valid, + input logic dmi_req_ready, + input dm::dmi_resp_t dmi_resp, + output logic dmi_resp_ready, + input logic dmi_resp_valid ); `include "cheshire/typedef.svh" @@ -88,6 +95,19 @@ module vip_cheshire_soc import cheshire_pkg::*; #( import "DPI-C" function byte get_entry(output longint entry); import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); + import "DPI-C" function int debug_tick +( + output bit debug_req_valid, + input bit debug_req_ready, + output int debug_req_bits_addr, + output int debug_req_bits_op, + output int debug_req_bits_data, + + input bit debug_resp_valid, + output bit debug_resp_ready, + input int debug_resp_bits_resp, + input int debug_resp_bits_data +); //////////// // DRAM // @@ -954,6 +974,32 @@ module vip_cheshire_soc import cheshire_pkg::*; #( if (exit_code) $error("[SLINK] FAILED: return code %0d", exit_code); else $display("[SLINK] SUCCESS"); endtask + task automatic wait_boot_pk(); + #(ClkPeriodSys * 200000 * 2); // wait 2s, pk should be booted (take around 1.5s). + endtask + + ////////////// + // SimDTM // + ////////////// + + logic [31:0] sim_exit; // TODO: wire this up in the testbench + logic [1:0] dmi_req_bits_op; + assign dmi_req.op = dm::dtm_op_e'(dmi_req_bits_op); // need to check if it's this variable, + + SimDTM i_SimDTM ( + .clk ( clk ), + .reset ( rst_n ), + .debug_req_valid ( dmi_req_valid ), + .debug_req_ready ( dmi_req_ready ), + .debug_req_bits_addr ( dmi_req.addr ), + .debug_req_bits_op ( dmi_req_bits_op ), + .debug_req_bits_data ( dmi_req.data ), + .debug_resp_valid ( dmi_resp_valid ), + .debug_resp_ready ( dmi_resp_ready ), + .debug_resp_bits_resp ( dmi_resp.resp ), + .debug_resp_bits_data ( dmi_resp.data ), + .exit ( sim_exit ) + ); endmodule From dcba07956d879da5b41dbdb174a09fbdb18ad21f Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 9 Jul 2025 15:26:35 +0200 Subject: [PATCH 03/26] FESVR : Add a variable to use fesvr and new compilation script for it --- cheshire.mk | 10 +++++++++ hw/cheshire_soc.sv | 30 ++++++++++++++++++-------- target/sim/src/fixture_cheshire_soc.sv | 18 ++++++++++------ target/sim/src/tb_cheshire_soc.sv | 12 ++++++++--- target/sim/src/vip_cheshire_soc.sv | 18 ++++++++++------ 5 files changed, 63 insertions(+), 25 deletions(-) diff --git a/cheshire.mk b/cheshire.mk index 8e0028af8..055d292aa 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -151,10 +151,18 @@ $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS)" > $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ +$(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc_fesvr.tcl: $(CHS_ROOT)/Bender.yml + $(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS) +define+FESVR_DTM" > $@ + echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ + $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml $(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ chmod +x $@ +$(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc_fesvr.sh: $(CHS_ROOT)/Bender.yml + $(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS) +define+FESVR_DTM" --vlogan-bin="$(VLOGAN)" > $@ + chmod +x $@ + .PRECIOUS: $(CHS_ROOT)/target/sim/models $(CHS_ROOT)/target/sim/models: mkdir -p $@ @@ -173,7 +181,9 @@ $(CHS_ROOT)/target/sim/models/24FC1025.v: $(CHS_ROOT)/Bender.yml | $(CHS_ROOT)/t CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/s25fs512s.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl +CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc_fesvr.tcl CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh +CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc_fesvr.sh ########### # DRAMSys # diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index a4a0aa754..af84c3ae2 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -97,6 +97,16 @@ module cheshire_soc import cheshire_pkg::*; #( output logic [Cfg.VgaRedWidth -1:0] vga_red_o, output logic [Cfg.VgaGreenWidth-1:0] vga_green_o, output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o, +`ifdef FESVR_DTM + // DMI interface + input dm::dmi_req_t dmi_req_i, + input logic dmi_req_valid_i, + output logic dmi_req_ready_o, + + output dm::dmi_resp_t dmi_resp_o, + input logic dmi_resp_ready_i, + output logic dmi_resp_valid_o, +`endif // USB interface input logic usb_clk_i, input logic usb_rst_ni, @@ -105,15 +115,7 @@ module cheshire_soc import cheshire_pkg::*; #( output logic [UsbNumPorts-1:0] usb_dm_oe_o, input logic [UsbNumPorts-1:0] usb_dp_i, output logic [UsbNumPorts-1:0] usb_dp_o, - output logic [UsbNumPorts-1:0] usb_dp_oe_o, - // DMI interface - input dm::dmi_req_t dmi_req_i, - input logic dmi_req_valid_i, - output logic dmi_req_ready_o, - - output dm::dmi_resp_t dmi_resp_o, - input logic dmi_resp_ready_i, - output logic dmi_resp_valid_o + output logic [UsbNumPorts-1:0] usb_dp_oe_o ); `include "axi/typedef.svh" @@ -921,6 +923,7 @@ module cheshire_soc import cheshire_pkg::*; #( .master_r_rdata_i ( dbg_sba_rdata ), .master_r_err_i ( dbg_sba_err ), .master_r_other_err_i ( 1'b0 ), + `ifdef FESVR_DTM .dmi_rst_ni ( rst_ni ), // not handled by SimDTM and his done like this in dmi_jtag .dmi_req_valid_i ( dmi_req_valid_i ), .dmi_req_ready_o ( dmi_req_ready_o ), @@ -928,6 +931,15 @@ module cheshire_soc import cheshire_pkg::*; #( .dmi_resp_valid_o ( dmi_resp_valid_o ), .dmi_resp_ready_i ( dmi_resp_ready_i ), .dmi_resp_o ( dmi_resp_o ) + `else + .dmi_rst_ni ( dbg_dmi_rst_n ), + .dmi_req_valid_i ( dbg_dmi_req_valid ), + .dmi_req_ready_o ( dbg_dmi_req_ready ), + .dmi_req_i ( dbg_dmi_req ), + .dmi_resp_valid_o ( dbg_dmi_rsp_valid ), + .dmi_resp_ready_i ( dbg_dmi_rsp_ready ), + .dmi_resp_o ( dbg_dmi_rsp ) + `endif ); axi_mst_req_t axi_dbg_req; diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 1b9745f1c..4dcfd058b 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -63,6 +63,7 @@ module fixture_cheshire_soc #( logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i; logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o; +`ifdef FESVR_DTM //DMI dm::dmi_req_t dmi_req; logic dmi_req_valid; @@ -70,6 +71,7 @@ module fixture_cheshire_soc #( dm::dmi_resp_t dmi_resp; logic dmi_resp_ready; logic dmi_resp_valid; +`endif cheshire_soc #( .Cfg ( DutCfg ), @@ -143,6 +145,14 @@ module fixture_cheshire_soc #( .vga_red_o ( ), .vga_green_o ( ), .vga_blue_o ( ), + `ifdef FESVR_DTM + .dmi_req_valid_i ( dmi_req_valid ), + .dmi_req_ready_o ( dmi_req_ready ), + .dmi_req_i ( dmi_req ), + .dmi_resp_valid_o ( dmi_resp_valid ), + .dmi_resp_ready_i ( dmi_resp_ready ), + .dmi_resp_o ( dmi_resp ), + `endif .usb_clk_i ( 1'b0 ), .usb_rst_ni ( 1'b1 ), .usb_dm_i ( '0 ), @@ -150,13 +160,7 @@ module fixture_cheshire_soc #( .usb_dm_oe_o ( ), .usb_dp_i ( '0 ), .usb_dp_o ( ), - .usb_dp_oe_o ( ), - .dmi_req_valid_i ( dmi_req_valid ), - .dmi_req_ready_o ( dmi_req_ready ), - .dmi_req_i ( dmi_req ), - .dmi_resp_valid_o ( dmi_resp_valid ), - .dmi_resp_ready_i ( dmi_resp_ready ), - .dmi_resp_o ( dmi_resp ) + .usb_dp_oe_o ( ) ); //////////////////////// diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index 548c08250..9a9c61cb7 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -37,6 +37,9 @@ module tb_cheshire_soc #( // Wait for reset fix.vip.wait_for_reset(); +// if using fesvr, the preloading is handled by fesvr dtn +`ifndef FESVR_DTM + // Preload in idle mode or wait for completion in autonomous boot if (boot_mode == 0) begin // Idle boot: preload with the specified mode @@ -46,8 +49,9 @@ module tb_cheshire_soc #( fix.vip.jtag_elf_run(preload_elf); fix.vip.jtag_wait_for_eoc(exit_code); end 1: begin // Serial Link - /*fix.vip.slink_elf_run(preload_elf); - fix.vip.slink_wait_for_eoc(exit_code);*/ + fix.vip.slink_elf_run(preload_elf); + fix.vip.slink_wait_for_eoc(exit_code); + fix.vip.wait_boot_pk(); end 2: begin // UART fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end default: begin @@ -65,7 +69,9 @@ module tb_cheshire_soc #( // Wait for the UART to finish reading the current byte wait (fix.vip.uart_reading_byte == 0); - //$finish; + $finish; +`endif + end endmodule diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 6dccf4631..56343acec 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -68,18 +68,20 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire spih_sck, inout wire [SpihNumCs-1:0] spih_csb, inout wire [ 3:0] spih_sd, - // Serial link interface - output logic [SlinkNumChan-1:0] slink_rcv_clk_i, - input logic [SlinkNumChan-1:0] slink_rcv_clk_o, - output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, - input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o, +`ifdef FESVR_DTM // DMI output dm::dmi_req_t dmi_req, output logic dmi_req_valid, input logic dmi_req_ready, input dm::dmi_resp_t dmi_resp, output logic dmi_resp_ready, - input logic dmi_resp_valid + input logic dmi_resp_valid, +`endif + // Serial link interface + output logic [SlinkNumChan-1:0] slink_rcv_clk_i, + input logic [SlinkNumChan-1:0] slink_rcv_clk_o, + output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i, + input logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o ); `include "cheshire/typedef.svh" @@ -95,6 +97,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( import "DPI-C" function byte get_entry(output longint entry); import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); +`ifdef FESVR_DTM import "DPI-C" function int debug_tick ( output bit debug_req_valid, @@ -108,6 +111,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( input int debug_resp_bits_resp, input int debug_resp_bits_data ); +`endif //////////// // DRAM // @@ -978,6 +982,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( #(ClkPeriodSys * 200000 * 2); // wait 2s, pk should be booted (take around 1.5s). endtask +`ifdef FESVR_DTM ////////////// // SimDTM // ////////////// @@ -1000,6 +1005,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .debug_resp_bits_data ( dmi_resp.data ), .exit ( sim_exit ) ); +`endif endmodule From 292c2e105696222f2f7d7735608b36229e55c93c Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 9 Jul 2025 16:17:22 +0200 Subject: [PATCH 04/26] wait_boot_pk: Add comment for it use case --- target/sim/src/tb_cheshire_soc.sv | 9 +++------ target/sim/src/vip_cheshire_soc.sv | 5 ++++- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index 9a9c61cb7..732a36670 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -37,9 +37,8 @@ module tb_cheshire_soc #( // Wait for reset fix.vip.wait_for_reset(); -// if using fesvr, the preloading is handled by fesvr dtn +// if using fesvr, the preloading is handled by fesvr dtm `ifndef FESVR_DTM - // Preload in idle mode or wait for completion in autonomous boot if (boot_mode == 0) begin // Idle boot: preload with the specified mode @@ -51,7 +50,7 @@ module tb_cheshire_soc #( end 1: begin // Serial Link fix.vip.slink_elf_run(preload_elf); fix.vip.slink_wait_for_eoc(exit_code); - fix.vip.wait_boot_pk(); + //fix.vip.wait_boot_pk(); end 2: begin // UART fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end default: begin @@ -70,8 +69,6 @@ module tb_cheshire_soc #( wait (fix.vip.uart_reading_byte == 0); $finish; -`endif - end - +`endif endmodule diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 56343acec..e148607fa 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -978,7 +978,10 @@ module vip_cheshire_soc import cheshire_pkg::*; #( if (exit_code) $error("[SLINK] FAILED: return code %0d", exit_code); else $display("[SLINK] SUCCESS"); endtask - task automatic wait_boot_pk(); + + // when running pk, there is not eoc, so it will never ends, + //that why you should us this function instead of slink_wait_for_eoc + task automatic wait_boot_pk(); #(ClkPeriodSys * 200000 * 2); // wait 2s, pk should be booted (take around 1.5s). endtask From 006161aaa78d37c264293e39260fee09930d7782 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Fri, 11 Jul 2025 13:09:24 +0200 Subject: [PATCH 05/26] SimDTM : Add a logic to start it --- target/sim/src/tb_cheshire_soc.sv | 38 +++++++++++++++++++++++++++--- target/sim/src/vip_cheshire_soc.sv | 25 ++++++++++---------- 2 files changed, 48 insertions(+), 15 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index 732a36670..b5d536a43 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -29,6 +29,11 @@ module tb_cheshire_soc #( if (!$value$plusargs("BINARY=%s", preload_elf)) preload_elf = ""; if (!$value$plusargs("IMAGE=%s", boot_hex)) boot_hex = ""; +`ifdef FESVR_DTM + // locking SimDTM + assign fix.vip.start_SimDTM = 1'b0; +`endif + // Set boot mode and preload boot image if there is one fix.vip.set_boot_mode(boot_mode); fix.vip.i2c_eeprom_preload(boot_hex); @@ -37,9 +42,36 @@ module tb_cheshire_soc #( // Wait for reset fix.vip.wait_for_reset(); -// if using fesvr, the preloading is handled by fesvr dtm -`ifndef FESVR_DTM - // Preload in idle mode or wait for completion in autonomous boot +`ifdef FESVR_DTM + if (boot_mode == 0) begin + // Idle boot: preload with the specified mode + case (preload_mode) + // JTAG : jtag_dmi not connected when using fesvr + 1: begin // Serial Link + fix.vip.wait_boot_pk(); // tmp : to check that it works + assign fix.vip.start_SimDTM = 1'b1; + end 2: begin // UART + fix.vip.wait_boot_pk(); // tmp : to check that it works + assign fix.vip.start_SimDTM = 1'b1; + end default: begin + $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); + end + endcase + end else if (boot_mode == 1) begin + $fatal(1, "Unsupported boot mode %d (SD Card)!", boot_mode); + end else begin + // Autonomous boot: Only poll return code + fix.vip.jtag_init(); + fix.vip.jtag_wait_for_eoc(exit_code); + end + + // Wait for the UART to finish reading the current byte + wait (fix.vip.uart_reading_byte == 0); + + // finish will end the simulation but it's still running.. + //$finish; + end +`else if (boot_mode == 0) begin // Idle boot: preload with the specified mode case (preload_mode) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index e148607fa..229fa36ff 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -990,23 +990,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // SimDTM // ////////////// + logic start_SimDTM; // wired up in the testbench logic [31:0] sim_exit; // TODO: wire this up in the testbench logic [1:0] dmi_req_bits_op; assign dmi_req.op = dm::dtm_op_e'(dmi_req_bits_op); // need to check if it's this variable, SimDTM i_SimDTM ( - .clk ( clk ), - .reset ( rst_n ), - .debug_req_valid ( dmi_req_valid ), - .debug_req_ready ( dmi_req_ready ), - .debug_req_bits_addr ( dmi_req.addr ), - .debug_req_bits_op ( dmi_req_bits_op ), - .debug_req_bits_data ( dmi_req.data ), - .debug_resp_valid ( dmi_resp_valid ), - .debug_resp_ready ( dmi_resp_ready ), - .debug_resp_bits_resp ( dmi_resp.resp ), - .debug_resp_bits_data ( dmi_resp.data ), - .exit ( sim_exit ) + .clk ( clk ), + .reset ( rst_n & start_SimDTM ), + .debug_req_valid ( dmi_req_valid ), + .debug_req_ready ( dmi_req_ready ), + .debug_req_bits_addr ( dmi_req.addr ), + .debug_req_bits_op ( dmi_req_bits_op ), + .debug_req_bits_data ( dmi_req.data ), + .debug_resp_valid ( dmi_resp_valid ), + .debug_resp_ready ( dmi_resp_ready ), + .debug_resp_bits_resp ( dmi_resp.resp ), + .debug_resp_bits_data ( dmi_resp.data ), + .exit ( sim_exit ) ); `endif From 2fddf4b3c13c518920b664de07125b9addc85a6a Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Fri, 11 Jul 2025 15:18:35 +0200 Subject: [PATCH 06/26] target/sim: Preload of pk done with slink then fesvr dtm take the lead --- target/sim/src/elfloader.cpp | 10 ++++++++-- target/sim/src/tb_cheshire_soc.sv | 7 ++----- target/sim/src/vip_cheshire_soc.sv | 18 ++++++++++++++++++ 3 files changed, 28 insertions(+), 7 deletions(-) diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp index f03538e66..aa31a4693 100644 --- a/target/sim/src/elfloader.cpp +++ b/target/sim/src/elfloader.cpp @@ -411,7 +411,13 @@ extern "C" char read_elf(const char *filename) { } #endif -dtm_t* dtm; +class preload_aware_dtm_t : public dtm_t { + public: + preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {} + bool is_address_preloaded(addr_t taddr, size_t len) override { return true; } +}; + +preload_aware_dtm_t* dtm; /*------------------------ From SimDTM.cc ------------------------*/ @@ -437,7 +443,7 @@ extern "C" int debug_tick htif_argv[1] = (char*)"/scratch/ga25f6/cheshire/sw/apps/pk_dram"; htif_argv[2] = (char*)"/scratch/ga25f6/cheshire/sw/apps/helloworld.o"; - dtm = new dtm_t(htif_argc, htif_argv); + dtm = new preload_aware_dtm_t(htif_argc, htif_argv); } diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index b5d536a43..f26abd272 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -46,12 +46,9 @@ module tb_cheshire_soc #( if (boot_mode == 0) begin // Idle boot: preload with the specified mode case (preload_mode) - // JTAG : jtag_dmi not connected when using fesvr + // Preload done only using slink in this case cause it's the fastest way available 1: begin // Serial Link - fix.vip.wait_boot_pk(); // tmp : to check that it works - assign fix.vip.start_SimDTM = 1'b1; - end 2: begin // UART - fix.vip.wait_boot_pk(); // tmp : to check that it works + fix.vip.slink_elf_prerun(preload_elf); assign fix.vip.start_SimDTM = 1'b1; end default: begin $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 229fa36ff..6a0246a77 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -971,6 +971,24 @@ module vip_cheshire_soc import cheshire_pkg::*; #( $display("[SLINK] Wrote launch signal and entry point 0x%h", entry); endtask + // Preload a binary without running it -> prerun ? + task automatic slink_elf_prerun(input string binary); + doub_bt entry; + // Wait for bootrom to ungate Serial Link + if (DutCfg.LlcNotBypass) begin + word_bt regval; + $display("[SLINK] Wait for LLC configuration"); + slink_poll_bit0(AmLlc + axi_llc_reg_pkg::AXI_LLC_CFG_SPM_LOW_OFFSET, regval, 20); + end + // Preload + slink_elf_preload(binary, entry); + // Write entry point + slink_write_32(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_1_OFFSET, entry[63:32]); + slink_write_32(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_0_OFFSET, entry[32:0]); + // Not resuming hart 0, handled by fesvr's dtm + $display("[SLINK] Wrote entry point 0x%h", entry); + endtask + // Wait for termination signal and get return code task automatic slink_wait_for_eoc(output word_bt exit_code); slink_poll_bit0(AmRegs + cheshire_reg_pkg::CHESHIRE_SCRATCH_2_OFFSET, exit_code, 800); From 7936028d0878521be7d3fcc19abea2c0ae7667d1 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 16 Jul 2025 16:24:06 +0200 Subject: [PATCH 07/26] target/sim: Handling end of simulation with fesvr --- target/sim/src/tb_cheshire_soc.sv | 22 ++++------------------ target/sim/src/vip_cheshire_soc.sv | 8 ++++++++ 2 files changed, 12 insertions(+), 18 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index f26abd272..b212e8e90 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -42,34 +42,20 @@ module tb_cheshire_soc #( // Wait for reset fix.vip.wait_for_reset(); -`ifdef FESVR_DTM if (boot_mode == 0) begin - // Idle boot: preload with the specified mode +`ifdef FESVR_DTM + // Idle boot: preload with the specified mode, only slink when fesvr case (preload_mode) // Preload done only using slink in this case cause it's the fastest way available 1: begin // Serial Link fix.vip.slink_elf_prerun(preload_elf); assign fix.vip.start_SimDTM = 1'b1; + fix.vip.fesvr_wait_for_exit(exit_code); end default: begin $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); end endcase - end else if (boot_mode == 1) begin - $fatal(1, "Unsupported boot mode %d (SD Card)!", boot_mode); - end else begin - // Autonomous boot: Only poll return code - fix.vip.jtag_init(); - fix.vip.jtag_wait_for_eoc(exit_code); - end - - // Wait for the UART to finish reading the current byte - wait (fix.vip.uart_reading_byte == 0); - - // finish will end the simulation but it's still running.. - //$finish; - end `else - if (boot_mode == 0) begin // Idle boot: preload with the specified mode case (preload_mode) 0: begin // JTAG @@ -86,6 +72,7 @@ module tb_cheshire_soc #( $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); end endcase +`endif end else if (boot_mode == 1) begin $fatal(1, "Unsupported boot mode %d (SD Card)!", boot_mode); end else begin @@ -99,5 +86,4 @@ module tb_cheshire_soc #( $finish; end -`endif endmodule diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 6a0246a77..1237c5528 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -1027,6 +1027,14 @@ module vip_cheshire_soc import cheshire_pkg::*; #( .debug_resp_bits_data ( dmi_resp.data ), .exit ( sim_exit ) ); + + task automatic fesvr_wait_for_exit(output word_bt exit_code); + while (~sim_exit[0]) begin + #(ClkPeriodSys * 100); + end + if (sim_exit == 1) $error("[FESVR] SUCCESS"); + else $display("[FESVR] FAILED: return code %0d", sim_exit); + endtask `endif endmodule From 8f2b8610ae59b82edc8f0005386af0983f330eeb Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Thu, 24 Jul 2025 17:01:50 +0200 Subject: [PATCH 08/26] target/sim : using chandle to use a dtm class --- target/sim/src/SimDTM.sv | 83 ------------------------ target/sim/src/elfloader.cpp | 48 ++++++++------ target/sim/src/tb_cheshire_soc.sv | 5 +- target/sim/src/vip_cheshire_soc.sv | 101 +++++++++++++++++++++-------- 4 files changed, 105 insertions(+), 132 deletions(-) delete mode 100644 target/sim/src/SimDTM.sv diff --git a/target/sim/src/SimDTM.sv b/target/sim/src/SimDTM.sv deleted file mode 100644 index 445599ab0..000000000 --- a/target/sim/src/SimDTM.sv +++ /dev/null @@ -1,83 +0,0 @@ -// See LICENSE.SiFive for license details. -//VCS coverage exclude_file - -import "DPI-C" function int debug_tick -( - output bit debug_req_valid, - input bit debug_req_ready, - output int debug_req_bits_addr, - output int debug_req_bits_op, - output int debug_req_bits_data, - - input bit debug_resp_valid, - output bit debug_resp_ready, - input int debug_resp_bits_resp, - input int debug_resp_bits_data -); - -module SimDTM( - input clk, - input reset, - - output debug_req_valid, - input debug_req_ready, - output [ 6:0] debug_req_bits_addr, - output [ 1:0] debug_req_bits_op, - output [31:0] debug_req_bits_data, - - input debug_resp_valid, - output debug_resp_ready, - input [ 1:0] debug_resp_bits_resp, - input [31:0] debug_resp_bits_data, - - output [31:0] exit -); - - //bit r_reset; - - wire #0.1 __debug_req_ready = debug_req_ready; - wire #0.1 __debug_resp_valid = debug_resp_valid; - wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, debug_resp_bits_resp}; - wire [31:0] #0.1 __debug_resp_bits_data = debug_resp_bits_data; - - bit __debug_req_valid; - int __debug_req_bits_addr; - int __debug_req_bits_op; - int __debug_req_bits_data; - bit __debug_resp_ready; - int __exit; - - assign #0.1 debug_req_valid = __debug_req_valid; - assign #0.1 debug_req_bits_addr = __debug_req_bits_addr[6:0]; - assign #0.1 debug_req_bits_op = __debug_req_bits_op[1:0]; - assign #0.1 debug_req_bits_data = __debug_req_bits_data[31:0]; - assign #0.1 debug_resp_ready = __debug_resp_ready; - assign #0.1 exit = __exit; - - always @(posedge clk) - begin - /* reset condition was not working... - r_reset <= reset; - if (reset || r_reset) */ - if(!reset) - begin - __debug_req_valid = 0; - __debug_resp_ready = 0; - __exit = 0; - end - else - begin - __exit = debug_tick( - __debug_req_valid, - __debug_req_ready, - __debug_req_bits_addr, - __debug_req_bits_op, - __debug_req_bits_data, - __debug_resp_valid, - __debug_resp_ready, - __debug_resp_bits_resp, - __debug_resp_bits_data - ); - end - end -endmodule diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp index aa31a4693..c1fe32d9c 100644 --- a/target/sim/src/elfloader.cpp +++ b/target/sim/src/elfloader.cpp @@ -157,12 +157,21 @@ std::map> mems; uint64_t entry = 0; int section_index = 0; +// custom class for dtm +class preload_aware_dtm_t : public dtm_t { + public: + preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {} + bool is_address_preloaded(addr_t taddr, size_t len) override { return true; } +}; + extern "C" { char get_entry(long long *entry_ret); char get_section(long long *address_ret, long long *len_ret); char read_section(long long address, const svOpenArrayHandle buffer, long long len); char read_elf(const char *filename); + void* debug_new(char *pk_path, char *app_path); int debug_tick( + preload_aware_dtm_t* dtm, unsigned char* debug_req_valid, unsigned char debug_req_ready, int* debug_req_bits_addr, @@ -172,6 +181,7 @@ extern "C" { unsigned char* debug_resp_ready, int debug_resp_bits_resp, int debug_resp_bits_data); + int read_csr_dtm(); } static void write (uint64_t address, uint64_t len, uint8_t *buf) @@ -411,18 +421,29 @@ extern "C" char read_elf(const char *filename) { } #endif -class preload_aware_dtm_t : public dtm_t { - public: - preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {} - bool is_address_preloaded(addr_t taddr, size_t len) override { return true; } -}; -preload_aware_dtm_t* dtm; + /*------------------------ -From SimDTM.cc +Inspired by SimDTM.cc ------------------------*/ + +extern "C" void* debug_new(char *pk_path, char *app_path) { + int htif_argc = 3; + char* htif_argv[htif_argc]; + htif_argv[0] = (char*)"htif"; + htif_argv[1] = pk_path; + htif_argv[2] = app_path; + + preload_aware_dtm_t *dtm = (preload_aware_dtm_t *) malloc(sizeof(preload_aware_dtm_t)); + dtm = new preload_aware_dtm_t(htif_argc, htif_argv); + + return (void *)dtm; +} + + extern "C" int debug_tick ( + preload_aware_dtm_t* dtm, unsigned char* debug_req_valid, unsigned char debug_req_ready, int* debug_req_bits_addr, @@ -434,19 +455,6 @@ extern "C" int debug_tick int debug_resp_bits_data ) { - if (!dtm) { - //the list of argv are the program that will be runned after pk is booted. - // Need to find a way to make it easier to change programs, maybe like it was done... - int htif_argc = 3; - char* htif_argv[htif_argc]; - htif_argv[0] = (char*)"htif"; - htif_argv[1] = (char*)"/scratch/ga25f6/cheshire/sw/apps/pk_dram"; - htif_argv[2] = (char*)"/scratch/ga25f6/cheshire/sw/apps/helloworld.o"; - - dtm = new preload_aware_dtm_t(htif_argc, htif_argv); - } - - dtm_t::resp resp_bits; resp_bits.resp = debug_resp_bits_resp; resp_bits.data = debug_resp_bits_data; diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index b212e8e90..e3cd89024 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -31,7 +31,7 @@ module tb_cheshire_soc #( `ifdef FESVR_DTM // locking SimDTM - assign fix.vip.start_SimDTM = 1'b0; + fix.vip.fesvr_stop(); `endif // Set boot mode and preload boot image if there is one @@ -49,7 +49,8 @@ module tb_cheshire_soc #( // Preload done only using slink in this case cause it's the fastest way available 1: begin // Serial Link fix.vip.slink_elf_prerun(preload_elf); - assign fix.vip.start_SimDTM = 1'b1; + fix.vip.fesvr_set(preload_elf, "/scratch/ga25f6/cheshire/sw/apps/helloworld.riscv"); + fix.vip.fesvr_start(); fix.vip.fesvr_wait_for_exit(exit_code); end default: begin $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 1237c5528..4b4844de5 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -98,18 +98,21 @@ module vip_cheshire_soc import cheshire_pkg::*; #( import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); `ifdef FESVR_DTM + import "DPI-C" function chandle debug_new(input string pk_path, input string app_path); import "DPI-C" function int debug_tick ( - output bit debug_req_valid, - input bit debug_req_ready, - output int debug_req_bits_addr, - output int debug_req_bits_op, - output int debug_req_bits_data, - - input bit debug_resp_valid, - output bit debug_resp_ready, - input int debug_resp_bits_resp, - input int debug_resp_bits_data + input chandle fesvr_dtm, + + output bit debug_req_valid, + input bit debug_req_ready, + output int debug_req_bits_addr, + output int debug_req_bits_op, + output int debug_req_bits_data, + + input bit debug_resp_valid, + output bit debug_resp_ready, + input int debug_resp_bits_resp, + input int debug_resp_bits_data ); `endif @@ -1008,32 +1011,76 @@ module vip_cheshire_soc import cheshire_pkg::*; #( // SimDTM // ////////////// - logic start_SimDTM; // wired up in the testbench + /*--------------------------------- + Mostly comming from SimDTM.sv +---------------------------------*/ + + chandle fesvr_dtm; + + logic start_SimDTM; // wired up in the testbench logic [31:0] sim_exit; // TODO: wire this up in the testbench logic [1:0] dmi_req_bits_op; assign dmi_req.op = dm::dtm_op_e'(dmi_req_bits_op); // need to check if it's this variable, - SimDTM i_SimDTM ( - .clk ( clk ), - .reset ( rst_n & start_SimDTM ), - .debug_req_valid ( dmi_req_valid ), - .debug_req_ready ( dmi_req_ready ), - .debug_req_bits_addr ( dmi_req.addr ), - .debug_req_bits_op ( dmi_req_bits_op ), - .debug_req_bits_data ( dmi_req.data ), - .debug_resp_valid ( dmi_resp_valid ), - .debug_resp_ready ( dmi_resp_ready ), - .debug_resp_bits_resp ( dmi_resp.resp ), - .debug_resp_bits_data ( dmi_resp.data ), - .exit ( sim_exit ) - ); + wire #0.1 __debug_req_ready = dmi_req_ready; + wire #0.1 __debug_resp_valid = dmi_resp_valid; + wire [31:0] #0.1 __debug_resp_bits_resp = {30'b0, dmi_resp.resp}; + wire [31:0] #0.1 __debug_resp_bits_data = dmi_resp.data; + + bit __debug_req_valid; + int __debug_req_bits_addr; + int __debug_req_bits_op; + int __debug_req_bits_data; + bit __debug_resp_ready; + int __exit; + + assign #0.1 dmi_req_valid = __debug_req_valid; + assign #0.1 dmi_req.addr = __debug_req_bits_addr[6:0]; + assign #0.1 dmi_req_bits_op = __debug_req_bits_op[1:0]; + assign #0.1 dmi_req.data = __debug_req_bits_data[31:0]; + assign #0.1 dmi_resp_ready = __debug_resp_ready; + assign #0.1 sim_exit = __exit; + + always @(posedge clk) + begin + if(!(rst_n & start_SimDTM)) begin + __debug_req_valid = 0; + __debug_resp_ready = 0; + __exit = 0; + end else begin + __exit = debug_tick( + fesvr_dtm, + __debug_req_valid, + __debug_req_ready, + __debug_req_bits_addr, + __debug_req_bits_op, + __debug_req_bits_data, + __debug_resp_valid, + __debug_resp_ready, + __debug_resp_bits_resp, + __debug_resp_bits_data + ); + end + end task automatic fesvr_wait_for_exit(output word_bt exit_code); while (~sim_exit[0]) begin #(ClkPeriodSys * 100); end - if (sim_exit == 1) $error("[FESVR] SUCCESS"); - else $display("[FESVR] FAILED: return code %0d", sim_exit); + if (sim_exit == 1) $display("[FESVR] SUCCESS"); + else $error("[FESVR] FAILED: return code %0d", sim_exit); + endtask + + task automatic fesvr_stop(); + start_SimDTM = 0; + endtask + + task automatic fesvr_start(); + start_SimDTM = 1; + endtask + + task automatic fesvr_set(input string kernel, input string binary); + fesvr_dtm = debug_new(kernel, binary); endtask `endif From 0854d8fb585ce3bbfa86cb32b496f0ea2e82d2a8 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Thu, 24 Jul 2025 17:04:27 +0200 Subject: [PATCH 09/26] bender.yml: removing SimDTM.sv --- Bender.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/Bender.yml b/Bender.yml index eaae185c8..edddb742b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -47,7 +47,6 @@ sources: - target: any(simulation, test) files: - - target/sim/src/SimDTM.sv - target/sim/models/s25fs512s.v - target/sim/models/24FC1025.v - target/sim/src/vip_cheshire_soc.sv From e5a13dedb691e7cab7a0677d5de413e2e2fb633c Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 28 Jul 2025 17:06:18 +0200 Subject: [PATCH 10/26] treewide: cleaner & with dmi_rst --- hw/cheshire_soc.sv | 15 +++++++++------ target/sim/src/elfloader.cpp | 1 - target/sim/src/fixture_cheshire_soc.sv | 2 ++ target/sim/src/vip_cheshire_soc.sv | 10 +++++----- 4 files changed, 16 insertions(+), 12 deletions(-) diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv index af84c3ae2..d1d0b914d 100644 --- a/hw/cheshire_soc.sv +++ b/hw/cheshire_soc.sv @@ -99,13 +99,14 @@ module cheshire_soc import cheshire_pkg::*; #( output logic [Cfg.VgaBlueWidth -1:0] vga_blue_o, `ifdef FESVR_DTM // DMI interface - input dm::dmi_req_t dmi_req_i, - input logic dmi_req_valid_i, - output logic dmi_req_ready_o, + input logic dmi_rst_ni, + input dm::dmi_req_t dmi_req_i, + input logic dmi_req_valid_i, + output logic dmi_req_ready_o, output dm::dmi_resp_t dmi_resp_o, - input logic dmi_resp_ready_i, - output logic dmi_resp_valid_o, + input logic dmi_resp_ready_i, + output logic dmi_resp_valid_o, `endif // USB interface input logic usb_clk_i, @@ -797,7 +798,9 @@ module cheshire_soc import cheshire_pkg::*; #( logic dbg_sba_err; // JTAG DMI to debug module + `ifndef FESVR_DTM logic dbg_dmi_rst_n; + `endif dm::dmi_req_t dbg_dmi_req; logic dbg_dmi_req_ready, dbg_dmi_req_valid; dm::dmi_resp_t dbg_dmi_rsp; @@ -924,7 +927,7 @@ module cheshire_soc import cheshire_pkg::*; #( .master_r_err_i ( dbg_sba_err ), .master_r_other_err_i ( 1'b0 ), `ifdef FESVR_DTM - .dmi_rst_ni ( rst_ni ), // not handled by SimDTM and his done like this in dmi_jtag + .dmi_rst_ni ( dmi_rst_ni ), // not handled by SimDTM and his done like this in dmi_jtag .dmi_req_valid_i ( dmi_req_valid_i ), .dmi_req_ready_o ( dmi_req_ready_o ), .dmi_req_i ( dmi_req_i ), diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp index c1fe32d9c..b955d97d3 100644 --- a/target/sim/src/elfloader.cpp +++ b/target/sim/src/elfloader.cpp @@ -181,7 +181,6 @@ extern "C" { unsigned char* debug_resp_ready, int debug_resp_bits_resp, int debug_resp_bits_data); - int read_csr_dtm(); } static void write (uint64_t address, uint64_t len, uint8_t *buf) diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv index 4dcfd058b..c88b909a1 100644 --- a/target/sim/src/fixture_cheshire_soc.sv +++ b/target/sim/src/fixture_cheshire_soc.sv @@ -65,6 +65,7 @@ module fixture_cheshire_soc #( `ifdef FESVR_DTM //DMI + logic dmi_rst_ni; dm::dmi_req_t dmi_req; logic dmi_req_valid; logic dmi_req_ready; @@ -146,6 +147,7 @@ module fixture_cheshire_soc #( .vga_green_o ( ), .vga_blue_o ( ), `ifdef FESVR_DTM + .dmi_rst_ni ( dmi_rst_ni ), .dmi_req_valid_i ( dmi_req_valid ), .dmi_req_ready_o ( dmi_req_ready ), .dmi_req_i ( dmi_req ), diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 4b4844de5..909e84069 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -70,6 +70,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( inout wire [ 3:0] spih_sd, `ifdef FESVR_DTM // DMI + output logic dmi_rst_ni, output dm::dmi_req_t dmi_req, output logic dmi_req_valid, input logic dmi_req_ready, @@ -1017,7 +1018,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( chandle fesvr_dtm; - logic start_SimDTM; // wired up in the testbench logic [31:0] sim_exit; // TODO: wire this up in the testbench logic [1:0] dmi_req_bits_op; assign dmi_req.op = dm::dtm_op_e'(dmi_req_bits_op); // need to check if it's this variable, @@ -1043,7 +1043,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( always @(posedge clk) begin - if(!(rst_n & start_SimDTM)) begin + if(!(rst_n & dmi_rst_ni)) begin __debug_req_valid = 0; __debug_resp_ready = 0; __exit = 0; @@ -1072,16 +1072,16 @@ module vip_cheshire_soc import cheshire_pkg::*; #( endtask task automatic fesvr_stop(); - start_SimDTM = 0; + dmi_rst_ni = 0; endtask task automatic fesvr_start(); - start_SimDTM = 1; + dmi_rst_ni = 1; endtask task automatic fesvr_set(input string kernel, input string binary); fesvr_dtm = debug_new(kernel, binary); - endtask + endtask `endif endmodule From c8c7e1f94efb110317ab2d731ef28d58945d0b5f Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 28 Jul 2025 17:07:07 +0200 Subject: [PATCH 11/26] target/sim: using BINARY variable for the app instead of pk --- target/sim/src/tb_cheshire_soc.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index e3cd89024..bc24fb7ee 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -48,10 +48,10 @@ module tb_cheshire_soc #( case (preload_mode) // Preload done only using slink in this case cause it's the fastest way available 1: begin // Serial Link - fix.vip.slink_elf_prerun(preload_elf); - fix.vip.fesvr_set(preload_elf, "/scratch/ga25f6/cheshire/sw/apps/helloworld.riscv"); - fix.vip.fesvr_start(); - fix.vip.fesvr_wait_for_exit(exit_code); + fix.vip.slink_elf_prerun("/scratch/ga25f6/pk_dram"); // preload with slink + fix.vip.fesvr_set("/scratch/ga25f6/pk_dram", preload_elf); // creating a dtm class + fix.vip.fesvr_start(); // starting dtm tick + fix.vip.fesvr_wait_for_exit(exit_code); //waiting on exit code to be zero end default: begin $fatal(1, "Unsupported preload mode %d (reserved)!", boot_mode); end From 06a3937834795f23138cb626fdb7e2eeaffde9ce Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 28 Jul 2025 17:33:23 +0200 Subject: [PATCH 12/26] target/sim: Parameter to precise pk path --- target/sim/src/tb_cheshire_soc.sv | 6 ++++-- target/sim/vcs/start.cheshire_soc.sh | 1 + target/sim/vsim/start.cheshire_soc.tcl | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index bc24fb7ee..d984db39e 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -16,6 +16,7 @@ module tb_cheshire_soc #( .UseDramSys (UseDramSys) ) fix(); + string pk_path; string preload_elf; string boot_hex; logic [1:0] boot_mode; @@ -28,6 +29,7 @@ module tb_cheshire_soc #( if (!$value$plusargs("PRELMODE=%d", preload_mode)) preload_mode = 0; if (!$value$plusargs("BINARY=%s", preload_elf)) preload_elf = ""; if (!$value$plusargs("IMAGE=%s", boot_hex)) boot_hex = ""; + if (!$value$plusargs("PK=%s", pk_path)) pk_path = ""; `ifdef FESVR_DTM // locking SimDTM @@ -48,8 +50,8 @@ module tb_cheshire_soc #( case (preload_mode) // Preload done only using slink in this case cause it's the fastest way available 1: begin // Serial Link - fix.vip.slink_elf_prerun("/scratch/ga25f6/pk_dram"); // preload with slink - fix.vip.fesvr_set("/scratch/ga25f6/pk_dram", preload_elf); // creating a dtm class + fix.vip.slink_elf_prerun(pk_path); // preload with slink + fix.vip.fesvr_set(pk_path, preload_elf); // creating a dtm class fix.vip.fesvr_start(); // starting dtm tick fix.vip.fesvr_wait_for_exit(exit_code); //waiting on exit code to be zero end default: begin diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index e8623fb3a..9d7754cc2 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -35,6 +35,7 @@ pargs="" [[ -n "${PRELMODE}" ]] && pargs+="+PRELMODE=${PRELMODE} " [[ -n "${BINARY}" ]] && pargs+="+BINARY=${BINARY} " [[ -n "${IMAGE}" ]] && pargs+="+IMAGE=${IMAGE} " +[[ -n "${PK}" ]] && pargs+="+PK=${PK} " # DRAMSys if [ -n "${USE_DRAMSYS}" ]; then diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index c732b1969..d6c7fc2a1 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -35,6 +35,7 @@ if { [info exists BOOTMODE] } { append pargs "+BOOTMODE=${BOOTMODE} " } if { [info exists PRELMODE] } { append pargs "+PRELMODE=${PRELMODE} " } if { [info exists BINARY] } { append pargs "+BINARY=${BINARY} " } if { [info exists IMAGE] } { append pargs "+IMAGE=${IMAGE} " } +if { [info exists PK] } { append pargs "+PK=${PK} " } # DRAMSys if { [info exists USE_DRAMSYS] } { From 3d50337ed95b448ec53b89262c4f840cc5f5789d Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Thu, 31 Jul 2025 14:04:25 +0200 Subject: [PATCH 13/26] target/sim/src: wait_boot_pk deprecatred --- target/sim/src/tb_cheshire_soc.sv | 1 - target/sim/src/vip_cheshire_soc.sv | 6 ------ 2 files changed, 7 deletions(-) diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index d984db39e..f76fabceb 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -68,7 +68,6 @@ module tb_cheshire_soc #( end 1: begin // Serial Link fix.vip.slink_elf_run(preload_elf); fix.vip.slink_wait_for_eoc(exit_code); - //fix.vip.wait_boot_pk(); end 2: begin // UART fix.vip.uart_debug_elf_run_and_wait(preload_elf, exit_code); end default: begin diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 909e84069..ef7334519 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -1001,12 +1001,6 @@ module vip_cheshire_soc import cheshire_pkg::*; #( else $display("[SLINK] SUCCESS"); endtask - // when running pk, there is not eoc, so it will never ends, - //that why you should us this function instead of slink_wait_for_eoc - task automatic wait_boot_pk(); - #(ClkPeriodSys * 200000 * 2); // wait 2s, pk should be booted (take around 1.5s). - endtask - `ifdef FESVR_DTM ////////////// // SimDTM // From 6efc15950bd22a6e13e5e23b4606a5c88d2365b6 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Thu, 31 Jul 2025 17:17:30 +0200 Subject: [PATCH 14/26] tqrget/sim/src: fix even exitcode that would cause the simulation to never finish --- target/sim/src/vip_cheshire_soc.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index ef7334519..47d5387fe 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -1058,7 +1058,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end task automatic fesvr_wait_for_exit(output word_bt exit_code); - while (~sim_exit[0]) begin + logic [31:0] sim_init = sim_exit; + while (sim_init == sim_exit) begin #(ClkPeriodSys * 100); end if (sim_exit == 1) $display("[FESVR] SUCCESS"); From 31081f10db58b96141d402e55a13e092b9747db6 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 4 Aug 2025 15:19:01 +0200 Subject: [PATCH 15/26] mt_doc: add documentation about new features & changes --- mt_doc/fesvr_support_cheshire.svg | 4 + mt_doc/readme.md | 129 ++++++++++++++++++++++++++++++ 2 files changed, 133 insertions(+) create mode 100644 mt_doc/fesvr_support_cheshire.svg create mode 100644 mt_doc/readme.md diff --git a/mt_doc/fesvr_support_cheshire.svg b/mt_doc/fesvr_support_cheshire.svg new file mode 100644 index 000000000..ca5774e9a --- /dev/null +++ b/mt_doc/fesvr_support_cheshire.svg @@ -0,0 +1,4 @@ + + + +
TB
TB
Fixture
Fixture
VIP
VIP
SoC
SoC
DM
DM
dmi_jtag
dmi_jtag
A
X
I
A...
dmi
dmi
JTAG VIP
JTAG VIP
dmi
dmi
jtag
jtag
SimDTM
SimDTM
dmi
dmi
FESVR
FESVR
DPI
DPI
call tasks
call tasks
wrapper
wrapper
drive clock and I/O
drive clock and I/O
cheshire
cheshireText is not SVG - cannot display \ No newline at end of file diff --git a/mt_doc/readme.md b/mt_doc/readme.md new file mode 100644 index 000000000..b40c57161 --- /dev/null +++ b/mt_doc/readme.md @@ -0,0 +1,129 @@ +# FESVR support on chesire + +# Getting Started + +## Things needed : + - fesvr + - pk + +### RISC-V Frontend Server : fesvr +Install fesvr : `` git clone https://github.com/riscv-software-src/riscv-isa-sim.git`` + +Make sure that **USE_CONTEXT** is not defined in *fesvr/context.h*, the **line 10** can be commented. + +You should also had ``fesvr_install_shared_lib = yes`` in *fesvr/fesvr.mk.in* it will install a shared lib, the static one will not work with sim tools. +Remember the path of the installation, it’s needed to modify **Cheshire.mk** and **target/sim/vXXX/start.cheshire_soc.XXX** and update the path. +``` +mkdir build install +cd build +../configure --prefix=`realpath ../install/` --without-boost-regex +make +make install +``` + +### Cheshire +Nothing change for the installation, 2 new script should be generated, to add fesvr usage when running vsim or vcs, make sure that you have given the right path to libfesvr.so in the previous step ! +Then you can run ``make all`` as usual. + +### RISC-V Proxy kernel : pk +You can git clone pk from my fork, and follow the installation from the readme, don’t forget to use -with_dts=path/to/cheshire.dts when doing the ../configure command. Like this + +``` +mkdir build install +cd build +../configure --prefix=`realpath ../install/` --host=riscv64-unknown-elf --with-dts=`realpath ../../cheshire/sw/boot/cheshire_spm.dts` +make +make install +``` +Keep in mind the path to your pk installation, it will be used in cheshire simulation + + +## Simulation +To run a simulation using fesvr dtm, with questa, do like this in *./target/sim/vsim*: +``` +set PK /path/riscv-pk/install/pk +set BINARY /path/sw/apps/helloworld.riscv +set BOOTMODE 0 +set PRELMODE 1 + +# Compile design WITH fesvr +source compile.cheshire_soc_fesvr.tcl + +# Start and run simulation +source start.cheshire_soc.tcl +run -all +``` +If you want to run an other simulation with a new app, you just have to set **BINARY** with an other value and run again the **start.cheshire_soc** script. + +# How it works +## Strucural change +![Cheshire fesvr supported block diagram](./fesvr_support_cheshire.svg) + +## Behavior of the simulation +There is several steps in the simulation, that can be observed by looking at the wave of dmi signals. + +First, pk is preloaded using serial link, this reduce the simulation time by using the burst mode of serial link to preload pk faster. + +Then, the frontend server (FESVR) take the lead, a dtm object is created, it will resume the core and start the proxy-kernel (pk). + +Once pk is booted, the FESVR will preload the binary using the debug module and runs it. When it's finished, the fesvr return an exitcode, allowing to know if everything went well or not. + + +# Changes done & Explanation +## DPI +2 DPI have been added, they are inspired by the DPI inside of *SimDTM.cc* and an upper class of *dtm_t* have been created. + +**preload_aware_dtm**: this upper class of dtm_t does change the *is_address_preloaded* function (from htif_f), this allow to preload the first binary that will be preloaded by the dtm object, in our case, pk.\ +This makes the simulation faster because when a binary is preloaded by the dtm, it uses dmi signals to communicate with the debug module, and only 64bits of data are transmitted. So it takes 24 instructions to write 64bits of the elf file in the memory of the SoC, as pk is a big program, around 90kB, it can be long to preload it (3-4min in real time when simulating) + +**debug_new**: it return a void* (chandle in sv) and takes 2 paths as arguments.\ +This DPI create a new dtm class, with the pk as a kernel and the binary that will be executed. It will be called by the testbench. + +**debug_tick**: it return an integer and takes a dtm object and dmi signals as arguments\ +This DPI call the *tick* function from dtm, this allow to get the value for the dmi request and 2 handshake signals, depending on dmi response and 2 corresponding handshake signals.\ +Overall this DPI allow to assign values to dmi signals, to ensure a proper communication with the debug module. It will be called in the VIP at every clockcycle. + +### Useful information about dtm +When a dtm class is created, everything take place at the initialisation.\ +An sub-htif object is initialised with the arguments coming from dtm arg. Then a function is called, *start_host_thread*, it will make a context switch and call the *producer_thread* function. That will enable the debugger of Cheshire and call the *run* function from htif.\ +This last function, preload the binary (if needed) and resume the core to run the binary. This function as an internal loop, until the binary as finished running and then return the exitcode. + +## VIP +Inside the VIP, a few changes have been done, the code from SimDTM has been reused with a few changes. +The way that the reset signal is handled as changed because it was not working for me and a *dmi_rst_ni* signal have been added. +A chandle have been added, to comply with the new feature of the DPI. It will be initialised thanks to the *fesvr_set* task. +Tasks have been created to handle the *dmi_rst_ni* signals. + +**Be careful, when running a testbench,** you must set fesvr before starting it, so call the task *fesvr_set* before *fesvr_start*. + +The task *fesvr_wait_for_exit* will loop until sim_exit has changed, so when the binary is finished. +It consider that the program should return 1, to say that everything went fine. In case of a problem, it should print the exitcode. + +The I/O have also been changed to add dmi signals when FESVR_DTM is defined, so when the fesvr compile script is used. + +## SoC +Inside of the SoC, dmi signals have been added as I/O, they do replace the dmi signals coming from the dmi_jtag module, that convert information coming from jtag to the debug module. This means that **when using fesvr, you can not use jtag.**\ +About the *dmi_rst_ni* signal, it is only used to reset a FIFO that contains the dmi signals inside of the debug module. + +## Testbench +Few changes have been done to handle and run fesvr. As you can see, the proxy kernel is preloaded using serial link.\ +Then a chandle for dtm_t is created and it is started by setting the dmi reset to 1, starting to use the dpi, debug_tick at every clock cycle. the task coming from vip will wait for the end and the simulation will finish. + +# Possible upgrade +### Running several app in a single simulation +To do this, changes must be done to the FESVR library. +There is a function in *htif.cc*, called *run*, that loop on a value of the object called **stopped**. This value is set at the initialisation of the object to *false* and when run is finished, it's set to *true*. +There is no other function changing this value. So this is the first modification that would be needed if you want to run a new binary with the same object. +x +Also, inside *dtm.cc*, there is a function called *producer_thread*. It is called at the end of the initialisation of the dtm class and used to connect the fesvr to the debug module and to run the program (with *htif_t::run*). The thing is that at the end, there is a loop with only nop, so this function never really finish. The end of the simulation is endled by the testbench thanks to the exitcode comming from *htif_t::run*. + +An other solution, would be to use the chandle feature, but there is no clean way to close the connection between the debug module and dtm, a proper destructor might be needed... +It would have to make sure that everything is finished and get back to running pk, that will poll htif registers. +This could allow to create a 1st dtm class, with pk and binary 1, then run it and destruct it properly, than you could create a 2nd dtm class, with + +# Others +The fesvr implementation inside of the CVA6 is a bit old and has not been update or evolved. It was inspired by the work done in Chipyard Framework. Inside this framework repository, we can find updated documentations with useful information that can come in hand to understand how it works and also to add features (TSI support or GDB - OpenOCD - JTAG support). + +[Chipyard - Boot process](https://chipyard.readthedocs.io/en/latest/Customization/Boot-Process.html#) + +[Chipyard - Chip communication](https://chipyard.readthedocs.io/en/latest/Advanced-Concepts/Chip-Communication.html) \ No newline at end of file From f8322a6965408457b045a945d3d7790c370a65c4 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Tue, 5 Aug 2025 11:40:06 +0200 Subject: [PATCH 16/26] target/sim/src: add support to run elf without pk --- target/sim/src/elfloader.cpp | 17 +++++++++++++++-- target/sim/src/tb_cheshire_soc.sv | 16 +++++++++++++--- target/sim/src/vip_cheshire_soc.sv | 13 +++++++++---- 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp index b955d97d3..a1353ed3c 100644 --- a/target/sim/src/elfloader.cpp +++ b/target/sim/src/elfloader.cpp @@ -169,7 +169,8 @@ extern "C" { char get_section(long long *address_ret, long long *len_ret); char read_section(long long address, const svOpenArrayHandle buffer, long long len); char read_elf(const char *filename); - void* debug_new(char *pk_path, char *app_path); + void* debug_new_pk(char *pk_path, char *app_path); + void* debug_new(char *app_path); int debug_tick( preload_aware_dtm_t* dtm, unsigned char* debug_req_valid, @@ -426,7 +427,7 @@ extern "C" char read_elf(const char *filename) { Inspired by SimDTM.cc ------------------------*/ -extern "C" void* debug_new(char *pk_path, char *app_path) { +extern "C" void* debug_new_pk(char *pk_path, char *app_path) { int htif_argc = 3; char* htif_argv[htif_argc]; htif_argv[0] = (char*)"htif"; @@ -439,6 +440,18 @@ extern "C" void* debug_new(char *pk_path, char *app_path) { return (void *)dtm; } +extern "C" void* debug_new(char *app_path) { + int htif_argc = 2; + char* htif_argv[htif_argc]; + htif_argv[0] = (char*)"htif"; + htif_argv[1] = app_path; + + preload_aware_dtm_t *dtm = (preload_aware_dtm_t *) malloc(sizeof(preload_aware_dtm_t)); + dtm = new preload_aware_dtm_t(htif_argc, htif_argv); + + return (void *)dtm; +} + extern "C" int debug_tick ( diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv index f76fabceb..fb849d46d 100644 --- a/target/sim/src/tb_cheshire_soc.sv +++ b/target/sim/src/tb_cheshire_soc.sv @@ -22,6 +22,7 @@ module tb_cheshire_soc #( logic [1:0] boot_mode; logic [1:0] preload_mode; bit [31:0] exit_code; + logic using_pk; initial begin // Fetch plusargs or use safe (fail-fast) defaults @@ -29,7 +30,10 @@ module tb_cheshire_soc #( if (!$value$plusargs("PRELMODE=%d", preload_mode)) preload_mode = 0; if (!$value$plusargs("BINARY=%s", preload_elf)) preload_elf = ""; if (!$value$plusargs("IMAGE=%s", boot_hex)) boot_hex = ""; - if (!$value$plusargs("PK=%s", pk_path)) pk_path = ""; + if (!$value$plusargs("PK=%s", pk_path)) begin + pk_path = ""; + using_pk = 0; + end else using_pk = 1; `ifdef FESVR_DTM // locking SimDTM @@ -49,9 +53,15 @@ module tb_cheshire_soc #( // Idle boot: preload with the specified mode, only slink when fesvr case (preload_mode) // Preload done only using slink in this case cause it's the fastest way available + // !! fesvr_set before fesvr_start !! 1: begin // Serial Link - fix.vip.slink_elf_prerun(pk_path); // preload with slink - fix.vip.fesvr_set(pk_path, preload_elf); // creating a dtm class + if (using_pk) begin + fix.vip.slink_elf_prerun(pk_path); // preload with slink + fix.vip.fesvr_set_pk(pk_path, preload_elf); // creating a dtm class + end else begin + fix.vip.slink_elf_prerun(preload_elf); // preload with slink + fix.vip.fesvr_set(preload_elf); // creating a dtm class + end fix.vip.fesvr_start(); // starting dtm tick fix.vip.fesvr_wait_for_exit(exit_code); //waiting on exit code to be zero end default: begin diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 47d5387fe..658317d75 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -99,7 +99,8 @@ module vip_cheshire_soc import cheshire_pkg::*; #( import "DPI-C" function byte get_section(output longint address, output longint len); import "DPI-C" context function byte read_section(input longint address, inout byte buffer[], input longint len); `ifdef FESVR_DTM - import "DPI-C" function chandle debug_new(input string pk_path, input string app_path); + import "DPI-C" function chandle debug_new_pk(input string pk_path, input string app_path); + import "DPI-C" function chandle debug_new(input string app_path); import "DPI-C" function int debug_tick ( input chandle fesvr_dtm, @@ -1062,7 +1063,7 @@ module vip_cheshire_soc import cheshire_pkg::*; #( while (sim_init == sim_exit) begin #(ClkPeriodSys * 100); end - if (sim_exit == 1) $display("[FESVR] SUCCESS"); + if (sim_exit == 1) $display("[FESVR] SUCCESS : code %0d", sim_exit); else $error("[FESVR] FAILED: return code %0d", sim_exit); endtask @@ -1074,8 +1075,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #( dmi_rst_ni = 1; endtask - task automatic fesvr_set(input string kernel, input string binary); - fesvr_dtm = debug_new(kernel, binary); + task automatic fesvr_set(input string binary); + fesvr_dtm = debug_new(binary); + endtask + + task automatic fesvr_set_pk(input string kernel, input string binary); + fesvr_dtm = debug_new_pk(kernel, binary); endtask `endif From b49daf8ad6f999b39a81449e9c244c6fabb58a48 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Tue, 5 Aug 2025 12:02:19 +0200 Subject: [PATCH 17/26] target/sim/src: proprely handling exitcode --- target/sim/src/vip_cheshire_soc.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/sim/src/vip_cheshire_soc.sv b/target/sim/src/vip_cheshire_soc.sv index 658317d75..70c3aef8a 100644 --- a/target/sim/src/vip_cheshire_soc.sv +++ b/target/sim/src/vip_cheshire_soc.sv @@ -1059,12 +1059,12 @@ module vip_cheshire_soc import cheshire_pkg::*; #( end task automatic fesvr_wait_for_exit(output word_bt exit_code); - logic [31:0] sim_init = sim_exit; - while (sim_init == sim_exit) begin + while (!sim_exit[0]) begin #(ClkPeriodSys * 100); end - if (sim_exit == 1) $display("[FESVR] SUCCESS : code %0d", sim_exit); - else $error("[FESVR] FAILED: return code %0d", sim_exit); + exit_code = sim_exit >> 1; + if (exit_code == 0) $display("[FESVR] SUCCESS"); + else $error("[FESVR] FAILED: return code %0d", exit_code); endtask task automatic fesvr_stop(); From 85764e94f0a4dba45c72aef3ecbdeda027d291da Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 6 Aug 2025 10:57:57 +0200 Subject: [PATCH 18/26] sw/deps: add riscv-pk and riscv-isa-sim for fesvr --- .gitmodules | 8 ++++++++ sw/deps/riscv-isa-sim | 1 + sw/deps/riscv-pk | 1 + 3 files changed, 10 insertions(+) create mode 160000 sw/deps/riscv-isa-sim create mode 160000 sw/deps/riscv-pk diff --git a/.gitmodules b/.gitmodules index 620a456ac..78504bf8a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -6,3 +6,11 @@ path = sw/deps/cva6-sdk url = https://github.com/pulp-platform/cva6-sdk.git ignore = dirty +[submodule "sw/deps/riscv-isa-sim"] + path = sw/deps/riscv-isa-sim + url = https://github.com/riscv-software-src/riscv-isa-sim + ignore = dirty +[submodule "sw/deps/riscv-pk"] + path = sw/deps/riscv-pk + url = https://github.com/riscv-software-src/riscv-pk.git + ignore = dirty diff --git a/sw/deps/riscv-isa-sim b/sw/deps/riscv-isa-sim new file mode 160000 index 000000000..d4568f669 --- /dev/null +++ b/sw/deps/riscv-isa-sim @@ -0,0 +1 @@ +Subproject commit d4568f6693c9e38a48264c4453a5de7f8b3d38a3 diff --git a/sw/deps/riscv-pk b/sw/deps/riscv-pk new file mode 160000 index 000000000..b4abf92e9 --- /dev/null +++ b/sw/deps/riscv-pk @@ -0,0 +1 @@ +Subproject commit b4abf92e9954aaed291d0282c580f94254f9b11c From 19c4d27cdda55680bef0c0ed4f1a9292a7612a32 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 6 Aug 2025 12:10:30 +0200 Subject: [PATCH 19/26] treewide: Update fesvr path to sw/deps --- cheshire.mk | 4 ++-- target/sim/vcs/start.cheshire_soc.sh | 2 +- target/sim/vsim/start.cheshire_soc.tcl | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/cheshire.mk b/cheshire.mk index 055d292aa..244c8c1a6 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -149,11 +149,11 @@ CHS_BOOTROM_ALL += $(CHS_ROOT)/hw/bootrom/cheshire_bootrom.sv $(CHS_ROOT)/hw/boo $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS)" > $@ - echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ + echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I$(realpath $(CHS_ROOT))/sw/deps/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc_fesvr.tcl: $(CHS_ROOT)/Bender.yml $(BENDER) script vsim -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOG_ARGS) +define+FESVR_DTM" > $@ - echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ + echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++17 -I$(realpath $(CHS_ROOT))/sw/deps/riscv-isa-sim/install/include" -cpppath "$(CXX_PATH)"' >> $@ $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh: $(CHS_ROOT)/Bender.yml $(BENDER) script vcs -t sim -t test $(CHS_BENDER_RTL_FLAGS) --vlog-arg="$(VLOGAN_ARGS)" --vlogan-bin="$(VLOGAN)" > $@ diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 9d7754cc2..00c708738 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -51,7 +51,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I/scratch/ga25f6/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=/scratch/ga25f6/riscv-isa-sim/install/lib -L/scratch/ga25f6/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../sw/deps/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=../../../sw/deps/riscv-isa-sim/install/lib -L../../../sw/deps/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl index d6c7fc2a1..8fca15ed6 100644 --- a/target/sim/vsim/start.cheshire_soc.tcl +++ b/target/sim/vsim/start.cheshire_soc.tcl @@ -50,7 +50,7 @@ if { [info exists USE_DRAMSYS] } { } # Need to link fesvr library -append flags "-gblso /scratch/ga25f6/riscv-isa-sim/install/lib/libfesvr.so" +append flags "-gblso ../../../sw/deps/riscv-isa-sim/install/lib/libfesvr.so" # tclint-disable-next-line command-args eval "vsim -c ${TESTBENCH} -t 1ps -vopt -voptargs=\"${VOPTARGS}\"" ${pargs} ${flags} From adaecb121908ee13fcff78a8ef3865b2a7ca889f Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 11 Aug 2025 11:44:40 +0200 Subject: [PATCH 20/26] mt_doc: more details, information and how to run with/without pk --- mt_doc/readme.md | 90 ++++++++++++++++++++++++++++++++---------------- 1 file changed, 61 insertions(+), 29 deletions(-) diff --git a/mt_doc/readme.md b/mt_doc/readme.md index b40c57161..e7bdb6fa9 100644 --- a/mt_doc/readme.md +++ b/mt_doc/readme.md @@ -6,42 +6,39 @@ - fesvr - pk -### RISC-V Frontend Server : fesvr -Install fesvr : `` git clone https://github.com/riscv-software-src/riscv-isa-sim.git`` +They are inside *sw/deps*, you will just need to run ``git submodule update --init --recursive`` to download them. -Make sure that **USE_CONTEXT** is not defined in *fesvr/context.h*, the **line 10** can be commented. +### RISC-V Frontend Server : fesvr +To build the fesvr, you can run make build-fesvr from cheshire directory.\ +It will create a shared library, that will be used by simulation tools and DPI. -You should also had ``fesvr_install_shared_lib = yes`` in *fesvr/fesvr.mk.in* it will install a shared lib, the static one will not work with sim tools. -Remember the path of the installation, it’s needed to modify **Cheshire.mk** and **target/sim/vXXX/start.cheshire_soc.XXX** and update the path. -``` -mkdir build install -cd build -../configure --prefix=`realpath ../install/` --without-boost-regex -make -make install -``` +Make sure that fesvr is correctly build, you should see in *sw/deps*, the lib in *riscv-isa-sim/install/lib* and 3 directories in *riscv-isa-sim/install/include* ### Cheshire -Nothing change for the installation, 2 new script should be generated, to add fesvr usage when running vsim or vcs, make sure that you have given the right path to libfesvr.so in the previous step ! +Nothing change for the installation, 2 new script should be generated, to add fesvr support when running vsim or vcs. Then you can run ``make all`` as usual. -### RISC-V Proxy kernel : pk -You can git clone pk from my fork, and follow the installation from the readme, don’t forget to use -with_dts=path/to/cheshire.dts when doing the ../configure command. Like this - +### RISC-V Proxy kernel : pk +To build pk, you can do as following : ``` mkdir build install cd build -../configure --prefix=`realpath ../install/` --host=riscv64-unknown-elf --with-dts=`realpath ../../cheshire/sw/boot/cheshire_spm.dts` +../configure --prefix=`realpath ../install/` --host=riscv64-unknown-elf --with-dts=`realpath ../../cheshire/sw/boot/cheshire.dtsi` make make install ``` -Keep in mind the path to your pk installation, it will be used in cheshire simulation +Keep in mind the path to your pk installation, it might be used in cheshire simulation ## Simulation -To run a simulation using fesvr dtm, with questa, do like this in *./target/sim/vsim*: +To run a simulation using fesvr dtm, with questa, you have two choice, to run it with pk or not. \ +The proxy kernel (pk) does bring syscall support and more, allowing to run program with standard lib and I/O, like *printf* for example.\ +Going without pk can be useful if you want to run binary from **riscv-tests**, such as benchmarks or isa tests, are they are made to easily run bare-metal with fesvr.\ +The choice of using comes to setting **PK** or not, when setting the parameter for the simulation in your tool. + +Here is an example of running a binary over pk: ``` -set PK /path/riscv-pk/install/pk +set PK /path/sw/deps/riscv-pk/install/pk set BINARY /path/sw/apps/helloworld.riscv set BOOTMODE 0 set PRELMODE 1 @@ -55,49 +52,71 @@ run -all ``` If you want to run an other simulation with a new app, you just have to set **BINARY** with an other value and run again the **start.cheshire_soc** script. +Giving the right compilation script, will make cheshire RTL compiled with fesvr support, you should run the one with **_fesvr** at the end, like in the example. + # How it works -## Strucural change -![Cheshire fesvr supported block diagram](./fesvr_support_cheshire.svg) ## Behavior of the simulation There is several steps in the simulation, that can be observed by looking at the wave of dmi signals. +### If using the proxy-kernel First, pk is preloaded using serial link, this reduce the simulation time by using the burst mode of serial link to preload pk faster. Then, the frontend server (FESVR) take the lead, a dtm object is created, it will resume the core and start the proxy-kernel (pk). Once pk is booted, the FESVR will preload the binary using the debug module and runs it. When it's finished, the fesvr return an exitcode, allowing to know if everything went well or not. +The exitcode is handled by the testbench, to finish the simulation. + +### Without the proxy-kernel +First, the binary is preloaded using serial link, like when using pk, to make the simulatio faster. + +Then, the frontend server (FESVR) take the lead, a dtm object is created, it will resume the core and start the binary. When it's finished, the fesvr return an exitcode, allowing to know if everything went well or not. + +The exitcode is handled by the testbench, to finish the simulation. + +## Strucural change +![Cheshire fesvr supported block diagram](./fesvr_support_cheshire.svg) + +All the changes happens when compiled with the FESVR parameter.\ +I/O have been added for the dmi signals, to connect the front-end server with the debug module of Cheshire.\ +The architecture of SimDTM as been taken and his now directly in the VIP. Which will take care of calling the DPI to communicate. # Changes done & Explanation ## DPI -2 DPI have been added, they are inspired by the DPI inside of *SimDTM.cc* and an upper class of *dtm_t* have been created. +3 DPI have been added, they are inspired by the DPI inside of *SimDTM.cc* and an upper class of *dtm_t* have been created. **preload_aware_dtm**: this upper class of dtm_t does change the *is_address_preloaded* function (from htif_f), this allow to preload the first binary that will be preloaded by the dtm object, in our case, pk.\ This makes the simulation faster because when a binary is preloaded by the dtm, it uses dmi signals to communicate with the debug module, and only 64bits of data are transmitted. So it takes 24 instructions to write 64bits of the elf file in the memory of the SoC, as pk is a big program, around 90kB, it can be long to preload it (3-4min in real time when simulating) -**debug_new**: it return a void* (chandle in sv) and takes 2 paths as arguments.\ +**debug_new_pk**: it return a void* (chandle in sv) and takes 2 paths as arguments.\ This DPI create a new dtm class, with the pk as a kernel and the binary that will be executed. It will be called by the testbench. +**debug_new**: it return a void* (chandle in sv) and takes a path as argument.\ +This DPI create a new dtm class, with the binary that will be executed. It will be called by the testbench.\ +So the difference with *debug_new_pk* is that there is no kernel used in this one, allowing to run application + **debug_tick**: it return an integer and takes a dtm object and dmi signals as arguments\ This DPI call the *tick* function from dtm, this allow to get the value for the dmi request and 2 handshake signals, depending on dmi response and 2 corresponding handshake signals.\ Overall this DPI allow to assign values to dmi signals, to ensure a proper communication with the debug module. It will be called in the VIP at every clockcycle. ### Useful information about dtm When a dtm class is created, everything take place at the initialisation.\ -An sub-htif object is initialised with the arguments coming from dtm arg. Then a function is called, *start_host_thread*, it will make a context switch and call the *producer_thread* function. That will enable the debugger of Cheshire and call the *run* function from htif.\ +A sub-htif object is initialised with the arguments coming from dtm arg. Then a function is called, *start_host_thread*, it will make a context switch and call the *producer_thread* function. That will enable the debugger of Cheshire and call the *run* function from htif.\ This last function, preload the binary (if needed) and resume the core to run the binary. This function as an internal loop, until the binary as finished running and then return the exitcode. ## VIP Inside the VIP, a few changes have been done, the code from SimDTM has been reused with a few changes. The way that the reset signal is handled as changed because it was not working for me and a *dmi_rst_ni* signal have been added. -A chandle have been added, to comply with the new feature of the DPI. It will be initialised thanks to the *fesvr_set* task. +A chandle have been added, to comply with the new feature of the DPI. It will be initialised thanks to the *fesvr_set* task.\ Tasks have been created to handle the *dmi_rst_ni* signals. +As you can see, the full code of SimDTM have been copied into the VIP, it's easier to do this way, as SimDTM has never been updated since it's in the CVA6 + **Be careful, when running a testbench,** you must set fesvr before starting it, so call the task *fesvr_set* before *fesvr_start*. -The task *fesvr_wait_for_exit* will loop until sim_exit has changed, so when the binary is finished. -It consider that the program should return 1, to say that everything went fine. In case of a problem, it should print the exitcode. +The task *fesvr_wait_for_exit* will loop until the bit 0 of sim_exit is set to 1, so when the binary is finished.\ +A shift is done on sim_exit to get the exit code of the program. Which will be used to know if the simulation was succesful or not. The I/O have also been changed to add dmi signals when FESVR_DTM is defined, so when the fesvr compile script is used. @@ -109,12 +128,25 @@ About the *dmi_rst_ni* signal, it is only used to reset a FIFO that contains the Few changes have been done to handle and run fesvr. As you can see, the proxy kernel is preloaded using serial link.\ Then a chandle for dtm_t is created and it is started by setting the dmi reset to 1, starting to use the dpi, debug_tick at every clock cycle. the task coming from vip will wait for the end and the simulation will finish. +## RISC-V Frontend Server : fesvr +### Problems encountered when installing it +Two main problems happen when installing the fesvr like explained in it documentation : +- No shared lib created -> needed by simulation tools +- wrong ucontext used -> assert error when running fesvr + +To solve the first problem, the shared lib can simply be created by adding ``fesvr_install_shared_lib = yes`` in *fesvr/fesvr.mk.in* but this would require to change the code, it can also be done by running a command in the terminal to create it directly than copying it in the *install/lib* directory. + +The second problem is caused by **USE_CONTEXT** being defined in *fesvr/context.h*.\ +This is due to **\_\_GLIBC\_\_** being defined because, when compiling context.cc, the flag ``-I/usr/include`` give the full repository which will cause **\_\_GLIBC\_\_** to be defined. But context.cc only needs one header inside of */usr/include*, so by giving it as an argument instead of the full directory when compiling context.cc, we can bypass this problem. + +A script allow to compile the shared lib, making it easier. + # Possible upgrade ### Running several app in a single simulation To do this, changes must be done to the FESVR library. There is a function in *htif.cc*, called *run*, that loop on a value of the object called **stopped**. This value is set at the initialisation of the object to *false* and when run is finished, it's set to *true*. There is no other function changing this value. So this is the first modification that would be needed if you want to run a new binary with the same object. -x + Also, inside *dtm.cc*, there is a function called *producer_thread*. It is called at the end of the initialisation of the dtm class and used to connect the fesvr to the debug module and to run the program (with *htif_t::run*). The thing is that at the end, there is a loop with only nop, so this function never really finish. The end of the simulation is endled by the testbench thanks to the exitcode comming from *htif_t::run*. An other solution, would be to use the chandle feature, but there is no clean way to close the connection between the debug module and dtm, a proper destructor might be needed... From 1f76091a049c873aa96b864b97055c156b3d6754 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 11 Aug 2025 12:51:33 +0200 Subject: [PATCH 21/26] treewide: Add script to compile fesvr and pk --- cheshire.mk | 4 +-- sw/sw.mk | 77 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 2 deletions(-) diff --git a/cheshire.mk b/cheshire.mk index 244c8c1a6..1b3f15466 100644 --- a/cheshire.mk +++ b/cheshire.mk @@ -206,8 +206,8 @@ include $(CHS_ROOT)/target/xilinx/xilinx.mk CHS_ALL += $(CHS_SW_ALL) $(CHS_HW_ALL) $(CHS_SIM_ALL) -chs-all: $(CHS_ALL) -chs-sw-all: $(CHS_SW_ALL) +chs-all: $(CHS_ALL) build-deps +chs-sw-all: $(CHS_SW_ALL) build-deps chs-hw-all: $(CHS_HW_ALL) chs-bootrom-all: $(CHS_BOOTROM_ALL) chs-sim-all: $(CHS_SIM_ALL) diff --git a/sw/sw.mk b/sw/sw.mk index baa9ee411..6daa58199 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -194,3 +194,80 @@ CHS_SW_TESTS += $(CHS_SW_TEST_ROM_DUMP:.rom.dump=.rom.memh) $(CHS_SW_TEST_ROM_DU # Add all dumps to test build CHS_SW_TESTS += $(CHS_SW_TEST_DUMP) + +######### +# FESVR # +######### +.PHONY: build-fesvr + +FESVR_DIR := sw/deps/riscv-isa-sim +FESVR_BUILD := $(FESVR_DIR)/build +FESVR_INSTALL := $(FESVR_DIR)/install +FESVR_PREFIX := $(shell realpath $(FESVR_INSTALL)) + +FESVR_OBJS := $(patsubst ../%.cc,%.o,$(FESVR_SRCS)) + +FESVR_LDFLAGS := -L. -Wl,--export-dynamic -L/usr/lib64 \ + -Wl,-rpath,$(FESVR_PREFIX)/lib \ + -shared + +FESVR_LIBS := -lpthread -ldl -lpthread + +FESVR_CXXFLAGS_COMMON := -MMD -MP \ + -DPREFIX=\"$(FESVR_PREFIX)/\" \ + -Wall -Wno-nonportable-include-path \ + -g -O2 -fPIC -std=c++2a \ + -iquote . -I.. -iquote ../fesvr -iquote ../riscv -iquote ../softfloat + +FESVR_CXXFLAGS := $(FESVR_CXXFLAGS_COMMON) +# context need to only have pthread.h +FESVR_CXXFLAGS_CONTEXT := $(FESVR_CXXFLAGS_COMMON) + + +# List of source files EXCLUDING context.cc +FESVR_SRCS := \ + ../fesvr/elfloader.cc \ + ../fesvr/htif.cc \ + ../fesvr/memif.cc \ + ../fesvr/dtm.cc \ + ../fesvr/syscall.cc \ + ../fesvr/device.cc \ + ../fesvr/rfb.cc \ + ../fesvr/htif_pthread.cc \ + ../fesvr/htif_hexwriter.cc \ + ../fesvr/dummy.cc \ + ../fesvr/option_parser.cc \ + ../fesvr/term.cc \ + ../fesvr/tsi.cc + +build-fesvr: + @mkdir -p $(FESVR_BUILD) $(FESVR_INSTALL)/lib \ + $(FESVR_INSTALL)/include/fesvr \ + $(FESVR_INSTALL)/include/riscv \ + $(FESVR_INSTALL)/include/softfloat + ( cd $(FESVR_BUILD) && \ + ../configure --prefix=$(FESVR_PREFIX) --without-boost-regex && \ + $(CXX) $(FESVR_CXXFLAGS) -c $(FESVR_SRCS) && \ + $(CXX) $(FESVR_CXXFLAGS_CONTEXT) -c ../fesvr/context.cc && \ + $(CXX) $(FESVR_LDFLAGS) -o libfesvr.so *.o $(FESVR_LIBS) ) + cp $(FESVR_BUILD)/libfesvr.so $(FESVR_INSTALL)/lib + cp $(FESVR_DIR)/fesvr/*.h $(FESVR_INSTALL)/include/fesvr + cp $(FESVR_DIR)/riscv/*.h $(FESVR_INSTALL)/include/riscv + cp $(FESVR_DIR)/softfloat/*.h $(FESVR_INSTALL)/include/softfloat + +.PHONY: build-pk + +PK_DIR := sw/deps/riscv-pk +PK_BUILD := $(PK_DIR)/build +PK_INSTALL := $(PK_DIR)/install +PK_PREFIX := $(shell realpath $(PK_INSTALL)) + +build-pk: + @mkdir $(PK_BUILD) $(PK_INSTALL) + ( cd $(PK_BUILD) && \ + ../configure --prefix=$(PK_PREFIX) --host=riscv64-unknown-elf --with-dts=$(CHS_SW_DIR)/boot/cheshire.dtsi && \ + make && \ + make install ) + +.PHONY: build-deps +build-deps: build-fesvr build-pk \ No newline at end of file From f038e67a6ea6c816616097a368fba770c02c8d31 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 11 Aug 2025 13:32:58 +0200 Subject: [PATCH 22/26] treewide: update documentation about new script and clean a script --- mt_doc/readme.md | 18 +++++++++++------- sw/sw.mk | 11 +++-------- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/mt_doc/readme.md b/mt_doc/readme.md index e7bdb6fa9..75e43d05f 100644 --- a/mt_doc/readme.md +++ b/mt_doc/readme.md @@ -8,17 +8,22 @@ They are inside *sw/deps*, you will just need to run ``git submodule update --init --recursive`` to download them. +### Cheshire +Nothing change for the installation, 2 new script should be generated, to add fesvr support when running vsim or vcs. +Then you can run ``make all`` as usual. + ### RISC-V Frontend Server : fesvr +FESVR should have been built when running the ``make all``.\ +Make sure that fesvr is correctly build, you should see in *sw/deps*, the lib in *riscv-isa-sim/install/lib* and 3 directories in *riscv-isa-sim/install/include* + To build the fesvr, you can run make build-fesvr from cheshire directory.\ It will create a shared library, that will be used by simulation tools and DPI. -Make sure that fesvr is correctly build, you should see in *sw/deps*, the lib in *riscv-isa-sim/install/lib* and 3 directories in *riscv-isa-sim/install/include* - -### Cheshire -Nothing change for the installation, 2 new script should be generated, to add fesvr support when running vsim or vcs. -Then you can run ``make all`` as usual. ### RISC-V Proxy kernel : pk +pk should have been built when running the ``make all``.\ +Keep in mind the path to your pk installation, it might be used in cheshire simulation. + To build pk, you can do as following : ``` mkdir build install @@ -27,7 +32,6 @@ cd build make make install ``` -Keep in mind the path to your pk installation, it might be used in cheshire simulation ## Simulation @@ -137,7 +141,7 @@ Two main problems happen when installing the fesvr like explained in it document To solve the first problem, the shared lib can simply be created by adding ``fesvr_install_shared_lib = yes`` in *fesvr/fesvr.mk.in* but this would require to change the code, it can also be done by running a command in the terminal to create it directly than copying it in the *install/lib* directory. The second problem is caused by **USE_CONTEXT** being defined in *fesvr/context.h*.\ -This is due to **\_\_GLIBC\_\_** being defined because, when compiling context.cc, the flag ``-I/usr/include`` give the full repository which will cause **\_\_GLIBC\_\_** to be defined. But context.cc only needs one header inside of */usr/include*, so by giving it as an argument instead of the full directory when compiling context.cc, we can bypass this problem. +This is due to **\_\_GLIBC\_\_** being defined because, when compiling context.cc, the flag ``-I/usr/include`` is used. Giving the full directory which will cause **\_\_GLIBC\_\_** to be defined. But context.cc does not needs it, in fact, not a single file compiled does need it (for fesvr library), so we can bypass this problem by not using this flag when compiling our own fesvr shared library. A script allow to compile the shared lib, making it easier. diff --git a/sw/sw.mk b/sw/sw.mk index 6daa58199..2f93bd1bb 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -213,17 +213,12 @@ FESVR_LDFLAGS := -L. -Wl,--export-dynamic -L/usr/lib64 \ FESVR_LIBS := -lpthread -ldl -lpthread -FESVR_CXXFLAGS_COMMON := -MMD -MP \ +FESVR_CXXFLAGS := -MMD -MP \ -DPREFIX=\"$(FESVR_PREFIX)/\" \ -Wall -Wno-nonportable-include-path \ -g -O2 -fPIC -std=c++2a \ -iquote . -I.. -iquote ../fesvr -iquote ../riscv -iquote ../softfloat -FESVR_CXXFLAGS := $(FESVR_CXXFLAGS_COMMON) -# context need to only have pthread.h -FESVR_CXXFLAGS_CONTEXT := $(FESVR_CXXFLAGS_COMMON) - - # List of source files EXCLUDING context.cc FESVR_SRCS := \ ../fesvr/elfloader.cc \ @@ -238,7 +233,8 @@ FESVR_SRCS := \ ../fesvr/dummy.cc \ ../fesvr/option_parser.cc \ ../fesvr/term.cc \ - ../fesvr/tsi.cc + ../fesvr/tsi.cc \ + ../fesvr/context.cc build-fesvr: @mkdir -p $(FESVR_BUILD) $(FESVR_INSTALL)/lib \ @@ -248,7 +244,6 @@ build-fesvr: ( cd $(FESVR_BUILD) && \ ../configure --prefix=$(FESVR_PREFIX) --without-boost-regex && \ $(CXX) $(FESVR_CXXFLAGS) -c $(FESVR_SRCS) && \ - $(CXX) $(FESVR_CXXFLAGS_CONTEXT) -c ../fesvr/context.cc && \ $(CXX) $(FESVR_LDFLAGS) -o libfesvr.so *.o $(FESVR_LIBS) ) cp $(FESVR_BUILD)/libfesvr.so $(FESVR_INSTALL)/lib cp $(FESVR_DIR)/fesvr/*.h $(FESVR_INSTALL)/include/fesvr From c3f984de356d8b63313f326e42ecd42c60f5a45e Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Mon, 11 Aug 2025 15:26:43 +0200 Subject: [PATCH 23/26] target/sim/vcs: Fix path to fesvr --- target/sim/vcs/start.cheshire_soc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 00c708738..9c99461dd 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -51,7 +51,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../sw/deps/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=../../../sw/deps/riscv-isa-sim/install/lib -L../../../sw/deps/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../../sw/deps/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=../../../../sw/deps/riscv-isa-sim/install/lib -L../../../../sw/deps/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" From ee694724fdcc30b24d560c596010d551bb0131e5 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 13 Aug 2025 17:01:22 +0200 Subject: [PATCH 24/26] treewide: Fix support of libfesvr in VCS --- sw/sw.mk | 5 ++++- target/sim/vcs/start.cheshire_soc.sh | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/sw/sw.mk b/sw/sw.mk index 2f93bd1bb..0d9f3e4c2 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -200,7 +200,7 @@ CHS_SW_TESTS += $(CHS_SW_TEST_DUMP) ######### .PHONY: build-fesvr -FESVR_DIR := sw/deps/riscv-isa-sim +FESVR_DIR := $(CHS_ROOT)/sw/deps/riscv-isa-sim FESVR_BUILD := $(FESVR_DIR)/build FESVR_INSTALL := $(FESVR_DIR)/install FESVR_PREFIX := $(shell realpath $(FESVR_INSTALL)) @@ -249,6 +249,9 @@ build-fesvr: cp $(FESVR_DIR)/fesvr/*.h $(FESVR_INSTALL)/include/fesvr cp $(FESVR_DIR)/riscv/*.h $(FESVR_INSTALL)/include/riscv cp $(FESVR_DIR)/softfloat/*.h $(FESVR_INSTALL)/include/softfloat + mkdir $(CHS_ROOT)/target/sim/vcs/simv.daidir + ( cd $(CHS_ROOT)/target/sim/vcs/simv.daidir && \ + ln -s $(FESVR_INSTALL)/lib/libfesvr.so . ) .PHONY: build-pk diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 9c99461dd..507987dfe 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -51,7 +51,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../../sw/deps/riscv-isa-sim/install/include" -LIBS "-rdynamic -Wl,-rpath=../../../../sw/deps/riscv-isa-sim/install/lib -L../../../../sw/deps/riscv-isa-sim/install/lib -lfesvr" ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I/scratch/ga25f6/cheshire/sw/deps/riscv-isa-sim/install/include" -L/scratch/ga25f6/cheshire/sw/deps/riscv-isa-sim/install/lib -lfesvr ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" From ea08c6f1e61669c16108f8b0aab3901158f57e46 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 13 Aug 2025 17:28:37 +0200 Subject: [PATCH 25/26] target/sim/vcs: Switching to relative path for fesvr --- target/sim/vcs/start.cheshire_soc.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 507987dfe..6657bf7a4 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -51,7 +51,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I/scratch/ga25f6/cheshire/sw/deps/riscv-isa-sim/install/include" -L/scratch/ga25f6/cheshire/sw/deps/riscv-isa-sim/install/lib -lfesvr ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../../sw/deps/riscv-isa-sim/install/include" -L../../../../sw/deps/riscv-isa-sim/install/lib -lfesvr ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n" From fcaefca403aef8ecb70614e8a3e5b538088e80a1 Mon Sep 17 00:00:00 2001 From: mtravaillard Date: Wed, 20 Aug 2025 11:46:22 +0200 Subject: [PATCH 26/26] treewide: clean fix for VCS shared lib linking issue --- sw/sw.mk | 3 --- target/sim/vcs/start.cheshire_soc.sh | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/sw/sw.mk b/sw/sw.mk index 0d9f3e4c2..b8cf59958 100644 --- a/sw/sw.mk +++ b/sw/sw.mk @@ -249,9 +249,6 @@ build-fesvr: cp $(FESVR_DIR)/fesvr/*.h $(FESVR_INSTALL)/include/fesvr cp $(FESVR_DIR)/riscv/*.h $(FESVR_INSTALL)/include/riscv cp $(FESVR_DIR)/softfloat/*.h $(FESVR_INSTALL)/include/softfloat - mkdir $(CHS_ROOT)/target/sim/vcs/simv.daidir - ( cd $(CHS_ROOT)/target/sim/vcs/simv.daidir && \ - ln -s $(FESVR_INSTALL)/lib/libfesvr.so . ) .PHONY: build-pk diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh index 6657bf7a4..837e9ee48 100755 --- a/target/sim/vcs/start.cheshire_soc.sh +++ b/target/sim/vcs/start.cheshire_soc.sh @@ -51,7 +51,7 @@ fi COLOR_NC='\e[0m' COLOR_BLUE='\e[0;34m' -${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../../sw/deps/riscv-isa-sim/install/include" -L../../../../sw/deps/riscv-isa-sim/install/lib -lfesvr ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log +${VCS_BIN} ${flags} -CFLAGS "-std=c++17 -I../../../../sw/deps/riscv-isa-sim/install/include" ../../../sw/deps/riscv-isa-sim/install/lib/libfesvr.so ../src/elfloader.cpp ${TESTBENCH} | tee elaborate.log # Start simulation printf ${COLOR_BLUE}"${VCS_VERSION} ${VERDI_VERSION} ./simv ${pargs}"${COLOR_NC}"\n"