diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 0c4dec8af..2cd29c01f 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -19,26 +19,26 @@ jobs:
     steps:
       -
         name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v6.0.3
         with:
           submodules: recursive
       -
         name: Install uv
-        uses: astral-sh/setup-uv@v6
+        uses: astral-sh/setup-uv@v8.2.0
         with:
           python-version: "3.11"
       -
         name: Install RISC-V GCC toolchain
-        uses: pulp-platform/pulp-actions/riscv-gcc-install@v2.4.4
+        uses: pulp-platform/pulp-actions/riscv-gcc-install@v2.5.1
         with:
           distro: ubuntu-22.04
           nightly-date: '2023.03.14'
           target: riscv64-elf
       -
         name: Install Bender
-        uses: pulp-platform/pulp-actions/bender-install@v2.4.4
+        uses: pulp-platform/pulp-actions/bender-install@v2.5.1
         with:
-          version: 0.31.0
+          version: 0.32.1
       -
         name: Build target
         run: uv run --locked make ${{ matrix.target }}-all
diff --git a/.github/workflows/dependabot.yml b/.github/workflows/dependabot.yml
new file mode 100644
index 000000000..c86269f59
--- /dev/null
+++ b/.github/workflows/dependabot.yml
@@ -0,0 +1,27 @@
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+version: 2
+updates:
+  # Python dependencies managed by uv (pyproject.toml + uv.lock)
+  - package-ecosystem: "uv"
+    directory: "/"
+    schedule:
+      interval: "monthly"
+    cooldown:
+      default-days: 7
+    groups:
+      python-deps:
+        patterns: ["*"]
+
+  # GitHub Actions used in .github/workflows
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "monthly"
+    cooldown:
+      default-days: 7
+    groups:
+      github-actions:
+        patterns: ["*"]
diff --git a/.github/workflows/docker-image.yml b/.github/workflows/docker-image.yml
index a4f81d653..524305ff9 100644
--- a/.github/workflows/docker-image.yml
+++ b/.github/workflows/docker-image.yml
@@ -4,7 +4,7 @@
 
 # Author: Jannis Schoenleber <janniss@iis.ee.ethz.ch>
 
-name: docker-image 
+name: docker-image
 
 on:
   push:
@@ -19,19 +19,19 @@ jobs:
     steps:
       -
         name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v6.0.3
       -
         name: Login to Docker Hub
-        uses: docker/login-action@v2
+        uses: docker/login-action@v4.2.0
         with:
           username: ${{ secrets.DOCKERHUB_USERNAME }}
           password: ${{ secrets.DOCKERHUB_TOKEN }}
       -
         name: Set up Docker Buildx
-        uses: docker/setup-buildx-action@v2
+        uses: docker/setup-buildx-action@v4.1.0
       -
         name: Build and push
-        uses: docker/build-push-action@v3
+        uses: docker/build-push-action@v7.2.0
         with:
           context: .
           file: ./.github/Dockerfile
diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml
index 97838ffec..4e248c486 100644
--- a/.github/workflows/gitlab-ci.yml
+++ b/.github/workflows/gitlab-ci.yml
@@ -15,7 +15,7 @@ jobs:
     steps:
       -
         name: Mirror and check
-        uses: pulp-platform/pulp-actions/gitlab-ci@v2.4.4
+        uses: pulp-platform/pulp-actions/gitlab-ci@v2.5.1
         # Skip on forks or pull requests from forks due to missing secrets.
         if: >
           github.repository == 'pulp-platform/cheshire' &&
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
index 9b6afd08f..558a58c44 100644
--- a/.github/workflows/lint.yml
+++ b/.github/workflows/lint.yml
@@ -15,10 +15,10 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v6.0.3
     -
       name: Check license
-      uses: pulp-platform/pulp-actions/lint-license@v2.4.4
+      uses: pulp-platform/pulp-actions/lint-license@v2.5.1
       with:
         license: |
           Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors).
@@ -33,7 +33,7 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v6.0.3
     -
       name: Run Verible
       uses: chipsalliance/verible-linter-action@main
@@ -50,10 +50,10 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v6.0.3
     -
       name: Run Clang-format
-      uses: DoozyX/clang-format-lint-action@v0.14
+      uses: DoozyX/clang-format-lint-action@v0.20
       with:
         extensions: 'c,h,cpp'
         clangFormatVersion: 14
@@ -66,10 +66,10 @@ jobs:
     steps:
     -
       name: Checkout
-      uses: actions/checkout@v3
+      uses: actions/checkout@v6.0.3
     -
       name: Install uv
-      uses: astral-sh/setup-uv@v6
+      uses: astral-sh/setup-uv@v8.2.0
       with:
         python-version: "3.11"
     -
diff --git a/.github/workflows/publish-docs.yml b/.github/workflows/publish-docs.yml
index aa9faf7c0..b001559a0 100644
--- a/.github/workflows/publish-docs.yml
+++ b/.github/workflows/publish-docs.yml
@@ -18,12 +18,12 @@ jobs:
     steps:
       -
         name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v6.0.3
         with:
           submodules: recursive
       -
         name: Install uv
-        uses: astral-sh/setup-uv@v6
+        uses: astral-sh/setup-uv@v8.2.0
         with:
           python-version: "3.11"
       -
diff --git a/hw/cheshire_addrmap_pkg.sv b/hw/cheshire_addrmap_pkg.sv
index 7960cbc37..cd2f16474 100644
--- a/hw/cheshire_addrmap_pkg.sv
+++ b/hw/cheshire_addrmap_pkg.sv
@@ -167,4 +167,4 @@ typedef enum logic [1:0] {
     I2C_24XX1025 = 2'd3
 } BootMode_e;
 
-endpackage;
+endpackage
diff --git a/hw/regs/cheshire_soc_regs.sv b/hw/regs/cheshire_soc_regs.sv
index 33b90363a..5def051f1 100644
--- a/hw/regs/cheshire_soc_regs.sv
+++ b/hw/regs/cheshire_soc_regs.sv
@@ -79,24 +79,7 @@ module cheshire_soc_regs (
     assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
 
     logic cpuif_req_masked;
-    logic external_req;
     logic external_pending;
-    logic external_wr_ack;
-    logic external_rd_ack;
-    always_ff @(posedge clk or negedge arst_n) begin
-        if(~arst_n) begin
-            external_pending <= '0;
-        end else begin
-            if(external_req & ~external_wr_ack & ~external_rd_ack) external_pending <= '1;
-            else if(external_wr_ack | external_rd_ack) external_pending <= '0;
-            `ifndef SYNTHESIS
-                assert_bad_ext_wr_ack: assert(!external_wr_ack || (external_pending | external_req))
-                    else $error("An external wr_ack strobe was asserted when no external request was active");
-                assert_bad_ext_rd_ack: assert(!external_rd_ack || (external_pending | external_req))
-                    else $error("An external rd_ack strobe was asserted when no external request was active");
-            `endif
-        end
-    end
 
     // Read & write latencies are balanced. Stalls not required
     // except if external
@@ -121,8 +104,9 @@ module cheshire_soc_regs (
     } decoded_reg_strb_t;
     decoded_reg_strb_t decoded_reg_strb;
     logic decoded_err;
-    logic decoded_strb_is_external;
+    logic decoded_req_is_external;
 
+    logic [6:0] decoded_addr;
     logic decoded_req;
     logic decoded_req_is_wr;
     logic [31:0] decoded_wr_data;
@@ -130,11 +114,11 @@ module cheshire_soc_regs (
 
     always_comb begin
         automatic logic is_valid_addr;
-        automatic logic is_invalid_rw;
+        automatic logic is_valid_rw;
         automatic logic is_external;
         is_external = '0;
-        is_valid_addr = '1; // No error checking on valid address access
-        is_invalid_rw = '0;
+        is_valid_addr = '1; // No valid address check
+        is_valid_rw = '1; // No valid RW check
         for(int i0=0; i0<16; i0++) begin
             decoded_reg_strb.scratch[i0] = cpuif_req_masked & (cpuif_addr == 7'h0 + (7)'(i0) * 7'h4);
         end
@@ -152,12 +136,28 @@ module cheshire_soc_regs (
         is_external |= cpuif_req_masked & (cpuif_addr == 7'h54) & !cpuif_req_is_wr;
         decoded_reg_strb.vga_params = cpuif_req_masked & (cpuif_addr == 7'h58) & !cpuif_req_is_wr;
         is_external |= cpuif_req_masked & (cpuif_addr == 7'h58) & !cpuif_req_is_wr;
-        decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
-        decoded_strb_is_external = is_external;
-        external_req = is_external;
+        decoded_err = '0;
+        decoded_req_is_external = is_external;
+    end
+    logic external_wr_ack;
+    logic external_rd_ack;
+    always_ff @(posedge clk or negedge arst_n) begin
+        if(~arst_n) begin
+            external_pending <= '0;
+        end else begin
+            if(decoded_req_is_external & ~external_wr_ack & ~external_rd_ack) external_pending <= '1;
+            else if(external_wr_ack | external_rd_ack) external_pending <= '0;
+            `ifndef SYNTHESIS
+                assert_bad_ext_wr_ack: assert(!external_wr_ack || (external_pending | decoded_req_is_external))
+                    else $error("An external wr_ack strobe was asserted when no external request was active");
+                assert_bad_ext_rd_ack: assert(!external_rd_ack || (external_pending | decoded_req_is_external))
+                    else $error("An external rd_ack strobe was asserted when no external request was active");
+            `endif
+        end
     end
 
     // Pass down signals to next stage
+    assign decoded_addr = cpuif_addr;
     assign decoded_req = cpuif_req_masked;
     assign decoded_req_is_wr = cpuif_req_is_wr;
     assign decoded_wr_data = cpuif_wr_data;
@@ -247,7 +247,7 @@ module cheshire_soc_regs (
         
         external_wr_ack = wr_ack;
     end
-    assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_strb_is_external);
+    assign cpuif_wr_ack = external_wr_ack | (decoded_req & decoded_req_is_wr & ~decoded_req_is_external);
     // Writes are always granted with no error response
     assign cpuif_wr_err = '0;
 
@@ -272,31 +272,53 @@ module cheshire_soc_regs (
 
     assign readback_external_rd_ack = readback_external_rd_ack_c;
 
+    logic [6:0] rd_mux_addr;
+    logic [6:0] pending_rd_addr;
+    // Hold read mux address to guarantee it is stable throughout any external accesses
+    always_ff @(posedge clk or negedge arst_n) begin
+        if(~arst_n) begin
+            pending_rd_addr <= '0;
+        end else begin
+            if(decoded_req) pending_rd_addr <= decoded_addr;
+        end
+    end
+    assign rd_mux_addr = decoded_req ? decoded_addr : pending_rd_addr;
+
     logic readback_err;
     logic readback_done;
     logic [31:0] readback_data;
-
-    // Assign readback values to a flattened array
-    logic [31:0] readback_array[23];
-    for(genvar i0=0; i0<16; i0++) begin
-        assign readback_array[i0 * 1 + 0][31:0] = (decoded_reg_strb.scratch[i0] && !decoded_req_is_wr) ? field_storage.scratch[i0].scratch.value : '0;
-    end
-    assign readback_array[16] = hwif_in.boot_mode.rd_ack ? hwif_in.boot_mode.rd_data : '0;
-    assign readback_array[17] = hwif_in.rtc_freq.rd_ack ? hwif_in.rtc_freq.rd_data : '0;
-    assign readback_array[18] = hwif_in.platform_rom.rd_ack ? hwif_in.platform_rom.rd_data : '0;
-    assign readback_array[19] = hwif_in.num_int_harts.rd_ack ? hwif_in.num_int_harts.rd_data : '0;
-    assign readback_array[20] = hwif_in.hw_features.rd_ack ? hwif_in.hw_features.rd_data : '0;
-    assign readback_array[21] = hwif_in.llc_size.rd_ack ? hwif_in.llc_size.rd_data : '0;
-    assign readback_array[22] = hwif_in.vga_params.rd_ack ? hwif_in.vga_params.rd_data : '0;
-
-    // Reduce the array
     always_comb begin
         automatic logic [31:0] readback_data_var;
-        readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_strb_is_external;
-        readback_err = '0;
         readback_data_var = '0;
-        for(int i=0; i<23; i++) readback_data_var |= readback_array[i];
+        for(int i0=0; i0<16; i0++) begin
+            if(rd_mux_addr == 7'h0 + (7)'(i0) * 7'h4) begin
+                readback_data_var[31:0] = field_storage.scratch[i0].scratch.value;
+            end
+        end
+        if(rd_mux_addr == 7'h40) begin
+            readback_data_var = hwif_in.boot_mode.rd_data;
+        end
+        if(rd_mux_addr == 7'h44) begin
+            readback_data_var = hwif_in.rtc_freq.rd_data;
+        end
+        if(rd_mux_addr == 7'h48) begin
+            readback_data_var = hwif_in.platform_rom.rd_data;
+        end
+        if(rd_mux_addr == 7'h4c) begin
+            readback_data_var = hwif_in.num_int_harts.rd_data;
+        end
+        if(rd_mux_addr == 7'h50) begin
+            readback_data_var = hwif_in.hw_features.rd_data;
+        end
+        if(rd_mux_addr == 7'h54) begin
+            readback_data_var = hwif_in.llc_size.rd_data;
+        end
+        if(rd_mux_addr == 7'h58) begin
+            readback_data_var = hwif_in.vga_params.rd_data;
+        end
         readback_data = readback_data_var;
+        readback_done = decoded_req & ~decoded_req_is_wr & ~decoded_req_is_external;
+        readback_err = '0;
     end
 
     assign external_rd_ack = readback_external_rd_ack;
diff --git a/pyproject.toml b/pyproject.toml
index b9eab3909..c11600f7d 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -6,21 +6,28 @@
 name = "cheshire"
 version = "0.1.0"
 requires-python = ">=3.11"
+# Runtime dependencies of the generators invoked by `cheshire.mk`; these are
+# inherited by projects integrating Cheshire as a uv workspace member.
 dependencies = [
-    "requests",
-    "hjson",
-    "mako",
-    "pyyaml",
-    "tabulate",
-    "yapf",
+    "hjson",            # `regtool`, `ipgen`
+    "mako",             # `regtool`, `ipgen`
+    "pyyaml",           # `regtool`
+    "tabulate",         # Required by `reggen.gen_md`
+    "flatdict>=4.1.0",  # Required by iDMA's `mario` generator
+    "setuptools<81",    # Required by old `regtool`
+    "peakrdl>=1.5.0",
+    "peakrdl-rawheader>=0.2.3",
+]
+
+# Tooling used only when developing Cheshire itself (docs, linting). Dependency
+# groups are not carried along a dependency edge, so a project depending on
+# Cheshire as a uv workspace member inherits `dependencies` above, but not these.
+[dependency-groups]
+dev = [
     "mkdocs",
     "mkdocs-material",
     "markdown-grid-tables",
     "tclint==0.4.2",
-    "flatdict>=4.1.0",
-    "setuptools<81", # Required by old `regtool`
-    "peakrdl>=1.5.0",
-    "peakrdl-rawheader>=0.2.3",
 ]
 
 [tool.uv]
diff --git a/sw/include/regs/cheshire.h b/sw/include/regs/cheshire.h
index 82213bfca..259093797 100644
--- a/sw/include/regs/cheshire.h
+++ b/sw/include/regs/cheshire.h
@@ -11,16 +11,15 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-
 #include <stdint.h>
 #include <assert.h>
 
-// Mem - cheshire.extrom
+// mem - cheshire.extrom
 typedef struct __attribute__ ((__packed__)) {
     uint32_t mem[65536];
 } cheshire__extrom_t;
 
-// Reg - cheshire.dma.status
+// reg - cheshire.dma.status
 #define CHESHIRE__DMA__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__DMA__STATUS__STATUS_bp 0
 #define CHESHIRE__DMA__STATUS__STATUS_bw 32
@@ -32,7 +31,7 @@ typedef union {
     uint32_t w;
 } cheshire__dma__status_t;
 
-// Reg - cheshire.dma._end
+// reg - cheshire.dma._end
 #define CHESHIRE__DMA___END___END_bm 0xffffffff
 #define CHESHIRE__DMA___END___END_bp 0
 #define CHESHIRE__DMA___END___END_bw 32
@@ -44,19 +43,19 @@ typedef union {
     uint32_t w;
 } cheshire__dma___end_t;
 
-// Addrmap - cheshire.dma
+// addrmap - cheshire.dma
 typedef struct __attribute__ ((__packed__)) {
     cheshire__dma__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__dma___end_t _end;
 } cheshire__dma_t;
 
-// Mem - cheshire.bootrom
+// mem - cheshire.bootrom
 typedef struct __attribute__ ((__packed__)) {
     uint32_t mem[65536];
 } cheshire__bootrom_t;
 
-// Reg - cheshire.clint.msip[]
+// reg - cheshire.clint.msip[]
 #define CHESHIRE__CLINT__MSIPX__PENDING_bm 0x1
 #define CHESHIRE__CLINT__MSIPX__PENDING_bp 0
 #define CHESHIRE__CLINT__MSIPX__PENDING_bw 1
@@ -73,7 +72,7 @@ typedef union {
     uint32_t w;
 } cheshire__clint__msipx_t;
 
-// Reg - cheshire.clint.mtimecmp[]
+// reg - cheshire.clint.mtimecmp[]
 #define CHESHIRE__CLINT__MTIMECMPX__LOW_bm 0xffffffff
 #define CHESHIRE__CLINT__MTIMECMPX__LOW_bp 0
 #define CHESHIRE__CLINT__MTIMECMPX__LOW_bw 32
@@ -90,7 +89,7 @@ typedef union {
     uint64_t w;
 } cheshire__clint__mtimecmpx_t;
 
-// Reg - cheshire.clint.mtime
+// reg - cheshire.clint.mtime
 #define CHESHIRE__CLINT__MTIME__LOW_bm 0xffffffff
 #define CHESHIRE__CLINT__MTIME__LOW_bp 0
 #define CHESHIRE__CLINT__MTIME__LOW_bw 32
@@ -107,7 +106,7 @@ typedef union {
     uint64_t w;
 } cheshire__clint__mtime_t;
 
-// Addrmap - cheshire.clint
+// addrmap - cheshire.clint
 typedef struct __attribute__ ((__packed__)) {
     cheshire__clint__msipx_t msip[1];
     uint8_t RESERVED_4_3fff[0x3ffc];
@@ -116,7 +115,7 @@ typedef struct __attribute__ ((__packed__)) {
     cheshire__clint__mtime_t mtime;
 } cheshire__clint_t;
 
-// Reg - cheshire.irq_router.status
+// reg - cheshire.irq_router.status
 #define CHESHIRE__IRQ_ROUTER__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__IRQ_ROUTER__STATUS__STATUS_bp 0
 #define CHESHIRE__IRQ_ROUTER__STATUS__STATUS_bw 32
@@ -128,7 +127,7 @@ typedef union {
     uint32_t w;
 } cheshire__irq_router__status_t;
 
-// Reg - cheshire.irq_router._end
+// reg - cheshire.irq_router._end
 #define CHESHIRE__IRQ_ROUTER___END___END_bm 0xffffffff
 #define CHESHIRE__IRQ_ROUTER___END___END_bp 0
 #define CHESHIRE__IRQ_ROUTER___END___END_bw 32
@@ -140,14 +139,14 @@ typedef union {
     uint32_t w;
 } cheshire__irq_router___end_t;
 
-// Addrmap - cheshire.irq_router
+// addrmap - cheshire.irq_router
 typedef struct __attribute__ ((__packed__)) {
     cheshire__irq_router__status_t status;
     uint8_t RESERVED_4_3fffb[0x3fff8];
     cheshire__irq_router___end_t _end;
 } cheshire__irq_router_t;
 
-// Reg - cheshire.axirt.status
+// reg - cheshire.axirt.status
 #define CHESHIRE__AXIRT__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__AXIRT__STATUS__STATUS_bp 0
 #define CHESHIRE__AXIRT__STATUS__STATUS_bw 32
@@ -159,7 +158,7 @@ typedef union {
     uint32_t w;
 } cheshire__axirt__status_t;
 
-// Reg - cheshire.axirt._end
+// reg - cheshire.axirt._end
 #define CHESHIRE__AXIRT___END___END_bm 0xffffffff
 #define CHESHIRE__AXIRT___END___END_bp 0
 #define CHESHIRE__AXIRT___END___END_bw 32
@@ -171,14 +170,14 @@ typedef union {
     uint32_t w;
 } cheshire__axirt___end_t;
 
-// Addrmap - cheshire.axirt
+// addrmap - cheshire.axirt
 typedef struct __attribute__ ((__packed__)) {
     cheshire__axirt__status_t status;
     uint8_t RESERVED_4_3fffb[0x3fff8];
     cheshire__axirt___end_t _end;
 } cheshire__axirt_t;
 
-// Reg - cheshire.regs.scratch[]
+// reg - cheshire.regs.scratch[]
 #define CHESHIRE__REGS__SCRATCHX__SCRATCH_bm 0xffffffff
 #define CHESHIRE__REGS__SCRATCHX__SCRATCH_bp 0
 #define CHESHIRE__REGS__SCRATCHX__SCRATCH_bw 32
@@ -190,7 +189,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__scratchx_t;
 
-// Reg - cheshire.regs.boot_mode
+// reg - cheshire.regs.boot_mode
 #define CHESHIRE__REGS__BOOT_MODE__BOOT_MODE_bm 0x3
 #define CHESHIRE__REGS__BOOT_MODE__BOOT_MODE_bp 0
 #define CHESHIRE__REGS__BOOT_MODE__BOOT_MODE_bw 2
@@ -202,7 +201,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__boot_mode_t;
 
-// Reg - cheshire.regs.rtc_freq
+// reg - cheshire.regs.rtc_freq
 #define CHESHIRE__REGS__RTC_FREQ__REF_FREQ_bm 0xffffffff
 #define CHESHIRE__REGS__RTC_FREQ__REF_FREQ_bp 0
 #define CHESHIRE__REGS__RTC_FREQ__REF_FREQ_bw 32
@@ -213,7 +212,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__rtc_freq_t;
 
-// Reg - cheshire.regs.platform_rom
+// reg - cheshire.regs.platform_rom
 #define CHESHIRE__REGS__PLATFORM_ROM__PLATFORM_ROM_bm 0xffffffff
 #define CHESHIRE__REGS__PLATFORM_ROM__PLATFORM_ROM_bp 0
 #define CHESHIRE__REGS__PLATFORM_ROM__PLATFORM_ROM_bw 32
@@ -224,7 +223,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__platform_rom_t;
 
-// Reg - cheshire.regs.num_int_harts
+// reg - cheshire.regs.num_int_harts
 #define CHESHIRE__REGS__NUM_INT_HARTS__NUM_HARTS_bm 0xffffffff
 #define CHESHIRE__REGS__NUM_INT_HARTS__NUM_HARTS_bp 0
 #define CHESHIRE__REGS__NUM_INT_HARTS__NUM_HARTS_bw 32
@@ -235,7 +234,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__num_int_harts_t;
 
-// Reg - cheshire.regs.hw_features
+// reg - cheshire.regs.hw_features
 #define CHESHIRE__REGS__HW_FEATURES__BOOTROM_bm 0x1
 #define CHESHIRE__REGS__HW_FEATURES__BOOTROM_bp 0
 #define CHESHIRE__REGS__HW_FEATURES__BOOTROM_bw 1
@@ -299,7 +298,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__hw_features_t;
 
-// Reg - cheshire.regs.llc_size
+// reg - cheshire.regs.llc_size
 #define CHESHIRE__REGS__LLC_SIZE__LLC_SIZE_bm 0xffffffff
 #define CHESHIRE__REGS__LLC_SIZE__LLC_SIZE_bp 0
 #define CHESHIRE__REGS__LLC_SIZE__LLC_SIZE_bw 32
@@ -310,7 +309,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__llc_size_t;
 
-// Reg - cheshire.regs.vga_params
+// reg - cheshire.regs.vga_params
 #define CHESHIRE__REGS__VGA_PARAMS__RED_WIDTH_bm 0xff
 #define CHESHIRE__REGS__VGA_PARAMS__RED_WIDTH_bp 0
 #define CHESHIRE__REGS__VGA_PARAMS__RED_WIDTH_bw 8
@@ -330,7 +329,7 @@ typedef union {
     uint32_t w;
 } cheshire__regs__vga_params_t;
 
-// Addrmap - cheshire.regs
+// addrmap - cheshire.regs
 typedef struct __attribute__ ((__packed__)) {
     cheshire__regs__scratchx_t scratch[16];
     cheshire__regs__boot_mode_t boot_mode;
@@ -342,7 +341,7 @@ typedef struct __attribute__ ((__packed__)) {
     cheshire__regs__vga_params_t vga_params;
 } cheshire__regs_t;
 
-// Reg - cheshire.llc.status
+// reg - cheshire.llc.status
 #define CHESHIRE__LLC__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__LLC__STATUS__STATUS_bp 0
 #define CHESHIRE__LLC__STATUS__STATUS_bw 32
@@ -354,7 +353,7 @@ typedef union {
     uint32_t w;
 } cheshire__llc__status_t;
 
-// Reg - cheshire.llc._end
+// reg - cheshire.llc._end
 #define CHESHIRE__LLC___END___END_bm 0xffffffff
 #define CHESHIRE__LLC___END___END_bp 0
 #define CHESHIRE__LLC___END___END_bw 32
@@ -366,14 +365,14 @@ typedef union {
     uint32_t w;
 } cheshire__llc___end_t;
 
-// Addrmap - cheshire.llc
+// addrmap - cheshire.llc
 typedef struct __attribute__ ((__packed__)) {
     cheshire__llc__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__llc___end_t _end;
 } cheshire__llc_t;
 
-// Reg - cheshire.uart.status
+// reg - cheshire.uart.status
 #define CHESHIRE__UART__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__UART__STATUS__STATUS_bp 0
 #define CHESHIRE__UART__STATUS__STATUS_bw 32
@@ -385,7 +384,7 @@ typedef union {
     uint32_t w;
 } cheshire__uart__status_t;
 
-// Reg - cheshire.uart._end
+// reg - cheshire.uart._end
 #define CHESHIRE__UART___END___END_bm 0xffffffff
 #define CHESHIRE__UART___END___END_bp 0
 #define CHESHIRE__UART___END___END_bw 32
@@ -397,14 +396,14 @@ typedef union {
     uint32_t w;
 } cheshire__uart___end_t;
 
-// Addrmap - cheshire.uart
+// addrmap - cheshire.uart
 typedef struct __attribute__ ((__packed__)) {
     cheshire__uart__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__uart___end_t _end;
 } cheshire__uart_t;
 
-// Reg - cheshire.i2c.status
+// reg - cheshire.i2c.status
 #define CHESHIRE__I2C__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__I2C__STATUS__STATUS_bp 0
 #define CHESHIRE__I2C__STATUS__STATUS_bw 32
@@ -416,7 +415,7 @@ typedef union {
     uint32_t w;
 } cheshire__i2c__status_t;
 
-// Reg - cheshire.i2c._end
+// reg - cheshire.i2c._end
 #define CHESHIRE__I2C___END___END_bm 0xffffffff
 #define CHESHIRE__I2C___END___END_bp 0
 #define CHESHIRE__I2C___END___END_bw 32
@@ -428,14 +427,14 @@ typedef union {
     uint32_t w;
 } cheshire__i2c___end_t;
 
-// Addrmap - cheshire.i2c
+// addrmap - cheshire.i2c
 typedef struct __attribute__ ((__packed__)) {
     cheshire__i2c__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__i2c___end_t _end;
 } cheshire__i2c_t;
 
-// Reg - cheshire.spih.status
+// reg - cheshire.spih.status
 #define CHESHIRE__SPIH__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__SPIH__STATUS__STATUS_bp 0
 #define CHESHIRE__SPIH__STATUS__STATUS_bw 32
@@ -447,7 +446,7 @@ typedef union {
     uint32_t w;
 } cheshire__spih__status_t;
 
-// Reg - cheshire.spih._end
+// reg - cheshire.spih._end
 #define CHESHIRE__SPIH___END___END_bm 0xffffffff
 #define CHESHIRE__SPIH___END___END_bp 0
 #define CHESHIRE__SPIH___END___END_bw 32
@@ -459,14 +458,14 @@ typedef union {
     uint32_t w;
 } cheshire__spih___end_t;
 
-// Addrmap - cheshire.spih
+// addrmap - cheshire.spih
 typedef struct __attribute__ ((__packed__)) {
     cheshire__spih__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__spih___end_t _end;
 } cheshire__spih_t;
 
-// Reg - cheshire.gpio.status
+// reg - cheshire.gpio.status
 #define CHESHIRE__GPIO__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__GPIO__STATUS__STATUS_bp 0
 #define CHESHIRE__GPIO__STATUS__STATUS_bw 32
@@ -478,7 +477,7 @@ typedef union {
     uint32_t w;
 } cheshire__gpio__status_t;
 
-// Reg - cheshire.gpio._end
+// reg - cheshire.gpio._end
 #define CHESHIRE__GPIO___END___END_bm 0xffffffff
 #define CHESHIRE__GPIO___END___END_bp 0
 #define CHESHIRE__GPIO___END___END_bw 32
@@ -490,14 +489,14 @@ typedef union {
     uint32_t w;
 } cheshire__gpio___end_t;
 
-// Addrmap - cheshire.gpio
+// addrmap - cheshire.gpio
 typedef struct __attribute__ ((__packed__)) {
     cheshire__gpio__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__gpio___end_t _end;
 } cheshire__gpio_t;
 
-// Reg - cheshire.slink.ctrl
+// reg - cheshire.slink.ctrl
 #define CHESHIRE__SLINK__CTRL__CLK_ENA_bm 0x1
 #define CHESHIRE__SLINK__CTRL__CLK_ENA_bp 0
 #define CHESHIRE__SLINK__CTRL__CLK_ENA_bw 1
@@ -526,7 +525,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__ctrl_t;
 
-// Reg - cheshire.slink.isolated
+// reg - cheshire.slink.isolated
 #define CHESHIRE__SLINK__ISOLATED__AXI_IN_bm 0x1
 #define CHESHIRE__SLINK__ISOLATED__AXI_IN_bp 0
 #define CHESHIRE__SLINK__ISOLATED__AXI_IN_bw 1
@@ -544,7 +543,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__isolated_t;
 
-// Reg - cheshire.slink.raw_mode_en
+// reg - cheshire.slink.raw_mode_en
 #define CHESHIRE__SLINK__RAW_MODE_EN__RAW_MODE_EN_bm 0x1
 #define CHESHIRE__SLINK__RAW_MODE_EN__RAW_MODE_EN_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_EN__RAW_MODE_EN_bw 1
@@ -557,7 +556,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_en_t;
 
-// Reg - cheshire.slink.raw_mode_in_data
+// reg - cheshire.slink.raw_mode_in_data
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA__RAW_MODE_IN_DATA_bm 0xff
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA__RAW_MODE_IN_DATA_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA__RAW_MODE_IN_DATA_bw 8
@@ -569,7 +568,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_in_data_t;
 
-// Reg - cheshire.slink.raw_mode_in_ch_sel
+// reg - cheshire.slink.raw_mode_in_ch_sel
 #define CHESHIRE__SLINK__RAW_MODE_IN_CH_SEL__RAW_MODE_IN_CH_SEL_bm 0xff
 #define CHESHIRE__SLINK__RAW_MODE_IN_CH_SEL__RAW_MODE_IN_CH_SEL_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_IN_CH_SEL__RAW_MODE_IN_CH_SEL_bw 8
@@ -582,7 +581,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_in_ch_sel_t;
 
-// Reg - cheshire.slink.raw_mode_out_data_fifo
+// reg - cheshire.slink.raw_mode_out_data_fifo
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO__RAW_MODE_OUT_DATA_FIFO_bm 0xff
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO__RAW_MODE_OUT_DATA_FIFO_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO__RAW_MODE_OUT_DATA_FIFO_bw 8
@@ -595,7 +594,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_out_data_fifo_t;
 
-// Reg - cheshire.slink.raw_mode_out_data_fifo_ctrl
+// reg - cheshire.slink.raw_mode_out_data_fifo_ctrl
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO_CTRL__CLEAR_bm 0x1
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO_CTRL__CLEAR_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_OUT_DATA_FIFO_CTRL__CLEAR_bw 1
@@ -618,7 +617,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_out_data_fifo_ctrl_t;
 
-// Reg - cheshire.slink.raw_mode_out_en
+// reg - cheshire.slink.raw_mode_out_en
 #define CHESHIRE__SLINK__RAW_MODE_OUT_EN__RAW_MODE_OUT_EN_bm 0x1
 #define CHESHIRE__SLINK__RAW_MODE_OUT_EN__RAW_MODE_OUT_EN_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_OUT_EN__RAW_MODE_OUT_EN_bw 1
@@ -631,7 +630,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_out_en_t;
 
-// Reg - cheshire.slink.flow_control_fifo_clear
+// reg - cheshire.slink.flow_control_fifo_clear
 #define CHESHIRE__SLINK__FLOW_CONTROL_FIFO_CLEAR__FLOW_CONTROL_FIFO_CLEAR_bm 0x1
 #define CHESHIRE__SLINK__FLOW_CONTROL_FIFO_CLEAR__FLOW_CONTROL_FIFO_CLEAR_bp 0
 #define CHESHIRE__SLINK__FLOW_CONTROL_FIFO_CLEAR__FLOW_CONTROL_FIFO_CLEAR_bw 1
@@ -644,7 +643,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__flow_control_fifo_clear_t;
 
-// Reg - cheshire.slink.raw_mode_in_data_valid[]
+// reg - cheshire.slink.raw_mode_in_data_valid[]
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA_VALIDX__RAW_MODE_IN_DATA_VALID_bm 0x1
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA_VALIDX__RAW_MODE_IN_DATA_VALID_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_IN_DATA_VALIDX__RAW_MODE_IN_DATA_VALID_bw 1
@@ -656,7 +655,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_in_data_validx_t;
 
-// Reg - cheshire.slink.raw_mode_out_ch_mask[]
+// reg - cheshire.slink.raw_mode_out_ch_mask[]
 #define CHESHIRE__SLINK__RAW_MODE_OUT_CH_MASKX__RAW_MODE_OUT_CH_MASK_bm 0x1
 #define CHESHIRE__SLINK__RAW_MODE_OUT_CH_MASKX__RAW_MODE_OUT_CH_MASK_bp 0
 #define CHESHIRE__SLINK__RAW_MODE_OUT_CH_MASKX__RAW_MODE_OUT_CH_MASK_bw 1
@@ -669,7 +668,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__raw_mode_out_ch_maskx_t;
 
-// Reg - cheshire.slink.tx_phy_clk_div[]
+// reg - cheshire.slink.tx_phy_clk_div[]
 #define CHESHIRE__SLINK__TX_PHY_CLK_DIVX__CLK_DIVS_bm 0x7ff
 #define CHESHIRE__SLINK__TX_PHY_CLK_DIVX__CLK_DIVS_bp 0
 #define CHESHIRE__SLINK__TX_PHY_CLK_DIVX__CLK_DIVS_bw 11
@@ -682,7 +681,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__tx_phy_clk_divx_t;
 
-// Reg - cheshire.slink.tx_phy_clk_start[]
+// reg - cheshire.slink.tx_phy_clk_start[]
 #define CHESHIRE__SLINK__TX_PHY_CLK_STARTX__CLK_DIVS_bm 0x7ff
 #define CHESHIRE__SLINK__TX_PHY_CLK_STARTX__CLK_DIVS_bp 0
 #define CHESHIRE__SLINK__TX_PHY_CLK_STARTX__CLK_DIVS_bw 11
@@ -695,7 +694,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__tx_phy_clk_startx_t;
 
-// Reg - cheshire.slink.tx_phy_clk_end[]
+// reg - cheshire.slink.tx_phy_clk_end[]
 #define CHESHIRE__SLINK__TX_PHY_CLK_ENDX__CLK_SHIFT_END_bm 0x7ff
 #define CHESHIRE__SLINK__TX_PHY_CLK_ENDX__CLK_SHIFT_END_bp 0
 #define CHESHIRE__SLINK__TX_PHY_CLK_ENDX__CLK_SHIFT_END_bw 11
@@ -708,7 +707,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__tx_phy_clk_endx_t;
 
-// Reg - cheshire.slink.channel_alloc_tx_cfg
+// reg - cheshire.slink.channel_alloc_tx_cfg
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CFG__BYPASS_EN_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CFG__BYPASS_EN_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CFG__BYPASS_EN_bw 1
@@ -732,7 +731,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_tx_cfg_t;
 
-// Reg - cheshire.slink.channel_alloc_tx_ctrl
+// reg - cheshire.slink.channel_alloc_tx_ctrl
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CTRL__CLEAR_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CTRL__CLEAR_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CTRL__CLEAR_bw 1
@@ -748,7 +747,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_tx_ctrl_t;
 
-// Reg - cheshire.slink.channel_alloc_rx_cfg
+// reg - cheshire.slink.channel_alloc_rx_cfg
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CFG__BYPASS_EN_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CFG__BYPASS_EN_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CFG__BYPASS_EN_bw 1
@@ -777,7 +776,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_rx_cfg_t;
 
-// Reg - cheshire.slink.channel_alloc_rx_ctrl
+// reg - cheshire.slink.channel_alloc_rx_ctrl
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CTRL__CLEAR_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CTRL__CLEAR_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CTRL__CLEAR_bw 1
@@ -789,7 +788,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_rx_ctrl_t;
 
-// Reg - cheshire.slink.channel_alloc_tx_ch_en[]
+// reg - cheshire.slink.channel_alloc_tx_ch_en[]
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CH_ENX__CHANNEL_ALLOC_TX_CH_EN_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CH_ENX__CHANNEL_ALLOC_TX_CH_EN_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_TX_CH_ENX__CHANNEL_ALLOC_TX_CH_EN_bw 1
@@ -802,7 +801,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_tx_ch_enx_t;
 
-// Reg - cheshire.slink.channel_alloc_rx_ch_en[]
+// reg - cheshire.slink.channel_alloc_rx_ch_en[]
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CH_ENX__CHANNEL_ALLOC_RX_CH_EN_bm 0x1
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CH_ENX__CHANNEL_ALLOC_RX_CH_EN_bp 0
 #define CHESHIRE__SLINK__CHANNEL_ALLOC_RX_CH_ENX__CHANNEL_ALLOC_RX_CH_EN_bw 1
@@ -815,7 +814,7 @@ typedef union {
     uint32_t w;
 } cheshire__slink__channel_alloc_rx_ch_enx_t;
 
-// Addrmap - cheshire.slink
+// addrmap - cheshire.slink
 typedef struct __attribute__ ((__packed__)) {
     cheshire__slink__ctrl_t ctrl;
     cheshire__slink__isolated_t isolated;
@@ -847,7 +846,7 @@ typedef struct __attribute__ ((__packed__)) {
     cheshire__slink__channel_alloc_rx_ch_enx_t channel_alloc_rx_ch_en[1];
 } cheshire__slink_t;
 
-// Reg - cheshire.vga.status
+// reg - cheshire.vga.status
 #define CHESHIRE__VGA__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__VGA__STATUS__STATUS_bp 0
 #define CHESHIRE__VGA__STATUS__STATUS_bw 32
@@ -859,7 +858,7 @@ typedef union {
     uint32_t w;
 } cheshire__vga__status_t;
 
-// Reg - cheshire.vga._end
+// reg - cheshire.vga._end
 #define CHESHIRE__VGA___END___END_bm 0xffffffff
 #define CHESHIRE__VGA___END___END_bp 0
 #define CHESHIRE__VGA___END___END_bw 32
@@ -871,14 +870,14 @@ typedef union {
     uint32_t w;
 } cheshire__vga___end_t;
 
-// Addrmap - cheshire.vga
+// addrmap - cheshire.vga
 typedef struct __attribute__ ((__packed__)) {
     cheshire__vga__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__vga___end_t _end;
 } cheshire__vga_t;
 
-// Reg - cheshire.usb.status
+// reg - cheshire.usb.status
 #define CHESHIRE__USB__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__USB__STATUS__STATUS_bp 0
 #define CHESHIRE__USB__STATUS__STATUS_bw 32
@@ -890,7 +889,7 @@ typedef union {
     uint32_t w;
 } cheshire__usb__status_t;
 
-// Reg - cheshire.usb._end
+// reg - cheshire.usb._end
 #define CHESHIRE__USB___END___END_bm 0xffffffff
 #define CHESHIRE__USB___END___END_bp 0
 #define CHESHIRE__USB___END___END_bw 32
@@ -902,14 +901,14 @@ typedef union {
     uint32_t w;
 } cheshire__usb___end_t;
 
-// Addrmap - cheshire.usb
+// addrmap - cheshire.usb
 typedef struct __attribute__ ((__packed__)) {
     cheshire__usb__status_t status;
     uint8_t RESERVED_4_ffb[0xff8];
     cheshire__usb___end_t _end;
 } cheshire__usb_t;
 
-// Reg - cheshire.bus_err.status
+// reg - cheshire.bus_err.status
 #define CHESHIRE__BUS_ERR__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__BUS_ERR__STATUS__STATUS_bp 0
 #define CHESHIRE__BUS_ERR__STATUS__STATUS_bw 32
@@ -921,7 +920,7 @@ typedef union {
     uint32_t w;
 } cheshire__bus_err__status_t;
 
-// Reg - cheshire.bus_err._end
+// reg - cheshire.bus_err._end
 #define CHESHIRE__BUS_ERR___END___END_bm 0xffffffff
 #define CHESHIRE__BUS_ERR___END___END_bp 0
 #define CHESHIRE__BUS_ERR___END___END_bw 32
@@ -933,14 +932,14 @@ typedef union {
     uint32_t w;
 } cheshire__bus_err___end_t;
 
-// Addrmap - cheshire.bus_err
+// addrmap - cheshire.bus_err
 typedef struct __attribute__ ((__packed__)) {
     cheshire__bus_err__status_t status;
     uint8_t RESERVED_4_3b[0x38];
     cheshire__bus_err___end_t _end;
 } cheshire__bus_err_t;
 
-// Reg - cheshire.plic.status
+// reg - cheshire.plic.status
 #define CHESHIRE__PLIC__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__PLIC__STATUS__STATUS_bp 0
 #define CHESHIRE__PLIC__STATUS__STATUS_bw 32
@@ -952,7 +951,7 @@ typedef union {
     uint32_t w;
 } cheshire__plic__status_t;
 
-// Reg - cheshire.plic._end
+// reg - cheshire.plic._end
 #define CHESHIRE__PLIC___END___END_bm 0xffffffff
 #define CHESHIRE__PLIC___END___END_bp 0
 #define CHESHIRE__PLIC___END___END_bw 32
@@ -964,14 +963,14 @@ typedef union {
     uint32_t w;
 } cheshire__plic___end_t;
 
-// Addrmap - cheshire.plic
+// addrmap - cheshire.plic
 typedef struct __attribute__ ((__packed__)) {
     cheshire__plic__status_t status;
     uint8_t RESERVED_4_3fffffb[0x3fffff8];
     cheshire__plic___end_t _end;
 } cheshire__plic_t;
 
-// Reg - cheshire.clic.status
+// reg - cheshire.clic.status
 #define CHESHIRE__CLIC__STATUS__STATUS_bm 0xffffffff
 #define CHESHIRE__CLIC__STATUS__STATUS_bp 0
 #define CHESHIRE__CLIC__STATUS__STATUS_bw 32
@@ -983,7 +982,7 @@ typedef union {
     uint32_t w;
 } cheshire__clic__status_t;
 
-// Reg - cheshire.clic._end
+// reg - cheshire.clic._end
 #define CHESHIRE__CLIC___END___END_bm 0xffffffff
 #define CHESHIRE__CLIC___END___END_bp 0
 #define CHESHIRE__CLIC___END___END_bw 32
@@ -995,29 +994,29 @@ typedef union {
     uint32_t w;
 } cheshire__clic___end_t;
 
-// Addrmap - cheshire.clic
+// addrmap - cheshire.clic
 typedef struct __attribute__ ((__packed__)) {
     cheshire__clic__status_t status;
     uint8_t RESERVED_4_3fffb[0x3fff8];
     cheshire__clic___end_t _end;
 } cheshire__clic_t;
 
-// Mem - cheshire.spm
+// mem - cheshire.spm
 typedef struct __attribute__ ((__packed__)) {
     uint32_t mem[16384];
 } cheshire__spm_t;
 
-// Mem - cheshire.spm_unc
+// mem - cheshire.spm_unc
 typedef struct __attribute__ ((__packed__)) {
     uint32_t mem[16777216];
 } cheshire__spm_unc_t;
 
-// Mem - cheshire.dram
+// mem - cheshire.dram
 typedef struct __attribute__ ((__packed__)) {
     uint32_t mem[2097152];
 } cheshire__dram_t;
 
-// Addrmap - cheshire
+// addrmap - cheshire
 typedef struct __attribute__ ((__packed__)) {
     cheshire__extrom_t extrom;
     uint8_t RESERVED_40000_ffffff[0xfc0000];
diff --git a/uv.lock b/uv.lock
index c3309bf02..5bdf86554 100644
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