diff --git a/Bender.yml b/Bender.yml
index ea8f550b..ccce57fa 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -51,7 +51,7 @@ sources:
   - rtl/rel_rr_arb_tree.sv
   - rtl/rel_spill_register.sv
 
-  - target: any(deprecated, axi_ecc, hci_ecc, pulp_ecc, test)
+  - target: any(deprecated, axi_ecc, hci_ecc, pulp_ecc, redundancy_cells_test)
     files:
       - rtl/ecc_concat_32_64.sv
       - rtl/lowrisc_ecc/prim_secded_pkg.sv
@@ -104,7 +104,7 @@ sources:
       - rtl/pulpissimo_tcls
     files:
       - rtl/pulpissimo_tcls/TCLS_unit.sv
-  - target: test
+  - target: redundancy_cells_test
     files:
       - test/tb_ecc_scrubber.sv
       - test/tb_ecc_secded.sv
diff --git a/rtl/HMR/hmr_unit.sv b/rtl/HMR/hmr_unit.sv
index bbabbce5..0695fa1e 100644
--- a/rtl/HMR/hmr_unit.sv
+++ b/rtl/HMR/hmr_unit.sv
@@ -921,8 +921,6 @@ module hmr_unit #(
      *** DMR only ***
      *****************/
     if (DMRFixed && NumCores % 2 != 0) $warning("Extra cores added not properly handled! :)");
-    // Binding DMR outputs to zero for now
-    assign dmr_failure_o     = '0;
 
     for (genvar i = 0; i < NumCores; i++) begin : gen_core_inputs
       localparam int unsigned SysCoreIndex = DMRFixed ? i/2 : dmr_core_id(dmr_group_id(i), 0);
diff --git a/run_tests.sh b/run_tests.sh
index 9afbaa8c..4fcd959d 100755
--- a/run_tests.sh
+++ b/run_tests.sh
@@ -18,7 +18,7 @@ set -e
 
 VSIM_LOGFILE=vsim.log
 
-bender script vsim -t test -t rtl --vlog-arg="-svinputport=compat" -t deprecated > compile.tcl
+bender script vsim -t redundancy_cells_test -t rtl --vlog-arg="-svinputport=compat" -t deprecated > compile.tcl
 echo "return 0" >> compile.tcl
 
 $VSIM -c -do 'quit -code [source compile.tcl]' > vcom.log