diff --git a/p/riscv_test.h b/p/riscv_test.h
index 3d4637a..5b44fec 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -57,6 +57,16 @@
   RVTEST_ENABLE_SUPERVISOR;                                             \
   .endm
 
+#define RVTEST_RV64VS                                                   \
+  .macro init;                                                          \
+  RVTEST_ENABLE_VIRTUAL_SUPERVISOR;                                     \
+  .endm
+
+#define RVTEST_RV64VU                                                   \
+  .macro init;                                                          \
+  RVTEST_ENABLE_VIRTUAL_USER;                                           \
+  .endm
+
 #define RVTEST_RV32M                                                    \
   .macro init;                                                          \
   RVTEST_ENABLE_MACHINE;                                                \
@@ -67,6 +77,16 @@
   RVTEST_ENABLE_SUPERVISOR;                                             \
   .endm
 
+#define RVTEST_RV32VS                                                   \
+  .macro init;                                                          \
+  RVTEST_ENABLE_VIRTUAL_SUPERVISOR;                                     \
+  .endm
+
+#define RVTEST_RV32VU                                                   \
+  .macro init;                                                          \
+  RVTEST_ENABLE_VIRTUAL_USER;                                           \
+  .endm
+
 #if __riscv_xlen == 64
 # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
 #else
@@ -124,10 +144,17 @@
   .align 2;                                                             \
 1:
 
-#define INIT_SATP                                                      \
+#define INIT_SATP                                                       \
   la t0, 1f;                                                            \
   csrw mtvec, t0;                                                       \
-  csrwi satp, 0;                                                       \
+  csrwi satp, 0;                                                        \
+  .align 2;                                                             \
+1:
+
+#define INIT_HGATP                                                      \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi hgatp, 0;                                                       \
   .align 2;                                                             \
 1:
 
@@ -138,7 +165,58 @@
   csrwi medeleg, 0;                                                     \
   csrwi mideleg, 0;                                                     \
   .align 2;                                                             \
-1:
+1:                                                                      \
+  la t0, 2f;                                                            \
+  csrw mtvec, t0;                                                       \
+  csrwi hie, 0;                                                         \
+  csrwi hedeleg, 0;                                                     \
+  csrwi hideleg, 0;                                                     \
+  .align 2;                                                             \
+2:
+
+#if __riscv_xlen == 64
+#define SET_MPV                                                         \
+  li a0, MSTATUS_MPV;                                                   \
+  csrs mstatus, a0;
+#else
+#define SET_MPV                                                         \
+  li a0, MSTATUSH_MPV;                                                  \
+  csrs mstatush, a0;
+#endif
+
+#define RVTEST_ENABLE_VIRTUAL_USER_FROM_HS                              \
+  li a0, HSTATUS_SPV;                                                   \
+  csrs hstatus, a0;                                                     \
+  li a0, SSTATUS_SPP;                                                   \
+  csrc sstatus, a0;                                                     \
+
+#define RVTEST_ENABLE_VIRTUAL_SUPERVISOR_FROM_HS                        \
+  li a0, HSTATUS_SPV;                                                   \
+  csrs hstatus, a0;                                                     \
+  li a0, SSTATUS_SPP;                                                   \
+  csrs sstatus, a0;                                                     \
+
+#define RVTEST_ENABLE_VIRTUAL_USER                                      \
+  li a0, MSTATUS_MPP;                                                   \
+  csrc mstatus, a0;                                                     \
+  SET_MPV                                                               \
+  li a0, MIP_VSSIP | MIP_VSTIP;                                         \
+  csrs hideleg, a0;                                                     \
+
+#define RVTEST_ENABLE_VIRTUAL_SUPERVISOR                                \
+  li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
+  csrs mstatus, a0;                                                     \
+  SET_MPV                                                               \
+  li a0, MIP_VSSIP | MIP_VSTIP;                                         \
+  csrs hideleg, a0;                                                     \
+
+#define RVTEST_ENABLE_USER_FROM_SUPERVISOR                              \
+  li a0, SSTATUS_SPP;                                                   \
+  csrc sstatus, a0;                                                     \
+
+#define RVTEST_ENABLE_USER                                              \
+  li a0, MSTATUS_MPP;                                                   \
+  csrc mstatus, a0;                                                     \
 
 #define RVTEST_ENABLE_SUPERVISOR                                        \
   li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1);                              \
@@ -197,6 +275,8 @@ trap_vector:                                                            \
         beq t5, t6, write_tohost;                                       \
         li t6, CAUSE_SUPERVISOR_ECALL;                                  \
         beq t5, t6, write_tohost;                                       \
+        li t6, CAUSE_VIRTUAL_SUPERVISOR_ECALL;                          \
+        beq t5, t6, write_tohost;                                       \
         li t6, CAUSE_MACHINE_ECALL;                                     \
         beq t5, t6, write_tohost;                                       \
         /* if an mtvec_handler is defined, jump to it */                \
@@ -221,6 +301,7 @@ reset_vector:                                                           \
         RISCV_MULTICORE_DISABLE;                                        \
         INIT_RNMI;                                                      \
         INIT_SATP;                                                      \
+        INIT_HGATP;                                                     \
         INIT_PMP;                                                       \
         DELEGATE_NO_TRAPS;                                              \
         li TESTNUM, 0;                                                  \
@@ -231,11 +312,14 @@ reset_vector:                                                           \
         la t0, stvec_handler;                                           \
         beqz t0, 1f;                                                    \
         csrw stvec, t0;                                                 \
-        li t0, (1 << CAUSE_LOAD_PAGE_FAULT) |                           \
-               (1 << CAUSE_STORE_PAGE_FAULT) |                          \
-               (1 << CAUSE_FETCH_PAGE_FAULT) |                          \
-               (1 << CAUSE_MISALIGNED_FETCH) |                          \
-               (1 << CAUSE_USER_ECALL) |                                \
+        li t0, (1 << CAUSE_LOAD_PAGE_FAULT)         |                   \
+               (1 << CAUSE_LOAD_GUEST_PAGE_FAULT)   |                   \
+               (1 << CAUSE_FETCH_PAGE_FAULT)        |                   \
+               (1 << CAUSE_FETCH_GUEST_PAGE_FAULT)  |                   \
+               (1 << CAUSE_STORE_PAGE_FAULT)        |                   \
+               (1 << CAUSE_STORE_GUEST_PAGE_FAULT)  |                   \
+               (1 << CAUSE_MISALIGNED_FETCH)        |                   \
+               (1 << CAUSE_USER_ECALL)              |                   \
                (1 << CAUSE_BREAKPOINT);                                 \
         csrw medeleg, t0;                                               \
 1:      csrwi mstatus, 0;                                               \