From d24ca82dd625481e4b61d570b2234c42713780d1 Mon Sep 17 00:00:00 2001 From: "riseproject-dev[bot]" <330740410+riseproject-dev[bot]@users.noreply.github.com> Date: Sat, 10 Oct 2026 09:25:44 +0000 Subject: [PATCH 1/2] lance-context: Add versions 0.6.6, 0.6.7 Signed-off-by: riseproject-dev[bot] <330740410+riseproject-dev[bot]@users.noreply.github.com> --- docs/packages/lance-context.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/packages/lance-context.yaml b/docs/packages/lance-context.yaml index 2d30330f8a70..595efbc03092 100644 --- a/docs/packages/lance-context.yaml +++ b/docs/packages/lance-context.yaml @@ -9,3 +9,5 @@ versions: - filename: lance_context-0.6.5-cp39-abi3-manylinux_2_39_riscv64.whl sha256: 92d24bb5ae04b93a78c2a04c35b8718f2dd1befa470916b8bb733d24959b1065 requires-python: '>=3.11, <3.14' +- version: 0.6.6 +- version: 0.6.7 From 577a8c1d6d5df9dce84a81cc23234d0ba91153d3 Mon Sep 17 00:00:00 2001 From: Ludovic Henry Date: Tue, 13 Oct 2026 00:58:35 +0000 Subject: [PATCH 2/2] lance-context: add patches for 0.6.6 and 0.6.7 The nightly version bump added 0.6.6/0.6.7 without patch directories, so both builds failed at "Apply lance-context patches". Copying 0.6.5's set forward is not enough: from 0.6.6 on, crates/lance-context-core depends on `lance = "9.0.0"` directly while `lancedb = "0.30.0"` still pulls in the 7.0.0 line, so both lines of lance-core/lance-linalg are compiled and both lack a riscv64 SIMD fallback. - 0001: rebased onto the new Cargo.toml context. - 0002/0004: unchanged (lance-core/lance-linalg 7.0.0). - 0005/0006: the same fallbacks rebased onto the 9.0.0 crates. - 0003: redirects all four crates via [patch.crates-io], the 7.0.0 pair under renamed `package =` keys (Cargo's way of patching more than one semver-incompatible version of a crate). The workflow vendors and patches the 9.0.0 pair when 0005 is present, so 0.6.5 builds as before. 0.6.6's tests/conftest.py also turns the missing lance-context-server binary into a hard failure when CI is set (it used to skip), so pytest runs with CI unset to keep the skip. --- .github/workflows/build-lance-context.yml | 24 +- ...remove-unused-lance-graph-dependency.patch | 38 + ...002-lance-core-riscv64-simd-fallback.patch | 45 + ...cargo-patch-lance-crates-for-riscv64.patch | 101 ++ ...4-lance-linalg-riscv64-simd-fallback.patch | 1435 +++++++++++++++++ ...nce-core-9.0.0-riscv64-simd-fallback.patch | 49 + ...e-linalg-9.0.0-riscv64-simd-fallback.patch | 1434 ++++++++++++++++ ...remove-unused-lance-graph-dependency.patch | 38 + ...002-lance-core-riscv64-simd-fallback.patch | 45 + ...cargo-patch-lance-crates-for-riscv64.patch | 101 ++ ...4-lance-linalg-riscv64-simd-fallback.patch | 1435 +++++++++++++++++ ...nce-core-9.0.0-riscv64-simd-fallback.patch | 49 + ...e-linalg-9.0.0-riscv64-simd-fallback.patch | 1434 ++++++++++++++++ 13 files changed, 6226 insertions(+), 2 deletions(-) create mode 100644 patches/lance-context/0.6.6/0001-remove-unused-lance-graph-dependency.patch create mode 100644 patches/lance-context/0.6.6/0002-lance-core-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.6/0003-cargo-patch-lance-crates-for-riscv64.patch create mode 100644 patches/lance-context/0.6.6/0004-lance-linalg-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.6/0005-lance-core-9.0.0-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.6/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.7/0001-remove-unused-lance-graph-dependency.patch create mode 100644 patches/lance-context/0.6.7/0002-lance-core-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.7/0003-cargo-patch-lance-crates-for-riscv64.patch create mode 100644 patches/lance-context/0.6.7/0004-lance-linalg-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.7/0005-lance-core-9.0.0-riscv64-simd-fallback.patch create mode 100644 patches/lance-context/0.6.7/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch diff --git a/.github/workflows/build-lance-context.yml b/.github/workflows/build-lance-context.yml index 525c7df9c62f..08fbcb147978 100644 --- a/.github/workflows/build-lance-context.yml +++ b/.github/workflows/build-lance-context.yml @@ -111,6 +111,23 @@ jobs: rm lance-linalg.tar.gz patch -p1 -d lance-linalg-7.0.0-riscv64 < python-wheels/patches/lance-context/${{ env.LANCE_CONTEXT_VERSION }}/0004-lance-linalg-riscv64-simd-fallback.patch + # From 0.6.6 on, crates/lance-context-core depends on `lance = "9.0.0"` + # directly while `lancedb = "0.30.0"` still pulls in the 7.0.0 line, + # so both lines get compiled and both need a riscv64-fixed copy; the + # 9.0.0 pair's patches (0005/0006) exist only in those versions' dirs. + PATCHES=python-wheels/patches/lance-context/${{ env.LANCE_CONTEXT_VERSION }} + if [ -f "$PATCHES/0005-lance-core-9.0.0-riscv64-simd-fallback.patch" ]; then + for crate in lance-core:0005 lance-linalg:0006; do + name=${crate%%:*} + num=${crate##*:} + curl -fsSL -A "python-wheels (https://github.com/riseproject-dev/python-wheels)" -o "$name.tar.gz" "https://crates.io/api/v1/crates/$name/9.0.0/download" + mkdir "$name-9.0.0-riscv64" + tar xzf "$name.tar.gz" -C "$name-9.0.0-riscv64" --strip-components=1 + rm "$name.tar.gz" + patch -p1 -d "$name-9.0.0-riscv64" < "$PATCHES/$num-$name-9.0.0-riscv64-simd-fallback.patch" + done + fi + git apply python-wheels/patches/lance-context/${{ env.LANCE_CONTEXT_VERSION }}/0003-cargo-patch-lance-crates-for-riscv64.patch - name: Free disk space @@ -172,10 +189,13 @@ jobs: # `pytest -v` from python/, no extra flags). test_rollout_remote.py # skips itself when target/debug/lance-context-server hasn't been # built, which it isn't here (that crate is a workspace member - # neither the Python wheel nor its tests otherwise need). + # neither the Python wheel nor its tests otherwise need). From 0.6.6 + # on that check lives in tests/conftest.py's `server` fixture and + # turns into a hard failure whenever `CI` is set, so `CI` is unset + # for pytest to keep the same skip. CIBW_TEST_COMMAND: >- cd python && - python -m pytest tests -v + env -u CI python -m pytest tests -v - uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a # v7.0.1 with: diff --git a/patches/lance-context/0.6.6/0001-remove-unused-lance-graph-dependency.patch b/patches/lance-context/0.6.6/0001-remove-unused-lance-graph-dependency.patch new file mode 100644 index 000000000000..729698df5774 --- /dev/null +++ b/patches/lance-context/0.6.6/0001-remove-unused-lance-graph-dependency.patch @@ -0,0 +1,38 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-context-core: drop the unused lance-graph dependency + +crates/lance-context-core/Cargo.toml depends on `lance-graph = "0.5.4"`, +but no Rust source file in this workspace imports `lance_graph` +(`grep -rln lance_graph crates/ python/` matches nothing); it is dead +weight in the dependency graph. lance-graph's own Cargo.toml pins +`lance`/`lance-core`/`lance-linalg` at an incompatible `1.x` line, which +Cargo resolves as yet another parallel copy of the whole lance-core/ +lance-linalg family, alongside the `9.0.0` one crates/lance-context-core +depends on directly (`lance = "9.0.0"`) and the `7.0.0` one +`lancedb = "0.30.0"` still pulls in. That `1.x` copy's lance-core +SIMD_SUPPORT closure and lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 +SIMD types have no riscv64 fallback either, so it would need its own +riscv64-patched copy (see 0003-cargo-patch-lance-crates-for-riscv64.patch) +just to compile a crate nothing uses. Removing the dead dependency +drops that whole copy from resolution instead. + +Upstream-Status: To upstream [not yet submitted to lance-format/lance-context] + +Signed-off-by: Ludovic Henry +--- +diff --git a/crates/lance-context-core/Cargo.toml b/crates/lance-context-core/Cargo.toml +index 55f7dce..9c2311a 100644 +--- a/crates/lance-context-core/Cargo.toml ++++ b/crates/lance-context-core/Cargo.toml +@@ -31,7 +31,6 @@ lance-context-api = { version = "0.6.6", path = "../lance-context-api" } + lance-index = "9.0.0" + lance-namespace = "9.0.0" + lancedb = "0.30.0" +-lance-graph = "0.5.4" + # Version-matched with lance-context-server/-master so one process-wide recorder + # serves every crate. + metrics = { version = "0.24", optional = true } +-- +2.43.0 diff --git a/patches/lance-context/0.6.6/0002-lance-core-riscv64-simd-fallback.patch b/patches/lance-context/0.6.6/0002-lance-core-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..58c2f4f76bd5 --- /dev/null +++ b/patches/lance-context/0.6.6/0002-lance-core-riscv64-simd-fallback.patch @@ -0,0 +1,45 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Mon, 06 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-core: add a portable riscv64 SIMD-tier fallback + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) picks a SIMD tier +via a `cfg`-gated closure with arms for aarch64, x86_64 and loongarch64 +only; none of them match riscv64, so the closure's block has no +trailing expression there and the crate fails to compile with "expected +`SimdSupport`, found `()`". Add a `None`-tier fallback arm beside the +existing ones for every architecture without a dedicated tier. + +Applied (via patches/lance-context/0.6.5/0003-cargo-patch-lance-crates-for-riscv64.patch) +to a local copy of this crate's 7.0.0 crates.io release, which +crates/lance-context-core's `lance = "7.0.0"` pulls in transitively +and cannot be patched in place (CLAUDE.md gotcha 300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/utils/cpu.rs b/src/utils/cpu.rs +index 4e7ab01..34ed3a0 100644 +--- a/src/utils/cpu.rs ++++ b/src/utils/cpu.rs +@@ -58,6 +58,17 @@ pub static SIMD_SUPPORT: LazyLock = LazyLock::new(|| { + SimdSupport::None + } + } ++ // riscv64 (and any other architecture without a dedicated tier above) has ++ // no SIMD kernels in lance yet; upstream's cfg arms have no catch-all, so ++ // this closure otherwise evaluates to `()` here instead of `SimdSupport`. ++ #[cfg(not(any( ++ target_arch = "aarch64", ++ target_arch = "x86_64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ SimdSupport::None ++ } + }); + + #[cfg(target_arch = "x86_64")] +-- +2.43.0 diff --git a/patches/lance-context/0.6.6/0003-cargo-patch-lance-crates-for-riscv64.patch b/patches/lance-context/0.6.6/0003-cargo-patch-lance-crates-for-riscv64.patch new file mode 100644 index 000000000000..77685502de3a --- /dev/null +++ b/patches/lance-context/0.6.6/0003-cargo-patch-lance-crates-for-riscv64.patch @@ -0,0 +1,101 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] cargo: redirect lance-core/lance-linalg to riscv64-patched + checkouts + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) and lance-linalg's +f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types (src/simd/{f32,i32,f64}.rs) +are compiled for x86_64/aarch64/loongarch64 only, with no fallback arm +for any other architecture (CLAUDE.md gotcha 300): the SIMD_SUPPORT +closure has no trailing expression on riscv64 ("expected SimdSupport, +found ()"), and the SIMD type structs are defined only under those +three `#[cfg(target_arch = ...)]` attributes while every method +implementing them is unconditional, so riscv64 hits "cannot find type +`f32x8` in this scope" as soon as lance-linalg is built. + +Two semver-incompatible lines of both crates are compiled here: 9.0.0, +via crates/lance-context-core's direct `lance = "9.0.0"`, and 7.0.0, +which `lancedb = "0.30.0"` (and lance-namespace-impls 7.0.0 under it) +still pulls in. (lance-graph's own, unused `1.x` copy is dropped +entirely by 0001-remove-unused-lance-graph-dependency.patch instead.) +Redirect all four to the riscv64-patched copies the workflow +materializes at build time from the pinned crates.io releases (see +0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch for 7.0.0 +and 0005/0006-lance-{core,linalg}-9.0.0-riscv64-simd-fallback.patch +for 9.0.0). The 7.0.0 pair is listed under renamed keys with +`package = ...`, which is how Cargo's [patch] table accepts more than +one semver-incompatible version of the same crate. Each copy is at the +same version Cargo.lock already pins -- only the `source`/`checksum` +lines of those four entries change there, so every other dependency +stays pinned exactly as upstream released it. + +Upstream-Status: Inappropriate [redirects pinned dependencies to local checkouts materialized at build time; the fix itself belongs in lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/Cargo.lock b/Cargo.lock +index ac263f7..d87b7b3 100644 +--- a/Cargo.lock ++++ b/Cargo.lock +@@ -6491,8 +6491,6 @@ dependencies = [ + [[package]] + name = "lance-core" + version = "7.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "13f84020da5a484e2f07dd1796e09785ed7cd889857ebc4cb77e32ef214ee594" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -6528,8 +6526,6 @@ dependencies = [ + [[package]] + name = "lance-core" + version = "9.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "238c8a58308e7718d6bd96b53494eb7953fa299778bc4911cc571c3576e9446d" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -7387,8 +7383,6 @@ dependencies = [ + [[package]] + name = "lance-linalg" + version = "7.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "6b4c51cad0ac780b02dc4da48528479e7693c03e8d05390510bbc69ca2a9a1f1" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -7405,8 +7399,6 @@ dependencies = [ + [[package]] + name = "lance-linalg" + version = "9.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "0e5a9b99bd1f49bc2fe5afb81323141abc506c818f589de95dbab4f6143d9a88" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +diff --git a/Cargo.toml b/Cargo.toml +index 2efab19..e85f652 100644 +--- a/Cargo.toml ++++ b/Cargo.toml +@@ -17,3 +17,18 @@ license = "Apache-2.0" + + [workspace.metadata] + # reserved for future use ++ ++# lance-core's SIMD_SUPPORT static and lance-linalg's f32x8/f32x16/i32x8/ ++# f64x4/f64x8 SIMD types compile only for x86_64/aarch64/loongarch64 ++# upstream (CLAUDE.md gotcha 300); the riscv64-patched copies below are ++# materialized from the pinned crates.io releases by the workflow at ++# build time. Both the 9.0.0 line (crates/lance-context-core's direct ++# `lance = "9.0.0"`) and the 7.0.0 line (still pulled in by ++# `lancedb = "0.30.0"`) are compiled, so each is redirected; the second ++# pair uses renamed `package =` keys, which is how Cargo's [patch] table ++# takes more than one semver-incompatible version of the same crate. ++[patch.crates-io] ++lance-core = { path = "lance-core-9.0.0-riscv64" } ++lance-linalg = { path = "lance-linalg-9.0.0-riscv64" } ++lance-core-7 = { package = "lance-core", path = "lance-core-7.0.0-riscv64" } ++lance-linalg-7 = { package = "lance-linalg", path = "lance-linalg-7.0.0-riscv64" } +-- +2.43.0 diff --git a/patches/lance-context/0.6.6/0004-lance-linalg-riscv64-simd-fallback.patch b/patches/lance-context/0.6.6/0004-lance-linalg-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..3aaf5e355308 --- /dev/null +++ b/patches/lance-context/0.6.6/0004-lance-linalg-riscv64-simd-fallback.patch @@ -0,0 +1,1435 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Mon, 06 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-linalg: add a portable riscv64 SIMD fallback + +lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types +(src/simd/{f32,f64,i32}.rs) are defined, and every trait impl for them +written, only under `#[cfg(target_arch = "x86_64"/"aarch64"/ +"loongarch64")]` -- unlike u8x16/u8x32 (src/simd/u8.rs), which already +carry a portable fallback. riscv64 hits "cannot find type `f32x8` in +this scope" as soon as lance-linalg (a dependency of lance, which +crates/lance-context-core depends on directly) is built. Add the same +shape of fallback for the three missing types: an array-backed struct +plus a scalar implementation of every method the SIMD/FloatSimd traits +require, gated `#[cfg(not(any(target_arch = "x86_64", target_arch = +"aarch64", target_arch = "loongarch64")))]` beside the existing +per-architecture arms, which are otherwise untouched. Add/Sub/Mul on +i32x8 use wrapping arithmetic to match the silent-wraparound semantics +of the SIMD instructions they replace. + +Applied (via patches/lance-context/0.6.5/0003-cargo-patch-lance-crates-for-riscv64.patch) +to a local copy of this crate's 7.0.0 crates.io release, which +crates/lance-context-core's `lance = "7.0.0"` pulls in transitively +and cannot be patched in place (CLAUDE.md gotcha 300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/simd/f32.rs b/src/simd/f32.rs +index 7804299..e219e0e 100644 +--- a/src/simd/f32.rs ++++ b/src/simd/f32.rs +@@ -35,6 +35,17 @@ pub struct f32x8(float32x4x2_t); + #[derive(Clone, Copy)] + pub struct f32x8(v8f32); + ++/// 8 of 32-bit `f32` values. Portable scalar fallback for architectures with ++/// no dedicated SIMD tier above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x8([f32; 8]); ++ + impl std::fmt::Debug for f32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 8]; +@@ -91,6 +102,27 @@ impl f32x8 { + ]; + Self::load_unaligned(values.as_ptr()) + } ++ ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ let ptr = slice.as_ptr(); ++ ++ let values = [ ++ *ptr.add(indices[0] as usize), ++ *ptr.add(indices[1] as usize), ++ *ptr.add(indices[2] as usize), ++ *ptr.add(indices[3] as usize), ++ *ptr.add(indices[4] as usize), ++ *ptr.add(indices[5] as usize), ++ *ptr.add(indices[6] as usize), ++ *ptr.add(indices[7] as usize), ++ ]; ++ Self::load_unaligned(values.as_ptr()) ++ } + } + } + +@@ -120,6 +152,14 @@ impl SIMD for f32x8 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_w(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + fn zeros() -> Self { +@@ -135,6 +175,14 @@ impl SIMD for f32x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -151,6 +199,14 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -167,6 +223,18 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f32) { +@@ -182,6 +250,14 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f32) { +@@ -197,6 +273,16 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -225,6 +311,14 @@ impl SIMD for f32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f32 { +@@ -259,6 +353,14 @@ impl SIMD for f32x8 { + let m2 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m2))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -277,6 +379,18 @@ impl SIMD for f32x8 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -310,6 +424,18 @@ impl SIMD for f32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -329,6 +455,16 @@ impl FloatSimd for f32x8 { + unsafe { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -352,6 +488,18 @@ impl Add for f32x8 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -371,6 +519,16 @@ impl AddAssign for f32x8 { + unsafe { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -394,6 +552,18 @@ impl Sub for f32x8 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -413,6 +583,16 @@ impl SubAssign for f32x8 { + unsafe { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -436,6 +616,18 @@ impl Mul for f32x8 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -461,6 +653,16 @@ pub struct f32x16(float32x4x4_t); + #[derive(Clone, Copy)] + pub struct f32x16(v8f32, v8f32); + ++/// 16 of 32-bit `f32` values. Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x16([f32; 16]); ++ + impl std::fmt::Debug for f32x16 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 16]; +@@ -510,6 +712,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvreplgr2vr_w(transmute(val))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 16]) ++ } + } + + #[inline] +@@ -530,6 +740,14 @@ impl SIMD for f32x16 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 16]) ++ } + } + + #[inline] +@@ -553,6 +771,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -576,6 +802,18 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -598,6 +836,14 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -620,6 +866,16 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> f32 { +@@ -653,6 +909,14 @@ impl SIMD for f32x16 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -691,6 +955,14 @@ impl SIMD for f32x16 { + let m1 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m1))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + #[inline] +@@ -716,6 +988,18 @@ impl SIMD for f32x16 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0), lasx_xvfmin_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -768,6 +1052,19 @@ impl SIMD for f32x16 { + } + None + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ None ++ } + } + } + +@@ -795,6 +1092,16 @@ impl FloatSimd for f32x16 { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_s(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -824,6 +1131,18 @@ impl Add for f32x16 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0), lasx_xvfadd_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -851,6 +1170,16 @@ impl AddAssign for f32x16 { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + self.1 = lasx_xvfadd_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -880,6 +1209,18 @@ impl Mul for f32x16 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0), lasx_xvfmul_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -909,6 +1250,18 @@ impl Sub for f32x16 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0), lasx_xvfsub_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -936,6 +1289,16 @@ impl SubAssign for f32x16 { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + self.1 = lasx_xvfsub_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/f64.rs b/src/simd/f64.rs +index 32c0d38..a057bf7 100644 +--- a/src/simd/f64.rs ++++ b/src/simd/f64.rs +@@ -33,6 +33,17 @@ pub struct f64x4(float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x4(v4f64); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x4([f64; 4]); ++ + impl std::fmt::Debug for f64x4 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 4]; +@@ -69,6 +80,14 @@ impl SIMD for f64x4 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_d(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 4]) ++ } + } + + fn zeros() -> Self { +@@ -84,6 +103,14 @@ impl SIMD for f64x4 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 4]) ++ } + } + + #[inline] +@@ -100,6 +127,14 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -116,6 +151,18 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f64) { +@@ -131,6 +178,14 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f64) { +@@ -146,6 +201,16 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -169,6 +234,14 @@ impl SIMD for f64x4 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f64 { +@@ -194,6 +267,14 @@ impl SIMD for f64x4 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -212,6 +293,18 @@ impl SIMD for f64x4 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -241,6 +334,16 @@ impl FloatSimd for f64x4 { + unsafe { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -264,6 +367,18 @@ impl Add for f64x4 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -283,6 +398,16 @@ impl AddAssign for f64x4 { + unsafe { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -306,6 +431,18 @@ impl Sub for f64x4 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -325,6 +462,16 @@ impl SubAssign for f64x4 { + unsafe { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -348,6 +495,18 @@ impl Mul for f64x4 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -376,6 +535,16 @@ pub struct f64x8(float64x2x2_t, float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x8(v4f64, v4f64); + ++/// Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x8([f64; 8]); ++ + impl std::fmt::Debug for f64x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 8]; +@@ -419,6 +588,14 @@ impl SIMD for f64x8 { + let v = transmute(lasx_xvreplgr2vr_d(transmute(val))); + Self(v, v) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -439,6 +616,14 @@ impl SIMD for f64x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -462,6 +647,14 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -485,6 +678,18 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -508,6 +713,14 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -531,6 +744,16 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> f64 { +@@ -557,6 +780,14 @@ impl SIMD for f64x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -588,6 +819,14 @@ impl SIMD for f64x8 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + #[inline] +@@ -611,6 +850,18 @@ impl SIMD for f64x8 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0), lasx_xvfmin_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -649,6 +900,16 @@ impl FloatSimd for f64x8 { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_d(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -676,6 +937,18 @@ impl Add for f64x8 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0), lasx_xvfadd_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -703,6 +976,16 @@ impl AddAssign for f64x8 { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + self.1 = lasx_xvfadd_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -730,6 +1013,18 @@ impl Mul for f64x8 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0), lasx_xvfmul_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -757,6 +1052,18 @@ impl Sub for f64x8 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0), lasx_xvfsub_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -784,6 +1091,16 @@ impl SubAssign for f64x8 { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + self.1 = lasx_xvfsub_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/i32.rs b/src/simd/i32.rs +index fa8cdaf..60e5202 100644 +--- a/src/simd/i32.rs ++++ b/src/simd/i32.rs +@@ -30,6 +30,17 @@ pub struct i32x8(int32x4x2_t); + #[derive(Clone, Copy)] + pub struct i32x8(v8i32); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct i32x8(pub(crate) [i32; 8]); ++ + impl std::fmt::Debug for i32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0; 8]; +@@ -67,6 +78,14 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvreplgr2vr_w(val)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -83,6 +102,14 @@ impl SIMD for i32x8 { + { + Self::splat(0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0; 8]) ++ } + } + + #[inline] +@@ -99,6 +126,14 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -115,6 +150,18 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -135,6 +182,16 @@ impl SIMD for i32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> i32 { +@@ -151,6 +208,14 @@ impl SIMD for i32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> i32 { +@@ -173,6 +238,18 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvmin_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: i32) -> Option { +@@ -206,6 +283,18 @@ impl SIMD for i32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -230,6 +319,18 @@ impl Add for i32x8 { + unsafe { + Self(lasx_xvadd_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -249,6 +350,16 @@ impl AddAssign for i32x8 { + unsafe { + self.0 = lasx_xvadd_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ } + } + } + +@@ -272,6 +383,18 @@ impl Sub for i32x8 { + unsafe { + Self(lasx_xvsub_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -291,6 +414,16 @@ impl SubAssign for i32x8 { + unsafe { + self.0 = lasx_xvsub_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ } + } + } + +@@ -314,6 +447,18 @@ impl Mul for i32x8 { + unsafe { + Self(lasx_xvmul_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_mul(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +-- +2.43.0 diff --git a/patches/lance-context/0.6.6/0005-lance-core-9.0.0-riscv64-simd-fallback.patch b/patches/lance-context/0.6.6/0005-lance-core-9.0.0-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..cd28a4aab117 --- /dev/null +++ b/patches/lance-context/0.6.6/0005-lance-core-9.0.0-riscv64-simd-fallback.patch @@ -0,0 +1,49 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-core: add a portable riscv64 SIMD-tier fallback (9.0.0) + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) picks a SIMD tier +via a `cfg`-gated closure with arms for aarch64, x86_64 and loongarch64 +only; none of them match riscv64, so the closure's block has no +trailing expression there and the crate fails to compile with "expected +`SimdSupport`, found `()`". Add a `None`-tier fallback arm beside the +existing ones for every architecture without a dedicated tier. + +Same change as 0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch +(which target this crate's 7.0.0 release), rebased onto the 9.0.0 +crates.io release that crates/lance-context-core's `lance = "9.0.0"` +pulls in; the fallback arms themselves are unchanged. Applied (via +0003-cargo-patch-lance-crates-for-riscv64.patch) to a local copy of +lance-core 9.0.0 materialized by the workflow, since it is a transitive +crates.io dependency and cannot be patched in place (CLAUDE.md gotcha +300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/utils/cpu.rs b/src/utils/cpu.rs +index c4d5a97..8aefaee 100644 +--- a/src/utils/cpu.rs ++++ b/src/utils/cpu.rs +@@ -210,6 +210,17 @@ pub static SIMD_SUPPORT: LazyLock = LazyLock::new(|| { + SimdSupport::None + } + } ++ // riscv64 (and any other architecture without a dedicated tier above) has ++ // no SIMD kernels in lance yet; upstream's cfg arms have no catch-all, so ++ // this closure otherwise evaluates to `()` here instead of `SimdSupport`. ++ #[cfg(not(any( ++ target_arch = "aarch64", ++ target_arch = "x86_64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ SimdSupport::None ++ } + }); + + #[cfg(target_arch = "x86_64")] +-- +2.43.0 diff --git a/patches/lance-context/0.6.6/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch b/patches/lance-context/0.6.6/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..b6101c15f79c --- /dev/null +++ b/patches/lance-context/0.6.6/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch @@ -0,0 +1,1434 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-linalg: add a portable riscv64 SIMD fallback (9.0.0) + +lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types +(src/simd/{f32,f64,i32}.rs) are defined, and every trait impl for them +written, only under `#[cfg(target_arch = "x86_64"/"aarch64"/ +"loongarch64")]`; riscv64 hits "cannot find type `f32x8` in this +scope" as soon as lance-linalg is built. Add an array-backed struct +plus a scalar implementation of every method the SIMD/FloatSimd traits +require, gated `#[cfg(not(any(target_arch = "x86_64", target_arch = +"aarch64", target_arch = "loongarch64")))]` beside the existing +per-architecture arms, which are otherwise untouched. + +Same change as 0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch +(which target this crate's 7.0.0 release), rebased onto the 9.0.0 +crates.io release that crates/lance-context-core's `lance = "9.0.0"` +pulls in; the fallback arms themselves are unchanged. Applied (via +0003-cargo-patch-lance-crates-for-riscv64.patch) to a local copy of +lance-linalg 9.0.0 materialized by the workflow, since it is a transitive +crates.io dependency and cannot be patched in place (CLAUDE.md gotcha +300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/simd/f32.rs b/src/simd/f32.rs +index 4ce7f64..2b2d3bc 100644 +--- a/src/simd/f32.rs ++++ b/src/simd/f32.rs +@@ -35,6 +35,17 @@ pub struct f32x8(float32x4x2_t); + #[derive(Clone, Copy)] + pub struct f32x8(v8f32); + ++/// 8 of 32-bit `f32` values. Portable scalar fallback for architectures with ++/// no dedicated SIMD tier above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x8([f32; 8]); ++ + impl std::fmt::Debug for f32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 8]; +@@ -119,6 +130,27 @@ impl f32x8 { + ]; + Self::load_unaligned(values.as_ptr()) + } ++ ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ let ptr = slice.as_ptr(); ++ ++ let values = [ ++ *ptr.add(indices[0] as usize), ++ *ptr.add(indices[1] as usize), ++ *ptr.add(indices[2] as usize), ++ *ptr.add(indices[3] as usize), ++ *ptr.add(indices[4] as usize), ++ *ptr.add(indices[5] as usize), ++ *ptr.add(indices[6] as usize), ++ *ptr.add(indices[7] as usize), ++ ]; ++ Self::load_unaligned(values.as_ptr()) ++ } + } + } + +@@ -172,6 +204,14 @@ impl SIMD for f32x8 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_w(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + fn zeros() -> Self { +@@ -187,6 +227,14 @@ impl SIMD for f32x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -203,6 +251,14 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -219,6 +275,18 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f32) { +@@ -234,6 +302,14 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f32) { +@@ -249,6 +325,16 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -277,6 +363,14 @@ impl SIMD for f32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f32 { +@@ -311,6 +405,14 @@ impl SIMD for f32x8 { + let m2 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m2))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -329,6 +431,18 @@ impl SIMD for f32x8 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -362,6 +476,18 @@ impl SIMD for f32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -381,6 +507,16 @@ impl FloatSimd for f32x8 { + unsafe { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -404,6 +540,18 @@ impl Add for f32x8 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -423,6 +571,16 @@ impl AddAssign for f32x8 { + unsafe { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -446,6 +604,18 @@ impl Sub for f32x8 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -465,6 +635,16 @@ impl SubAssign for f32x8 { + unsafe { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -488,6 +668,18 @@ impl Mul for f32x8 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -516,6 +708,16 @@ pub struct f32x16(float32x4x4_t); + #[derive(Clone, Copy)] + pub struct f32x16(v8f32, v8f32); + ++/// 16 of 32-bit `f32` values. Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x16([f32; 16]); ++ + impl std::fmt::Debug for f32x16 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 16]; +@@ -561,6 +763,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvreplgr2vr_w(transmute(val))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 16]) ++ } + } + + #[inline] +@@ -577,6 +787,14 @@ impl SIMD for f32x16 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 16]) ++ } + } + + #[inline] +@@ -596,6 +814,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -615,6 +841,18 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -633,6 +871,14 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -651,6 +897,16 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -681,6 +937,14 @@ impl SIMD for f32x16 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -715,6 +979,14 @@ impl SIMD for f32x16 { + let m1 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m1))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + #[inline] +@@ -736,6 +1008,18 @@ impl SIMD for f32x16 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0), lasx_xvfmin_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -782,6 +1066,19 @@ impl SIMD for f32x16 { + } + None + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ None ++ } + } + } + +@@ -805,6 +1102,16 @@ impl FloatSimd for f32x16 { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_s(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -830,6 +1137,18 @@ impl Add for f32x16 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0), lasx_xvfadd_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -853,6 +1172,16 @@ impl AddAssign for f32x16 { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + self.1 = lasx_xvfadd_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -878,6 +1207,18 @@ impl Mul for f32x16 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0), lasx_xvfmul_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -903,6 +1244,18 @@ impl Sub for f32x16 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0), lasx_xvfsub_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -926,6 +1279,16 @@ impl SubAssign for f32x16 { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + self.1 = lasx_xvfsub_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/f64.rs b/src/simd/f64.rs +index 1276f54..1ee729b 100644 +--- a/src/simd/f64.rs ++++ b/src/simd/f64.rs +@@ -33,6 +33,17 @@ pub struct f64x4(float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x4(v4f64); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x4([f64; 4]); ++ + impl std::fmt::Debug for f64x4 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 4]; +@@ -69,6 +80,14 @@ impl SIMD for f64x4 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_d(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 4]) ++ } + } + + fn zeros() -> Self { +@@ -84,6 +103,14 @@ impl SIMD for f64x4 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 4]) ++ } + } + + #[inline] +@@ -100,6 +127,14 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -116,6 +151,18 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f64) { +@@ -131,6 +178,14 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f64) { +@@ -146,6 +201,16 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -169,6 +234,14 @@ impl SIMD for f64x4 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f64 { +@@ -194,6 +267,14 @@ impl SIMD for f64x4 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -212,6 +293,18 @@ impl SIMD for f64x4 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -241,6 +334,16 @@ impl FloatSimd for f64x4 { + unsafe { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -264,6 +367,18 @@ impl Add for f64x4 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -283,6 +398,16 @@ impl AddAssign for f64x4 { + unsafe { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -306,6 +431,18 @@ impl Sub for f64x4 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -325,6 +462,16 @@ impl SubAssign for f64x4 { + unsafe { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -348,6 +495,18 @@ impl Mul for f64x4 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -377,6 +536,16 @@ pub struct f64x8(float64x2x2_t, float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x8(v4f64, v4f64); + ++/// Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x8([f64; 8]); ++ + impl std::fmt::Debug for f64x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 8]; +@@ -416,6 +585,14 @@ impl SIMD for f64x8 { + let v = transmute(lasx_xvreplgr2vr_d(transmute(val))); + Self(v, v) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -432,6 +609,14 @@ impl SIMD for f64x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -451,6 +636,14 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -470,6 +663,18 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -489,6 +694,14 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -508,6 +721,16 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -531,6 +754,14 @@ impl SIMD for f64x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -558,6 +789,14 @@ impl SIMD for f64x8 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + #[inline] +@@ -577,6 +816,18 @@ impl SIMD for f64x8 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0), lasx_xvfmin_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -612,6 +863,16 @@ impl FloatSimd for f64x8 { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_d(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -635,6 +896,18 @@ impl Add for f64x8 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0), lasx_xvfadd_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -658,6 +931,16 @@ impl AddAssign for f64x8 { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + self.1 = lasx_xvfadd_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -681,6 +964,18 @@ impl Mul for f64x8 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0), lasx_xvfmul_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -704,6 +999,18 @@ impl Sub for f64x8 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0), lasx_xvfsub_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -727,6 +1034,16 @@ impl SubAssign for f64x8 { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + self.1 = lasx_xvfsub_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/i32.rs b/src/simd/i32.rs +index fa8cdaf..60e5202 100644 +--- a/src/simd/i32.rs ++++ b/src/simd/i32.rs +@@ -30,6 +30,17 @@ pub struct i32x8(int32x4x2_t); + #[derive(Clone, Copy)] + pub struct i32x8(v8i32); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct i32x8(pub(crate) [i32; 8]); ++ + impl std::fmt::Debug for i32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0; 8]; +@@ -67,6 +78,14 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvreplgr2vr_w(val)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -83,6 +102,14 @@ impl SIMD for i32x8 { + { + Self::splat(0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0; 8]) ++ } + } + + #[inline] +@@ -99,6 +126,14 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -115,6 +150,18 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -135,6 +182,16 @@ impl SIMD for i32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> i32 { +@@ -151,6 +208,14 @@ impl SIMD for i32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> i32 { +@@ -173,6 +238,18 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvmin_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: i32) -> Option { +@@ -206,6 +283,18 @@ impl SIMD for i32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -230,6 +319,18 @@ impl Add for i32x8 { + unsafe { + Self(lasx_xvadd_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -249,6 +350,16 @@ impl AddAssign for i32x8 { + unsafe { + self.0 = lasx_xvadd_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ } + } + } + +@@ -272,6 +383,18 @@ impl Sub for i32x8 { + unsafe { + Self(lasx_xvsub_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -291,6 +414,16 @@ impl SubAssign for i32x8 { + unsafe { + self.0 = lasx_xvsub_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ } + } + } + +@@ -314,6 +447,18 @@ impl Mul for i32x8 { + unsafe { + Self(lasx_xvmul_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_mul(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0001-remove-unused-lance-graph-dependency.patch b/patches/lance-context/0.6.7/0001-remove-unused-lance-graph-dependency.patch new file mode 100644 index 000000000000..a8ea9ae43af6 --- /dev/null +++ b/patches/lance-context/0.6.7/0001-remove-unused-lance-graph-dependency.patch @@ -0,0 +1,38 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-context-core: drop the unused lance-graph dependency + +crates/lance-context-core/Cargo.toml depends on `lance-graph = "0.5.4"`, +but no Rust source file in this workspace imports `lance_graph` +(`grep -rln lance_graph crates/ python/` matches nothing); it is dead +weight in the dependency graph. lance-graph's own Cargo.toml pins +`lance`/`lance-core`/`lance-linalg` at an incompatible `1.x` line, which +Cargo resolves as yet another parallel copy of the whole lance-core/ +lance-linalg family, alongside the `9.0.0` one crates/lance-context-core +depends on directly (`lance = "9.0.0"`) and the `7.0.0` one +`lancedb = "0.30.0"` still pulls in. That `1.x` copy's lance-core +SIMD_SUPPORT closure and lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 +SIMD types have no riscv64 fallback either, so it would need its own +riscv64-patched copy (see 0003-cargo-patch-lance-crates-for-riscv64.patch) +just to compile a crate nothing uses. Removing the dead dependency +drops that whole copy from resolution instead. + +Upstream-Status: To upstream [not yet submitted to lance-format/lance-context] + +Signed-off-by: Ludovic Henry +--- +diff --git a/crates/lance-context-core/Cargo.toml b/crates/lance-context-core/Cargo.toml +index a5d0f25..928c52a 100644 +--- a/crates/lance-context-core/Cargo.toml ++++ b/crates/lance-context-core/Cargo.toml +@@ -31,7 +31,6 @@ lance-context-api = { version = "0.6.7", path = "../lance-context-api" } + lance-index = "9.0.0" + lance-namespace = "9.0.0" + lancedb = "0.30.0" +-lance-graph = "0.5.4" + # Version-matched with lance-context-server/-master so one process-wide recorder + # serves every crate. + metrics = { version = "0.24", optional = true } +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0002-lance-core-riscv64-simd-fallback.patch b/patches/lance-context/0.6.7/0002-lance-core-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..58c2f4f76bd5 --- /dev/null +++ b/patches/lance-context/0.6.7/0002-lance-core-riscv64-simd-fallback.patch @@ -0,0 +1,45 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Mon, 06 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-core: add a portable riscv64 SIMD-tier fallback + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) picks a SIMD tier +via a `cfg`-gated closure with arms for aarch64, x86_64 and loongarch64 +only; none of them match riscv64, so the closure's block has no +trailing expression there and the crate fails to compile with "expected +`SimdSupport`, found `()`". Add a `None`-tier fallback arm beside the +existing ones for every architecture without a dedicated tier. + +Applied (via patches/lance-context/0.6.5/0003-cargo-patch-lance-crates-for-riscv64.patch) +to a local copy of this crate's 7.0.0 crates.io release, which +crates/lance-context-core's `lance = "7.0.0"` pulls in transitively +and cannot be patched in place (CLAUDE.md gotcha 300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/utils/cpu.rs b/src/utils/cpu.rs +index 4e7ab01..34ed3a0 100644 +--- a/src/utils/cpu.rs ++++ b/src/utils/cpu.rs +@@ -58,6 +58,17 @@ pub static SIMD_SUPPORT: LazyLock = LazyLock::new(|| { + SimdSupport::None + } + } ++ // riscv64 (and any other architecture without a dedicated tier above) has ++ // no SIMD kernels in lance yet; upstream's cfg arms have no catch-all, so ++ // this closure otherwise evaluates to `()` here instead of `SimdSupport`. ++ #[cfg(not(any( ++ target_arch = "aarch64", ++ target_arch = "x86_64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ SimdSupport::None ++ } + }); + + #[cfg(target_arch = "x86_64")] +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0003-cargo-patch-lance-crates-for-riscv64.patch b/patches/lance-context/0.6.7/0003-cargo-patch-lance-crates-for-riscv64.patch new file mode 100644 index 000000000000..cbd5577f4719 --- /dev/null +++ b/patches/lance-context/0.6.7/0003-cargo-patch-lance-crates-for-riscv64.patch @@ -0,0 +1,101 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] cargo: redirect lance-core/lance-linalg to riscv64-patched + checkouts + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) and lance-linalg's +f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types (src/simd/{f32,i32,f64}.rs) +are compiled for x86_64/aarch64/loongarch64 only, with no fallback arm +for any other architecture (CLAUDE.md gotcha 300): the SIMD_SUPPORT +closure has no trailing expression on riscv64 ("expected SimdSupport, +found ()"), and the SIMD type structs are defined only under those +three `#[cfg(target_arch = ...)]` attributes while every method +implementing them is unconditional, so riscv64 hits "cannot find type +`f32x8` in this scope" as soon as lance-linalg is built. + +Two semver-incompatible lines of both crates are compiled here: 9.0.0, +via crates/lance-context-core's direct `lance = "9.0.0"`, and 7.0.0, +which `lancedb = "0.30.0"` (and lance-namespace-impls 7.0.0 under it) +still pulls in. (lance-graph's own, unused `1.x` copy is dropped +entirely by 0001-remove-unused-lance-graph-dependency.patch instead.) +Redirect all four to the riscv64-patched copies the workflow +materializes at build time from the pinned crates.io releases (see +0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch for 7.0.0 +and 0005/0006-lance-{core,linalg}-9.0.0-riscv64-simd-fallback.patch +for 9.0.0). The 7.0.0 pair is listed under renamed keys with +`package = ...`, which is how Cargo's [patch] table accepts more than +one semver-incompatible version of the same crate. Each copy is at the +same version Cargo.lock already pins -- only the `source`/`checksum` +lines of those four entries change there, so every other dependency +stays pinned exactly as upstream released it. + +Upstream-Status: Inappropriate [redirects pinned dependencies to local checkouts materialized at build time; the fix itself belongs in lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/Cargo.lock b/Cargo.lock +index ae51867..517dc44 100644 +--- a/Cargo.lock ++++ b/Cargo.lock +@@ -6491,8 +6491,6 @@ dependencies = [ + [[package]] + name = "lance-core" + version = "7.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "13f84020da5a484e2f07dd1796e09785ed7cd889857ebc4cb77e32ef214ee594" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -6528,8 +6526,6 @@ dependencies = [ + [[package]] + name = "lance-core" + version = "9.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "238c8a58308e7718d6bd96b53494eb7953fa299778bc4911cc571c3576e9446d" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -7387,8 +7383,6 @@ dependencies = [ + [[package]] + name = "lance-linalg" + version = "7.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "6b4c51cad0ac780b02dc4da48528479e7693c03e8d05390510bbc69ca2a9a1f1" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +@@ -7405,8 +7399,6 @@ dependencies = [ + [[package]] + name = "lance-linalg" + version = "9.0.0" +-source = "registry+https://github.com/rust-lang/crates.io-index" +-checksum = "0e5a9b99bd1f49bc2fe5afb81323141abc506c818f589de95dbab4f6143d9a88" + dependencies = [ + "arrow-array 58.3.0", + "arrow-buffer 58.3.0", +diff --git a/Cargo.toml b/Cargo.toml +index 2efab19..e85f652 100644 +--- a/Cargo.toml ++++ b/Cargo.toml +@@ -17,3 +17,18 @@ license = "Apache-2.0" + + [workspace.metadata] + # reserved for future use ++ ++# lance-core's SIMD_SUPPORT static and lance-linalg's f32x8/f32x16/i32x8/ ++# f64x4/f64x8 SIMD types compile only for x86_64/aarch64/loongarch64 ++# upstream (CLAUDE.md gotcha 300); the riscv64-patched copies below are ++# materialized from the pinned crates.io releases by the workflow at ++# build time. Both the 9.0.0 line (crates/lance-context-core's direct ++# `lance = "9.0.0"`) and the 7.0.0 line (still pulled in by ++# `lancedb = "0.30.0"`) are compiled, so each is redirected; the second ++# pair uses renamed `package =` keys, which is how Cargo's [patch] table ++# takes more than one semver-incompatible version of the same crate. ++[patch.crates-io] ++lance-core = { path = "lance-core-9.0.0-riscv64" } ++lance-linalg = { path = "lance-linalg-9.0.0-riscv64" } ++lance-core-7 = { package = "lance-core", path = "lance-core-7.0.0-riscv64" } ++lance-linalg-7 = { package = "lance-linalg", path = "lance-linalg-7.0.0-riscv64" } +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0004-lance-linalg-riscv64-simd-fallback.patch b/patches/lance-context/0.6.7/0004-lance-linalg-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..3aaf5e355308 --- /dev/null +++ b/patches/lance-context/0.6.7/0004-lance-linalg-riscv64-simd-fallback.patch @@ -0,0 +1,1435 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Mon, 06 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-linalg: add a portable riscv64 SIMD fallback + +lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types +(src/simd/{f32,f64,i32}.rs) are defined, and every trait impl for them +written, only under `#[cfg(target_arch = "x86_64"/"aarch64"/ +"loongarch64")]` -- unlike u8x16/u8x32 (src/simd/u8.rs), which already +carry a portable fallback. riscv64 hits "cannot find type `f32x8` in +this scope" as soon as lance-linalg (a dependency of lance, which +crates/lance-context-core depends on directly) is built. Add the same +shape of fallback for the three missing types: an array-backed struct +plus a scalar implementation of every method the SIMD/FloatSimd traits +require, gated `#[cfg(not(any(target_arch = "x86_64", target_arch = +"aarch64", target_arch = "loongarch64")))]` beside the existing +per-architecture arms, which are otherwise untouched. Add/Sub/Mul on +i32x8 use wrapping arithmetic to match the silent-wraparound semantics +of the SIMD instructions they replace. + +Applied (via patches/lance-context/0.6.5/0003-cargo-patch-lance-crates-for-riscv64.patch) +to a local copy of this crate's 7.0.0 crates.io release, which +crates/lance-context-core's `lance = "7.0.0"` pulls in transitively +and cannot be patched in place (CLAUDE.md gotcha 300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/simd/f32.rs b/src/simd/f32.rs +index 7804299..e219e0e 100644 +--- a/src/simd/f32.rs ++++ b/src/simd/f32.rs +@@ -35,6 +35,17 @@ pub struct f32x8(float32x4x2_t); + #[derive(Clone, Copy)] + pub struct f32x8(v8f32); + ++/// 8 of 32-bit `f32` values. Portable scalar fallback for architectures with ++/// no dedicated SIMD tier above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x8([f32; 8]); ++ + impl std::fmt::Debug for f32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 8]; +@@ -91,6 +102,27 @@ impl f32x8 { + ]; + Self::load_unaligned(values.as_ptr()) + } ++ ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ let ptr = slice.as_ptr(); ++ ++ let values = [ ++ *ptr.add(indices[0] as usize), ++ *ptr.add(indices[1] as usize), ++ *ptr.add(indices[2] as usize), ++ *ptr.add(indices[3] as usize), ++ *ptr.add(indices[4] as usize), ++ *ptr.add(indices[5] as usize), ++ *ptr.add(indices[6] as usize), ++ *ptr.add(indices[7] as usize), ++ ]; ++ Self::load_unaligned(values.as_ptr()) ++ } + } + } + +@@ -120,6 +152,14 @@ impl SIMD for f32x8 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_w(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + fn zeros() -> Self { +@@ -135,6 +175,14 @@ impl SIMD for f32x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -151,6 +199,14 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -167,6 +223,18 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f32) { +@@ -182,6 +250,14 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f32) { +@@ -197,6 +273,16 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -225,6 +311,14 @@ impl SIMD for f32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f32 { +@@ -259,6 +353,14 @@ impl SIMD for f32x8 { + let m2 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m2))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -277,6 +379,18 @@ impl SIMD for f32x8 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -310,6 +424,18 @@ impl SIMD for f32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -329,6 +455,16 @@ impl FloatSimd for f32x8 { + unsafe { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -352,6 +488,18 @@ impl Add for f32x8 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -371,6 +519,16 @@ impl AddAssign for f32x8 { + unsafe { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -394,6 +552,18 @@ impl Sub for f32x8 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -413,6 +583,16 @@ impl SubAssign for f32x8 { + unsafe { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -436,6 +616,18 @@ impl Mul for f32x8 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -461,6 +653,16 @@ pub struct f32x16(float32x4x4_t); + #[derive(Clone, Copy)] + pub struct f32x16(v8f32, v8f32); + ++/// 16 of 32-bit `f32` values. Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x16([f32; 16]); ++ + impl std::fmt::Debug for f32x16 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 16]; +@@ -510,6 +712,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvreplgr2vr_w(transmute(val))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 16]) ++ } + } + + #[inline] +@@ -530,6 +740,14 @@ impl SIMD for f32x16 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 16]) ++ } + } + + #[inline] +@@ -553,6 +771,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -576,6 +802,18 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -598,6 +836,14 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -620,6 +866,16 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> f32 { +@@ -653,6 +909,14 @@ impl SIMD for f32x16 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -691,6 +955,14 @@ impl SIMD for f32x16 { + let m1 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m1))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + #[inline] +@@ -716,6 +988,18 @@ impl SIMD for f32x16 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0), lasx_xvfmin_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -768,6 +1052,19 @@ impl SIMD for f32x16 { + } + None + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ None ++ } + } + } + +@@ -795,6 +1092,16 @@ impl FloatSimd for f32x16 { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_s(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -824,6 +1131,18 @@ impl Add for f32x16 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0), lasx_xvfadd_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -851,6 +1170,16 @@ impl AddAssign for f32x16 { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + self.1 = lasx_xvfadd_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -880,6 +1209,18 @@ impl Mul for f32x16 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0), lasx_xvfmul_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -909,6 +1250,18 @@ impl Sub for f32x16 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0), lasx_xvfsub_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -936,6 +1289,16 @@ impl SubAssign for f32x16 { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + self.1 = lasx_xvfsub_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/f64.rs b/src/simd/f64.rs +index 32c0d38..a057bf7 100644 +--- a/src/simd/f64.rs ++++ b/src/simd/f64.rs +@@ -33,6 +33,17 @@ pub struct f64x4(float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x4(v4f64); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x4([f64; 4]); ++ + impl std::fmt::Debug for f64x4 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 4]; +@@ -69,6 +80,14 @@ impl SIMD for f64x4 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_d(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 4]) ++ } + } + + fn zeros() -> Self { +@@ -84,6 +103,14 @@ impl SIMD for f64x4 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 4]) ++ } + } + + #[inline] +@@ -100,6 +127,14 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -116,6 +151,18 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f64) { +@@ -131,6 +178,14 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f64) { +@@ -146,6 +201,16 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -169,6 +234,14 @@ impl SIMD for f64x4 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f64 { +@@ -194,6 +267,14 @@ impl SIMD for f64x4 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -212,6 +293,18 @@ impl SIMD for f64x4 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -241,6 +334,16 @@ impl FloatSimd for f64x4 { + unsafe { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -264,6 +367,18 @@ impl Add for f64x4 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -283,6 +398,16 @@ impl AddAssign for f64x4 { + unsafe { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -306,6 +431,18 @@ impl Sub for f64x4 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -325,6 +462,16 @@ impl SubAssign for f64x4 { + unsafe { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -348,6 +495,18 @@ impl Mul for f64x4 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -376,6 +535,16 @@ pub struct f64x8(float64x2x2_t, float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x8(v4f64, v4f64); + ++/// Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x8([f64; 8]); ++ + impl std::fmt::Debug for f64x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 8]; +@@ -419,6 +588,14 @@ impl SIMD for f64x8 { + let v = transmute(lasx_xvreplgr2vr_d(transmute(val))); + Self(v, v) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -439,6 +616,14 @@ impl SIMD for f64x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -462,6 +647,14 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -485,6 +678,18 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -508,6 +713,14 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -531,6 +744,16 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> f64 { +@@ -557,6 +780,14 @@ impl SIMD for f64x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -588,6 +819,14 @@ impl SIMD for f64x8 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + #[inline] +@@ -611,6 +850,18 @@ impl SIMD for f64x8 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0), lasx_xvfmin_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -649,6 +900,16 @@ impl FloatSimd for f64x8 { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_d(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -676,6 +937,18 @@ impl Add for f64x8 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0), lasx_xvfadd_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -703,6 +976,16 @@ impl AddAssign for f64x8 { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + self.1 = lasx_xvfadd_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -730,6 +1013,18 @@ impl Mul for f64x8 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0), lasx_xvfmul_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -757,6 +1052,18 @@ impl Sub for f64x8 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0), lasx_xvfsub_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -784,6 +1091,16 @@ impl SubAssign for f64x8 { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + self.1 = lasx_xvfsub_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/i32.rs b/src/simd/i32.rs +index fa8cdaf..60e5202 100644 +--- a/src/simd/i32.rs ++++ b/src/simd/i32.rs +@@ -30,6 +30,17 @@ pub struct i32x8(int32x4x2_t); + #[derive(Clone, Copy)] + pub struct i32x8(v8i32); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct i32x8(pub(crate) [i32; 8]); ++ + impl std::fmt::Debug for i32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0; 8]; +@@ -67,6 +78,14 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvreplgr2vr_w(val)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -83,6 +102,14 @@ impl SIMD for i32x8 { + { + Self::splat(0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0; 8]) ++ } + } + + #[inline] +@@ -99,6 +126,14 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -115,6 +150,18 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -135,6 +182,16 @@ impl SIMD for i32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> i32 { +@@ -151,6 +208,14 @@ impl SIMD for i32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> i32 { +@@ -173,6 +238,18 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvmin_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: i32) -> Option { +@@ -206,6 +283,18 @@ impl SIMD for i32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -230,6 +319,18 @@ impl Add for i32x8 { + unsafe { + Self(lasx_xvadd_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -249,6 +350,16 @@ impl AddAssign for i32x8 { + unsafe { + self.0 = lasx_xvadd_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ } + } + } + +@@ -272,6 +383,18 @@ impl Sub for i32x8 { + unsafe { + Self(lasx_xvsub_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -291,6 +414,16 @@ impl SubAssign for i32x8 { + unsafe { + self.0 = lasx_xvsub_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ } + } + } + +@@ -314,6 +447,18 @@ impl Mul for i32x8 { + unsafe { + Self(lasx_xvmul_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_mul(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0005-lance-core-9.0.0-riscv64-simd-fallback.patch b/patches/lance-context/0.6.7/0005-lance-core-9.0.0-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..cd28a4aab117 --- /dev/null +++ b/patches/lance-context/0.6.7/0005-lance-core-9.0.0-riscv64-simd-fallback.patch @@ -0,0 +1,49 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-core: add a portable riscv64 SIMD-tier fallback (9.0.0) + +lance-core's SIMD_SUPPORT static (src/utils/cpu.rs) picks a SIMD tier +via a `cfg`-gated closure with arms for aarch64, x86_64 and loongarch64 +only; none of them match riscv64, so the closure's block has no +trailing expression there and the crate fails to compile with "expected +`SimdSupport`, found `()`". Add a `None`-tier fallback arm beside the +existing ones for every architecture without a dedicated tier. + +Same change as 0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch +(which target this crate's 7.0.0 release), rebased onto the 9.0.0 +crates.io release that crates/lance-context-core's `lance = "9.0.0"` +pulls in; the fallback arms themselves are unchanged. Applied (via +0003-cargo-patch-lance-crates-for-riscv64.patch) to a local copy of +lance-core 9.0.0 materialized by the workflow, since it is a transitive +crates.io dependency and cannot be patched in place (CLAUDE.md gotcha +300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/utils/cpu.rs b/src/utils/cpu.rs +index c4d5a97..8aefaee 100644 +--- a/src/utils/cpu.rs ++++ b/src/utils/cpu.rs +@@ -210,6 +210,17 @@ pub static SIMD_SUPPORT: LazyLock = LazyLock::new(|| { + SimdSupport::None + } + } ++ // riscv64 (and any other architecture without a dedicated tier above) has ++ // no SIMD kernels in lance yet; upstream's cfg arms have no catch-all, so ++ // this closure otherwise evaluates to `()` here instead of `SimdSupport`. ++ #[cfg(not(any( ++ target_arch = "aarch64", ++ target_arch = "x86_64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ SimdSupport::None ++ } + }); + + #[cfg(target_arch = "x86_64")] +-- +2.43.0 diff --git a/patches/lance-context/0.6.7/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch b/patches/lance-context/0.6.7/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch new file mode 100644 index 000000000000..b6101c15f79c --- /dev/null +++ b/patches/lance-context/0.6.7/0006-lance-linalg-9.0.0-riscv64-simd-fallback.patch @@ -0,0 +1,1434 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Ludovic Henry +Date: Tue, 13 Oct 2026 00:00:00 +0000 +Subject: [PATCH] lance-linalg: add a portable riscv64 SIMD fallback (9.0.0) + +lance-linalg's f32x8/f32x16/i32x8/f64x4/f64x8 SIMD types +(src/simd/{f32,f64,i32}.rs) are defined, and every trait impl for them +written, only under `#[cfg(target_arch = "x86_64"/"aarch64"/ +"loongarch64")]`; riscv64 hits "cannot find type `f32x8` in this +scope" as soon as lance-linalg is built. Add an array-backed struct +plus a scalar implementation of every method the SIMD/FloatSimd traits +require, gated `#[cfg(not(any(target_arch = "x86_64", target_arch = +"aarch64", target_arch = "loongarch64")))]` beside the existing +per-architecture arms, which are otherwise untouched. + +Same change as 0002/0004-lance-{core,linalg}-riscv64-simd-fallback.patch +(which target this crate's 7.0.0 release), rebased onto the 9.0.0 +crates.io release that crates/lance-context-core's `lance = "9.0.0"` +pulls in; the fallback arms themselves are unchanged. Applied (via +0003-cargo-patch-lance-crates-for-riscv64.patch) to a local copy of +lance-linalg 9.0.0 materialized by the workflow, since it is a transitive +crates.io dependency and cannot be patched in place (CLAUDE.md gotcha +300). + +Upstream-Status: To upstream [not yet submitted to lance-format/lance] + +Signed-off-by: Ludovic Henry +--- +diff --git a/src/simd/f32.rs b/src/simd/f32.rs +index 4ce7f64..2b2d3bc 100644 +--- a/src/simd/f32.rs ++++ b/src/simd/f32.rs +@@ -35,6 +35,17 @@ pub struct f32x8(float32x4x2_t); + #[derive(Clone, Copy)] + pub struct f32x8(v8f32); + ++/// 8 of 32-bit `f32` values. Portable scalar fallback for architectures with ++/// no dedicated SIMD tier above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x8([f32; 8]); ++ + impl std::fmt::Debug for f32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 8]; +@@ -119,6 +130,27 @@ impl f32x8 { + ]; + Self::load_unaligned(values.as_ptr()) + } ++ ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ let ptr = slice.as_ptr(); ++ ++ let values = [ ++ *ptr.add(indices[0] as usize), ++ *ptr.add(indices[1] as usize), ++ *ptr.add(indices[2] as usize), ++ *ptr.add(indices[3] as usize), ++ *ptr.add(indices[4] as usize), ++ *ptr.add(indices[5] as usize), ++ *ptr.add(indices[6] as usize), ++ *ptr.add(indices[7] as usize), ++ ]; ++ Self::load_unaligned(values.as_ptr()) ++ } + } + } + +@@ -172,6 +204,14 @@ impl SIMD for f32x8 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_w(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + fn zeros() -> Self { +@@ -187,6 +227,14 @@ impl SIMD for f32x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -203,6 +251,14 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -219,6 +275,18 @@ impl SIMD for f32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f32) { +@@ -234,6 +302,14 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f32) { +@@ -249,6 +325,16 @@ impl SIMD for f32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -277,6 +363,14 @@ impl SIMD for f32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f32 { +@@ -311,6 +405,14 @@ impl SIMD for f32x8 { + let m2 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m2))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -329,6 +431,18 @@ impl SIMD for f32x8 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f32) -> Option { +@@ -362,6 +476,18 @@ impl SIMD for f32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -381,6 +507,16 @@ impl FloatSimd for f32x8 { + unsafe { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -404,6 +540,18 @@ impl Add for f32x8 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -423,6 +571,16 @@ impl AddAssign for f32x8 { + unsafe { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -446,6 +604,18 @@ impl Sub for f32x8 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -465,6 +635,16 @@ impl SubAssign for f32x8 { + unsafe { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -488,6 +668,18 @@ impl Mul for f32x8 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -516,6 +708,16 @@ pub struct f32x16(float32x4x4_t); + #[derive(Clone, Copy)] + pub struct f32x16(v8f32, v8f32); + ++/// 16 of 32-bit `f32` values. Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f32x16([f32; 16]); ++ + impl std::fmt::Debug for f32x16 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f32; 16]; +@@ -561,6 +763,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvreplgr2vr_w(transmute(val))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 16]) ++ } + } + + #[inline] +@@ -577,6 +787,14 @@ impl SIMD for f32x16 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 16]) ++ } + } + + #[inline] +@@ -596,6 +814,14 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -615,6 +841,18 @@ impl SIMD for f32x16 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -633,6 +871,14 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -651,6 +897,16 @@ impl SIMD for f32x16 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -681,6 +937,14 @@ impl SIMD for f32x16 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -715,6 +979,14 @@ impl SIMD for f32x16 { + let m1 = lasx_xvfmin_s(transmute(m1), transmute(m2)); + transmute(lasx_xvpickve2gr_w::<0>(transmute(m1))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f32::INFINITY, f32::min) ++ } + } + + #[inline] +@@ -736,6 +1008,18 @@ impl SIMD for f32x16 { + unsafe { + Self(lasx_xvfmin_s(self.0, rhs.0), lasx_xvfmin_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -782,6 +1066,19 @@ impl SIMD for f32x16 { + } + None + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ None ++ } + } + } + +@@ -805,6 +1102,16 @@ impl FloatSimd for f32x16 { + self.0 = lasx_xvfmadd_s(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_s(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -830,6 +1137,18 @@ impl Add for f32x16 { + unsafe { + Self(lasx_xvfadd_s(self.0, rhs.0), lasx_xvfadd_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -853,6 +1172,16 @@ impl AddAssign for f32x16 { + self.0 = lasx_xvfadd_s(self.0, rhs.0); + self.1 = lasx_xvfadd_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -878,6 +1207,18 @@ impl Mul for f32x16 { + unsafe { + Self(lasx_xvfmul_s(self.0, rhs.0), lasx_xvfmul_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -903,6 +1244,18 @@ impl Sub for f32x16 { + unsafe { + Self(lasx_xvfsub_s(self.0, rhs.0), lasx_xvfsub_s(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f32; 16]; ++ for i in 0..16 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -926,6 +1279,16 @@ impl SubAssign for f32x16 { + self.0 = lasx_xvfsub_s(self.0, rhs.0); + self.1 = lasx_xvfsub_s(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..16 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/f64.rs b/src/simd/f64.rs +index 1276f54..1ee729b 100644 +--- a/src/simd/f64.rs ++++ b/src/simd/f64.rs +@@ -33,6 +33,17 @@ pub struct f64x4(float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x4(v4f64); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x4([f64; 4]); ++ + impl std::fmt::Debug for f64x4 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 4]; +@@ -69,6 +80,14 @@ impl SIMD for f64x4 { + unsafe { + Self(transmute(lasx_xvreplgr2vr_d(transmute(val)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 4]) ++ } + } + + fn zeros() -> Self { +@@ -84,6 +103,14 @@ impl SIMD for f64x4 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 4]) ++ } + } + + #[inline] +@@ -100,6 +127,14 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -116,6 +151,18 @@ impl SIMD for f64x4 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + unsafe fn store(&self, ptr: *mut f64) { +@@ -131,6 +178,14 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + unsafe fn store_unaligned(&self, ptr: *mut f64) { +@@ -146,6 +201,16 @@ impl SIMD for f64x4 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -169,6 +234,14 @@ impl SIMD for f64x4 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> f64 { +@@ -194,6 +267,14 @@ impl SIMD for f64x4 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + fn min(&self, rhs: &Self) -> Self { +@@ -212,6 +293,18 @@ impl SIMD for f64x4 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: f64) -> Option { +@@ -241,6 +334,16 @@ impl FloatSimd for f64x4 { + unsafe { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -264,6 +367,18 @@ impl Add for f64x4 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -283,6 +398,16 @@ impl AddAssign for f64x4 { + unsafe { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -306,6 +431,18 @@ impl Sub for f64x4 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -325,6 +462,16 @@ impl SubAssign for f64x4 { + unsafe { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..4 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +@@ -348,6 +495,18 @@ impl Mul for f64x4 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 4]; ++ for i in 0..4 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -377,6 +536,16 @@ pub struct f64x8(float64x2x2_t, float64x2x2_t); + #[derive(Clone, Copy)] + pub struct f64x8(v4f64, v4f64); + ++/// Portable scalar fallback -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct f64x8([f64; 8]); ++ + impl std::fmt::Debug for f64x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0.0_f64; 8]; +@@ -416,6 +585,14 @@ impl SIMD for f64x8 { + let v = transmute(lasx_xvreplgr2vr_d(transmute(val))); + Self(v, v) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -432,6 +609,14 @@ impl SIMD for f64x8 { + { + Self::splat(0.0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0.0; 8]) ++ } + } + + #[inline] +@@ -451,6 +636,14 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -470,6 +663,18 @@ impl SIMD for f64x8 { + transmute(lasx_xvld::<32>(transmute(ptr))), + ) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -489,6 +694,14 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ self.store_unaligned(ptr); ++ } + } + + #[inline] +@@ -508,6 +721,16 @@ impl SIMD for f64x8 { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)); + lasx_xvst::<32>(transmute(self.1), transmute(ptr)); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + #[inline] +@@ -531,6 +754,14 @@ impl SIMD for f64x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + #[inline] +@@ -558,6 +789,14 @@ impl SIMD for f64x8 { + .copied() + .fold(f64::INFINITY, f64::min) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().copied().fold(f64::INFINITY, f64::min) ++ } + } + + #[inline] +@@ -577,6 +816,18 @@ impl SIMD for f64x8 { + unsafe { + Self(lasx_xvfmin_d(self.0, rhs.0), lasx_xvfmin_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -612,6 +863,16 @@ impl FloatSimd for f64x8 { + self.0 = lasx_xvfmadd_d(a.0, b.0, self.0); + self.1 = lasx_xvfmadd_d(a.1, b.1, self.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += a.0[i] * b.0[i]; ++ } ++ } + } + } + +@@ -635,6 +896,18 @@ impl Add for f64x8 { + unsafe { + Self(lasx_xvfadd_d(self.0, rhs.0), lasx_xvfadd_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] + rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -658,6 +931,16 @@ impl AddAssign for f64x8 { + self.0 = lasx_xvfadd_d(self.0, rhs.0); + self.1 = lasx_xvfadd_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] += rhs.0[i]; ++ } ++ } + } + } + +@@ -681,6 +964,18 @@ impl Mul for f64x8 { + unsafe { + Self(lasx_xvfmul_d(self.0, rhs.0), lasx_xvfmul_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] * rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -704,6 +999,18 @@ impl Sub for f64x8 { + unsafe { + Self(lasx_xvfsub_d(self.0, rhs.0), lasx_xvfsub_d(self.1, rhs.1)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0.0f64; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i] - rhs.0[i]; ++ } ++ Self(result) ++ } + } + } + +@@ -727,6 +1034,16 @@ impl SubAssign for f64x8 { + self.0 = lasx_xvfsub_d(self.0, rhs.0); + self.1 = lasx_xvfsub_d(self.1, rhs.1); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] -= rhs.0[i]; ++ } ++ } + } + } + +diff --git a/src/simd/i32.rs b/src/simd/i32.rs +index fa8cdaf..60e5202 100644 +--- a/src/simd/i32.rs ++++ b/src/simd/i32.rs +@@ -30,6 +30,17 @@ pub struct i32x8(int32x4x2_t); + #[derive(Clone, Copy)] + pub struct i32x8(v8i32); + ++/// Portable scalar fallback for architectures with no dedicated SIMD tier ++/// above (riscv64 included) -- CLAUDE.md gotcha 300. ++#[allow(non_camel_case_types)] ++#[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++)))] ++#[derive(Clone, Copy)] ++pub struct i32x8(pub(crate) [i32; 8]); ++ + impl std::fmt::Debug for i32x8 { + fn fmt(&self, f: &mut Formatter<'_>) -> std::fmt::Result { + let mut arr = [0; 8]; +@@ -67,6 +78,14 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvreplgr2vr_w(val)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([val; 8]) ++ } + } + + #[inline] +@@ -83,6 +102,14 @@ impl SIMD for i32x8 { + { + Self::splat(0) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self([0; 8]) ++ } + } + + #[inline] +@@ -99,6 +126,14 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ Self::load_unaligned(ptr) ++ } + } + + #[inline] +@@ -115,6 +150,18 @@ impl SIMD for i32x8 { + { + Self(transmute(lasx_xvld::<0>(transmute(ptr)))) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for (i, r) in result.iter_mut().enumerate() { ++ *r = unsafe { *ptr.add(i) }; ++ } ++ Self(result) ++ } + } + + #[inline] +@@ -135,6 +182,16 @@ impl SIMD for i32x8 { + unsafe { + lasx_xvst::<0>(transmute(self.0), transmute(ptr)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ unsafe { ++ for (i, v) in self.0.iter().enumerate() { ++ *ptr.add(i) = *v; ++ } ++ } + } + + fn reduce_sum(&self) -> i32 { +@@ -151,6 +208,14 @@ impl SIMD for i32x8 { + { + self.as_array().iter().sum() + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ self.0.iter().sum() ++ } + } + + fn reduce_min(&self) -> i32 { +@@ -173,6 +238,18 @@ impl SIMD for i32x8 { + unsafe { + Self(lasx_xvmin_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].min(rhs.0[i]); ++ } ++ Self(result) ++ } + } + + fn find(&self, val: i32) -> Option { +@@ -206,6 +283,18 @@ impl SIMD for i32x8 { + } + } + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ if self.0[i] == val { ++ return Some(i as i32); ++ } ++ } ++ } + None + } + } +@@ -230,6 +319,18 @@ impl Add for i32x8 { + unsafe { + Self(lasx_xvadd_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -249,6 +350,16 @@ impl AddAssign for i32x8 { + unsafe { + self.0 = lasx_xvadd_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_add(rhs.0[i]); ++ } ++ } + } + } + +@@ -272,6 +383,18 @@ impl Sub for i32x8 { + unsafe { + Self(lasx_xvsub_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +@@ -291,6 +414,16 @@ impl SubAssign for i32x8 { + unsafe { + self.0 = lasx_xvsub_w(self.0, rhs.0); + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ for i in 0..8 { ++ self.0[i] = self.0[i].wrapping_sub(rhs.0[i]); ++ } ++ } + } + } + +@@ -314,6 +447,18 @@ impl Mul for i32x8 { + unsafe { + Self(lasx_xvmul_w(self.0, rhs.0)) + } ++ #[cfg(not(any( ++ target_arch = "x86_64", ++ target_arch = "aarch64", ++ target_arch = "loongarch64" ++ )))] ++ { ++ let mut result = [0i32; 8]; ++ for i in 0..8 { ++ result[i] = self.0[i].wrapping_mul(rhs.0[i]); ++ } ++ Self(result) ++ } + } + } + +-- +2.43.0