RISC-V inline assembly ignores input register constraints

[fintelia]

This code:

#![no_std]
#![feature(asm)]
#![feature(start)]
#![feature(lang_items)]

#[lang = "eh_personality"] extern fn eh_personality() {}
#[panic_handler] fn panic(info: &::core::panic::PanicInfo) -> ! { loop {} }
#[start] fn start(_argc: isize, _argv: *const *const u8) -> isize {0}
#[no_mangle] pub fn abort() -> ! { loop {} }

#[no_mangle]
pub fn _start(a: [u32; 6]) {
    unsafe {
        asm!(""
             :: "r{sp}"(a[4]), "r{t0}"(a[5])
             : "volatile"
        );
    }
}

When compiled for the riscv64imac target:

$ cargo rustc --release --target riscv64imac-unknown-none-elf

Ignores the input register constraints which say to use sp and t0 (defaulting to a0 and a1 instead):

0000000000011000 <_start>:
   11000:	01456583          	lwu	a1,20(a0)
   11004:	01056503          	lwu	a0,16(a0)
   11008:	8082                	ret

[lenary]

I have looked deeper into this and the issue lies both with your inline asm call, and with the LLVM backend.

On the one hand, as documented in https://llvm.org/docs/LangRef.html#constraint-codes (which the rust asm macro is a thin shim on top of), r and {<reg>} are mutually exclusive choices. Why LLVM doesn't issue a warning if you write a constraint r{<reg>}, I don't know. I am looking to prepare a patch on this.

However, this bug also shows the same underlying issue as #60392. If you specify {sp} or {t0}, LLVM will warn you that it couldn't allocate input reg for constraint '{sp}' (this warning is prefixed with error:, but that doesn't stop llvm writing out assembly for the function with no trace of the inline assembly). Again, if you specify the architectural register name, not the ABI name (so, x2 rather than sp), you get the behaviour you are looking for. It is likely that any fix I make for this part of the problem will also cover #60392.

[lenary]

Correction: The constraint code set r{<reg>} means either r or {<reg>} and LLVM is allowed to choose. LLVM does not have many heuristics around this, and seems in this case to choose the first constraint from the set that works, which in this case is the more-general r constraint. Potentially LLVM should issue a warning if these overlap, but with constraint code sets and constraint code set alternatives (LLVM IR: Constraint Codes), this may be hard to achieve.

Update: Looking at the code in LLVM, when you specify a constraint set, it will always try to choose the most general constraint, and doesn't have enough information at that moment to work out if the constraints overlap. This means if you specify r{<reg>}, it will always choose the constraint r, at which point you lose control of the specific register that the compiler will use.

[lenary]

I have just landed https://reviews.llvm.org/rL368303, which solves the bug where you can only use the architectural register names. This has not been back-ported to 9.0, so may take some time to arrive in Rust. For the moment, use the architectural names.

[Amanieu]

This issue does not apply to the new asm! (RFC 2850) which properly handles register names for operands.

The legacy llvm_asm! is deprecated and is no longer maintained.