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RISC-V inline assembly ignores clobber constraints #60392
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A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.A-inline-assemblyArea: Inline assembly (`asm!(…)`)Area: Inline assembly (`asm!(…)`)C-bugCategory: This is a bug.Category: This is a bug.O-riscvTarget: RISC-V architectureTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.requires-nightlyThis issue requires a nightly compiler in some way. When possible, use a F-* label instead.This issue requires a nightly compiler in some way. When possible, use a F-* label instead.
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A-LLVMArea: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.A-inline-assemblyArea: Inline assembly (`asm!(…)`)Area: Inline assembly (`asm!(…)`)C-bugCategory: This is a bug.Category: This is a bug.O-riscvTarget: RISC-V architectureTarget: RISC-V architectureT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.requires-nightlyThis issue requires a nightly compiler in some way. When possible, use a F-* label instead.This issue requires a nightly compiler in some way. When possible, use a F-* label instead.
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This code:
When compiled for the riscv64imac target (and other riscv targets):
Produces code which uses the clobbered registers to pass in values, resulting in the inputs being overwritten before they can be used:
See also: #60391