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ac93ee4
initial checkin of first cut OTF
TurboVega Jan 4, 2024
cb9c05c
Add items to issues list
TurboVega Jan 4, 2024
fb38a9d
Fix punctuation in mode list
TurboVega Jan 4, 2024
97f4f1b
fix to z-order
TurboVega Jan 4, 2024
d0304ee
support tiles from PSRAM
TurboVega Jan 5, 2024
dd73dfd
updated slideshow demos
TurboVega Jan 5, 2024
3683fb5
fix typo
TurboVega Jan 5, 2024
6369e41
new split 640 demo runs but flickers
TurboVega Jan 5, 2024
51cc32d
try not using PSRAM for split 640 demo
TurboVega Jan 5, 2024
a8b6a82
don't buffer pixel data for certain commands
TurboVega Jan 8, 2024
396f058
fix index bug
Jan 8, 2024
1d601c4
force 100% opaque pixels on solid bitmaps
Jan 8, 2024
9072db4
several bug fixes
Jan 8, 2024
e149fec
Merge branch 'AgonConsole8:main' into otf-early-cut
TurboVega Jan 8, 2024
d36d9aa
changed some int16_t to uint16_t
TurboVega Jan 9, 2024
29581bb
showing transparent apple?
TurboVega Jan 9, 2024
25424e7
got 4 sizes of bitmaps to show
TurboVega Jan 9, 2024
98c2b01
more masked alpha setting
TurboVega Jan 9, 2024
8739ec9
add support for duplicating and flipping bitmaps
TurboVega Jan 9, 2024
e7c8e3f
got some text in 640x480 mode, with debug stuff
Jan 9, 2024
d286b37
clean up debug code
Jan 9, 2024
04e4c1c
issue notation
TurboVega Jan 10, 2024
31d4baf
starting to work on new scrolling demo
Jan 10, 2024
538ac71
Merge branch 'otf-early-cut' of https://github.com/turbovega/agon-vdp…
Jan 10, 2024
8bd580c
git full tile array to show in demo
Jan 10, 2024
2502b48
interim checkin; reworking tile array scrolling
TurboVega Jan 12, 2024
b446cf5
interim checkin; working on new common fcns
TurboVega Jan 16, 2024
4ea4344
interim; compiles
TurboVega Jan 16, 2024
182ef22
inserted blend call wrappers
TurboVega Jan 16, 2024
3424211
Update otf_text_area.md
TurboVega Jan 20, 2024
3781390
Merge branch 'AgonConsole8:main' into otf-early-cut
TurboVega Jan 25, 2024
0e378c4
fake having protocol 4 for the moment
TurboVega Jan 25, 2024
f9ef51a
show markers better
Jan 29, 2024
1adb2e8
copied some BDPP code from EZ80 sources as a start
Jan 29, 2024
3f101cd
narrowing down code copied from EZ80
Jan 30, 2024
a4aef7f
added uhci fcns (unused yet)
Jan 31, 2024
56ac9cf
Removed unused code
Jan 31, 2024
80cee0c
interim checkin; reworking test code
Feb 2, 2024
90176ca
interim; still reworking test
Feb 2, 2024
f351b8f
interim; reworking test
Feb 2, 2024
5ebb2da
interim checkin; got input interrupt
Feb 5, 2024
a86e013
got data by not stopping Serial2
Feb 5, 2024
c7a4bc6
still gets data w/Serial2 on
Feb 5, 2024
08c2c06
reads multiple incoming packets
Feb 6, 2024
eb7a7b3
try read and write
Feb 6, 2024
2724760
rx data with Serial2 turned off
Feb 6, 2024
2b446a5
reading about half the packets
Feb 6, 2024
1412086
before trying to use 2 receive buffers
Feb 6, 2024
dc0de5e
packet counter is still every other one
Feb 6, 2024
a476058
packets coming in better
Feb 7, 2024
e1927eb
still shows every other packet number
Feb 7, 2024
a3535f0
a little cleanup
Feb 7, 2024
8e36253
altered separator and escape chars
Feb 8, 2024
d2c8f46
Merge branch 'AgonConsole8:main' into bdpp
TurboVega Feb 9, 2024
200de1f
Merge branch 'AgonConsole8:main' into otf-early-cut
TurboVega Feb 9, 2024
4937022
interim checkin; working to clean up bdpp
Feb 12, 2024
a102a90
interim checkin; paring down bddp code
Feb 13, 2024
0dd7635
interim checkin; partially integrated; buggy
Feb 13, 2024
a83afbd
see packets, but not perfect
Feb 13, 2024
e684b90
debug cleanups
Feb 14, 2024
b5171e4
separate RX queue per stream
Feb 14, 2024
b89f7d8
adding BDPP stream processors
Feb 14, 2024
c3fff1c
working to get TX going
Feb 14, 2024
122eee1
saw some data to EZ80
Feb 15, 2024
a7a5c12
delete transmitted packet
Feb 15, 2024
9705c4a
started on BDPP doc
Feb 16, 2024
5ceef4c
Add early command list
Feb 16, 2024
ae69e24
use 2 RX interrupt choices
Feb 22, 2024
bcf23c9
playing with some settings
Feb 22, 2024
0dd3708
remove some debug code
Feb 23, 2024
c56b672
fix silly typos
Feb 23, 2024
be7306b
debug stuff
Feb 23, 2024
22829d1
ignore temp build file
Feb 23, 2024
0712e46
still debugging
Feb 23, 2024
6231583
increase char timeout
Feb 25, 2024
83f5c85
current debug code
Feb 28, 2024
b030711
reworking RX buffering
Mar 4, 2024
f8a4698
interim; debugging
Mar 4, 2024
ae90913
still debugging crash
Mar 4, 2024
bc20786
better; seeing most packets
Mar 4, 2024
d6e9b67
showing more packets
Mar 4, 2024
798e560
remove READY flag
Mar 5, 2024
32a5e53
1-byte data size
Mar 5, 2024
184b17d
remove debug code
Mar 5, 2024
9a0ea61
more typing in BDPP doc
Mar 5, 2024
8f322fc
working on doc and sample code
Mar 6, 2024
376dba1
tie in bdpp and stub for otf
Mar 6, 2024
7ad22ab
debugging app pkt transfer
Mar 6, 2024
701e59d
successful req/rsp
Mar 7, 2024
61950f3
fix response content flag
Mar 7, 2024
5a06049
working on doc
TurboVega Mar 8, 2024
c3d8f4f
Fix typo
TurboVega Mar 8, 2024
7d8f9b2
added new BDPP VDU commands
TurboVega Mar 10, 2024
0950d84
fix typo
TurboVega Mar 10, 2024
31d7230
Added BDPP command for version info
TurboVega Mar 11, 2024
eb42ab3
added transfer test app
TurboVega Mar 12, 2024
857aa89
bug fix in test app
Mar 13, 2024
458e419
transfer went ok
Mar 13, 2024
505606a
lower RX threshold
Mar 13, 2024
cd49a2d
add new test; support CTS w/BDDP OFF)
Mar 14, 2024
c4a7942
Delay before using CTS with newer MOS
Mar 14, 2024
5c4d03e
compile out debug code
Mar 14, 2024
9437e46
interim checkin; working on demo
Mar 14, 2024
23bf69b
working on demo
Mar 15, 2024
a6a5158
fixes to grabbing buffer to packet
Mar 15, 2024
5e962f2
working on using banked RAM
TurboVega Mar 17, 2024
b40c5d6
remove banked mem code
TurboVega Mar 17, 2024
ec2fd30
interim checking; more demo code
TurboVega Mar 19, 2024
3aa024b
working on demo
Mar 20, 2024
6c92a9c
more demo
Mar 20, 2024
121ae02
save code for comparison
Mar 21, 2024
98502db
bug fixes and debug output
TurboVega Mar 22, 2024
0746752
more bug fixes
Mar 22, 2024
7738bf5
got demo to work
Mar 22, 2024
ea844f7
remove debug code
Mar 22, 2024
06a2993
Merge branch 'main' into bdpp
Mar 22, 2024
2212858
remove extra line
Mar 22, 2024
d63bae5
adding code for (de)compression
TurboVega Mar 25, 2024
48c0dcd
bug fixes
Mar 25, 2024
7c6f8ff
undo debug flag
Mar 25, 2024
9b20e42
add use of compression header
TurboVega Mar 26, 2024
7624bba
bug fixes
Mar 26, 2024
8bafbd7
turn off debug flag
Mar 26, 2024
4c3d40f
kill temp file
Mar 26, 2024
2209475
Merge branch 'AgonConsole8:main' into otf-early-cut
TurboVega Mar 28, 2024
35d5383
Merge branch 'bdpp' into otf-early-cut
TurboVega Mar 28, 2024
73ed4eb
Merge branch 'compression' into otf-early-cut
TurboVega Mar 28, 2024
0f0080d
some cleanup
TurboVega Mar 28, 2024
4dc0077
working on primdemo again
TurboVega Mar 29, 2024
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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,4 @@
.vscode
.DS_Store
video/build
video.ino.cpp
1 change: 1 addition & 0 deletions platformio.ini
Original file line number Diff line number Diff line change
Expand Up @@ -30,3 +30,4 @@ build_flags =
monitor_filters = esp32_exception_decoder
monitor_speed = 115200
upload_speed = 600000
build_type = debug
4 changes: 4 additions & 0 deletions video/agon.h
Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@
#define VDP_CONTROLKEYS 0x98 // Control keys on/off
#define VDP_BUFFERED 0xA0 // Buffered commands
#define VDP_UPDATER 0xA1 // Update VDP
#define VDP_BDPP 0xA2 // Enable BDPP
#define VDP_LOGICALCOORDS 0xC0 // Switch BBC Micro style logical coords on and off
#define VDP_LEGACYMODES 0xC1 // Switch VDP 1.03 compatible modes on and off
#define VDP_SWITCHBUFFER 0xC3 // Double buffering control
Expand Down Expand Up @@ -212,6 +213,9 @@ enum AudioState : uint8_t { // Audio channel state
#define BUFFERED_REVERSE 0x18 // Reverse the order of data in a buffer
#define BUFFERED_COPY_REF 0x19 // Copy references to blocks from multiple buffers into one buffer
#define BUFFERED_COPY_AND_CONSOLIDATE 0x1A // Copy blocks from multiple buffers into one buffer and consolidate them
#define BUFFERED_GET_DATA_BYTES 0x1B // Get data bytes and return them in a BDPP packet
#define BUFFERED_COMPRESS 0x1C // Compress blocks from multiple buffers into one buffer
#define BUFFERED_DECOMPRESS 0x1D // Decompress blocks from multiple buffers into one buffer

#define BUFFERED_DEBUG_INFO 0x20 // Get debug info about a buffer

Expand Down
111 changes: 111 additions & 0 deletions video/bdpp/bdp_protocol.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,111 @@
//
// Title: Agon Video BIOS
// Author: Dean Belfield
// Subtitle: Bidirectional Packet Protocol
// Author: Curtis Whitley
// Contributors:
// Created: 29/01/2024
// Last Updated: 29/01/2024
//

#include "bdp_protocol.h"
#include <HardwareSerial.h>
#include <string.h>
#include <queue>
#include "soc/uhci_struct.h"
#include "soc/uart_struct.h"
#include "soc/uart_periph.h"
#include "driver/uart.h"
#include "uhci_driver.h"
#include "uhci_hal.h"

#define UHCI_NUM UHCI_NUM_0
#define UART_NUM UART_NUM_2
#define DEBUG_BDPP 0

#if DEBUG_BDPP
extern void debug_log(const char* fmt, ...);
#endif

bool bdpp_initialized; // Whether the driver has been initialized
std::queue<Packet*> bdpp_tx_queue; // Transmit (TX) packet queue
std::queue<UhciPacket*> bdpp_rx_queue[BDPP_MAX_STREAMS]; // Receive (RX) packet queue

//--------------------------------------------------

// Get whether the driver has been initialized.
bool bdpp_is_initialized() {
return bdpp_initialized;
}

// Initialize the BDPP driver.
//
void bdpp_initialize_driver() {
#if DEBUG_BDPP
debug_log("Activating BDPP.\n");
#endif

Serial2.end(); // stop existing communication

uart_config_t uart_config = {
.baud_rate = 1152000,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_CTS_RTS,
.rx_flow_ctrl_thresh = 64,
.source_clk = UART_SCLK_APB
};

uhci_driver_install(UHCI_NUM, 0);
uhci_attach_uart_port(UHCI_NUM, UART_NUM, &uart_config);
uart_dma_read();
bdpp_initialized = true;
}

// Queue a packet for transmission to the EZ80.
// The packet is expected to be full (to contain all data that
// VDP wants to place into it) when this function is called.
void bdpp_queue_tx_packet(Packet* packet) {
auto uhci_packet = packet->get_uhci_packet();
auto act_size = packet->get_uhci_packet()->get_actual_data_size();

#if DEBUG_BDPP
{
debug_log("Queue TX pkt: %02hX %02hX %02hX (%hu):",
uhci_packet->get_flags(),
uhci_packet->indexes,
uhci_packet->act_size, act_size);
auto data = uhci_packet->get_data();
for (uint16_t i = 0; i < act_size; i++) {
debug_log(" %02hX", data[i]);
}
debug_log("\n");
}
#endif
auto old_int = uhci_disable_interrupts();
bdpp_tx_queue.push(packet);
uhci_enable_interrupts(old_int);
uart_dma_start_transmitter();
}

// Check for a received packet being available.
bool bdpp_rx_packet_available(uint8_t stream_index) {
auto old_int = uhci_disable_interrupts();
bool available = !bdpp_rx_queue[stream_index].empty();
uhci_enable_interrupts(old_int);
return available;
}

// Get a received packet.
UhciPacket* bdpp_get_rx_packet(uint8_t stream_index) {
UhciPacket* packet = NULL;
auto old_int = uhci_disable_interrupts();
auto queue = &bdpp_rx_queue[stream_index];
if (!queue->empty()) {
packet = queue->front();
queue->pop();
}
uhci_enable_interrupts(old_int);
return packet;
}
37 changes: 37 additions & 0 deletions video/bdpp/bdp_protocol.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
//
// Title: Agon Video BIOS
// Author: Dean Belfield
// Subtitle: Bidirectional Packet Protocol
// Author: Curtis Whitley
// Contributors:
// Created: 29/01/2024
// Last Updated: 29/01/2024
//

#ifndef BDPP_PROTOCOL_H
#define BDPP_PROTOCOL_H

#include "packet.h"

typedef uint8_t bool_t; // To match what the EZ80 is using for this

#define ESP32_COMM_PROTOCOL_VERSION 0x04 // Range is 0x04 to 0x0F, for future enhancements

// Initialize the BDPP driver.
void bdpp_initialize_driver();

// Get whether the driver has been initialized.
bool bdpp_is_initialized();

// Queue a packet for transmission to the EZ80.
// The packet is expected to be full (to contain all data that
// VDP wants to place into it) when this function is called.
void bdpp_queue_tx_packet(Packet* packet);

// Check for a received packet being available.
bool bdpp_rx_packet_available(uint8_t stream_index);

// Get a received packet.
UhciPacket* bdpp_get_rx_packet(uint8_t stream_index);

#endif // BDPP_PROTOCOL_H
200 changes: 200 additions & 0 deletions video/bdpp/bdp_stream.h
Original file line number Diff line number Diff line change
@@ -0,0 +1,200 @@
//
// Title: Agon Video BIOS
// Author: Dean Belfield
// Subtitle: Bidirectional Packet Protocol
// Author: Curtis Whitley
// Contributors:
// Created: 13/02/2024
// Last Updated: 13/02/2024
//

#pragma once
#include <Stream.h>
#include "bdpp/bdp_protocol.h"

#define DEBUG_BDPP 0

#if DEBUG_BDPP
extern void debug_log(const char* f, ...);
#endif

// This class represents a stream of data coming from BDPP.
//
class BdppStream : public Stream {
public:
// Construct a stream
//
// This defaults to stream #0, and is intended for creating
// an array of streams. To set the proper stream index, use
// the set_stream_index() function, below.
//
BdppStream() {
packet_index = 0;
stream_index = 0;
rx_packet = NULL;
tx_packet = NULL;
data_index = 0;
}

// Destroy the stream.
//
virtual ~BdppStream() {
if (rx_packet) {
delete rx_packet;
}
if (tx_packet) {
delete tx_packet;
}
}

// Set the stream index for this stream.
//
void set_stream_index(uint8_t stream_index) {
this->stream_index = stream_index;
}


#if DEBUG_BDPP
void show_rx_packet(UhciPacket* packet) {
auto act_size = packet->get_actual_data_size();
auto data = packet->get_data();
debug_log("RX pkt: %02hX %02hX %02hX (%u): ",
packet->get_flags(),
packet->indexes,
packet->act_size, act_size);
for (uint16_t i = 0; i < act_size; i++) {
auto ch = data[i];
if (ch == 0x20) {
debug_log("-");
} else if (ch > 0x20 && ch < 0x7E) {
debug_log("%c", ch);
} else {
debug_log("[%02hX]", ch);
}
}
debug_log("\n");
}
#endif

// Check for available data
//
// Data is available if we have a current packet where
// not all data bytes have been consumed (we discard
// packets that have a zero actual data size).
//
// If there is no current packet, but we can pull one from
// the packet queue, and the packet has a non-zero size,
// then data is available.
//
virtual int available() {
while (true) {
if (rx_packet) {
return rx_packet->get_actual_data_size() - data_index;
}
if (bdpp_rx_packet_available(stream_index)) {
rx_packet = bdpp_get_rx_packet(stream_index);
#if DEBUG_BDPP
show_rx_packet(rx_packet);
#endif
auto act_size = rx_packet->get_actual_data_size();
if (act_size) {
data_index = 0;
return act_size;
}
// ignore empty packet
rx_packet = NULL;
} else {
return 0; // no data available
}
}
}

// Read data from the current packet, if any.
//
// After reading a data byte, if the current packet has no more
// data left in it, we delete that packet (trusting that the
// "available()" function will grab another one from the queue later).
//
virtual int read() {
if (available()) {
auto result = (int)(uint)(rx_packet->get_data()[data_index++]);
if (data_index >= rx_packet->get_actual_data_size()) {
rx_packet = NULL;
}
return result;
} else {
return -1;
}
}

// Peek at available data, if any exists.
//
// This will return an available data byte, but will not remove
// that byte from the current packet.
//
virtual int peek() {
if (available()) {
return (int)(uint)(rx_packet->get_data()[data_index]);
} else {
return -1;
}
}

// Write data to the stream.
//
// This builds an outgoing (TX) packet, and sends it when full.
//
virtual size_t write(uint8_t data_byte) {
if (!tx_packet) {
tx_packet = Packet::create_driver_tx_packet(
BDPP_PKT_FLAG_PRINT | BDPP_PKT_FLAG_MIDDLE,
packet_index++, stream_index);
if (packet_index >= BDPP_MAX_DRIVER_PACKETS) {
packet_index = 0;
}
}
tx_packet->get_uhci_packet()->append_data(data_byte);
if (tx_packet->is_full()) {
bdpp_queue_tx_packet(tx_packet);
tx_packet = NULL;
}
return 1;
}

// Make available for writing.
//
virtual int availableForWrite() {
return true;
}

// Flush the stream.
//
// This will flush any packet currently being built.
//
virtual void flush() {
if (tx_packet) {
bdpp_queue_tx_packet(tx_packet);
tx_packet = NULL;
}
}

// Start an app-owned packet
//
// This will flush any existing TX packet, and start a new one,
// intended for a particular app-owned packet index at the EZ80.
//
Packet* start_app_response_packet(uint8_t packet_index) {
flush();
tx_packet = Packet::create_app_tx_packet(
BDPP_PKT_FLAG_PRINT | BDPP_PKT_FLAG_FIRST | BDPP_PKT_FLAG_RESPONSE,
packet_index, stream_index);
return tx_packet;
}

protected:
uint8_t packet_index; // index of an outgoing packet
uint8_t stream_index; // index of this string (0..BDPP_MAX_STREAMS-1)
uint16_t data_index; // index into data portion of current packet
UhciPacket* rx_packet; // current packet used to extract data
Packet* tx_packet; // current packet used to output data
};
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