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RADEFT symbols are in a kicad_sym library file. RADEFT footprints are in a .pretty folder file.
pls work
in process of implementing changes for rev2
uploaded cygnet devboard v1 firmware reference & updated schematic and layout for v2 demo. to do: assign new jlc part numbers
Uses CD-PA1616D from Adafruit
Using RP2350. To do list listed inside KiCAD main page. Will continue to work on it in available time.
- more decoupling caps - i2c address config
-implemented 3.3v to 12v boost converter -radfet readout circuitry done (i think) -added readout circuitry from oresat & proves fc v5c board -finished gps schematic (need footprint still) -added few LEDs main priorities: -watchdog circuit -calculate voltage div resistor values for 12v -gps footprint
- removed pullup resistors on i2c 0 (proves board has the pullups)
- will be adding nand flash for more long term storage of gps and radfet data & telemetry - gps footprint not finished but started. will finish when i get access to a mouse
- refined gps footprint - reorganized schematic
jfets no more for now. Also added footprints to some symbols.
- using analog switch ic to switch between sense & readout (tmux1133) - added non inverting buffer for voltage readout - haven't fully deep dived into the new components & must look into more
-replaced custom circuitry with radfet readout modules -cleaned up sensor schematic page -changed temp sensor -added more missing footprints
layout yay
Might need to make a footprint for the power switch, since i couldn't find anything online
- fixed issue with ospi chip select line & clk line - replaced 1k pulldowns with 10k pulldowns and added 1k series resistors to 1.8V line for boot config lines -removed unused global label tags from som and changed to nc - repinmuxed for potential watchdog and ospi changes to do: -microSD -reallocate gpios (extras to breakout) -create 8pin jst connector for lucid camera (12V pwr) - give satnogs additional uart - reorg/rename global labels -watchdog input pin reassign to c62 potentially after feedback from max
Not 100% sure on the LSM6DSO footprint, that needs to get checked.
-fixed the microsd implementation -fixed an oopsie where i accidentally removed the ethernet som connections and marked as nc (2am oopsie lol), -renamed the som global labels as their som signals -modified watchdog input from the jtag trst to the dedicated wdog output pin on som to do: -breakout connectors for gpio & adc -test/debug points/ports - connect 1 more gpio to ebyte connection - connect uart2 to satnogs, no longer free use as breakout -check footprints
-more load switches -more organization of pin definition & external board connection page -cmos image sensor power connection debug/test/utility header pins
Only thing i didn't touch was watchdogs. That might still need to be changed.
-finished debug/utility header pin section (may have to reassign some gpios again tho) - added can bus transceiver and connection to satnogs - reassigned/ ensured no i2c address conflict - resolved critical error in LTC-3115 power regulator symbol where output power was shorted to sync pin -resolved critical symbol issue in which imx8x som power good symbol shorted to gnd, which would result in nonfunctional board & 2 jtag pins shorted to do: - assign gpio to a load switch - resolve erc issues - footprint check (shunt resistor change, some new ics need footprints, cmos image sensor 8 pin jst connector, etc)
…ent (Radfet) connections" This reverts commit 38d5a61.
…PIO level shifter, footprint selection & pathway fix component footprints for most part have been selected going to double check again tmr imx8x som bth samtec connector footprint needs to be adjusted as reference footprint uses each connector as individual symbol, while we have as part of one symbol (spacing between connector is important so som can fit in) also one component didnt have part (uart mux) and havent assigned implemented can bus interface with satnogs, moved around gpios, level shifted 8 gpios, fixed few missing connections (gps 1pps, a load switch enable gpio), resolved some erc errors/ symbol shorts, incorrect pinmux implementation around A9&10 for uSD and gpio, reannotated schematic, fixed footprint reference paths
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phyCORE-i.MX 8X Carrier Board — Revision 1.0 Schematics (03-22-2026)
Summary
This pull request introduces the Revision 1.0 (2026-03-22) schematics for the CADENCE phyCORE-i.MX 8X Carrier Board.
The design provides a platform for the i.MX 8X System on Module (SOM) for use in CADENCE as a flight computer.
Key Features
Schematic Page Overview
Page 1 — Block Diagram
Page 2 — IMX8X SOM Samtec Connectors and Notes
Page 3 — Power System
Power distribution tree implementation:
Page 4 — External Watchdog Timer
Page 5 — User Controls
Page 6 — microSD Interface
Page 7 — Flash and MRAM Memory
Page 8 — Ethernet PHY
Page 9 — Ethernet Connectors
Page 10 — USB Ports
Page 11 — Payload Board Connection
External payload interface:
Page 12 — Blank
Page 13 — GPS and Power Monitor
Page 14 — Onboard Sensors
Sensor/peripheral suite includes:
Page 15 — Debug USB (UART/JTAG)
Page 16 — External and SATNOGS Connections
Interfaces for:
Notes