UNIVERSITY OF WEST ATTICA
SCHOOL OF ENGINEERING
DEPARTMENT OF COMPUTER ENGINEERING AND INFORMATICS

University of West Attica · Department of Computer Engineering and Informatics

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Digital Circuit Design

Register Files

Vasileios Evangelos Athanasiou
Student ID: 19390005

GitHub · LinkedIn

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Supervision

Supervisor: Ioannis Vogiatzis, Professor

UNIWA Profile · LinkedIn

Supervisor: Panagiotis Karkazis, Associate Professor

UNIWA Profile · LinkedIn

Co-supervisor: Athanasios Milidonis, Postdoctoral Researcher

Scholar · LinkedIn

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Athens, May 2023

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README

Register Files

The project focuses on modeling, simulating, and verifying sequential logic circuits using VHDL.
Each circuit is implemented using a clear architectural style and is accompanied by a testbench to validate its behavior under different timing and control conditions.

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Table of Contents

Section	Folder / File	Description
1	assign/	Laboratory assignment material
1.1	assign/Lab4b_UniWA-BSc-DSD_VHDL#2b.pdf	Laboratory exercise description (English)
1.2	assign/Εργαστήριο4β_ΠΑΔΑ-ΣΨΣ_VHDL#2β.pdf	Laboratory exercise description (Greek)
2	docs/	Theoretical documentation on register files
2.1	docs/Register-Files.pdf	Register files theory and architecture (English)
2.2	docs/Αρχεία-Καταχώρησης.pdf	Register files theory and architecture (Greek)
3	src/	VHDL source code implementations
3.1	src/reg8.vhd	8-bit register implementation
3.2	src/regfile.vhd	Register file implementation
3.3	src/regfileUpd.vhd	Updated register file implementation
4	waves/	Simulation waveform outputs
4.1	waves/wave1.png	Simulation waveform snapshot
4.2	waves/wave2.png	Simulation waveform snapshot
4.3	waves/wave3.png	Simulation waveform snapshot
4.4	waves/wave4.png	Simulation waveform snapshot
4.5	waves/wave5.png	Simulation waveform snapshot
4.6	waves/wave6.png	Simulation waveform snapshot
4.7	waves/waveF*.bmp	Register file simulation waveforms
4.8	waves/waveU*.bmp	Updated register file simulation waveforms
5	README.md	Project documentation
6	INSTALL.md	Usage instructions

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1. Technical Specifications

1.1 Simple 4-Bit Register

A 4-bit register designed using D-type flip-flops with the following characteristics:

Inputs

• D: 4-bit data input
• Resetn: Asynchronous active-low reset
• Clock: System clock

Outputs

• Q: 4-bit data output

Behavior

• On the rising edge of the clock, the input D is transferred to the output Q, provided Resetn = '1'.
• If Resetn = '0', the output is immediately cleared to "0000".

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2. Register File (4×4)

A more advanced register file consisting of four 4-bit registers.

Generics

• dw: Data width (4 bits)
• size: Number of registers (4)
• addrw: Address width (2 bits)

Interface

• A: Input data
• Addr: 2-bit address selecting the target register
• we: Write enable signal
• clk: System clock
• C: Output data from the selected register

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3. Simulation Results

The project includes timing diagrams verifying correct functionality for the following operations:

Operation	Address	Data	Status
Write Register	00	0101	Verified
Write Register	10	1101	Verified
Write Register	01	0010	Verified

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4. Implementation Details

• Language: VHDL
• Libraries Used:
  • ieee.std_logic_1164
  • ieee.numeric_std
• The register file utilizes an array type (regArray) to model internal storage elements, enabling scalable and clean design.