🎓 Electronics Engineer | 🧠 M.Sc. in Electronic Sciences (INAOE) | 📍 PhD student in ASIC Verification
🔬 Passionate about digital design, FPGAs, UVM-based verification, and scientific instrumentation systems
I am an electronics engineer with experience in digital architecture design for FPGA and ASIC platforms, development of Physical Unclonable Functions (PUFs) for cancellable biometrics, and functional verification using SystemVerilog and UVM. I am currently pursuing a PhD at INAOE, where my work focuses on developing verification methodologies for Application-Specific Integrated Circuits (ASICs).
- Verilog / VHDL / SystemVerilog
- FPGA platforms (Xilinx, Intel, Renesas ForgeFPGA)
- Simulation and synthesis tools (Vivado, Quartus, ModelSim, DSim)
- Python for scripting and data analysis
- UVM (Universal Verification Methodology)
- Design of SAR ADCs, TDCs, and ΣΔ modulators
- 🔐 Research on Physical Unclonable Functions (PUFs) for hardware security and cancellable biometrics
- 🧪 Development of automated UVM testbench templates
- 🔄 Integration of verification workflows using GitHub and CI-style automation
To develop robust and scalable functional verification solutions for ASIC and FPGA designs, contributing to scientific and industrial projects that demand high reliability, precision, and hardware-level confidence.
- 📧 enrique.namigtle@inaoe.edu.mx
- [ResearchGate]
- 📄 CV