GitHub - Needahh/Verilog_ProjectsS: Simple HDL Projects and Simulations(Verilog/SystemVerilog

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
README.md		README.md
adder.v		adder.v
adder.vcd		adder.vcd
adder_tb.v		adder_tb.v
adder_tb.vvp		adder_tb.vvp
cyclic_lamp.v		cyclic_lamp.v
cyclic_lamp_tb.v		cyclic_lamp_tb.v
half_adder.v		half_adder.v
half_adder.vcd		half_adder.vcd
half_adder_tb.v		half_adder_tb.v
half_adder_tb.vvp		half_adder_tb.vvp
latch1.v		latch1.v
latch1.vcd		latch1.vcd
latch1_tb.v		latch1_tb.v
latch1_tb.vvp		latch1_tb.vvp
muxtest.v		muxtest.v
muxtest.vcd		muxtest.vcd
muxtest_tb.v		muxtest_tb.v
muxtest_tb.vvp		muxtest_tb.vvp
xor_bitwise.v		xor_bitwise.v
xor_bitwise_tb.v		xor_bitwise_tb.v