Popular repositories Loading

1. Full_Adder Full_Adder Public

   This project implements a 1-bit Full Adder in Verilog RTL and demonstrates the complete RTL-to-netlist ASIC flow using Cadence tools. The design is verified by simulation, synthesized using Cadence…

   Verilog

2. RippleCarryAdder-rtl- RippleCarryAdder-rtl- Public

   This project implements a ripple carry adder using Verilog RTL and demonstrates the complete RTL-to-netlist ASIC flow with Cadence tools. The design is verified through simulation, synthesized usin…

   Verilog

3. lfsr8bit-rtl2gdsii- lfsr8bit-rtl2gdsii- Public

   This project implements an 8-bit LFSR using Verilog RTL and demonstrates the complete ASIC flow from RTL to GDS II using Cadence tools. The design is simulated, synthesized with Cadence Genus, veri…

4. serialadder-rtl2gdsii- serialadder-rtl2gdsii- Public

   This project implements a serial adder using Verilog RTL and demonstrates the complete ASIC design flow from RTL to GDS II using Cadence tools. The design is verified by simulation, synthesized usi…

   Tcl

5. SISO-RTL- SISO-RTL- Public

   This project implements a shift register using Verilog RTL and demonstrates the ASIC flow from RTL to GDS II using Cadence tools. The design is verified by simulation, synthesized with Cadence Genu…

   Tcl

6. ALU-rtl-netlist- ALU-rtl-netlist- Public

   This project implements an ALU using Verilog RTL and demonstrates the RTL-to-netlist ASIC flow using Cadence tools. The design is verified through simulation, synthesized using Cadence Genus, and v…

   Verilog