This repository contains selected hardware, RTL, and embedded systems projects demonstrating experience in computer architecture, RTL design, embedded firmware, and hardware–software integration. The focus is on low-level implementation, verification, and hands-on hardware debugging using industry-relevant tools.
Technologies: SystemVerilog, RISC-V RV32I, Vivado, FPGA
Designed and implemented a 32-bit RV32I-compliant RISC-V processor with a classic 5-stage pipeline (IF, ID, EX, MEM, WB). The processor was written in SystemVerilog, verified through RTL simulation, and synthesized and tested on FPGA using Vivado.
- Modular datapath and control design
- Hazard detection logic with pipeline stalling for data and control hazards
- Data forwarding paths to reduce stalls and improve throughput
- Pipeline control for correct instruction sequencing and state propagation
- Developed SystemVerilog testbenches to validate instruction execution and pipeline behavior
- Verified correct stalling and forwarding behavior using waveform analysis
- Debugged pipeline control and timing issues through iterative simulation
- RTL design in SystemVerilog
- Simulation and waveform inspection
- FPGA synthesis and testing using Vivado
📂 Source Code: RISC-V Processor
Technologies: C, STM32L476, Register-Level Programming, ADC, PWM, UART, Watchdog Timer
Designed and implemented a real-time embedded sun-tracking system using an STM32 microcontroller. The system measures light intensity via photoresistors and dynamically adjusts servo motors to maintain optimal alignment.
- Bare-metal firmware using direct register access (no HAL)
- ADC-based sensing with dual photoresistors
- PWM-based motor control for servo actuation
- UART interface for command input and debugging
- Watchdog timer integration for fault detection and recovery
- Validated peripheral behavior and signal timing using oscilloscopes and digital multimeters
- Debugged hardware–firmware integration issues during system bring-up
- Verified real-time behavior and peripheral configuration
📂 Source Code: Sun-Tracking Firmware
These projects emphasize:
- Hardware correctness before optimization
- Clear separation of datapath, control, and verification logic
- Debugging through signals, registers, and waveforms
- Understanding architectural and system-level tradeoffs
- HDL & RTL: SystemVerilog
- Embedded: C, STM32, Bare-Metal Programming
- Hardware Tools: FPGA, Vivado, Yosys, Oscilloscope, Digital Multimeter
- Version Control: Git, GitHub
Ryan Salute 📧 rsalute100@gmail.com 🔗 LinkedIn 💻 GitHub