*Make sure to clone ascon-verilog's repo and place it in HW directory.

ASCON-HS-Project

Hardware Security Project: Hardware and Software Implementation of ASCON (NIST SP 800-232)

Overview

This repository contains a dual hardware-software verification project for the ASCON lightweight cryptographic algorithm. It features a high-performance software model written in Rust and a SystemVerilog hardware implementation. The hardware RTL is rigorously verified against golden test vectors generated by the software model using a cocotb and Verilator co-simulation testbench.

Project Structure

• HW/: SystemVerilog RTL source files for the ASCON core.
• SW/: Rust source code (main.rs) for the software implementation and test vector generation.
• test.py: Python cocotb testbench for hardware simulation.
• Makefile: Build configurations for Verilator and Yosys synthesis.

Supported Variants

• ASCON-AEAD128 (Authenticated Encryption with Associated Data)
• ASCON-Hash256
• ASCON-XOF128 & ASCON-CXOF128 (Extendable Output Functions)

Prerequisites

Ensure the following tools are installed on your system:

• Rust Toolchain: rustc and cargo (for the software model).
• Verilator: Cycle-accurate C++ simulator for SystemVerilog.
• Python 3: With the cocotb framework installed (pip install cocotb).
• Make: For executing the simulation build scripts.

Usage Instructions

1. Generate Golden Test Vectors (Software)

Navigate to the software directory and run the Rust model to generate cryptographically random test vectors. This will append a new run to the vectors.txt file containing the Initialization Vector, Key, Nonce, Plaintext, Ciphertext, and Tags.

cd SW
cargo run --release

2. Run Hardware Verification (Co-simulation)

With vectors.txt generated in the root directory, execute the testbench. The cocotb script will parse the Rust vectors (packing them into little-endian format), drive them into the Verilog hardware state machine, and assert that the hardware outputs match the software perfectly.

make SIM=verilator TESTCASE=test_rust_vectors

Security Features

The hardware implementation includes inherent countermeasures against physical attacks:

• Constant-Time Execution: The core permutation layer operates independently of data and key values, mitigating timing side-channel attacks.
• Strict Domain Separation: State matrices are securely separated before plaintext absorption via targeted constant XORing (e.g., 0x8000000000000000), strictly adhering to the NIST SP 800-232 standard.