Add Zbs single-bit operations implementation (RV32, SystemVerilog)#191
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Add Zbs single-bit operations implementation (RV32, SystemVerilog)#191
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🔧 DE1-SoC Synthesis Report Summary Diff📊 Fitter Summary (.fit.summary)@@ -1,4 +1,4 @@
-Fitter Status : Successful - Thu Mar 5 15:07:10 2026
+Fitter Status : Successful - Fri Mar 6 06:40:05 2026
Quartus Prime Version : 25.1std.0 Build 1129 10/21/2025 SC Lite Edition
Revision Name : utoss-risc-v
Top-level Entity Name : top⏱️ Timing Analysis Summary (.sta.summary)No changes detected Comparing synthesis results from main branch vs. this PR |
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Thanks for the PR! Let us merge #190 first, so that you can use the |
src/ext/b/zbs.sv
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| // Zbs: Single-Bit Operations (RV32) | ||
| // | ||
| // Implements: | ||
| // - bclr / bclri | ||
| // - bset / bseti | ||
| // - binv / binvi | ||
| // - bext / bexti | ||
| // | ||
| // Design note: | ||
| // - Purely combinational ALU block | ||
| // - reg2[4:0] used as bit index | ||
| // - R/I distinction handled in decoder | ||
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for the documentation here I would just specify the section of the specification that corresponds to Zbs extension
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Just merged #190 , please rebase onto latest main so you can use |
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Implements RV32 Zbs single-bit operations:
Design follows abstract ALU pattern: