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1. APB-Master-Bridge APB-Master-Bridge Public

   The master of APB bus is the bridge between the previous system bus and APB bus. This bridge is also a slave to the previous system bus. So, it has two interfaces, previous bus slave interface and …

   Verilog 8 2

2. Register_File Register_File Public

   This is the Verilog code and synthesis output of my parameterized register file that operates at 10 MHz.

   Verilog 2

3. GPS_Tracking_System_AAAYYE GPS_Tracking_System_AAAYYE Public

   C 1

4. YousefSherif YousefSherif Public

5. Washing-Machine-Controller Washing-Machine-Controller Public

   Verilog

6. Up_Down_Counter Up_Down_Counter Public

   This is the Verilog code and synthesis output of my parameterized up-down counter.

   Tcl