[None][perf] Fuse MiniMax-M3 MSA block selection - #18
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Add the MiniMax-M3 MSA sparse attention backend with CUDA-graph support and integrate the MSA fmha_sm100 kernels as a git submodule at 3rdparty/MSA. Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
[None][perf] Fused GEMM + SwiGLU-OAI
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
…x-M3 on the MSA backend (#4) Signed-off-by: Zheyu Fu <zheyuf@nvidia.com>
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
Signed-off-by: Balaram Buddharaju <169953907+brb-nv@users.noreply.github.com>
[None][perf] Fuse MiniMax-M3 MoE routing
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
…branch [TRTLLM-14255][fix] migrate MiniMax M3 to loader v2 for TP8 support
Signed-off-by: peihengh <259410613+peihu-nv@users.noreply.github.com>
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@coderabbitai summary
Description
MiniMax-M3 MSA block selection currently runs validity masking, forced-block handling, top-k, and sorting as separate PyTorch operations. This PR replaces that sequence with one CUDA custom op that returns ascending
int32block IDs with-1padding.Matched serving A/B results:
Test Coverage
python -m pytest -q tests/unittest/_torch/attention/sparse/test_minimax_m3_msa_selector.py(26 passed)tests/integration/defs/accuracy/test_llm_api_pytorch.py::TestMiniMaxM3::test_nvfp4[use_msa=True](passed; MMLU 84.80%, GSM8K 90.60%)PR Checklist
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