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What happens for a readwrite memory port with read-under-write => old and latency of 2 -- both read and write in the same cycle?!

Status: Open.

#263 In chipsalliance/firrtl-spec;

· programmerjake opened on Dec 6, 2024

what happens for combinational loops through a register's async reset input?

Status: Open.

#260 In chipsalliance/firrtl-spec;

· programmerjake opened on Dec 2, 2024

stateful declarations shouldn't be allowed in conditions (was: what happens when you read from inactive enum variants)

Status: Open.

#255 In chipsalliance/firrtl-spec;

· programmerjake opened on Nov 15, 2024

what is an enum's corresponding mask type? for memory write ports

Status: Open.

#211 In chipsalliance/firrtl-spec;

· programmerjake opened on May 13, 2024

are zero field/variant enum/bundle types legal

Status: Open.

#208 In chipsalliance/firrtl-spec;

· programmerjake opened on Apr 25, 2024

Add CI/CD flow to bump CIRCT Version

Status: Open.

#180 In chipsalliance/firrtl-spec;

· seldridge opened on Feb 20, 2024

Add Lowering Convention to External, Public Modules

Status: Open.

#171 In chipsalliance/firrtl-spec;

· seldridge opened on Feb 11, 2024

Introduce LTL as a part of firrtl specification

Status: Open.

#157 In chipsalliance/firrtl-spec;

· sequencer opened on Dec 1, 2023

Ability to reference and generate modules with escaped identifiers?

Status: Open.

#134 In chipsalliance/firrtl-spec;

· smarter opened on Oct 18, 2023

Add a bitcast primitive to match CIRCT's <code>firrtl.bitcast</code> ?

Status: Open.

#133 In chipsalliance/firrtl-spec;

· smarter opened on Oct 18, 2023

Should the File Preamble be enhanced to include the ABI version?

Status: Open.

#132 In chipsalliance/firrtl-spec;

· smarter opened on Oct 18, 2023

Add CHIRRTL memories, cmem/smem, to the Specification

Status: Open.

#131 In chipsalliance/firrtl-spec;

· seldridge opened on Sep 29, 2023