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cirofabianbermudez/README.md

Hi πŸ‘‹, I'm Ciro

I'm a Electronic/Verification engineer

  • πŸ’¬ Ask me about C/C++, Verilog, SystemVerilog, UVM.
  • 🌱 I'm currently learning SystemC.
  • πŸ’‘ I'm interested in VLSI, Chip design and FPGAs.

Skills:

C C++ CMake Python R Lua PowerShell Bash Script Markdown YAML LaTeX Neovim Visual Studio Code Obsidian HTML5 CSS3 Git GitHub GitLab GitHub Actions GitLab CI Github Pages Gitpod FFmpeg Inkscape Linux Pop!_OS MySQL Matplotlib NumPy Pandas SciPy

VLSI:

Pinned Loading

  1. uart_ip uart_ip Public

    UART ip FPGA verilog/systemverilog

    C++

  2. i2c_ip i2c_ip Public

    I2C ip FPGA verilog/systemverilog

    SystemVerilog 1

  3. spi_ip spi_ip Public

    SPI IP FPGA Verilog/SystemVerilog

    Tcl

  4. fifo_ip fifo_ip Public

    FIFO ip FPGA verilog/systemverilog

    SystemVerilog

  5. uvmcollab/uvmcollab.github.io uvmcollab/uvmcollab.github.io Public

    Source repository for the UVM-Collab documentation site, a unified reference for verification frameworks, tools, and guidelines.

    Python