AsteRISC is a flexible multi-cycle RISC-V core designed for design space exploration.
It is written in platform-independent SystemVerilog and targets both FPGAs and ASIC technologies.
Supported RISC-V extensions: RV32[I/E][M][C][Zicsr]
- Architectural flexibility for generating a wide array of microarchitectures.
- Designed to cater to diverse performance requirements and application scenarios.
- Suited for both FPGA and physical (ASIC) implementation.
- Uses Odatix to help you find the configuration that best suits your application needs.
For any inquiries or support, feel free to contact me at jonathan.saussereau@ims-bordeaux.fr.
Note: AsteRISC is under active development, and we appreciate your feedback and contributions to make it even more powerful and user-friendly.