Wires over regs ?

[Paulo-D2000]

Hi sir on the diagram I see that RD1_D -> RD1_E is a wire and AluResult_M -> AluResult_W is also a wire... But on your verilog sources they're linked by registers...

[HamzaShabbir517]

They can't be a wire. As RD1_D is going from decode stage to Execute Stage so they have to be reg. Same is with ALU_Result.