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fix: Update Python requirements for reggen and future Cheshire update with PeakRDL #315

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fix: Update Python requirements for reggen and future Cheshire update with PeakRDL #315

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a8722d4
fix: Update Python requirements for reggen
CyrilKoe May 28, 2026
60a7508
fix: Reduce sw artifacts
CyrilKoe Jun 1, 2026
8acf83d
feat: Update vivado
CyrilKoe Jun 2, 2026
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2 changes: 1 addition & 1 deletion carfield.mk
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Expand Up @@ -57,7 +57,7 @@ include $(CAR_ROOT)/bender-safed.mk
######################

CAR_NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:carfield/carfield-nonfree.git
CAR_NONFREE_COMMIT ?= 57afcb6
CAR_NONFREE_COMMIT ?= 1217f1f

## @section Carfield platform nonfree components
## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC
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8 changes: 6 additions & 2 deletions requirements.txt
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@@ -1,8 +1,8 @@
hjson
jsonref
jsonschema
Mako==1.1.6
PyYAML==6.0
Mako
PyYAML
pyelftools==0.29
requests
mako
Expand All @@ -14,3 +14,7 @@ mkdocs-material
mkdocs-glightbox
dataclasses
jstyleson
flatdict
peakrdl
peakrdl-rawheader
setuptools<81
8 changes: 4 additions & 4 deletions target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
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Expand Up @@ -25,7 +25,7 @@ set script_folder [_tcl::get_script_folder]
################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2020.2
set scripts_vivado_version 2022.1
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
Expand Down Expand Up @@ -137,7 +137,7 @@ xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:ddr4:2.2\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:util_ds_buf:2.1\
xilinx.com:ip:util_ds_buf:2.2\
xilinx.com:ip:vio:3.0\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:xdma:4.1\
Expand Down Expand Up @@ -353,15 +353,15 @@ proc create_root_design { parentCell } {
] $psr_333

# Create instance: util_ds_buf_0, and set properties
set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0 ]
set util_ds_buf_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_0 ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {IBUFDS} \
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {Custom} \
CONFIG.USE_BOARD_FLOW {true} \
] $util_ds_buf_0

# Create instance: util_ds_buf_1, and set properties
set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_1 ]
set util_ds_buf_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.2 util_ds_buf_1 ]
set_property -dict [ list \
CONFIG.C_BUF_TYPE {IBUFDSGTE} \
CONFIG.DIFF_CLK_IN_BOARD_INTERFACE {pcie_refclk} \
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2 changes: 1 addition & 1 deletion target/xilinx/scripts/flash_spi.tcl
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Expand Up @@ -8,7 +8,7 @@
open_hw_manager

connect_hw_server -url $::env(XILINX_HOST):$::env(XILINX_PORT)
open_hw_target [get_hw_targets $::env(XILINX_FPGA_PATH)]
open_hw_target [get_hw_targets]

set file $::env(FILE)
set offset $::env(OFFSET)
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2 changes: 1 addition & 1 deletion target/xilinx/scripts/program.tcl
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Expand Up @@ -9,7 +9,7 @@ puts $::env(XILINX_BIT)
open_hw_manager

connect_hw_server -url $::env(XILINX_HOST):$::env(XILINX_PORT)
open_hw_target [get_hw_targets $::env(XILINX_FPGA_PATH)]
open_hw_target [get_hw_targets]

if {$::env(XILINX_BOARD) eq "genesys2"} {
set hw_device [get_hw_devices xc7k325t_0]
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2 changes: 1 addition & 1 deletion target/xilinx/xilinx.mk
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Expand Up @@ -10,7 +10,7 @@
# Makefile variables (user inputs are in capital letters)
#

VIVADO ?= vitis-2020.2 vivado
VIVADO ?= vitis-2022.1 vivado

XILINX_PROJECT ?= carfield
# XILINX_FLAVOR in {vanilla,bd} see carfield_bd.mk
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