Add Verilator simulation backend - #57
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make run platform=verilator runs a prebuilt Vmagia_tb from the MAGIA repo. Stimuli generation is factored out of the rtl branch into a shared rtl_stimuli target; both backends drive the same testbench with the same plusargs. The model is not built here. MAGIA_VERILATOR_BIN must point at one built with `make verilate` in the MAGIA repo, and since the mesh size is compiled into the model, tiles= has to match it. Verilator prints no "Errors:" summary and exits 0 when it runs out of events without reaching $finish, so sim_ret_errors.sh does not apply. Add sim_ret_errors_verilator.sh, keyed on the testbench's end-of-simulation line. Also fixes the hardcoded ./build/bin path in the stimuli step, which broke whenever CMAKE_BUILDDIR was overridden.
make MAGIA platform=verilator verilates the mesh instead of building the QuestaSim libraries. Parameter seds, environment bootstrap and the rest of the chain are shared with the rtl path; only the final build command differs. tiles= now reparameterizes the model, so the previous "model is fixed at 4x4" caveat is gone. platform defaults to rtl for MAGIA and rtl-clean, leaving existing invocations and CI unchanged. run still requires it explicitly. Reject up front what verilator.mk rejects later: tiles=1 or mesh_dv=0 (the flow is mesh-only) and magia_v1 (selects CV32E40X). rtl-clean platform=verilator runs clean-verilate. Note hw-clean-all deletes .bender, which invalidates a verilator model built from the same checkout.
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Replaces the parse_s19.pl | s19tomem.py pipeline with a single Rust pass over the SREC, dropping the intermediate verif.txt. Both rtl and verilator pick it up: they already share rtl_stimuli. Built on demand with rustc into build/tools/s19tomem; one file, so no cargo project. Vendored from the MAGIA repo, where it is not committed and absent from the pinned commit. That copy ports MAGIA's s19tomem.py, which uses DATA_SIZE=0x30000; the SDK's used 0x60000, kept here so the data window does not shrink and drop everything above 0xcc04_0000. Output is byte-identical to the old pipeline on test_helloworld, trailing-newline asymmetry included.
FrancescoConti
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Left in draft to avoid merging accidentally before pulp-platform/MAGIA#98 |
Drops verilator_fst: gui already means "let me look at the waveform", and for verilator that is an FST rather than an interactive window. The dump goes to <test>.fst in the test dir, overridable via VERILATOR_FST, and the run prints gtkwave and surfer commands for it when it ends. fast_sim stays QuestaSim-only.
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Depends on pulp-platform/MAGIA#98, which should be merged first.
Add Verilator as a simulation backend
Adds
verilatoralongsidertlandgvsocas a simulation platform, covering both building the model and running tests on it.The
verilatorflow provides an intermediate step between a commercial RTL flow and the non-cycle-accurategvsocflow in terms of speed, signal visibility, and supported features.Usage
The flow is similar to the existing
rtlflow.make MAGIA platform=verilator tiles=4 # verilate the mesh (few minutes) make build test=test_helloworld tiles=4 make run test=test_helloworld platform=verilator tiles=4make MAGIA platform=verilatorapplies exactly the same parameter edits to the RTL as the commercial build (num_cores,core,N_TILES_X/Y,FSYNC_STALL) and shares the whole environment bootstrap; only the final build command differs —verilateinstead ofbuild-hw.New options:
verilator_jobs(16),verilator_threads(4),MAGIA_VERILATOR_BIN(model path).make rtl-clean platform=verilatorrunsclean-verilate.platformdefaults tortlforMAGIAandrtl-clean, so existing invocations are unchanged;make runstill requires it explicitly. By default, theverilatormodel does not trace waveforms; it does ifgui=1is passed, saving them in FST format.Requires Verilator >= 5.046 and a MAGIA checkout containing
verilator/verilator.mk.Runtime comparison
test_helloworld, 4x4 mesh,target_platform=magia_v3, on a Intel Xeon Platinum 8480+.rtlrtlverilator(1 thread,gui=0)verilator(4 threads,gui=0)verilator(4 threads,gui=1)gvsocNote: these results are heavily dependent on the specific configuration and test, and are provided here only to frame the relative speed of the various flows.
Notes for review
make runinvokesVmagia_tbdirectly rather than going through the MAGIA repo'smake verilate-run. That target declaresverilate-run: all, andallreaches$(BIN): $(CRT) $(OBJ), so it would try to compilesw/tests/<test>.cinside the RTL repo — a file that does not exist for SDK-injected tests.Stimuli generation replaced.
parse_s19.pl | s19tomem.pybecomes a single Rust pass over the SREC (scripts/s19tomem.rs), dropping the intermediateverif.txt. Built on demand withrustcintobuild/tools/s19tomem. Both backends pick it up — they share thertl_stimulitarget, which this PR also factors out of thertlbranch. Output is byte-identical to the old pipeline. This is not specifically related to Verilator, but I added it here because the old Python pipeline was very slow and this costs basically nothing.make MAGIArejectstiles=1/mesh_dv=0(the flow is mesh-only) andtarget_platform=magia_v1(selects CV32E40X, whose hierarchical core traces would need per-tile filenames resolved at run time), with an explanatory error rather than a failure later in the build.No CI changes in this PR.