Draft: Major updates - #435

Draft

FrancescoConti wants to merge 62 commits into

Commits on May 25, 2024

Add zyboz7 FPGA port

micprog
authored and
FrancescoConti
committed
7c92ea6
Make vsim compilation properly stop at errors + update runtime for CV32E40X
FrancescoConti
committed
24a8353
Add extremely preliminary FIR XIFU
FrancescoConti
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0ab6d4e
Fix missing deps in manually hacked Bender.lock
FrancescoConti
committed
5866b31
Update Bender.lock, Bender.yml, Xilinx constraints, memory size.
FrancescoConti
committed
6af8d64
Fix Bender.lock
FrancescoConti
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4ae9651
Use deps in GitHub only
FrancescoConti
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313a2d9
Fix Bender.lock manually
FrancescoConti
committed
5f9c992
Update Bender + update runtime + add minimal test for XIFU
FrancescoConti
committed
cb455fe
Add symlinks to FIR HWPE & XIFU + CV32E40X + pulp_soc to deps folder
FrancescoConti
committed
8abe60a
Update Bender.yml/lock with beautified pulp_soc
FrancescoConti
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ba79d88
In this branch, use CORE_TYPE=3 (CV32E40X)
FrancescoConti
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14a62ae
Update pulp_soc version
FrancescoConti
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e69a949
Fix pulp_soc
FrancescoConti
committed
4d6b495
Fix defaults to CV32E40X in the right places
FrancescoConti
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2dd3062
Adapt to LLVM-based setup + tracing in CV32E40X
FrancescoConti
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5e85bd3
Log all signals automatically in QuestaSim
FrancescoConti
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d97c5da
Update versions + tests, working XIFU
FrancescoConti
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4df67b1
remove ssh from Bender.lock and .yml
FrancescoConti
committed
ea4e376
Realign Bender + sw submodules after rebase (to check)
FrancescoConti
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41d9535
Update pulp_soc
FrancescoConti
committed
c800588

Commits on May 31, 2024

Fix potential (?) syntax error on some machines
FrancescoConti
committed
c0edc2d
Update fir-xifu (and pulp_soc)
FrancescoConti
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c6a54d4

Commits on Jul 26, 2024

Add synthesis dependencies
FrancescoConti
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39b48ff
Improvements to ease non-free synthesis flow
FrancescoConti
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0fa54bc
point CI to LLVM (currently, EFCL Summer School version) in this branch
FrancescoConti
committed
be268ec

Commits on Oct 25, 2024

Add tiny entry in README + small fix to make checkout-synthesis rule
FrancescoConti
committed
2e2b98a

Commits on Jan 16, 2025

Initial support for Verilator (not really tested)
FrancescoConti
committed
fe55493

Commits on Jan 21, 2025

Cleanup of tb_pulp.sv
FrancescoConti
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efa307e
Update Verilated Bender.yml, minor tb_pulp fix, Verilator tracing with
FrancescoConti
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939ecd2
Minor fixes
FrancescoConti
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30ef384
Further minor fix
FrancescoConti
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948c689
Update pulp-runtime for Verilator support with platform=verilator
FrancescoConti
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f710a0b
Support bootmode=fast_debug in Verilator
FrancescoConti
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bbd234e

Commits on Jan 23, 2025

Commits on Jan 31, 2025

Commits on Feb 1, 2025

Add draft of Verilator CI
FrancescoConti
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d10b3f4
Change container stuff for Verilator CI
FrancescoConti
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4e5f72a
Add actual sanity test for Verilator (minimal)
FrancescoConti
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5a93977

Commits on May 13, 2025

Small changes
FrancescoConti
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9d7856c
Add Verilator-based CI
FrancescoConti
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6ebffdb
fix dependency setup -> tests
FrancescoConti
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d602672
verilator-ci: add forgotten source script to verilator CI tests
FrancescoConti
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db062db
verilator-ci: remove hello world test
FrancescoConti
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c2aef4e
verilator-ci: source correct runtime
FrancescoConti
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fa822bf
verilator-ci: fix typo
FrancescoConti
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5225349
verilator-ci: update pulp-runtime with tiny fix to ITB generation
FrancescoConti
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cdee25f
fix to itb generation to enable CI (again)
FrancescoConti
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cbecb14

Commits on May 14, 2025

Commits on May 15, 2025