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[HW] Fix hmr_unit.sv syntax #39

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[HW] Fix hmr_unit.sv syntax #39

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33d8bca
[HW] Fix hmr_unit.sv syntax
dcammarata01 Aug 7, 2026
2e84fac
[SVH] Fixing BITWISE macro to avoid VCS errors
dcammarata01 Aug 7, 2026
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3 changes: 1 addition & 2 deletions include/redundancy_cells/voters.svh
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Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,7 @@

// Helper Macro to use enums bitwise
// This has no effect on array of bits, but does not work on plain logic!
`define BITWISE(a) \
a[$bits(a)-1:0]
`define BITWISE(a) {a}[$bits(a)-1:0]


// Cell Instantiation Macros
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11 changes: 6 additions & 5 deletions rtl/HMR/hmr_unit.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -878,11 +878,12 @@
if (i >= NumTMRCores) begin
core_setback_o [i] = '0;
end
end
if (i < NumTMRCores && (TMRFixed || core_in_tmr[i])) begin : gen_tmr_mode
assign core_inputs_o[i] = sys_inputs_i[SysCoreIndex];
end else begin : gen_independent_mode
assign core_inputs_o[i] = sys_inputs_i[i];

Check warning on line 881 in rtl/HMR/hmr_unit.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] rtl/HMR/hmr_unit.sv#L881 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"./rtl/HMR/hmr_unit.sv" range:{start:{line:881 column:1}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:881 column:1} end:{line:882}} text:"\n"}
if (i < NumTMRCores && (TMRFixed || core_in_tmr[i])) begin : gen_tmr_mode
core_inputs_o[i] = sys_inputs_i[SysCoreIndex];
end else begin : gen_independent_mode
core_inputs_o[i] = sys_inputs_i[i];
end
end
end

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