Support for non-secure (NS) binaries

src/cmake/rp2_common.cmake

@@ -110,6 +110,7 @@ if (NOT PICO_BARE_METAL)
 
     if (PICO_COMBINED_DOCS OR NOT PICO_RP2040)
         pico_add_subdirectory(rp2_common/pico_sha256)
+        pico_add_subdirectory(rp2_common/pico_secure)
     endif()
 
     pico_add_subdirectory(rp2_common/pico_stdio_semihosting)

src/rp2_common/boot_bootrom_headers/include/boot/bootrom_constants.h

@@ -341,4 +341,42 @@ typedef struct cflash_flags {
 #define CFLASH_OP_VALUE_READ            _u(2)
 #define CFLASH_OP_MAX                   _u(2)
 
+#ifndef __riscv
+/*! \brief Return a well known secure call code based on four ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are used to call well known secure functions from non-secure code.
+ *
+ * NOTE: ASCII characters are all < 0x80, so will always start with `0b0xxx`, as required by the rom_secure_call() documentation.
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \param c3 the third character
+ * \param c4 the fourth character
+ * \return the 'code' to use in rom_secure_call(), and handled by rom_default_callback()
+ */
+#define SECURE_CALL_WELL_KNOWN_CODE(c1, c2, c3, c4) ((c1) | ((c2) << 8) | ((c3) << 16) | ((c4) << 24))
+
+#define SECURE_CALL_stdio_out_chars                             SECURE_CALL_WELL_KNOWN_CODE('I', 'O', 'O', 'C')
+
+#define SECURE_CALL_get_rand_64                                 SECURE_CALL_WELL_KNOWN_CODE('R', 'D', '6', '4')
+
+#define SECURE_CALL_dma_allocate_unused_channel_for_nonsecure   SECURE_CALL_WELL_KNOWN_CODE('D', 'A', 'C', 'H')
+
+#define SECURE_CALL_user_irq_claim_unused_for_nonsecure         SECURE_CALL_WELL_KNOWN_CODE('U', 'I', 'R', 'Q')
+
+#define SECURE_CALL_clock_get_hz                                SECURE_CALL_WELL_KNOWN_CODE('C', 'K', 'G', 'H')
+
+#define SECURE_CALL_pio_claim_unused_pio_for_nonsecure          SECURE_CALL_WELL_KNOWN_CODE('P', 'I', 'O', 'C')
+
+#define SECURE_CALL_pads_bank0_set_bits                         SECURE_CALL_WELL_KNOWN_CODE('P', '0', 'S', 'B')
+#define SECURE_CALL_pads_bank0_clear_bits                       SECURE_CALL_WELL_KNOWN_CODE('P', '0', 'C', 'B')
+#define SECURE_CALL_pads_bank0_write_masked                     SECURE_CALL_WELL_KNOWN_CODE('P', '0', 'W', 'M')
+#define SECURE_CALL_pads_bank0_read                             SECURE_CALL_WELL_KNOWN_CODE('P', '0', 'R', 'D')
+
+#define SECURE_CALL_reset_block_mask                        SECURE_CALL_WELL_KNOWN_CODE('R', 'T', 'R', 'M')
+#define SECURE_CALL_unreset_block_mask                      SECURE_CALL_WELL_KNOWN_CODE('R', 'T', 'U', 'M')
+#define SECURE_CALL_unreset_block_mask_wait_blocking        SECURE_CALL_WELL_KNOWN_CODE('R', 'T', 'U', 'W')
+#endif
+
 #endif

src/rp2_common/hardware_flash/include/hardware/flash.h

@@ -42,9 +42,12 @@
 #define PARAM_ASSERTIONS_ENABLED_HARDWARE_FLASH 0
 #endif
 #endif
-#define FLASH_PAGE_SIZE (1u << 8)
-#define FLASH_SECTOR_SIZE (1u << 12)
-#define FLASH_BLOCK_SIZE (1u << 16)
+#define FLASH_PAGE_SHIFT 8u
+#define FLASH_PAGE_SIZE (1u << FLASH_PAGE_SHIFT)
+#define FLASH_SECTOR_SHIFT 12u
+#define FLASH_SECTOR_SIZE (1u << FLASH_SECTOR_SHIFT)
+#define FLASH_BLOCK_SHIFT 16u
+#define FLASH_BLOCK_SIZE (1u << FLASH_BLOCK_SHIFT)
 
 #ifndef FLASH_UNIQUE_ID_SIZE_BYTES
 #define FLASH_UNIQUE_ID_SIZE_BYTES 8

src/rp2_common/hardware_gpio/CMakeLists.txt

@@ -1,2 +1,6 @@
 pico_simple_hardware_target(gpio)
-pico_mirrored_target_link_libraries(hardware_gpio INTERFACE hardware_irq)
+pico_mirrored_target_link_libraries(hardware_gpio INTERFACE hardware_irq)
+
+if (PICO_RP2350)
+    pico_mirrored_target_link_libraries(hardware_gpio INTERFACE pico_bootrom)
+endif()

src/rp2_common/hardware_gpio/gpio.c

@@ -27,7 +27,7 @@ static raw_irq_mask_type_t raw_irq_mask[NUM_CORES];
 // Get the raw value from the pin, bypassing any muxing or overrides.
 int gpio_get_pad(uint gpio) {
     check_gpio_param(gpio);
-    hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+    pads_bank0_set_bits(gpio, PADS_BANK0_GPIO0_IE_BITS);
     return (io_bank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS)
             >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB;
 }
@@ -39,7 +39,7 @@ void gpio_set_function(uint gpio, gpio_function_t fn) {
     check_gpio_param(gpio);
     invalid_params_if(HARDWARE_GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS);
     // Set input enable on, output disable off
-    hw_write_masked(&pads_bank0_hw->io[gpio],
+    pads_bank0_write_masked(gpio,
                    PADS_BANK0_GPIO0_IE_BITS,
                    PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
     );
@@ -48,7 +48,7 @@ void gpio_set_function(uint gpio, gpio_function_t fn) {
     io_bank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
 #if HAS_PADS_BANK0_ISOLATION
     // Remove pad isolation now that the correct peripheral is in control of the pad
-    hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS);
+    pads_bank0_clear_bits(gpio, PADS_BANK0_GPIO0_ISO_BITS);
 #endif
 }
 /// \end::gpio_set_function[]
@@ -62,8 +62,8 @@ gpio_function_t gpio_get_function(uint gpio) {
 // i.e. weak pull to whatever is current high/low state of GPIO.
 void gpio_set_pulls(uint gpio, bool up, bool down) {
     check_gpio_param(gpio);
-    hw_write_masked(
-            &pads_bank0_hw->io[gpio],
+    pads_bank0_write_masked(
+            gpio,
             (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB),
             PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS
     );
@@ -106,28 +106,28 @@ void gpio_set_oeover(uint gpio, uint value) {
 void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
     check_gpio_param(gpio);
     if (enabled)
-        hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+        pads_bank0_set_bits(gpio, PADS_BANK0_GPIO0_SCHMITT_BITS);
     else
-        hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+        pads_bank0_clear_bits(gpio, PADS_BANK0_GPIO0_SCHMITT_BITS);
 }
 
 
 bool gpio_is_input_hysteresis_enabled(uint gpio) {
     check_gpio_param(gpio);
-    return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
+    return (pads_bank0_read(gpio) & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
 }
 
 void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
     check_gpio_param(gpio);
-    hw_write_masked(&pads_bank0_hw->io[gpio],
+    pads_bank0_write_masked(gpio,
                     (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB,
                     PADS_BANK0_GPIO0_SLEWFAST_BITS
     );
 }
 
 enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
     check_gpio_param(gpio);
-    return (enum gpio_slew_rate)((pads_bank0_hw->io[gpio]
+    return (enum gpio_slew_rate)((pads_bank0_read(gpio)
                                   & PADS_BANK0_GPIO0_SLEWFAST_BITS)
             >> PADS_BANK0_GPIO0_SLEWFAST_LSB);
 }
@@ -137,15 +137,15 @@ enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
 static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, "");
 void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
     check_gpio_param(gpio);
-    hw_write_masked(&pads_bank0_hw->io[gpio],
+    pads_bank0_write_masked(gpio,
                     (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB,
                     PADS_BANK0_GPIO0_DRIVE_BITS
     );
 }
 
 enum gpio_drive_strength gpio_get_drive_strength(uint gpio) {
     check_gpio_param(gpio);
-    return (enum gpio_drive_strength)((pads_bank0_hw->io[gpio]
+    return (enum gpio_drive_strength)((pads_bank0_read(gpio)
                                        & PADS_BANK0_GPIO0_DRIVE_BITS)
             >> PADS_BANK0_GPIO0_DRIVE_LSB);
 }
@@ -186,7 +186,7 @@ static void _gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_b
 void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) {
     // either this call disables the interrupt or callback should already be set.
     // this protects against enabling the interrupt without callback set
-    assert(!enabled || irq_has_handler(IO_IRQ_BANK0));
+    assert(!enabled || irq_has_handler(DEFAULT_IO_IRQ_BANK0));
 
     // Separate mask/force/status per-core, so check which core called, and
     // set the relevant IRQ controls.
@@ -201,32 +201,32 @@ void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled
     if (enabled) gpio_set_irq_callback(callback);
     gpio_set_irq_enabled(gpio, events, enabled);
     if (!enabled) gpio_set_irq_callback(callback);
-    if (enabled) irq_set_enabled(IO_IRQ_BANK0, true);
+    if (enabled) irq_set_enabled(DEFAULT_IO_IRQ_BANK0, true);
 }
 
 void gpio_set_irq_callback(gpio_irq_callback_t callback) {
     uint core = get_core_num();
     if (callbacks[core]) {
         if (!callback) {
-            irq_remove_handler(IO_IRQ_BANK0, gpio_default_irq_handler);
+            irq_remove_handler(DEFAULT_IO_IRQ_BANK0, gpio_default_irq_handler);
         }
         callbacks[core] = callback;
     } else if (callback) {
         callbacks[core] = callback;
-        irq_add_shared_handler(IO_IRQ_BANK0, gpio_default_irq_handler, GPIO_IRQ_CALLBACK_ORDER_PRIORITY);
+        irq_add_shared_handler(DEFAULT_IO_IRQ_BANK0, gpio_default_irq_handler, GPIO_IRQ_CALLBACK_ORDER_PRIORITY);
     }
 }
 
 void gpio_add_raw_irq_handler_with_order_priority_masked(uint32_t gpio_mask, irq_handler_t handler, uint8_t order_priority) {
     hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event
     raw_irq_mask[get_core_num()] |= gpio_mask;
-    irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority);
+    irq_add_shared_handler(DEFAULT_IO_IRQ_BANK0, handler, order_priority);
 }
 
 void gpio_add_raw_irq_handler_with_order_priority_masked64(uint64_t gpio_mask, irq_handler_t handler, uint8_t order_priority) {
     hard_assert(!(raw_irq_mask[get_core_num()] & gpio_mask)); // should not add multiple handlers for the same event
     raw_irq_mask[get_core_num()] |= (raw_irq_mask_type_t) gpio_mask;
-    irq_add_shared_handler(IO_IRQ_BANK0, handler, order_priority);
+    irq_add_shared_handler(DEFAULT_IO_IRQ_BANK0, handler, order_priority);
 }
 
 void gpio_add_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) {
@@ -239,13 +239,13 @@ void gpio_add_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler
 
 void gpio_remove_raw_irq_handler_masked(uint32_t gpio_mask, irq_handler_t handler) {
     assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added
-    irq_remove_handler(IO_IRQ_BANK0, handler);
+    irq_remove_handler(DEFAULT_IO_IRQ_BANK0, handler);
     raw_irq_mask[get_core_num()] &= ~gpio_mask;
 }
 
 void gpio_remove_raw_irq_handler_masked64(uint64_t gpio_mask, irq_handler_t handler) {
     assert(raw_irq_mask[get_core_num()] & gpio_mask); // should not remove handlers that are not added
-    irq_remove_handler(IO_IRQ_BANK0, handler);
+    irq_remove_handler(DEFAULT_IO_IRQ_BANK0, handler);
     raw_irq_mask[get_core_num()] &= (raw_irq_mask_type_t)~gpio_mask;
 }
 
@@ -267,9 +267,9 @@ void gpio_debug_pins_init(void) {
 void gpio_set_input_enabled(uint gpio, bool enabled) {
     check_gpio_param(gpio);
     if (enabled)
-        hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+        pads_bank0_set_bits(gpio, PADS_BANK0_GPIO0_IE_BITS);
     else
-        hw_clear_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+        pads_bank0_clear_bits(gpio, PADS_BANK0_GPIO0_IE_BITS);
 }
 
 void gpio_init(uint gpio) {

src/rp2_common/hardware_gpio/include/hardware/gpio.h

@@ -18,10 +18,27 @@
 #define PICO_USE_GPIO_COPROCESSOR 1
 #endif
 
+
+#if PICO_NONSECURE
+#define DEFAULT_IO_IRQ_BANK0 IO_IRQ_BANK0_NS
+#else
+#define DEFAULT_IO_IRQ_BANK0 IO_IRQ_BANK0
+#endif
+
+
 #if PICO_USE_GPIO_COPROCESSOR
 #include "hardware/gpio_coproc.h"
 #endif
 
+#if PICO_SECURE || PICO_NONSECURE
+#include "pico/bootrom.h" // uses helper functions due to Errata RP2350-E3
+#else
+#define pads_bank0_set_bits(gpio, bits) hw_set_bits(&pads_bank0_hw->io[gpio], bits)
+#define pads_bank0_clear_bits(gpio, bits) hw_clear_bits(&pads_bank0_hw->io[gpio], bits)
+#define pads_bank0_write_masked(gpio, bits, mask) hw_write_masked(&pads_bank0_hw->io[gpio], bits, mask)
+#define pads_bank0_read(gpio) pads_bank0_hw->io[gpio]
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -312,7 +329,7 @@ static inline void gpio_pull_up(uint gpio) {
  * \return true if the GPIO is pulled up
  */
 static inline bool gpio_is_pulled_up(uint gpio) {
-    return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0;
+    return (pads_bank0_read(gpio) & PADS_BANK0_GPIO0_PUE_BITS) != 0;
 }
 
 /*! \brief Set specified GPIO to be pulled down.
@@ -331,7 +348,7 @@ static inline void gpio_pull_down(uint gpio) {
  * \return true if the GPIO is pulled down
  */
 static inline bool gpio_is_pulled_down(uint gpio) {
-    return (pads_bank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0;
+    return (pads_bank0_read(gpio) & PADS_BANK0_GPIO0_PDE_BITS) != 0;
 }
 
 /*! \brief Disable pulls on specified GPIO

src/rp2_common/hardware_resets/include/hardware/resets.h

@@ -106,6 +106,9 @@
 extern "C" {
 #endif
 
+#if PICO_NONSECURE
+#include "pico/bootrom.h"
+#else
 static __force_inline  void reset_block_reg_mask(io_rw_32 *reset, uint32_t mask) {
     hw_set_bits(reset, mask);
 }
@@ -119,6 +122,7 @@ static __force_inline void unreset_block_reg_mask_wait_blocking(io_rw_32 *reset,
     while (~*reset_done & mask)
         tight_loop_contents();
 }
+#endif
 
 /// \tag::reset_funcs[]
 

src/rp2_common/pico_bootrom/CMakeLists.txt

@@ -9,8 +9,8 @@ target_sources(pico_bootrom INTERFACE
         )
 
 target_link_libraries(pico_bootrom_headers INTERFACE boot_picoboot_headers boot_bootrom_headers)
-pico_mirrored_target_link_libraries(pico_bootrom INTERFACE pico_base hardware_boot_lock pico_flash)
+pico_mirrored_target_link_libraries(pico_bootrom INTERFACE pico_base hardware_boot_lock pico_flash hardware_flash pico_rand hardware_dma hardware_irq pico_stdio hardware_pio)
 
 # bootrom.c includes boot/picobin.h
 # bootrom_lock.c includes pico/runtime_init.h
-target_link_libraries(pico_bootrom INTERFACE boot_picobin_headers pico_runtime_init_headers)
+target_link_libraries(pico_bootrom INTERFACE boot_picobin_headers pico_runtime_init_headers)