update to sail simulator build instructions and plugin, necessary for newer version of sail

[jeras]

The instructions for building sail did not work properly.
I updated the instructions and the names of the executables created by the newer version of sail.

[Alasdair]

Looks good to me, the version of OCaml listed there is 7 years old at this point so I suspect those instructions haven't worked in quite a while.

We only very recently switched (within the last month or so) to using cmake in the sail-riscv repo, so there may be some teething problems with the switch, please let us know over there if you run into further issues!

[jordancarlin]

It probably makes sense to direct most users to install the sail compiler using the precompiled binary instead of making everyone deal with opam. See the releases page of the Sail repo: https://github.com/rems-project/sail/releases.

[jeras]

I agree with @jordancarlin, regarding using the binary, it should be the recommended option in the RISCOF instructions. I only checked how NEORV32 is handling it and a binary is used there. Installing another package manager on your PC is a lot of storage and maintenance overhead.

The current instructions could probably replace the use of docker images with using a binary. I suspect the docker image is also an antique.

While following instructions I also encountered some other issues:

• typos in generated plugin code,
• if spike is used for reference, the generated plugin is incomplete, the CLI for spike only contains the executable, it is missing all arguments.

[RogueRat]

First of all: Thank you @jeras for your updated documentation, it was very helpful in my recent struggles with the SAIL Quickstart section.

Secondly: This needs to be updated further as, per the 0.8 version Release Notes, SAIL-RISCV now has one single executable rather than separate ones for 32-bit and 64-bit and that requires changes to the /sail_cSim/riscof_sail_cSim.py file.

The new, singular executable is named "sail_riscv_sim" and launches into 64-bit mode by default. The Quickstart setup is
all for a 32-bit implementation though.

Thus, in the "/sail_cSim/riscof_sail_cSim.py" file, make the following changes:

1. On line 31 and 32: Set the SAIL SIMULATOR executable variable "self.sail_exe" to:
   sail_riscv_sim for both instances (32-bit RISCV and 64-bit RISCV)

2. On line 104: Modify the "execute" variable if necessary; SAIL launches into 64-bit mode by default.
   The bit-setting and other core-modifications (extensions) are listed in a config file, which is
   usually custom. But there is a shortcut for launching into 32-bit mode. Use the option "--rv32".
   The "execute" variable consists of the "self.sail_exe"-string + a string of options and input.
   Simply prepend this option/input string with " --rv32". Make sure to include the space if you put
   it in front, as it will otherwise be merged into "sail_riscv_sim--rv32..." which is not a valid executable.

Obviously, the line-numbers might get changed etc. but this should give a good hint at what needs to be done.
Appending pictures to illustrate more clearly:

I hope this is helpful to somebody.

[jordancarlin]

Just a heads up to anyone trying to start using RISCOF: RISCOF (which was used with version 3 of the riscv-arch-test suite) is being deprecated as part of the update to riscv-arch-test version 4 (ACT4). All necessary tooling and instructions for ACT4 are directly in the https://github.com/riscv/riscv-arch-test repository now instead of requiring tools from several different repos.

[RogueRat]

@jordancarlin Thank you. That is useful information. If you don't mind: Where is the best source for finding what is the current standard with regards to RISC-V testing / certification and the like? I am working on a research project in which we use various RISC-V cores, both soft and hardened, but none of us are RISC-V experts.

[jordancarlin]

@jordancarlin Thank you. That is useful information. If you don't mind: Where is the best source for finding what is the current standard with regards to RISC-V testing / certification and the like? I am working on a research project in which we use various RISC-V cores, both soft and hardened, but none of us are RISC-V experts.

It is a rapidly evolving space at the moment, so unfortunately there is no great single spot to look at. The riscv-arch-test repo is where most of the development is currently being done, but several other test suites will be pulled together to create the final certification test suite that is in process right now.

[RogueRat]

@jordancarlin Thanks for getting back to me on that though. I'll be looking into the riscv-arch-test repo.
Is there maybe a way you can influence the RISCOF documentation to mention that it is being deprecated and point out what you've done here? I just spent over a week trying to get RISCOF to work and it would be nice to know that I'm the last.

[jordancarlin]

Is there maybe a way you can influence the RISCOF documentation to mention that it is being deprecated and point out what you've done here? I just spent over a week trying to get RISCOF to work and it would be nice to know that I'm the last.

Yes. We are working on getting deprecation notices added and archiving these repos. Should be done in the next few weeks.

[RogueRat]

@jordancarlin Glad to hear it. Thanks again for replying to me =)