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1. CORDIC-Based-16-Stage-Pipelined-Processor CORDIC-Based-16-Stage-Pipelined-Processor Public

   This project implements a 16-stage pipelined CORDIC processor for computing trigonometric functions using shift-add operations. The design is developed in Verilog HDL and targets high-speed, hardwa…

2. RSIC-V_Single_Cycle_Core_Processor RSIC-V_Single_Cycle_Core_Processor Public

   Designed and implemented a 32-bit RISC-V Single Cycle Core Processor in Verilog HDL, integrating major datapath components including PC, Instruction Memory, Register File, ALU, Control Unit, Data M…

3. TCAD-SDE-Sentaurus-AlGaN-GaN-HEMT-Device-Design- TCAD-SDE-Sentaurus-AlGaN-GaN-HEMT-Device-Design- Public

   Designed and developed an AlGaN/GaN HEMT device structure in Sentaurus TCAD (SDE), including geometry creation, material definition, contact engineering, doping profile implementation, and mesh gen…

4. IFFT_using_IP_Core IFFT_using_IP_Core Public

   8-Point IFFT Implementation using Xilinx FFT IP Core in Vivado. This project demonstrates high-speed digital signal processing on FPGA, featuring fixed-point arithmetic, AXI4-Stream protocol integr…

5. BIT_ERROR_RATE_Analyser BIT_ERROR_RATE_Analyser Public

   Built a MATLAB OOP-based BER analyzer supporting BPSK/QPSK/M-QAM over AWGN, Rayleigh, and Rician channels, with BER-SNR visualization, theoretical vs simulated comparison, and target BER SNR estima…

6. SPI_PROTOCOL SPI_PROTOCOL Public

   This project implements the SPI (Serial Peripheral Interface) protocol using Verilog HDL. The design models a simple SPI transmitter using a finite state machine (FSM) to serially shift a 16-bit da…