Reconfigurable CGRA-Based ASIC-Compatible Architecture#176
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127004035-ctrl wants to merge 53 commits into
Open
Reconfigurable CGRA-Based ASIC-Compatible Architecture#176127004035-ctrl wants to merge 53 commits into
127004035-ctrl wants to merge 53 commits into
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…patible_Architecture/verification_top_fabric.v
…patible_Architecture/rtl directory
…patible_Architecture/pic
…patible_Architecture/synth.ys
…patible_Architecture/image_2026-03-31_191402354.png
…patible_Architecture/physical_design/reports/2_floorplan_final.rpt
…patible_Architecture/physical_design/reports/3_detailed_place.rpt
…patible_Architecture/physical_design/reports/3_global_place.rpt
…patible_Architecture/physical_design/reports/synth_stat.txt
…patible_Architecture/physical_design/results/ds
…patible_Architecture/physical_design/results/2_floorplan.odb
…patible_Architecture/pic
…patible_Architecture/validation.png
atuchiya
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Apr 29, 2026
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The files are under ISSCC26. Please move files under VLSI26
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As requested, we have moved our submission from ISSCC26 to VLSI26 folder. |
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This project designs a CGRA-inspired verification chip for ASICs using a 6×6 heterogeneous tile array. Each tile performs arithmetic operations (like addition, multiplication, etc.) and verifies results in real time using digit-sum (casting-out-nines) residue arithmetic, eliminating the need for stored reference models. The design is implemented using the SKY130HD library with OpenROAD, achieving efficient area usage and zero DRC violations.