16‑bit_vedic_multiplier_MAC_with_security_key_VLSI26#182
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…curity_key to VLSI26/submitted_notebooks/16‑bit_vedic_multiplier_MAC_with_security_key/k
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Name:Kamalesh E
Affiliation:Undergraduate student at Government College of
Technology-Coimbatore.
Director of Membership at GCT IEEE Student Branch.
E-mail:kama.71772314122@gct.ac.in
Membership status: IEEE Student Member
Membership Number:101660592
Best Regards,
Kamalesh E
GCT IEEE Student Branch
kama.71772314122@gct.ac.in
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This project presents the design and implementation of a 16-bit Vedic Multiplier-based Multiply-Accumulate (MAC) unit integrated with a hardware security key mechanism, targeting high-performance and secure VLSI applications.
The multiplier is designed using the Vedic Mathematics (Urdhva Tiryagbhyam) algorithm, which enables parallel partial product generation, resulting in reduced propagation delay and improved computational speed compared to conventional multipliers. This makes it highly suitable for DSP, AI accelerators, and real-time signal processing systems.