Submission - CABAgent: A Comprehensive Layout-Aware Analog Benchmark Generation Framework Driven by Self-Evolving LLM Agents for Analog Circuit Design Automation

.gitignore

@@ -2,6 +2,7 @@
 mm
 mm/*
 *.deb
+.env
 
 .vscode
 VLSI24/submitted_notebooks/Open3DFlow/tsv.spice

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "Notebooks/DAG_Processing_Unit/src/DPU_DAG_Processing_Unit"]
 	path = Notebooks/DAG_Processing_Unit/src/DPU_DAG_Processing_Unit
 	url = https://github.com/nimish15shah/DPU_DAG_Processing_Unit
+[submodule "VLSI26/submitted_notebooks/CABAgent/Layout-ALIGN"]
+	path = VLSI26/submitted_notebooks/CABAgent/Layout-ALIGN
+	url = https://github.com/HUJH511/ALIGN-public.git

VLSI26/submitted_notebooks/CABAgent/.gitignore

@@ -0,0 +1,33 @@
+# ---------- User-specified files to ignore ---------- 
+# Edit the following if necessary
+.conda/*
+.vscode/*
+logs/*
+!logs/README.md
+
+designs/*/*/inputs/constraints.json
+designs/*/*/inputs/testbench.spice
+designs/*/*/runs
+designs/*/*/results
+designs/*/*/xschem
+
+src/analogagent/playbook.json
+src/analogagent/problem_set.tsv
+src/analogagent/prompt_template.md
+src/analogagent/execution_error.md
+src/analogagent/retrieval_prompt.md
+src/analogagent/simulation_error.md
+src/cabgen/extract_mag.tcl
+
+.env
+.gitmodules
+*.pyc
+*.pt
+*.pth
+*.tar.gz
+
+*.ext
+*.sim
+*.nodes
+
+# ---------- End of user-specified list of files to ignore ---------- 

VLSI26/submitted_notebooks/CABAgent/Figures/README.md

@@ -0,0 +1 @@
+# Place for figures

VLSI26/submitted_notebooks/CABAgent/LICENSE.BSD-3-Clause

@@ -0,0 +1,29 @@
+BSD 3-Clause License
+
+Copyright (c) 2018, Regents of the University of California
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+* Neither the name of the copyright holder nor the names of its
+  contributors may be used to endorse or promote products derived from
+  this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

VLSI26/submitted_notebooks/CABAgent/README.md

@@ -0,0 +1,123 @@
+#   CABAgent: A <ins>C</ins>omprehensive Layout-Aware <ins>A</ins>nalog <ins>B</ins>enchmark Generation Framework Driven by Self-Evolving LLM <ins>Agent</ins>s for Analog Circuit Design Automation
+
+The lack of comprehensive, layout-verified benchmarks remains a major bottleneck for AI-powered analog circuit design automation. Existing studies often focus on schematic-level circuit generation or optimization under simplified device assumptions, without foundry PDK integration, physical verification, or post-layout evaluation, thereby limiting reproducibility and practical relevance. This paper presents CABAgent, a comprehensive layout-aware analog benchmark generation framework driven by self-evolving LLM agents. Starting from natural-language circuit descriptions, interface constraints, and PDK information, CABAgent first generates validated SKY130-compatible SPICE netlists through a training-free multi-agent loop that couples circuit generation, static netlist checking, Ngspice-based validation, reflection, and knowledge curation. It then expands each validated seed into standardized benchmark packages by automatically exploring device sizing, bias conditions, and layout constraints, followed by pre-layout simulation, automatic layout generation, DRC/LVS verification, parasitic extraction, and post-layout evaluation. Using Gemini, the front end achieves 98.3% Pass@1 and 100% Pass@5 on analog circuit generation tasks. In its current implementation, CABAgent generates 20 circuit topologies and 1,000 benchmark packages within 10 hours. By producing reproducible multi-view artifacts that pair circuit intent, physical implementation, verification evidence, and pre-/post-layout performance labels, CABAgent provides a practical foundation for reproducible evaluation and future learning-based analog design research.
+
+
+##  Table of Content
+1. [Structure](#structure)
+2. [Getting Started](#getting-started)
+3. [License](#license)
+4. [Acknowledgement](#acknowledgement)
+
+
+##  Structure
+While it is possible to have a stand-alone notebook, we have decided to split up the code into modules to improve readability and documentation. The following outline the directory structure.
+```
+./CABAgent/
+|
+├───.conda
+├───.vscode
+├───designs
+│   ├───COMP
+│   |   └───SKY130
+|   │       ├───inputs
+|   │       ├───runs
+|   │       └───results
+|   │           ├───Pkg0
+|   │           ├───Pkg1
+|   │           ├───...
+|   │           └───benchmark.json
+|   └───...
+├───Layout-ALIGN (submodule)
+├───logs
+├───src
+│   ├───analogagent
+│   |   ├───__init__.py
+|   |   ├───agents.py
+|   |   ├───curator.py
+|   |   ├───main_run.py
+|   |   ├───playbook.py
+|   |   └───postprocess.py
+│   ├───cabgen
+│   |   ├───__init__.py
+│   |   ├───bench_gen.py
+│   |   ├───dconfig.py
+│   |   ├───eda_tools.py
+│   |   ├───log_manager.py
+│   |   ├───netlist.py
+│   |   ├───spec_manager.py
+│   |   ├───visualizing.py
+|   |   └───workspace.py
+│   ├───dconfigs
+│   |   ├───COMP.yaml
+|   |   └───...
+│   └───design_pipeline.py
+├───.env
+├───.gitignore
+├───.gitmodules
+├───LICENSE
+├───README.md
+└───CABAgent.ipynb
+```
+
+
+##  Getting Started
+
+### Environment Setup
+```
+./home/
+|
+├───EDA_Tools
+│   ├───magic
+│   ├───netgen
+│   └───open_pdks
+└───CABAgent
+```
+
+Suggest to setup following environment under `EDA_Tools`
+```
+%% install dependent packages
+$ cd /home/EDA_Tools
+$ sudo pip3 install flake8 setuptools-scm
+$ sudo apt update
+$ sudo apt install build-essential tcl-dev tk-dev libx11-dev libcairo2-dev
+$ sudo apt install flex bison 
+
+%% install magic
+$ git clone https://github.com/RTimothyEdwards/magic.git
+$ cd magic
+$ ./configure
+$ make
+$ sudo make install
+
+%% install netgen
+$ cd /home/EDA_Tools
+$ git clone git://opencircuitdesign.com/netgen
+$ cd netgen
+$ ./configure
+$ make
+$ sudo make install
+
+%% install open pdk
+cd /home/EDA_Tools
+git clone https://github.com/RTimothyEdwards/open_pdks
+cd open_pdks
+./configure --enable-sky130-pdk --enable-sram-sky130
+make
+sudo make install
+make veryclean
+```
+
+Ngspice and Klayout will be installed under `/usr/bin/` by default
+```
+sudo apt update
+sudo apt install ngspice
+sudo apt install klayout
+```
+
+
+##  License
+This project is licensed under BSD 3 Clause. 
+
+##  Acknowledgement
+This project is supported by RIE2025 Manufacturing, Trade and Connectivity (MTC) Programmatic Fund, High Linearity Silicon Germanium Photonic Modulator for 6G Analog Radio over Fiber Project, under Grant M24M8b0004

VLSI26/submitted_notebooks/CABAgent/designs/COMP/SKY130/inputs/ckt_netlist.spice

@@ -0,0 +1,30 @@
+XM4 net3 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 CLK VDD VDD sky130_fd_pr__pfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM1 net3 VIN net2 VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net1 VIP net2 VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net2 CLK VSS VSS sky130_fd_pr__nfet_01v8 L=LT W=WT nf=NFT ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 OUTN net3 VSS VSS sky130_fd_pr__nfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 OUTN OUTP VSS VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net4 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=L6 W=W6 nf=NF6 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net4 net3 VDD VDD sky130_fd_pr__pfet_01v8 L=L7 W=W7 nf=NF7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 OUTP net1 VSS VSS sky130_fd_pr__nfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 OUTP OUTN VSS VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM13 net5 net1 VSS VSS sky130_fd_pr__nfet_01v8 L=L6 W=W6 nf=NF6 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM15 net5 net1 VDD VDD sky130_fd_pr__pfet_01v8 L=L7 W=W7 nf=NF7 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM9 OUTN OUTP net4 VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM14 OUTP OUTN net5 VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29'
++ pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1

VLSI26/submitted_notebooks/CABAgent/designs/COMP/SKY130/inputs/ckt_param.spice

@@ -0,0 +1 @@
+.param VDD=1.8 VIN=0.9 Ton=5n Tperiod=10n NFT=10 WT=4.2 LT=0.15 NF1=10 W1=4.2 L1=0.15 NF2=10 W2=4.2 L2=0.15 NF3=4 W3=1.68 L3=0.15 NF4=6 W4=2.52 L4=0.15 NF5=12 W5=5.04 L5=0.15 NF6=4 W6=1.68 L6=0.15 NF7=10 W7=4.2 L7=0.15

VLSI26/submitted_notebooks/CABAgent/designs/OTA_5T/SKY130/inputs/ckt_netlist.spice

@@ -0,0 +1,12 @@
+XM1 net_pmos_mirror_gate VIP net_tail_source VSS sky130_fd_pr__nfet_01v8 L=L_NMOS_DIFF W=W_NMOS_DIFF nf=NF_NMOS_DIFF ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 VOUT VIN net_tail_source VSS sky130_fd_pr__nfet_01v8 L=L_NMOS_DIFF W=W_NMOS_DIFF nf=NF_NMOS_DIFF ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net_tail_source IB VSS VSS sky130_fd_pr__nfet_01v8 L=L_NMOS_TAIL W=W_NMOS_TAIL nf=NF_NMOS_TAIL ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net_pmos_mirror_gate net_pmos_mirror_gate VDD VDD sky130_fd_pr__pfet_01v8 L=L_PMOS_LOAD W=W_PMOS_LOAD nf=NF_PMOS_LOAD ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 VOUT net_pmos_mirror_gate VDD VDD sky130_fd_pr__pfet_01v8 L=L_PMOS_LOAD W=W_PMOS_LOAD nf=NF_PMOS_LOAD ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 IB IB VSS VSS sky130_fd_pr__nfet_01v8 L=L_NMOS_BIAS W=W_NMOS_BIAS nf=NF_NMOS_BIAS ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1

VLSI26/submitted_notebooks/CABAgent/designs/OTA_5T/SKY130/inputs/ckt_param.spice

@@ -0,0 +1 @@
+.param VDD=1.8 VCM=0.9 IB=50u vi=0.05 fi=100000 L_NMOS_DIFF=0.15 W_NMOS_DIFF=4.2 NF_NMOS_DIFF=4 L_NMOS_TAIL=0.15 W_NMOS_TAIL=8.4 NF_NMOS_TAIL=8 L_PMOS_LOAD=0.15 W_PMOS_LOAD=4.2 NF_PMOS_LOAD=4 L_NMOS_BIAS=0.15 W_NMOS_BIAS=8.4 NF_NMOS_BIAS=8

VLSI26/submitted_notebooks/CABAgent/designs/OTA_FC/SKY130/inputs/ckt_netlist.spice

@@ -0,0 +1,24 @@
+XM1 IB IB VSS VSS sky130_fd_pr__nfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net_tail IB VSS VSS sky130_fd_pr__nfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net1 VIP net_tail VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 net2 VIN net_tail VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net1 VBP VDD VDD sky130_fd_pr__pfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 net2 VBP VDD VDD sky130_fd_pr__pfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 net3 VCP net1 VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 VOUT VCP net2 VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net3 VCN net4 VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net4 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=L6 W=W6 nf=NF6 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM11 VOUT VCN net5 VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM12 net5 net3 VSS VSS sky130_fd_pr__nfet_01v8 L=L6 W=W6 nf=NF6 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1

VLSI26/submitted_notebooks/CABAgent/designs/OTA_FC/SKY130/inputs/ckt_param.spice

@@ -0,0 +1 @@
+.param VDD=1.8 VCM=0.9 IB=50u vi=0.05 fi=100000 L1=0.5 W1=4.2 NF1=2 L2=0.5 W2=4.2 NF2=2 L3=0.5 W3=8.4 NF3=4 L4=0.5 W4=4.2 NF4=2 L5=0.5 W5=4.2 NF5=2 L6=0.5 W6=4.2 NF6=2

VLSI26/submitted_notebooks/CABAgent/designs/OTA_TC/SKY130/inputs/ckt_netlist.spice

@@ -0,0 +1,20 @@
+XM1 net2 VIN net1 VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM2 net3 VIP net1 VSS sky130_fd_pr__nfet_01v8 L=L1 W=W1 nf=NF1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM3 net4 VCN net2 VSS sky130_fd_pr__nfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM4 VOUT VCN net3 VSS sky130_fd_pr__nfet_01v8 L=L2 W=W2 nf=NF2 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM5 net4 VCP net6 VDD sky130_fd_pr__pfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM6 VOUT VCP net7 VDD sky130_fd_pr__pfet_01v8 L=L3 W=W3 nf=NF3 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM7 IB IB VSS VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM8 net1 IB VSS VSS sky130_fd_pr__nfet_01v8 L=L4 W=W4 nf=NF4 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM9 net6 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
+XM10 net7 net4 VDD VDD sky130_fd_pr__pfet_01v8 L=L5 W=W5 nf=NF5 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)'
++ ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1