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[ISSCC26] MAC-Based Systolic Array Accelerator for ML Inference - Suliat Saka#187

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[ISSCC26] MAC-Based Systolic Array Accelerator for ML Inference - Suliat Saka#187
Needahh wants to merge 6 commits into
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@Needahh

@Needahh Needahh commented Apr 15, 2026

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Submitting a parameterized MAC-based systolic array accelerator for ML inference.

  • Author: Suliat Saka, University of Lagos
  • Weight-stationary dataflow (same architecture as Google TPU)
  • 4×4 systolic array, 16 MAC units, 8-bit fixed-point
  • Verified using Icarus Verilog against numpy golden reference
  • Synthesized on Sky130A using OpenLane v1.0.2
  • Timing closure at 50MHz, zero DRC/LVS violations
  • License: Apache 2.0

@atuchiya atuchiya left a comment

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The files are created under ISSCC26.
Please move files into VLSI26.

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