Repro: VSS trace runs through the SWD_NRST net label (STM32C071) - #778
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Repro: VSS trace runs through the SWD_NRST net label (STM32C071)#778seveibar wants to merge 1 commit into
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STM32C071 MCU with a 100n decoupling capacitor to its left. The elbow for C_MCU.2 -> U_MCU.5 (VSS) places its vertical segment at the horizontal midpoint between the capacitor and the chip (x = -1.7), running from y = -0.56 up to y = 0.1. That segment passes straight through the SWD_NRST net label rect (x -2.001..-0.801, y -0.2..0.0) anchored on U_MCU.6 / PF2, and crosses the PA0 pin row on its way. The test asserts the trace clears both the label and the PA0 pin lead, so it fails until the routing accounts for anchored net labels. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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What
Adds a failing reproduction for a schematic where the VSS trace is routed straight through an anchored net label.
The schematic: an STM32C071FBP6 (20-pin, 0.2 pitch) with a 100n decoupling capacitor to its left.
C_MCU.1→ VDD (pin 4) andC_MCU.2→ VSS (pin 5) are direct connections;SWD_NRSTis a net label anchored on PF2 (pin 6) facingx-.The bug
The elbow for
C_MCU.2-U_MCU.5puts its riser at the horizontal midpoint between the capacitor and the chip:The vertical segment at
x = -1.7runs fromy = -0.56up toy = 0.10, cutting straight through the SWD_NRST label rect and across the PA0/PF2 pin rows.NetLabelPlacementSolveranchors SWD_NRST at PF2 without accounting for the VSS trace, and nothing downstream separates them.The snapshot SVG shows the trace crossing the label band.
Status
The test fails on this branch — that is the reproduction. CI will be red until the routing is fixed. Opening as a draft for that reason.
The test asserts two things:
U_MCU.7) pin lead — currently passesThe second assertion is there because the originally reported render had the riser closer to the chip, where it crossed the PA0 lead itself. Keeping both means a fix that just shifts the riser toward the chip doesn't trade one symptom for the other.
Note on the input problem
The input was reconstructed by measuring the reported schematic render rather than exported from core via
DEBUG=Group_doInitialSchematicTraceRender. Pin coordinates, the capacitor position, and net label widths are estimates that match the rendered layout; the capacitor uses this repo's standard 0.53 × 1.1 symbol. If the original board's exported JSON turns up, swapping it in would make the repro exact.🤖 Generated with Claude Code