UCIe IP

An open-source implementation of the UCIe 3.0 specification.

You can request a copy of the UCIe specification here.

Setup

Make sure Scala is installed, then check out the submodules:

git submodule update --init --recursive

Generating RTL

The top level is UcieTL: the analog PHY, the UCIe digital stack (protocol layer, die-to-die adapter, and logical PHY), and the register block reachable over TileLink. The emitted module name carries moduleId when it is nonzero, so the default parameters emit UcieTL, and a second instance parameterized with moduleId = 1 emits UcieTL_1 instead of deduping into the first. To generate it, run the following from the scala/ folder:

./mill test.testOnly edu.berkeley.cs.uciedigital.tilelink.TileLinkSpec -- -z "should generate valid SystemVerilog"

This writes SystemVerilog to scala/build/UcieTL_should_generate_valid_SystemVerilog. UcieTL has diplomatic ports, so it is elaborated inside RTLHarness, which supplies the TileLink master and the clock source those ports need.

Omitting -- -z ... runs the rest of TileLinkSpec, which includes Verilator, VCS, and Xcelium simulations.

Some individual blocks have their own generators under scala/src, each writing to a subdirectory of scala/generatedVerilog. For example:

./mill runMain edu.berkeley.cs.uciedigital.logphy.MainLogicalPhy
./mill runMain edu.berkeley.cs.uciedigital.protocol.MainProtocolLayer

To list every block generator:

./mill show allLocalMainClasses

Tests

To run the RTL tests, make sure Scala is installed.

Then, run the following from the scala/ folder.

./mill test

To run the VAMS tests, make sure the XCELIUM_HOME environment variable is correctly set and xrun is on your PATH.

Then, run the following from the rs/ folder:

cargo t

That runs every bench against every abstraction level of the analog models. To iterate against the cheap one only:

cargo t eye

Organization

Chisel RTL for all digital components can be found in the scala/ directory.

Verilog testbenches and AMS models can be found in the verilog/ folder. The analog PHY is modelled at more than one level of abstraction there -- verilog/models/eye is the least that puts an eye in front of the receiver and so the least that can be trained against, verilog/models/circuit is the front end as it is built -- and verilog/README.md describes the levels, the contract they share, and how a simulation picks one.

Rust code for orchestrating tests can be found in the rs/ folder.

Contributing

If you'd like to contribute, please let us know. You can:

• Open an issue.
• Email rahulkumar@berkeley.edu and rohankumar@berkeley.edu.

Documentation updates, tests, and bugfixes are always welcome. For larger feature additions, please discuss your ideas with us before implementing them.

Contributions can be submitted by opening a pull request against the main branch of this repository.

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you shall be licensed under the BSD 3-Clause license, without any additional terms or conditions.

Before opening a pull request, run the following from the scala/ folder:

./mill mill.scalalib.scalafmt/reformatAll