Skip to content
View Har67's full-sized avatar

Block or report Har67

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Harshi_RISC-V-SoC-Tapeout-Program_VSD Harshi_RISC-V-SoC-Tapeout-Program_VSD Public

  2. Volt-Edge-Labs Volt-Edge-Labs Public

  3. pipeline-register-_OptoML pipeline-register-_OptoML Public

    Single-stage SystemVerilog pipeline register with valid handshake & backpressure support

    SystemVerilog

  4. riscv-architectural-certification-learning riscv-architectural-certification-learning Public

    Exploration and setup of RISC-V Architectural Certification Tests (ACT4)

  5. AMD-Single-Shot AMD-Single-Shot Public

    AI-powered RTL Verification Risk & Coverage Analysis Platform

    Python

  6. VoltEdge-Labs-WW1 VoltEdge-Labs-WW1 Public

    Forked from voltedgelabs1-interns/VoltEdge-Labs-WW1

    Free Source Tool installation guidelines for interns

    Python