AI-assisted pre-verification risk analysis for SystemVerilog RTL designs.
This tool helps design and verification engineers evaluate RTL quality by analyzing:
- Reset presence and integrity
- Assertion and coverage usage
- Potential failure and mismatch risks
- Control signal and timing sensitivity
- Test scenario guidance
- Waveform activity analysis
Built with Streamlit, Python, and rule-based analysis.
- Risk Score — Overall verification readiness
- Risk Contributors — Clear explanation of gaps
- Assertions & Coverage Review
- Failure & Regression Indicators
- Robustness & Assumption Analysis
- Test & VIP Guidance
- Upload VCD waveform
- Toggle density visualization
- Clock/reset sensitivity
- Glitch & DV impact insights
- Clone repo
git clone https://github.com/Har67/AMD-Single-Shot.git cd AMD-Single-Shot