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F4 UART: mask received data to 8 bits, align with F7/H7 - #12109
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With parity enabled the F4 data register holds the parity bit in bit 8, and it was passed through to the rx callback. F7/H7 drivers already mask to 8 bits. Protocol handlers comparing the received value directly, e.g. the SBUS 0x2F start byte, never matched on F4.
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PR Summary by QodoMask parity bit before F4 UART receive callbacks
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RAM / Flash usage vs. base commit
See RAM/flash optimization guide for techniques to reduce usage. |
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Test firmware build ready — commit Download firmware for PR #12109 251 targets built. Find your board's
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Thanks! |
Was preventing 32 Channel support over SBUS. Align to F7 / H7:
https://github.com/iNavFlight/inav/blob/maintenance-10.x/src/main/drivers/serial_uart_stm32f7xx.c#L259
https://github.com/iNavFlight/inav/blob/maintenance-10.x/src/main/drivers/serial_uart_stm32h7xx.c#L305