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F4 UART: mask received data to 8 bits, align with F7/H7 - #12109

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sensei-hacker merged 1 commit into
iNavFlight:maintenance-10.xfrom
jlpoltrack:sbus-f4-highframe-fix
Nov 15, 2026
Merged

sensei-hacker merged 1 commit into
iNavFlight:maintenance-10.xfrom
jlpoltrack:sbus-f4-highframe-fix

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@jlpoltrack

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With parity enabled the F4 data register holds the parity bit in bit 8,
and it was passed through to the rx callback. F7/H7 drivers already mask
to 8 bits. Protocol handlers comparing the received value directly, e.g.
the SBUS 0x2F start byte, never matched on F4.
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🐞 Bugs (0) 📘 Rule violations (0) 📎 Requirement gaps (0)

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PR Summary by Qodo

Mask parity bit before F4 UART receive callbacks

🐞 Bug fix 🕐 Less than 10 minutes

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AI Description

• Mask F4 UART callback data to eight bits so parity cannot alter received bytes.
• Restore SBUS frame detection for 32-channel reception, consistent with F7 and H7.
Diagram

graph TD
  A["F4 UART register"] --> B["F4 IRQ handler"] --> C["Receive callback"] --> D["SBUS parser"]
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High-Level Assessment

Masking at the F4 UART callback boundary fixes the value for every callback consumer and matches F7/H7 behavior. Masking only in SBUS would leave other callback consumers exposed.

Files changed (1) +1 / -1

Bug fix (1) +1 / -1
serial_uart_stm32f4xx.cLimit F4 UART callback data to eight bits +1/-1

Limit F4 UART callback data to eight bits

• Masks the UART data register with 0xFF before invoking a receive callback, preventing bit 8 from changing byte comparisons in parity-enabled protocols. The receive-buffer path is unchanged.

src/main/drivers/serial_uart_stm32f4xx.c

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github-actions Bot commented Oct 6, 2026

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RAM / Flash usage vs. base commit e87050f — commit ba39efa

Using the nearest available size baseline — the PR's exact base commit has no stored baseline yet.

Target Flash Δ RAM Δ
MATEKF405 ±0 B (±0.00%) CCM: ±0 B (±0.00%)
RAM: ±0 B (±0.00%)
MATEKF722 ±0 B (±0.00%) ITCM_RAM: ±0 B (±0.00%)
RAM: ±0 B (±0.00%)
TCM: ±0 B (±0.00%)
MATEKF765 ±0 B (±0.00%) DTCM_RAM: ±0 B (±0.00%)
SRAM1: ±0 B (±0.00%)
MATEKH743 ±0 B (±0.00%) D2_RAM: ±0 B (±0.00%)
DTCM_RAM: ±0 B (±0.00%)
ITCM_RAM: ±0 B (±0.00%)
RAM: ±0 B (±0.00%)

See RAM/flash optimization guide for techniques to reduce usage.

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github-actions Bot commented Oct 6, 2026

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Test firmware build ready — commit ba39efa

Download firmware for PR #12109

251 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.

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Thanks!

@sensei-hacker sensei-hacker modified the milestones: 10.1, 10.0 Nov 15, 2026
@sensei-hacker
sensei-hacker merged commit 42b609e into iNavFlight:maintenance-10.x Nov 15, 2026
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3 participants