CHIPS Alliance

All

112 repositories

caliptra-sw
Public
Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test
Rust
•
Apache License 2.0
•75•129•200•75•Updated Dec 8, 2025Dec 8, 2025
caliptra-ss
Public
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
security rot ocp root-of-trust caliptra opencomputeproject
SystemVerilog
•
Apache License 2.0
•31•34•68•8•Updated Dec 8, 2025Dec 8, 2025
sv-tests
Public
Test suite designed to check compliance with the SystemVerilog standard.
rtl verilog systemverilog hdl compliance-testing symbiflow
SystemVerilog
•
ISC License
•83•350•46•29•Updated Dec 8, 2025Dec 8, 2025
caliptra-mcu-sw
Public
Caliptra MCU Software
Rust
•
Apache License 2.0
•30•21•82•11•Updated Dec 8, 2025Dec 8, 2025
chips-alliance-website
Public
SCSS
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MIT License
•7•4•8•8•Updated Dec 8, 2025Dec 8, 2025
Cores-VeeR-EL2
Public
VeeR EL2 Core
fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital
SystemVerilog
•
Apache License 2.0
•90•306•27•5•Updated Dec 8, 2025Dec 8, 2025
t1
Public
Scala
•
Apache License 2.0
•41•303•18•29•Updated Dec 8, 2025Dec 8, 2025
caliptra-rtl
Public
HW Design Collateral for Caliptra RoT IP
SystemVerilog
•
Apache License 2.0
•70•120•89•19•Updated Dec 8, 2025Dec 8, 2025
i3c-core
Public
SystemVerilog
•
Apache License 2.0
•14•37•14•4•Updated Dec 8, 2025Dec 8, 2025
sv-tests-results
Public
Output of the sv-tests runs.
HTML
•5•7•0•0•Updated Dec 8, 2025Dec 8, 2025
verilator
Public
Verilator open-source SystemVerilog simulator and lint system
C++
•
GNU Lesser General Public License v3.0
•721•41•0•0•Updated Dec 7, 2025Dec 7, 2025
chisel
Public
Chisel: A Modern Hardware Design Language
scala chip-generator chisel rtl chisel3 firrtl verilog
Scala
•
Apache License 2.0
•640•4.5k•346•142•Updated Dec 7, 2025Dec 7, 2025
firrtl-spec
Public
The specification for the FIRRTL language
TeX
•30•62•25•17•Updated Dec 6, 2025Dec 6, 2025
caliptra-dpe
Public
High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs
Rust
•
Apache License 2.0
•28•20•23•11•Updated Dec 5, 2025Dec 5, 2025
espresso
Public
C
•18•41•7•0•Updated Dec 5, 2025Dec 5, 2025
Caliptra
Public
Caliptra IP and firmware for integrated Root of Trust block
Apache License 2.0
•54•356•55•9•Updated Dec 4, 2025Dec 4, 2025
caliptra-web
Public
Astro
•
Apache License 2.0
•4•0•0•0•Updated Dec 4, 2025Dec 4, 2025
diplomacy
Public
Scala
•
Apache License 2.0
•16•22•9•1•Updated Dec 4, 2025Dec 4, 2025
guineveer
Public
C
•
Apache License 2.0
•2•3•0•0•Updated Dec 2, 2025Dec 2, 2025
adams-bridge
Public
Post-Quantum Cryptography IP Core (Crystals-Dilithium)
cryptography digital-signature lattice pqc ml-dsa-87
SystemVerilog
•
Apache License 2.0
•8•40•16•1•Updated Nov 13, 2025Nov 13, 2025
riscv-vector-tests
Public
Unit tests generator for RVV 1.0
generator spike riscv testsuite rvv
Go
•
Apache License 2.0
•32•97•10•1•Updated Nov 11, 2025Nov 11, 2025
uvm-verilator
Public
SystemVerilog
•
Apache License 2.0
•23•110•1•0•Updated Nov 11, 2025Nov 11, 2025
caliptra-ureg
Public
Rust
•
Apache License 2.0
•6•7•0•1•Updated Nov 7, 2025Nov 7, 2025
tac
Public
CHIPS Alliance Technical Advisory Council
Apache License 2.0
•26•7•17•3•Updated Oct 8, 2025Oct 8, 2025
riscv-dv
Public
Random instruction generator for RISC-V processor verification
Python
•
Apache License 2.0
•364•1.2k•129•21•Updated Oct 1, 2025Oct 1, 2025
chisel-template
Public template
A template project for beginning new Chisel work
Shell
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The Unlicense
•196•674•14•2•Updated Sep 22, 2025Sep 22, 2025
verible-actions-common
Public
Apache License 2.0
•8•2•0•0•Updated Sep 17, 2025Sep 17, 2025
caliptra-infra
Public
Various tools used for Caliptra's Continuous Integration flows
Rust
•
Apache License 2.0
•1•0•0•1•Updated Sep 16, 2025Sep 16, 2025
.github
Public
Organization profile for CHIPS Alliance
1•0•2•0•Updated Sep 16, 2025Sep 16, 2025
Surelog
Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
parser linter preprocessor antlr verilog python-api systemverilog uvm elaboration vpi
C++
•
Apache License 2.0
•77•430•47•0•Updated Sep 6, 2025Sep 6, 2025