RISC-V RV32I Open Source Design Submission (VLSI26)

[Har67]

This pull request contains my submission for the IEEE SSCS Code-a-Chip VLSI26 track.

Project: RISC-V RV32I Open Source Design

Contents included:

• Jupyter Notebook with full design and flow explanation
• OpenLane physical design flow results
• Key logs and reports
• Screenshots of waveform and implementation results

The design was implemented using OpenLane and demonstrates synthesis, floorplanning, placement, CTS, and routing stages.

Thank you for reviewing my submission.

[atuchiya]

Please add following information or send e-mail to program lead (Akira Tsuchiya, a_tsuchiya@ieee.org):

• your affiliation
• contact e-mail address
• membership status (IEEE member or not, SSCS member or not)